Display substrate and display device

Abstract

A display substrate and a display device, wherein the display substrate comprises a base, the base comprising a display area and a peripheral area; the display area comprises a plurality of sub-pixels, a plurality of data lines, and a plurality of power lines; the peripheral area comprises at least one test data signal line, at least one test control signal line, and a plurality of test units, the plurality of test units being located on a side of the plurality of data lines away from the display area, at least one of the plurality of test units being electrically connected to at least one of the plurality of data lines, at least one test data signal line, and at least one test control signal line; the peripheral area further comprises a first power bus and a plurality of connection portions, the first power bus being located on a side of the plurality of test units away from the display area; the plurality of connection portions being electrically connected to the first power bus and to the plurality of power lines, and the plurality of connection portions extending toward the display area along the area between the plurality of test units.

Description

Technical Field

[0001] The present disclosure relates to, but is not limited to, the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) is an active light-emitting display device with the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, and extremely high response speed. Summary of the Invention

[0003] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0004] An exemplary embodiment of the present disclosure provides a display substrate, including:

[0005] a substrate comprising a display area and a peripheral area located on at least one side of the display area;

[0006] A plurality of sub-pixels are located in the display area;

[0007] a plurality of data lines located in the display area and electrically connected to the plurality of sub-pixels, the plurality of data lines being configured to provide data signals to the plurality of sub-pixels;

[0008] a plurality of power lines located in the display area and electrically connected to the plurality of sub-pixels, the plurality of power lines being configured to provide power signals to the plurality of sub-pixels;

[0009] at least one test data signal line located in the peripheral area;

[0010] at least one test control signal line located in the peripheral area;

[0011] a plurality of test units located in the peripheral area and on a side of the plurality of data lines away from the display area, at least one of the plurality of test units being electrically connected to at least one of the plurality of data lines, the at least one test data signal line, and the at least one test control signal line, and being configured to transmit a signal provided by the at least one test data signal line to the at least one data line according to a signal provided by the at least one test control signal line;

[0012] a first power bus located in the peripheral area and on a side of the plurality of test units away from the display area;

[0013] A plurality of connection portions are electrically connected to the first power bus and the plurality of power lines, and the plurality of connection portions extend toward the display area along areas between the plurality of test units.

[0014] In an exemplary embodiment, the display substrate further includes a second power bus located between the plurality of test units and the display area, wherein the plurality of connection portions are electrically connected to the first power bus and the second power bus, respectively.

[0015] In an exemplary embodiment, the first power bus, the second power bus, and the plurality of connection portions define a plurality of first openings arranged in an array, and orthographic projections of the plurality of test units on the substrate are located in the plurality of first openings.

[0016] In an exemplary embodiment, the second power bus includes a plurality of second openings, the test unit includes a plurality of transistors, and drains of the plurality of transistors are located in the plurality of second openings.

[0017] In an exemplary embodiment, the test unit includes a first test transistor, a second test transistor, and a third test transistor; the at least one test data signal line includes a first test data signal line, a second test data signal line, and a third test data signal line; the at least one test control signal line includes a first test control signal line, a second test control signal line, and a third test control signal line; the multiple data lines include a first data line and a second data line arranged alternately; the source of the first test transistor and the source of the second test transistor are respectively connected to the first test data signal line and the second test data signal line, the drain of the first test transistor and the drain of the second test transistor are connected to the first data line, and the gate of the first test transistor and the gate of the second test transistor are respectively connected to the third test control signal line and the second test control signal line; the source of the third transistor is connected to the third test data signal line, the drain of the third transistor is connected to the second data line, and the gate of the third transistor is connected to the first test control signal line.

[0018] In an exemplary embodiment, the test unit further includes a fourth test transistor and a fifth test transistor, the drain of the fourth test transistor and the drain of the fifth test transistor are connected to another first data line, the gate of the fourth test transistor and the gate of the fifth test transistor are connected to the second test control signal line and the third test control signal line, respectively, and the source of the fourth test transistor and the source of the fifth test transistor are connected to the first test data signal line and the second test data signal line.

[0019] In an exemplary embodiment, the first test transistor, the second test transistor, and the third test transistor are located in one first opening among the plurality of first openings, and the fourth test transistor and the fifth test transistor are located in first openings adjacent to the one first opening.

[0020] In an exemplary embodiment, the first test transistor, the second test transistor, the fourth test transistor, and the fifth test transistor are located in one first opening among the plurality of first openings, and the third test transistor is located in a first opening adjacent to the one first opening.

[0021] In an exemplary embodiment, the test unit further includes a fourth test transistor, a fifth test transistor and a sixth test transistor, the drain of the fourth test transistor and the drain of the fifth test transistor are connected to another first data line, the gate of the fourth test transistor and the gate of the fifth test transistor are connected to the second test control signal line and the third test control signal line, respectively, the source of the fourth test transistor and the source of the fifth test transistor are connected to the first test data signal line and the second test data signal line; the source of the sixth test transistor is connected to the third test data signal line, the drain of the sixth test transistor is connected to another second data line, and the gate of the sixth test transistor is connected to the first test control signal line.

[0022] In an exemplary embodiment, the first test transistor, the second test transistor, and the third test transistor are located in one first opening among the plurality of first openings, and the fourth test transistor, the fifth test transistor, and the sixth test transistor are located in first openings adjacent to the one first opening.

[0023] In an exemplary embodiment, the test unit includes a seventh test transistor, an eighth test transistor, and a ninth test transistor; the at least one test data signal line includes a fourth test data signal line, a fifth test data signal line, and a sixth test data signal line; the at least one test control signal line includes a fourth test control signal line;

[0024] The multiple data lines include a third data line, a fourth data line and a fifth data line arranged alternately; the drain of the seventh test transistor is connected to the third data line, the source of the seventh test transistor is connected to the fourth test data signal line, and the gate of the seventh test transistor is connected to the fourth test control signal line; the drain of the eighth test transistor is connected to the fourth data line, the source of the eighth test transistor is connected to the fifth test data signal line, and the gate of the eighth test transistor is connected to the fourth test control signal line; the drain of the ninth test transistor is connected to the fifth data line, the source of the ninth test transistor is connected to the sixth test data signal line; and the gate of the ninth test transistor is connected to the fourth test control signal line.

[0025] In an exemplary embodiment, the seventh test transistor, the eighth test transistor, and the ninth test transistor are located in one first opening among the plurality of first openings.

[0026] In an exemplary embodiment, the at least one test control signal line and the at least one test data signal line are arranged in parallel along an extending direction of the connecting portion and are located between the plurality of test units and the first power bus.

[0027] In an exemplary embodiment, at least one of the plurality of connection portions further includes a third opening, an orthographic projection of the third opening on the substrate overlapping an orthographic projection of at least one of the at least one test data signal line and the at least one test control signal line on the substrate.

[0028] In an exemplary embodiment, in a plane perpendicular to the display substrate, the display substrate includes a buffer layer, a first active layer, a gate insulating layer, a first gate metal layer, a first insulating layer, a second gate metal layer, a second insulating layer and a first source-drain metal layer stacked on the base; the test control signal line, the test data signal line, the first power bus and the power line are all located on the first source-drain metal layer; the connecting portion is located on the second gate metal layer, and the connecting portion is respectively connected to the first power bus and the multiple power lines through vias on the second insulating layer; or, the connecting portion is located on the first gate metal layer, and the connecting portion is respectively connected to the first power bus and the multiple power lines through vias passing through the first insulating layer and the second insulating layer.

[0029] In an exemplary embodiment, in a plane perpendicular to the display substrate, the display substrate includes a buffer layer, a first active layer, a gate insulating layer, a first gate metal layer, a first insulating layer, a second gate metal layer, a second insulating layer and a first source-drain metal layer stacked on the base; the test control signal line, the test data signal line, the first power bus and the power line are all located on the first source-drain metal layer; the connecting portion includes a first connecting portion and a second connecting portion, the second connecting portion is located on the second gate metal layer, and the second connecting portion is respectively connected to the first power bus and the power line through vias on the second insulating layer; the first connecting portion is located on the first gate metal layer, and the first connecting portion is respectively connected to the first power bus and the power line through vias passing through the first insulating layer and the second insulating layer.

[0030] In an exemplary embodiment, the display substrate further comprises a plurality of data signal input lines located in the peripheral area, the plurality of data signal input lines being located on a side of the plurality of test units away from the display area, and at least one of the plurality of data signal input lines being electrically connected to the at least one test unit.

[0031] An exemplary embodiment of the present disclosure further provides a display device, comprising any one of the aforementioned display substrates.

[0032] Other aspects will become apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The accompanying drawings are intended to provide a further understanding of the technical solutions of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure and do not constitute a limitation of the technical solutions of the present disclosure. The shapes and sizes of the components in the drawings do not reflect the actual scale and are intended only to illustrate the contents of the present disclosure.

[0034] Figure 1 A schematic structural diagram showing a substrate according to an exemplary embodiment of the present disclosure;

[0035] Figure 2 This is a schematic diagram showing an enlarged structure of a test unit and a connection portion of a substrate according to an exemplary embodiment of the present disclosure;

[0036] Figure 3 This is a circuit diagram of a pixel circuit in a display substrate according to an embodiment of the present disclosure;

[0037] Figure 4 Schematic diagram of the structure of a display area of a display substrate according to an embodiment of the present disclosure;

[0038] Figure 5 This is one of the structural schematic diagrams showing the test unit area in the substrate according to an exemplary embodiment of the present disclosure;

[0039] Figure 6 for Figure 5 A schematic structural diagram of the active layer in the test unit area shown;

[0040] Figure 7 for Figure 5 A schematic structural diagram of the layer where the first gate metal layer of the test unit area is located;

[0041] Figure 8 for Figure 5 A schematic structural diagram of the layer where the second gate metal layer of the test unit area is located;

[0042] Figure 9 for Figure 5 Schematic diagram of vias in the insulating layer of the test cell area shown;

[0043] Figure 10 for Figure 5 A schematic structural diagram of the source and drain metal layers in the test unit area shown;

[0044] Figure 11This is a schematic diagram showing a circuit structure of a test unit in a substrate according to an exemplary embodiment of the present disclosure;

[0045] Figure 12 This is a second structural schematic diagram showing a test unit area in a substrate according to an exemplary embodiment of the present disclosure;

[0046] Figure 13 The third structural schematic diagram showing the test unit area in the substrate according to the exemplary embodiment of the present disclosure;

[0047] Figure 14 This is a second schematic diagram showing the circuit structure of a test unit in a substrate according to an exemplary embodiment of the present disclosure;

[0048] Figure 15 This is a fourth structural schematic diagram showing a test unit area in a substrate according to an exemplary embodiment of the present disclosure;

[0049] Figure 16 for Figure 15 A schematic structural diagram of the active layer in the test unit area shown;

[0050] Figure 17 for Figure 15 A schematic structural diagram of the layer where the first gate metal layer of the test unit area is located;

[0051] Figure 18 for Figure 15 A schematic structural diagram of the layer where the second gate metal layer of the test unit area is located;

[0052] Figure 19 for Figure 15 Schematic diagram of vias in the insulating layer of the test cell area shown;

[0053] Figure 20 for Figure 15 A schematic structural diagram of the source and drain metal layers in the test unit area shown;

[0054] Figure 21 The third schematic diagram of the circuit structure of the test unit in the substrate is shown in the exemplary embodiment of the present disclosure;

[0055] Figure 22 Schematic diagram of the structure of the display substrate after forming the first source and drain metal layer pattern according to the exemplary embodiment of the present disclosure (wherein the display area 10 corresponds to Figure 1 The display area in the BB' area corresponds to Figure 2 BB' area in the

[0056] Figure 23 This is a structural schematic diagram showing the position of the lower frame of the substrate according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0057] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0058] In the drawings, the sizes of various components, layer thicknesses, or regions may be exaggerated for clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to these dimensions, and the shapes and sizes of the components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate idealized examples, and one embodiment of the present disclosure is not limited to the shapes or numerical values shown in the drawings.

[0059] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0060] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0061] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0062] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0063] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" may be interchanged.

[0064] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0065] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0066] The term "about" in the present disclosure refers to a numerical value that is not strictly defined and allows for process and measurement errors.

[0067] like Figure 1 and Figure 2 As shown, an exemplary embodiment of the present disclosure provides a display substrate, comprising:

[0068] A substrate (not shown) comprising a display area 10 and a peripheral area 20 located on at least one side of the display area 10;

[0069] A plurality of sub-pixels 1 are located in a display area 10;

[0070] a plurality of data lines 11 located in the display area 10 and electrically connected to the plurality of sub-pixels 1, the plurality of data lines 11 being configured to provide data signals to the plurality of sub-pixels 1;

[0071] a plurality of power lines 14 located in the display area 10 and electrically connected to the plurality of sub-pixels 1, the plurality of power lines 14 being configured to provide power signals to the plurality of sub-pixels 1;

[0072] a plurality of test units 330 located in the peripheral area 20 and on a side of the plurality of data lines 11 away from the display area 10, at least one of the plurality of test units 330 being electrically connected to at least one of the plurality of data lines 11, at least one test data signal line 332, and at least one test control signal line 331, and configured to transmit a signal provided by the at least one test data signal line 332 to the at least one data line 11 based on a signal provided by the at least one test control signal line 331;

[0073] The first power bus 321 is located in the peripheral area 20 and on a side of the plurality of test units 330 away from the display area 10 ;

[0074] The plurality of connection portions 322 are electrically connected to the first power bus 321 and the plurality of power lines 14 . The plurality of connection portions 322 extend toward the display area 10 along the areas between the plurality of test units 330 .

[0075] In an exemplary embodiment, referring to Figure 1 The display substrate also includes a plurality of data signal input lines 203 located in the peripheral area 20. The plurality of data signal input lines 203 are located on a side of the plurality of test units 330 away from the display area 10. The plurality of data signal input lines 203 are electrically connected to the plurality of data lines 11 respectively; at least one of the plurality of data signal input lines 203 is electrically connected to at least one test unit 330.

[0076] In an exemplary embodiment, referring to Figure 1 and Figure 2 The display substrate further includes a second power bus 323 located between the plurality of test units 330 and the display area 10 , wherein the plurality of connection portions 322 are electrically connected to the first power bus 321 and the second power bus 323 , respectively.

[0077] In an exemplary embodiment, referring to Figure 2 The first power bus 321 , the second power bus 323 and the plurality of connection portions 322 define a plurality of first openings 324 arranged in an array, and the orthographic projections of the plurality of test units 330 on the substrate are located in the plurality of first openings 324 .

[0078] Reference Figure 1 The base of the display substrate of the embodiment of the present disclosure can be a flexible base or a rigid base. The middle part of the base is a display area 10 for display. The sub-pixels 1 (or sub-pixels) for display are arranged in the display area 10. The periphery of the display area 10 is a peripheral area 20 with other structures.

[0079] Here, “a certain structure is located in a certain area” means that the positive projection of the structure on the substrate is located within the scope of the area.

[0080] The display area 10 of the substrate is provided with a plurality of sub-pixels 1 for display. Each sub-pixel 1 is a smallest point that can independently emit light of a desired brightness and color. The specific form of the sub-pixel 1 is varied, as long as it can achieve independent display. Typically, multiple sub-pixels 1 form a "pixel" that can display light of any color and brightness. Each "pixel" is a "point" in the image to be displayed.

[0081] The display area 10 is further provided with leads for providing driving signals to the sub-pixels 1, such as data lines 11 for providing data signals (data voltages) to the sub-pixels 1. The data lines 11 extend along a first direction 991.

[0082] Reference Figure 1 In some embodiments, the display area 10 is further provided with other leads such as gate lines 12 and control lines 13. The gate lines 12 and control lines 13 extend along a second direction 992. The first direction 991 intersects with the second direction 992 (i.e., they are not parallel to each other), so that each intersection of the data line 11 and the gate line 12 defines a sub-pixel 1. By controlling the gate line 12 and the data line 11 together, the sub-pixel 1 at the intersection can be displayed.

[0083] In some embodiments, the first direction 991 is perpendicular to the second direction 992, that is, the first direction 991 may be a column direction ( Figure 1 The second direction 992 may be a row direction perpendicular to the column direction ( Figure 1 (middle is horizontal).

[0084] It should be understood that Figure 1 The use of "rectangles" to represent the various units (including the test unit 330, the drive unit 21, etc.) and the sub-pixel 1 is only for schematic purposes. In fact, each unit (including the test unit 330, the drive unit 21, etc.) and the sub-pixel 1 is composed of multiple devices, and the area they occupy is not necessarily a rectangle. It should be understood that, based on area limitations, in many drawings of the embodiments of the present disclosure, the shapes, sizes, size ratios, numbers, number ratios, positions, etc. of the various structures of the sub-pixel 1 leads (such as signal lines), connectors, units, areas, etc. are only exemplary and not limitations on the embodiments of the present disclosure. For example, the actual number of gate lines 12, data lines 11, control lines 13, etc. should be less than Figure 1 More shown in .

[0085] Reference Figure 1In some embodiments, the sub-pixels 1 in the display area 10 are arranged in a matrix, that is, in multiple rows and columns. The data lines 11 are parallel to the column direction, and each data line 11 is electrically connected to a column of sub-pixels 1; the gate lines 12 are parallel to the row direction, and each gate line 12 is electrically connected to a row of sub-pixels 1; and the control lines 13 are parallel to the row direction, and each control line 13 is electrically connected to a row of sub-pixels 1.

[0086] Thus, when displaying each frame, a conduction signal (a signal that turns on the transistor) is fed to each gate line 12 in turn (time-sharing). When each gate line 12 receives the conduction signal, each data line 11 writes the data signal into each sub-pixel 1 (e.g., a row of sub-pixels 1) electrically connected to the gate line 12, and stores the data signal in the storage capacitor Cst, allowing the sub-pixel 1 to display according to the stored data signal for the remainder of the frame. The control line 13 is used to control whether the sub-pixel 1 can emit light.

[0087] In the peripheral area 20 of the substrate, multiple test units 330 and multiple pads 71 are also provided. The multiple test units 330 are located between the multiple data lines 11 and the multiple data signal input lines 203, or in other words, the multiple test units 330 are located between the first power bus 321 and the second power bus 323, and the multiple pads 71 are located on the side of the test unit 330 away from the display area 10.

[0088] The pad 71 is a structure provided on the substrate for obtaining signals. Specifically, it can be a sheet-like metal layer or layers provided on the substrate. For example, the pad 71 can be a structure (such as a pin) for bonding to a flexible printed circuit board (FPC) or a driver chip (IC), thereby obtaining signals from the flexible printed circuit board or the driver chip. Specifically, at least a portion of the pad 71 is used to provide data signals to the data line 11. That is, at least a portion of the pad 71 is used to provide data signals to the data line 11 during display to control the sub-pixel 1 connected to the data line 11 to display the desired content. At least a portion of the pad 71 is used to provide a positive power signal to the power line (exemplarily, the power line includes a positive power line and a negative power line. The positive power line can be composed of the first power bus 321, multiple connecting portions 322, the second power bus 323, and multiple power lines 14 within the display area 10). At least a portion of the pad 71 is used to provide a clock signal to the display.

[0089] The test unit 330 is electrically connected to the test data signal line 332 and the test control signal line 331, so that each test unit 330 is used to provide (simultaneously or separately) the signal (data signal) of the test data signal line 332 to multiple data lines 11 electrically connected thereto according to the control of the test control signal line 331, so as to determine whether the sub-pixels 1 electrically connected to these data lines 11 can be lit, and whether there are dead pixels or bright pixels.

[0090] In rigid OLED products, the test circuitry used for unit testing is typically placed within the upper bezel of the display panel. This requires transmitting the test signal from the signal input terminal at the lower bezel of the display panel along the left and right sides of the display panel to the upper bezel. During this process, the long test signal traces create a high circuit impedance, reducing the signal drive capability of the test signal traces and, in severe cases, even affecting the unit test results of the product. Furthermore, the test signal traces on the left and right sides of the display panel limit further reduction in the left and right bezels, hindering the narrow-bezel design of the display panel.

[0091] The display substrate of the disclosed embodiment, by placing the test unit 330 on the side of the data line 11 away from the display area 10, avoids the problem of large circuit impedance generated when the test unit 330 is placed on top of the display area 10, thereby enhancing signal driving capability, improving the test effect of the unit test, saving signal routing space on the left and right frames, and facilitating a narrow frame design. In addition, the display substrate of the disclosed embodiment, by providing multiple connecting portions 322 between the first power bus 321 and the multiple power lines, significantly reduces the current in a single line, thereby reducing the impact of the increased resistance caused by the layer jumper on the voltage drop, which is beneficial to display uniformity and reduces product power consumption.

[0092] In some embodiments, reference Figure 1 The peripheral area 20 is divided into a first half area and a second half area opposite to each other on both sides of the display area 10 along the second direction 992; the driving unit 21 located in the first half area is a gate driving unit 211, and the gate driving unit 211 is configured to provide gate driving signals to multiple gate lines 12.

[0093] Reference Figure 1 The peripheral area 20 can be divided into two "half areas ( Figure 1 In some embodiments, the driving unit 21 in the first half area may be a gate driving unit 211 that provides gate driving signals to the plurality of gate lines 12, so that the gate driving unit 211 is connected to the corresponding gate lines 12 nearby. The driving unit 21 in the second half area is a gate driving unit 212, which is configured to provide gate driving signals to the plurality of gate lines 13, so that the gate driving unit 212 is connected to the corresponding gate lines 13 nearby.

[0094] In an exemplary embodiment, each gate driving unit 211 may be a gate shift register (GOA), and multiple gate shift registers are cascaded, so that the multiple gate shift registers can provide driving signals to multiple gate lines 12 respectively.

[0095] In an exemplary embodiment, each gate driving unit 212 may be a gate shift register (EMGOA), and multiple gate shift registers are cascaded, so that the multiple gate shift registers can respectively provide driving signals to multiple gate lines 13.

[0096] In some embodiments, the driving units 21 in the two half-areas can also be gate driving units 211, and provide gate driving signals to different gate lines 12 respectively, or provide gate driving signals to each gate line 12 from both sides simultaneously (i.e., double-sided driving).

[0097] In an exemplary embodiment, referring to Figure 2 At least one test control signal line 331 and at least one test data signal line 332 are arranged in parallel along the extending direction of the connecting portion 322 and are located between the plurality of test units 330 and the first power bus 321 .

[0098] In an exemplary embodiment, referring to Figure 2 At least one connection portion 322 among the multiple connection portions 322 includes a third opening 322a, and the positive projection of the third opening 322a on the substrate overlaps with the positive projection of at least one test signal line on the substrate, and the test signal line includes a test control signal line 331 and a test data signal line 332.

[0099] Because the test signal line and the connection portion 322 overlap, a large amount of parasitic capacitance is formed in the overlapping area, which can easily cause signal input differences at different traces of the connection portion 322 (for bidirectional driving, the circuit impedance (RC loading) of the areas at both ends of the display area 10 is usually small, while the circuit impedance of the area in the middle of the display area is large), causing poor display (commonly seen as gradually brighter toward the middle). The display substrate of the present embodiment provides one or more third openings 322a in the connection portion 322 where it overlaps with the test signal line, thereby dividing the connection portion 322 in this portion into multiple thin lines, thereby reducing the impact of parasitic capacitance at this location.

[0100] In an exemplary embodiment, Figure 2 As shown, the interval b between the test unit 330 and the connection portion 322 is greater than the minimum exposure accuracy between patterns on the same layer. For example, if the minimum exposure accuracy between patterns on the same layer is 3 microns, the interval b between the test unit 330 and the connection portion 322 is greater than 3 microns. For example, the interval b between the test unit 330 and the connection portion 322 can be 5 microns.

[0101] In some embodiments, each sub-pixel 1 is provided with a pixel circuit for making the sub-pixel 1 emit light.

[0102] For example, the structure of the pixel circuit can refer to Figure 3 , is a 7T1C structure, which includes a first transistor T1, a second transistor T2, a driving transistor T3 (third transistor), a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a storage capacitor Cst, an organic light emitting diode OLED, a first reset terminal Reset, a second reset terminal Reset', an initialization terminal Vinit, a gate line terminal Gate, a data line terminal Data, a control line terminal EM, a positive terminal VDD, a negative terminal VSS, and the like; wherein each transistor can be a P-type transistor (such as PMOS) or an N-type transistor (such as NMOS). The data line terminal Data can be connected to the data line 11, the gate line terminal Gate can be connected to the gate line 12, the control line terminal EM can be connected to the control line 13, the first reset terminal Reset and the second reset terminal Reset' can be simultaneously connected to the gate line of the previous row, the second reset terminal Reset' can also be connected to the gate line of the current row, and the other terminals can also be connected to corresponding signal sources.

[0103] In the above pixel circuit, by writing a suitable data signal to the gate of the driving transistor T3 , the current flowing through the driving transistor T3 can be controlled, thereby controlling the organic light emitting diode OLED to emit light with a corresponding brightness, thereby realizing the display of the sub-pixel 1 .

[0104] The positive terminal VDD is electrically connected to a positive signal source (such as through a positive line), and the negative terminal VSS is electrically connected to a negative signal source (such as the cathode layer 153 of the organic light emitting diode OLED (such as Figure 4 As shown), the control electrode line terminal EM is connected to the control electrode line 13, the gate line terminal Gate is connected to the gate line 12, and the data line terminal Data is connected to the data line 11; the other terminals are also electrically connected to the corresponding signal sources.

[0105] Of course, the specific structures of the sub-pixel 1 and the pixel circuit are not limited to the above methods.

[0106] Reference Figure 4 In some embodiments, each sub-pixel 1 includes a driving transistor T3 and a storage capacitor Cst; wherein,

[0107] The driving transistor T3 comprises:

[0108] a first active layer 111 located on one side of the substrate;

[0109] a gate insulating layer 190 located on a side of the first active layer 111 away from the substrate;

[0110] A first gate 112 located on a side of the gate insulating layer 190 away from the substrate;

[0111] A first insulating layer 191 located on a side of the first gate 112 away from the substrate;

[0112] a second insulating layer 192 (interlayer insulating layer ILD) located on a side of the first insulating layer 191 away from the substrate;

[0113] Located on a side of the second insulating layer 192 away from the substrate, the first source electrode 113 and the first drain electrode 114 are electrically connected to the first active layer 111;

[0114] The storage capacitor Cst includes:

[0115] The first pole piece 121 is provided on the same layer as the first gate 112;

[0116] The second pole piece 122 is located between the first insulating layer 191 and the second insulating layer 192 .

[0117] When the pixel circuit of each sub-pixel 1 includes a driving transistor T3 and a storage capacitor Cst, the stacking relationship of the partial structures in the sub-pixel 1 can refer to Figure 4 .

[0118] Of course, the sub-pixel 1 may also include other structures.

[0119] For example, refer to Figure 4 A buffer layer 193 (Buffrt) may be provided between the first gate electrode 112 and the substrate for improving the contact performance between the first gate electrode 112 and the substrate. A planarization layer 194 (PLN) may be provided on the side of the first source electrode 113 and the first drain electrode 114 away from the substrate. The above-mentioned organic light-emitting diode OLED may be provided on the side of the planarization layer 194 away from the substrate. The organic light-emitting diode OLED may include an anode layer 151 connected to the first drain electrode 114, and a light-emitting layer 152 and a cathode layer 153 provided on the side of the anode layer 151 away from the substrate, so that the anode layer 151, the light-emitting layer 152, and the cathode layer 153 stacked on each other constitute the organic light-emitting diode OLED; and the organic light-emitting diode OLED may be defined by a pixel defining layer 154 (PDL), and the cathode layer 153 may be provided with an encapsulation layer 155 and other structures on the side away from the substrate.

[0120] Of course, the structure of the above sub-pixel 1 can be changed.

[0121] For example, the encapsulation layer 155 can be further divided into an organic encapsulation layer, an inorganic encapsulation layer, etc., and can even include a stacked structure of organic encapsulation layers and inorganic encapsulation layers; and the sub-pixel 1 can also be provided with other structures such as a reflective layer and a color filter film.

[0122] It should be understood that the structures of each layer of other transistors in the sub-pixel 1 can be arranged in the same layer as the corresponding structure of the driving transistor T3.

[0123] In the following description, the layers of some other structures are exemplarily introduced based on the stacking method.

[0124] In an exemplary embodiment, Figure 2 、 Figure 5 、 Figure 12 、 Figure 13 and Figure 15 As shown, the test signal line includes a test control signal line 331 and a test data signal line 332, and at least one test unit 330 includes multiple test transistors, the gate of each test transistor is connected to a test control signal line 331, the drain is connected to a data line 11, and the source is connected to a test data signal line 332; each test signal line is connected to multiple test units 330.

[0125] Because each test data signal line 332 and test control signal line 331 is connected to multiple test cells 330, these few test signal lines do not occupy a large layout area. By supplying a conduction signal to the test control signal line 331, the signal in the test data signal line 332 passes through the transistors in different test cells 330 and enters the corresponding multiple data lines 11, thereby enabling testing of the display substrate.

[0126] In an exemplary embodiment, referring to Figure 5 、 Figure 12 、 Figure 13 and Figure 15 The second power bus 323 includes a plurality of second openings 323 a , and the drains of the plurality of test transistors in the test unit 330 are located in the plurality of second openings 323 a .

[0127] In an exemplary embodiment, Figure 5 、 Figure 12 or Figure 13 As shown, the test unit 330 includes a first test transistor 330a, a second test transistor 330b and a third test transistor 330c; at least one test data signal line 332 includes a first test data signal line CTDR, a second test data signal line CTDB and a third test data signal line CTDG; at least one test control signal line 331 includes a first test control signal line SWG, a second test control signal line SWRB and a third test control signal line SWBR; and a plurality of data lines 11 include alternately arranged first data lines 111 and second data lines 112.

[0128] The source of the first test transistor 330a and the source of the second test transistor 330b are connected to the first test data signal line CTDR and the second test data signal line CTDB, respectively. The drain of the first test transistor 330a and the drain of the second test transistor 330b are connected to the first data line 111. The gate of the first test transistor 330a and the gate of the second test transistor 330b are connected to the third test control signal line SWBR and the second test control signal line SWRB, respectively.

[0129] A source of the third test transistor 330 c is connected to the third test data signal line CTDG, a drain of the third test transistor 330 c is connected to the second data line 112 , and a gate of the third test transistor 330 c is connected to the first test control signal line SWG.

[0130] In an exemplary embodiment, Figure 5 As shown, the test unit 330 further includes a fourth test transistor 330d, a fifth test transistor 330e, and a sixth test transistor 330f. The drain of the fourth test transistor 330d and the drain of the fifth test transistor 330e are connected to another first data line 111, the gate of the fourth test transistor 330d and the gate of the fifth test transistor 330e are connected to the second test control signal line SWRB and the third test control signal line SWBR, respectively, and the source of the fourth test transistor 330d and the source of the fifth test transistor 330e are connected to the first test data signal line CTDR and the second test data signal line CTDB.

[0131] A source of the sixth test transistor 330 f is connected to the third test data signal line CTDG, a drain of the sixth test transistor 330 f is connected to another second data line 112 , and a gate of the sixth test transistor 330 f is connected to the first test control signal line SWG.

[0132] In an exemplary embodiment, the first test transistor 330a, the second test transistor 330b and the third test transistor 330c are located in one first opening among the plurality of first openings, and the fourth test transistor 330d, the fifth test transistor 330e and the sixth test transistor 330f are located in first openings adjacent to the aforementioned first opening.

[0133] The distribution of the layers of the various structures of the test unit 330 may be varied.

[0134] For example, refer to Figure 4 , Figures 5 to 10 , the active layer 111' ( Figure 6) are arranged at intervals along the second direction 992 (and can be provided in the same layer as the first active layer 111) and are covered by the gate insulating layer 190; and the gate 112' of each test transistor can be provided in the same layer as the first gate 112, and at the same time, a plurality of connecting portions 322 and part of the data signal input line 203 ( Figure 7 ); and the same layer as the second electrode 122 may be provided with a structure 11a (or regarded as a part of the data line 11) for electrically connecting the drain of the test transistor to the corresponding data line 11 and a part of the data signal input line 203, and a structure 332a ( Figure 8 ); and the first source 113 and the first drain 114 are in the same layer, the source 113 'and the drain 114 'of the test transistor may be provided ( Figure 10 ), and the test control signal line 331, the test data signal line 332, the first power bus 321 and the second power bus 323; and through the via 192a ( Figure 9 ), the electrical connection of the corresponding structure can be achieved.

[0135] The specific form of the above test unit 330 and the distribution of the layers of each structure therein are only exemplary and not limiting to the embodiments of the present disclosure, and therefore will not be described in detail here.

[0136] Reference Figure 11The display substrate of this embodiment has a total of three test data signal lines 332 and three test control signal lines 331. Each test unit 330 includes six test transistors for controlling four data lines 11 (corresponding to the above four columns of sub-pixels 1, two columns of sub-pixels 1 in each of the four columns of sub-pixels 1 are green, and in each of the remaining two columns of sub-pixels 1, red and blue sub-pixels 1 are alternately arranged, and in the two columns of sub-pixels 1, two sub-pixels 1 in any row are blue and red respectively). Each test unit 330 includes a first test transistor 330a, a second test transistor 330b, a third test transistor 330c, a fourth test transistor 330d, a fifth test transistor 330e, and a sixth test transistor 330f. The drains of the first test transistor 330a and the second test transistor 330b are connected to a column of mixed red and blue sub-pixels 1, and the drains of the fourth test transistor 330d and the fifth test transistor 330e are connected to the drains of the other A column of mixed red and blue sub-pixels 1, the drain of the third test transistor 330c is connected to a column of green sub-pixels 1, the drain of the sixth test transistor 330f is connected to another column of green sub-pixels 1, the sources of the first test transistor 330a and the fourth test transistor 330d are connected to the first test data signal line CTDR, the sources of the second test transistor 330b and the fifth test transistor 330e are connected to the second test data signal line CTDB, the sources of the third test transistor 330c and the sixth test transistor 330f are connected to the third test data signal line CTDG, the gates of the first test transistor 330a and the fifth test transistor 330e are connected to the third test control signal line SWBR, the gates of the second test transistor 330b and the fourth test transistor 330d are connected to the second test control signal line SWRB; the gates of the third test transistor 330c and the sixth test transistor 330f are connected to the first test control signal line SWG.

[0137] It can be seen from the above settings that by alternately providing turn-on signals to the second test control signal line SWRB and the third test control signal line SWBR, the first test data signal line CTDR and the second test data signal line CTDB can control the blue and red sub-pixels 1 respectively, while the first test control signal line SWG and the third test data signal line CTDG control all green sub-pixels 1, so that the sub-pixels 1 of the same color display the same brightness.

[0138] In an exemplary embodiment, Figure 12 or Figure 13As shown, the test unit 330 may further include a fourth test transistor 330d and a fifth test transistor 330e, the drain of the fourth test transistor 330d and the drain of the fifth test transistor 330e are connected to another first data line 111, the gate of the fourth test transistor 330d and the gate of the fifth test transistor 330e are connected to the second test control signal line SWRB and the third test control signal line SWBR, respectively, and the source of the fourth test transistor 330d and the source of the fifth test transistor 330e are connected to the first test data signal line CTDR and the second test data signal line CTDB.

[0139] In an exemplary embodiment, Figure 12 As shown, the first test transistor 330a, the second test transistor 330b and the third test transistor 330c are located in one first opening among the plurality of first openings, and the fourth test transistor 330d and the fifth test transistor 330e are located in a first opening adjacent to the aforementioned first opening.

[0140] In an exemplary embodiment, Figure 13 As shown, the first test transistor 330a, the second test transistor 330b, the fourth test transistor 330d and the fifth test transistor 330e are located in one first opening among the plurality of first openings, and the third test transistor 330c is located in a first opening adjacent to the aforementioned first opening.

[0141] Reference Figure 14The display substrate of this embodiment has a total of three test data signal lines 332 and three test control signal lines 331. Each test unit 330 includes five test transistors for controlling four data lines 11 (corresponding to the above four columns of sub-pixels 1, two columns of sub-pixels 1 in each of the four columns of sub-pixels 1 are green, and in each of the remaining two columns of sub-pixels 1, red and blue sub-pixels 1 are alternately arranged, and in the two columns of sub-pixels 1, two sub-pixels 1 in any row are blue and red respectively). Each test unit 330 includes a first test transistor 330a, a second test transistor 330b, a third test transistor 330c, a fourth test transistor 330d, and a fifth test transistor 330e. The drains of the first test transistor 330a and the second test transistor 330b are connected to a column of mixed red and blue sub-pixels 1, and the drains of the fourth test transistor 330 are connected to a column of mixed red and blue sub-pixels 1. d and the drain of the fifth test transistor 330e are connected to another column of mixed red and blue sub-pixels 1, the drain of the third test transistor 330c is connected to two columns of green sub-pixels 1, the sources of the first test transistor 330a and the fourth test transistor 330d are connected to the first test data signal line CTDR, the sources of the second test transistor 330b and the fifth test transistor 330e are connected to the second test data signal line CTDB, the source of the third test transistor 330c is connected to the third test data signal line CTDG, the gates of the first test transistor 330a and the fifth test transistor 330e are connected to the third test control signal line SWBR, the gates of the second test transistor 330b and the fourth test transistor 330d are connected to the second test control signal line SWRB; the gate of the third test transistor 330c is connected to the first test control signal line SWG.

[0142] It can be seen from the above settings that by alternately providing turn-on signals to the second test control signal line SWRB and the third test control signal line SWBR, the first test data signal line CTDR and the second test data signal line CTDB can control the blue and red sub-pixels 1 respectively, while the first test control signal line SWG and the third test data signal line CTDG control all green sub-pixels 1, so that the sub-pixels 1 of the same color display the same brightness.

[0143] In an exemplary embodiment, N test units 330 may be disposed between two adjacent connection portions 322 , where N is a natural number greater than or equal to 1.

[0144] Illustratively, one test unit 330 or two test units 330 may be disposed between two adjacent connection portions 322 .

[0145] In an exemplary embodiment, referring to Figures 15 to 21, the test control signal line 331 can include only one, the number of test data signal lines 332 can be equal to the number of test transistors in each test unit 330 (such as 3), each test data signal line 332 is connected to the source of each test transistor in each test unit 330, and the drains of different test transistors are connected to different data lines 11, and the gates of all test transistors in all test units 330 are connected to the test control signal line 331.

[0146] like Figure 15 As shown, the test unit includes a seventh test transistor 330g, an eighth test transistor 330h and a ninth test transistor 330i; at least one test data signal line 332 includes a fourth test data signal line CTDR, a fifth test data signal line CTDB and a sixth test data signal line CTDG; at least one test control signal line 331 includes a fourth test control signal line SWRGB; and a plurality of data lines 11 include a third data line 113, a fourth data line 114 and a fifth data line 115 arranged alternately.

[0147] The drain of the seventh test transistor 330g is connected to the third data line 113, the source of the seventh test transistor 330g is connected to the fourth test data signal line CTDR, and the gate of the seventh test transistor 330g is connected to the fourth test control signal line SWRGB; the drain of the eighth test transistor 330h is connected to the fourth data line 114, the source of the eighth test transistor 330h is connected to the fifth test data signal line CTDB, and the gate of the eighth test transistor 330h is connected to the fourth test control signal line SWRGB; the drain of the ninth test transistor 330i is connected to the fifth data line 115, the source of the ninth test transistor 330i is connected to the sixth test data signal line CTDG, and the gate of the ninth test transistor 330i is connected to the fourth test control signal line SWRGB.

[0148] In an exemplary embodiment, the seventh test transistor 330 g , the eighth test transistor 330 h , and the ninth test transistor 330 i are located in one first opening among the plurality of first openings.

[0149] In this case, refer to Figure 15 The sub-pixels 1 connected to each data line 11 can have the same color (in the figure, R represents a red sub-pixel, G represents a green sub-pixel, and B represents a blue sub-pixel), and the sub-pixels 1 connected to the data lines 11 corresponding to each test data signal line 332 have the same color. Therefore, by continuously inputting the same test signal to the test data signal line 332, the sub-pixels 1 of the same color can display the same brightness (such as displaying a white picture or other monochrome picture as a whole), which is convenient for locating defective sub-pixels.

[0150] Reference Figures 15 to 20, the active layer 111' ( Figure 16 ) are arranged at intervals along the second direction 992 (and can be provided in the same layer as the first active layer 111) and are covered by the gate insulating layer 190; and the gate 112' of each test transistor can be provided in the same layer as the first gate 112, and at the same time, a plurality of connecting portions 322 and a data signal input line 203 are also provided in the layer ( Figure 17 ); and the same layer as the second electrode 122 may be provided with a structure 11a (or regarded as a part of the data line 11) for electrically connecting the drain of the test transistor to the corresponding data line 11 and a structure 332a ( Figure 18 ); and the first source 113 and the first drain 114 are in the same layer, the source 113 'and the drain 114 'of the test transistor may be provided ( Figure 20 ), and the test control signal line 331, the test data signal line 332, the first power bus 321 and the second power bus 323; and through the via 192a ( Figure 19 ), the electrical connection of the corresponding structure can be achieved.

[0151] Reference Figure 21 The display substrate of this embodiment has a total of 3 test data signal lines 332 and 1 test control signal line 331. Each test unit 330 includes 3 test transistors (a seventh test transistor 330g, an eighth test transistor 330h, and a ninth test transistor 330i) for controlling 3 data lines 11 (corresponding to the above 3 columns of sub-pixels 1. In every 3 columns of sub-pixels 1, one column of sub-pixels 1 is green, one column of sub-pixels 1 is red, and one column of sub-pixels 1 is blue).

[0152] In an exemplary embodiment, Figure 22 As shown, in a plane perpendicular to the display substrate, the display substrate may include: a substrate 100, a buffer layer 193 arranged on the substrate 100, a first active layer arranged on the buffer layer 193, a gate insulating layer 190 arranged on the first active layer, a first gate metal layer arranged on the gate insulating layer 190, a first insulating layer 191 arranged on the first gate metal layer, a second gate metal layer arranged on the first insulating layer 191, a second insulating layer 192 arranged on the second gate metal layer, and a first source-drain metal layer arranged on the second insulating layer 192.

[0153] In the display substrate of this embodiment, the buffer layer 193 may not be provided between the substrate 100 and the first active layer.

[0154] In an exemplary embodiment, Figure 22As shown, the test signal line, the first power bus 321 and the second power bus 323 can all be located on the first source and drain metal layer, the connecting portion 322 can be located on the second gate metal layer, and the connecting portion 322 is respectively connected to the first power bus 321 and the second power bus 323 through vias on the second insulating layer 192.

[0155] In an exemplary embodiment, Figure 22 As shown, the connection portion 322 may include a plurality of parallel first connection portions 3221 and second connection portions 3222, the first connection portion 3221 being located on the first gate metal layer, the second connection portion 3222 being located on the second gate metal layer, the first connection portion 3221 being connected to the first power bus 321 and the second power bus 323 respectively through vias passing through the third insulating layer 191 and the fourth insulating layer 192, and the second connection portion 3222 being connected to the first power bus 321 and the second power bus 323 respectively through vias on the fourth insulating layer 192.

[0156] The display substrate of the embodiment of the present disclosure further reduces the metal routing resistance at the line switching position by utilizing the first connection portion 3221 on the first gate metal layer and the second connection portion 3222 on the second gate metal layer to connect in parallel, thereby further alleviating the impact of the increased resistance caused by the layer switching jumper on the voltage drop, which is beneficial to display uniformity and reduces product power consumption.

[0157] In an exemplary embodiment, the test signal line, the first power bus 321 and the second power bus 323 are all located on the first source and drain metal layer, the connecting portion 322 can be located on the first gate metal layer, and the connecting portion 322 is connected to the first power bus 321 and the second power bus 323 respectively through vias passing through the third insulating layer 191 and the fourth insulating layer 192.

[0158] In an exemplary embodiment, within a plane perpendicular to the display substrate, the display substrate may further include a fifth insulating layer and a first planar layer disposed on the first source / drain metal layer, and a second source / drain metal layer disposed on the first planar layer. The test signal line, the first power bus 321, and the second power bus 323 may also be disposed on the second source / drain metal layer, and the connection portion 322 may be disposed on the first source / drain metal layer, the second gate metal layer, or the first gate metal layer, although this disclosure is not limited thereto.

[0159] In an exemplary embodiment, in a plane perpendicular to the display substrate, the display substrate may further include an anode, a pixel definition layer (PDL), a spacer column (PS), an organic light emitting layer, a cathode, and an encapsulation layer formed in the display area 10, as shown in FIG. Figure 23As shown, the encapsulation layer extends to cover the test unit 330. The display substrate of the embodiment of the present disclosure places the test unit 330 inside the encapsulation layer to isolate moisture and prevent the test unit 330 from being easily corroded in a high temperature and high humidity environment, resulting in poor display.

[0160] In an exemplary embodiment, the encapsulation layer may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first encapsulation layer and the third encapsulation layer are made of inorganic materials, and the second encapsulation layer is made of organic materials.

[0161] In an exemplary embodiment, Figure 23 As shown, the distance a between the test unit 330 and the edge of the display area 10 near the test unit 330 is less than or equal to a preset first distance. The preset first distance can be set based on the actual size of the wiring space. The display substrate of the embodiment of the present disclosure places the test unit 330 close to the display area 10 to shorten the distance between the test unit 330 and the display area 10, thereby enhancing the driving capability of the test circuit.

[0162] In an exemplary embodiment, the display substrate further includes an anode, a pixel definition (PDL) layer, a spacer column (PS), an organic light-emitting layer, a cathode, and an encapsulation layer formed in the display area 10. The encapsulation layer may include a stacked first encapsulation layer, a second encapsulation layer, and a third encapsulation layer. The first encapsulation layer and the third encapsulation layer are made of inorganic materials, and the second encapsulation layer is made of organic materials.

[0163] The present disclosure also provides a display device comprising the display substrate of the aforementioned embodiment. The display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system.

[0164] The drawings in this disclosure only relate to the structures involved in this disclosure, and other structures may refer to general designs. In the absence of conflict, the embodiments of this disclosure, that is, the features in the embodiments, may be combined with each other to obtain new embodiments.

[0165] It should be understood by those skilled in the art that the technical solutions of the present disclosure may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present disclosure, and all should be included in the scope of the claims of the present disclosure.

Claims

1. A display substrate, wherein: include: a substrate comprising a display area and a peripheral area located on at least one side of the display area; A plurality of sub-pixels are located in the display area; a plurality of data lines located in the display area and electrically connected to the plurality of sub-pixels, the plurality of data lines being configured to provide data signals to the plurality of sub-pixels; a plurality of power lines located in the display area and electrically connected to the plurality of sub-pixels, the plurality of power lines being configured to provide power signals to the plurality of sub-pixels; at least one test data signal line located in the peripheral area; at least one test control signal line located in the peripheral area; a plurality of test units located in the peripheral area and on a side of the plurality of data lines away from the display area, at least one of the plurality of test units being electrically connected to at least one of the plurality of data lines, the at least one test data signal line, and the at least one test control signal line, and being configured to transmit a signal provided by the at least one test data signal line to the at least one data line and a sub-pixel electrically connected to the at least one data line based on a signal provided by the at least one test control signal line, so as to determine whether the sub-pixel can be illuminated; a first power bus located in the peripheral area and on a side of the plurality of test units away from the display area; a plurality of connecting portions electrically connected to the first power bus and the plurality of power lines, the plurality of connecting portions extending toward the display area along areas between the plurality of test units; a second power bus located between the plurality of test units and the display area, wherein the plurality of connection portions are electrically connected to the first power bus and the second power bus respectively; The first power bus, the second power bus, and the plurality of connection portions define a plurality of first openings arranged in an array, the plurality of test units include a plurality of test transistors, and the orthographic projections of the plurality of test transistors on the substrate are all located in the plurality of first openings; The test control signal line and the test data signal line are arranged between the second power bus and the first power bus. The display substrate includes multiple metal layers in a direction perpendicular to the display substrate. The test control signal line, the test data signal line, the second power bus and the first power bus are located on the same metal layer. The connecting portion and the gates of the multiple test transistors are located on another metal layer. The orthographic projection of the test control signal line on the substrate and the orthographic projection of the test unit on the substrate and the orthographic projection of the connecting portion on the substrate all have overlapping areas; the orthographic projection of the test data signal line on the substrate and the orthographic projection of the test unit on the substrate and the orthographic projection of the connecting portion on the substrate all have overlapping areas.

2. The display substrate according to claim 1, wherein The second power bus includes a plurality of second openings, the test unit includes a plurality of transistors, and drains of the plurality of transistors are located in the plurality of second openings.

3. The display substrate according to claim 1, wherein The test unit includes a first test transistor, a second test transistor and a third test transistor; The at least one test data signal line includes a first test data signal line, a second test data signal line and a third test data signal line; The at least one test control signal line includes a first test control signal line, a second test control signal line and a third test control signal line; The plurality of data lines include first data lines and second data lines that are alternately arranged; The source of the first test transistor and the source of the second test transistor are connected to the first test data signal line and the second test data signal line respectively, the drain of the first test transistor and the drain of the second test transistor are connected to the first data line, and the gate of the first test transistor and the gate of the second test transistor are connected to the third test control signal line and the second test control signal line respectively; A source of the third transistor is connected to the third test data signal line, a drain of the third transistor is connected to the second data line, and a gate of the third transistor is connected to the first test control signal line.

4. The display substrate according to claim 3, wherein: The test unit also includes a fourth test transistor and a fifth test transistor, the drain of the fourth test transistor and the drain of the fifth test transistor are connected to another first data line, the gate of the fourth test transistor and the gate of the fifth test transistor are connected to the second test control signal line and the third test control signal line respectively, and the source of the fourth test transistor and the source of the fifth test transistor are connected to the first test data signal line and the second test data signal line.

5. The display substrate according to claim 4, wherein: The first test transistor, the second test transistor, and the third test transistor are located in one first opening of the plurality of first openings, and the fourth test transistor and the fifth test transistor are located in a first opening adjacent to the one first opening.

6. The display substrate according to claim 4, wherein: The first test transistor, the second test transistor, the fourth test transistor, and the fifth test transistor are located in one first opening among the plurality of first openings, and the third test transistor is located in a first opening adjacent to the one first opening.

7. The display substrate according to claim 3, wherein: The test unit further includes a fourth test transistor, a fifth test transistor, and a sixth test transistor, wherein the drain of the fourth test transistor and the drain of the fifth test transistor are connected to another first data line, the gate of the fourth test transistor and the gate of the fifth test transistor are connected to the second test control signal line and the third test control signal line, respectively, and the source of the fourth test transistor and the source of the fifth test transistor are connected to the first test data signal line and the second test data signal line; A source of the sixth test transistor is connected to the third test data signal line, a drain of the sixth test transistor is connected to another second data line, and a gate of the sixth test transistor is connected to the first test control signal line.

8. The display substrate according to claim 7, wherein: The first test transistor, the second test transistor, and the third test transistor are located in one first opening of the plurality of first openings, and the fourth test transistor, the fifth test transistor, and the sixth test transistor are located in first openings adjacent to the one first opening.

9. The display substrate according to claim 1, wherein: The test unit includes a seventh test transistor, an eighth test transistor and a ninth test transistor; The at least one test data signal line includes a fourth test data signal line, a fifth test data signal line and a sixth test data signal line; The at least one test control signal line includes a fourth test control signal line; The plurality of data lines include a third data line, a fourth data line and a fifth data line that are alternately arranged; The drain of the seventh test transistor is connected to the third data line, the source of the seventh test transistor is connected to the fourth test data signal line, and the gate of the seventh test transistor is connected to the fourth test control signal line; The drain of the eighth test transistor is connected to the fourth data line, the source of the eighth test transistor is connected to the fifth test data signal line, and the gate of the eighth test transistor is connected to the fourth test control signal line; A drain of the ninth test transistor is connected to the fifth data line, a source of the ninth test transistor is connected to the sixth test data signal line; and a gate of the ninth test transistor is connected to the fourth test control signal line.

10. The display substrate according to claim 9, wherein: The seventh test transistor, the eighth test transistor, and the ninth test transistor are located in one first opening among the plurality of first openings.

11. The display substrate according to claim 1, wherein: The at least one test control signal line and the at least one test data signal line are arranged in parallel along an extending direction of the connecting portion and are located between the plurality of test units and the first power bus.

12. The display substrate according to claim 1, wherein At least one of the plurality of connection portions further includes a third opening, an orthographic projection of the third opening on the substrate overlapping an orthographic projection of at least one of the at least one test data signal line and the at least one test control signal line on the substrate.

13. The display substrate according to any one of claims 1 to 12, wherein: In a plane perpendicular to the display substrate, the display substrate includes a buffer layer, a first active layer, a gate insulating layer, a first gate metal layer, a first insulating layer, a second gate metal layer, a second insulating layer and a first source-drain metal layer stacked on the base; The test control signal line, the test data signal line, the first power bus and the power line are all located on the first source-drain metal layer; The connecting portion is located on the second gate metal layer, and the connecting portion is connected to the first power bus and the multiple power lines respectively through vias on the second insulating layer; or, the connecting portion is located on the first gate metal layer, and the connecting portion is connected to the first power bus and the multiple power lines respectively through vias passing through the first insulating layer and the second insulating layer.

14. The display substrate according to any one of claims 1 to 12, wherein: In a plane perpendicular to the display substrate, the display substrate includes a buffer layer, a first active layer, a gate insulating layer, a first gate metal layer, a first insulating layer, a second gate metal layer, a second insulating layer and a first source-drain metal layer stacked on the base; The test control signal line, the test data signal line, the first power bus and the power line are all located on the first source-drain metal layer; The connecting portion includes a first connecting portion and a second connecting portion, the second connecting portion is located on the second gate metal layer, and the second connecting portion is connected to the first power bus and the power line respectively through vias on the second insulating layer; the first connecting portion is located on the first gate metal layer, and the first connecting portion is connected to the first power bus and the power line respectively through vias passing through the first insulating layer and the second insulating layer.

15. The display substrate according to any one of claims 1 to 14, further comprising a plurality of data signal input lines located in the peripheral area, the plurality of data signal input lines being located on a side of the plurality of test units away from the display area, at least one of the plurality of data signal input lines being electrically connected to the at least one test unit.

16. A display device comprising the display substrate according to any one of claims 1 to 15.

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