Instruction fetch unit used to predict the target of subroutine return instructions.

Abstract

This application discloses an instruction fetch unit for predicting the target of a subroutine return instruction. The instruction fetch unit is configured to, in response to detecting a subroutine call and link instruction, calculate the predicted target address for the corresponding subroutine return instruction and store it in the prediction stack, and, if certain conditions are met, also store the predicted target instruction bundle in the prediction stack. The instruction fetch unit is further configured to, in response to detecting a subroutine return instruction, use the predicted target address in the prediction stack to determine the address of the next instruction bundle to be fetched, and, if certain conditions are met, make any validly predicted target instruction bundle in the prediction stack the next bundle to be decoded.

Description

[0001] This application is a divisional application of the application filed on September 26, 2016, with application number 201610853165.2 and invention title "Instruction Fetching Unit for Predicting the Target of Subroutine Return Instruction". background

[0002] Programs that execute on a processor include various types of instructions, such as subroutine calls and linking instructions.

[0003] Subroutine calls and link instructions are instructions that jump to the subroutine (a piece of code that performs a specific task) at the destination address and return to the calling point after the subroutine has been executed. Specifically, the last instruction of a subroutine is a return instruction that guides the processor back to the calling point and begins execution of instructions. Therefore, subroutines can only be called by link instructions that store the return to the main program.

[0004] If the processor's instruction fetch unit takes into account the relationship between call and link instructions and their corresponding subroutine return instructions, it can fetch instructions from the program more efficiently.

[0005] The embodiments described below are provided as examples only and are not intended to limit the implementation of any or all of the known shortcomings of processor instruction fetch units.

[0006] Overview

[0007] This overview is provided in a simplified form to introduce a series of concepts, which will be further described in detail below. This overview is not intended to identify key or essential features of the claimed subject matter, nor is it intended to assist in determining the scope of the claimed subject matter.

[0008] An instruction fetch unit is provided for efficiently fetching subroutine call and link instructions, as well as corresponding subroutine return instructions. The instruction fetch unit is configured to, in response to detecting a subroutine call and link instruction, calculate the predicted target address for the corresponding subroutine return instruction and store it in a prediction stack, and, if certain conditions are met, also store the predicted target instruction bundle in the prediction stack. The instruction fetch unit is further configured to, in response to detecting a subroutine return instruction, use the predicted target address in the prediction stack to determine the address of the next instruction bundle to be fetched, and, if certain conditions are met, make the predicted target instruction bundle in the prediction stack the next instruction bundle to be decoded.

[0009] A first aspect provides a multi-level instruction fetch unit for use in a processor, the multi-level instruction fetch unit comprising: a return prediction stack; and partial decoding logic in communication with the return prediction stack, the partial decoding logic being configured periodically to: receive a set of one or more instructions for execution; decode at least partially the received set of one or more instructions to determine whether the received set of one or more instructions includes subroutine call and link instructions or subroutine return instructions; in response to determining that the received set of one or more instructions includes subroutine call and link instructions, store one or more instructions of a prediction target group for the corresponding subroutine return instruction in the return prediction stack; and in response to determining that the received set of one or more instructions includes a subroutine return instruction, make the one or more instructions of the prediction target group stored in the return prediction stack become a set of one or more instructions received in the next cycle.

[0010] The second aspect provides a method for fetching instructions in a multi-level instruction fetch unit of a processor, the method comprising, in each cycle: receiving a set of one or more instructions for execution; at least partially decoding the received set of one or more instructions to determine whether the received set of one or more instructions includes subroutine call and link instructions or subroutine return instructions; in response to determining that the received set of one or more instructions includes subroutine call and link instructions, storing one or more instructions of a prediction target group for the corresponding subroutine return instruction in a return prediction stack; and in response to determining that the received set of one or more instructions includes a subroutine return instruction, making the one or more instructions of the prediction target group stored in the return prediction stack become a set of one or more instructions received in the next cycle.

[0011] The third aspect provides a computer-readable storage medium on which computer-readable program code is encoded, defining a processor that includes the instruction fetch unit of the first aspect.

[0012] The fourth aspect provides a computer-readable storage medium on which computer-readable program code is encoded, defining a processor configured to implement the methods of the second aspect.

[0013] This application also provides the following aspects:

[0014] 1) A multi-level instruction fetch unit (602) for use in a processor (100), the multi-level instruction fetch unit (602) comprising:

[0015] Return the prediction stack (604); and

[0016] A portion of the decoding logic (616), which communicates with the return prediction stack (604), is configured periodically as follows:

[0017] Receives a set of one or more instructions for execution;

[0018] At least partially decode a received set of one or more instructions to determine whether the received set of one or more instructions includes subroutine call and link instructions or subroutine return instructions;

[0019] In response to determining that the received set of one or more instructions includes subroutine call and link instructions, one or more instructions of the prediction target set for the corresponding subroutine return instruction are stored in the return prediction stack (604); and

[0020] In response to determining that the received set of one or more instructions includes a subroutine return instruction, one or more instructions of the prediction target set stored in the return prediction stack (604) become the received set of one or more instructions in the next cycle.

[0021] 2) According to the instruction fetching unit (602) described in 1), wherein the partial decoding logic (616) is further configured to predict the target address of the corresponding subroutine return instruction in response to determining that the received set of one or more instructions includes subroutine call and link instructions, and to store the predicted target address in the return prediction stack (604).

[0022] 3) According to the instruction fetch unit (602) described in 2), wherein the partial decoding logic (616) is configured to store one or more instructions of the prediction target group regarding the corresponding subroutine return instruction in the return prediction stack (604) in such a way as follows:

[0023] Determine whether one or more instructions of the predicted target group are a group of one or more instructions that immediately follow the received group of one or more instructions; and

[0024] In response to determining that one or more instructions of the predicted target group are a group of one or more instructions following the received group of one or more instructions, the received group of one or more instructions in the next cycle is stored in the return prediction stack (604).

[0025] 4) According to the instruction fetch unit (602) described in 3), wherein the partial decoding logic (616) is further configured to determine whether the cache level (608) of the instruction fetch unit (602) is fetching a set of one or more instructions in the current cycle; and if it is determined that the cache level (608) of the instruction fetch unit (602) is fetching a set of one or more instructions in the current cycle, then the partial decoding logic (616) will cause the set of one or more instructions received in the next cycle to be stored only in the return prediction stack (604).

[0026] 5) According to the instruction fetching unit (602) of 3) or 4), wherein the partial decoding logic (616) is configured to determine, based on the format of the received set of one or more instructions, whether one or more instructions of the prediction target group are a set of one or more instructions that immediately follow the received set of one or more instructions.

[0027] 6) The instruction fetching unit (602) according to 3) or 4), wherein the partial decoding logic (616) is configured to determine, based on the predicted target address, whether one or more instructions of the predicted target group are one or more instructions that immediately follow the received one or more instructions.

[0028] 7) The instruction fetching unit (602) according to 3) or 4) further includes a flag (618); and wherein the partial decoding logic (616) is configured to store a set of one or more instructions received in the next cycle in the return prediction stack (604) by setting the flag (618).

[0029] 8) According to the instruction fetching unit (602) of 7), wherein the partial decoding logic (616) is further configured to determine whether the flag (618) is set, and in response to determining that the flag (618) is set, to store the received set of one or more instructions in the return prediction stack (604).

[0030] 9) The instruction fetch unit (602) according to 3) or 4), wherein the partial decoding logic (616) is configured to further store one or more instructions of the prediction target group regarding the corresponding subroutine return instruction in the return prediction stack (604) in such a way as follows:

[0031] Determine whether one or more instructions of the predicted target group are the received group of one or more instructions; and

[0032] In response to determining that one or more instructions of the predicted target group are the received set of one or more instructions, the received set of one or more instructions is stored in the return prediction stack (604).

[0033] 10) The instruction fetch unit (602) according to any one of 1) to 4) further includes an instruction storage module (619); and wherein the partial decoding logic (616) is configured to store one or more instructions of the prediction target group in the instruction storage module (619) such that one or more instructions of the prediction target group stored in the return prediction stack (604) become one or more instructions received in the next cycle.

[0034] 11) The instruction fetching unit (602) according to 10) wherein the partial decoding logic (616) is further configured to determine whether the instruction storage module (619) includes a valid set of one or more instructions, and in response to determining that the instruction storage module (619) includes a valid set of one or more instructions, to use the valid set of one or more instructions as the received set of one or more instructions.

[0035] 12) The instruction fetching unit (602) according to any one of 2) to 4), wherein the partial decoding logic (616) is configured to cause one or more instructions of the prediction target group stored in the return prediction stack (604) to become one or more instructions of the receiving group in the next cycle:

[0036] Determine whether the returned prediction stack (604) includes one or more instructions for a valid prediction target group; and

[0037] In response to determining that the return prediction stack (604) includes one or more instructions of a valid prediction target group, the one or more instructions of the valid prediction target group in the return prediction stack (604) become one or more instructions of a received group in the next cycle.

[0038] 13) The instruction fetching unit (602) according to 12) further includes a next bundle logic (620), the next bundle logic being configured to generate an address for the next set of one or more instructions to be fetched based on the target address of the prediction stored in the return prediction stack in response to the partial decoding logic determining that the set of one or more instructions includes a subroutine return instruction.

[0039] 14) According to the instruction fetch unit (602) described in 13), wherein the next beam logic (620) is configured as follows:

[0040] In response to the partial decoding logic (616) determining that the return prediction stack (604) includes one or more instructions of a valid prediction target group, the address of the next set of instructions to be extracted is generated as an address offset from the target address of the prediction stored in the return prediction stack; and

[0041] In response to the partial decoding logic (616) determining that the return prediction stack (604) does not include one or more instructions of a valid prediction target group, an address for the next group of one or more instructions to be extracted is generated as the target address of the prediction stored in the return prediction stack.

[0042] 15) The instruction fetch unit (602) according to any one of 1) to 4) further includes a return prediction stack controller (1702) configured to monitor updates to one or more sets of instructions in the instruction cache to determine whether the updates affect one or more instructions of one or more prediction target sets stored in the return prediction stack (604); and to invalidate one or more instructions of the one or more prediction sets stored in the return prediction stack (604) in response to determining that the updates affect one or more instructions of one or more prediction target sets stored in the return prediction stack (604).

[0043] 16) The instruction fetching unit (602) according to any one of 1) to 4), wherein the received set of one or more instructions is an instruction bundle comprising two or more instructions.

[0044] 17) A method (800) for retrieving instructions in a multi-level instruction fetch unit of a processor, the method comprising, in a cycle:

[0045] Receives a set of one or more instructions for execution;

[0046] At least partially decode a received set of one or more instructions to determine whether the received set of one or more instructions includes subroutine call and link instructions or subroutine return instructions;

[0047] In response to determining that the received set of one or more instructions includes subroutine call and link instructions, one or more instructions of the prediction target set for the corresponding subroutine return instruction are stored in the return prediction stack (802); and

[0048] In response to determining that the received set of one or more instructions includes a subroutine return instruction, one or more instructions of the prediction target group stored in the return prediction stack become the received set of one or more instructions in the next cycle (804).

[0049] 18) The method (800) according to 17) wherein making one or more instructions of the prediction target group stored in the return prediction stack a group of one or more instructions to be received in the next cycle includes storing one or more instructions of the prediction target group in an instruction storage module.

[0050] Preferred features may be appropriately combined, as will be apparent to those skilled in the art, and may be combined with any aspect of the invention. Brief description of the attached diagram

[0051] Embodiments of the present invention will be described by way of example with reference to the following drawings, in which:

[0052] Figure 1This is a block diagram of an exemplary out-of-order processor;

[0053] Figure 2 This is a schematic diagram of an example program that includes subroutine calls and linking instructions;

[0054] Figure 3 It is used to predict the target address of the subroutine return instruction. Figure 1 A block diagram of an example instruction fetch unit;

[0055] Figure 4 yes Figure 3 The example returns a diagram of the prediction stack;

[0056] Figure 5 The diagram shows the process during program execution. Figure 3 Timing diagrams of the states of the instruction fetch unit over many cycles;

[0057] Figure 6 This is a block diagram of an example instruction fetch unit used to predict the target address and target instruction bundle of a subroutine return instruction;

[0058] Figure 7 yes Figure 6 A diagram showing the modified return prediction stack;

[0059] Figure 8 This is a flowchart of an example method for predicting the target address and target instruction bundle of a subroutine return instruction;

[0060] Figure 9 It is used to push data into Figure 6 The flowchart of the modified return prediction stack example method;

[0061] Figure 10 Is in use Figure 9 The method is Figure 6 Timing diagram of the modified instruction fetch unit's state over many cycles;

[0062] Figure 11 Is in use Figure 9 The method is Figure 6 Timing diagram of the modified instruction fetch unit's state over many cycles;

[0063] Figure 12 It is used from Figure 6 A flowchart of an example method that modifies and pops data from the prediction stack;

[0064] Figure 13 Is in use Figure 12 The method is Figure 6 Timing diagram of the modified instruction fetch unit's state over many cycles;

[0065] Figure 14 Is in use Figure 12 The method is Figure 6 Timing diagram of the modified instruction fetch unit's state over many cycles;

[0066] Figure 15 This is a flowchart of an example method for determining the address of the next instruction bundle to be extracted;

[0067] Figure 16 yes Figure 6 Timing diagrams of the modified instruction fetch unit's states over many cycles; and

[0068] Figure 17 yes Figure 6 A block diagram of an example FS level instruction fetch unit with an RPS controller;

[0069] Common reference figures are used throughout the accompanying drawings to denote similar features. Detailed description

[0070] Embodiments of the present invention are described below by way of example only. These examples represent the best methods currently known to the applicant for practicing the invention, but they are not the only methods by which the invention can be implemented. The description illustrates the function of the examples and the order of steps for constructing and operating the examples. However, the same or equivalent function and order can be accomplished by different examples.

[0071] This paper describes a method and a multi-level instruction fetch unit for predicting and storing target instructions for subroutine return instructions, so as not to waste cycles fetching target instructions after a subroutine return instruction is detected. The instruction fetch unit is configured to monitor subroutine call and link instructions in the fetched instructions. Once a subroutine call or link instruction is detected, the predicted target address for the corresponding subroutine return instruction is stored in a buffer, and in some cases, in the next cycle, the immediately following instruction bundle is stored in the associated buffer as the predicted target instruction bundle for the corresponding subroutine return instruction. When the instruction fetch unit subsequently detects a corresponding subroutine return instruction for the subroutine call or link instruction, the predicted target address and any predicted target instruction bundle are retrieved from the buffer so that the predicted target instruction bundle can be processed in the next cycle and the predicted target address can be used to fetch the next instruction bundle for execution.

[0072] First refer to Figure 1 The diagram illustrates an example out-of-order processor 100, in which the methods described herein and the instruction fetch unit can be implemented. Although Figure 1The example shows an out-of-order processor, but this method can also be implemented in processors that do not process instructions out of order (i.e., in ordered processors). In this example, processor 100 is a single-threaded processor; however, the method is also applicable to multi-threaded processors.

[0073] Processor 100 includes an instruction fetch unit 102, a decoding and renaming unit 104, a reordering buffer 106, a commit unit 108, and one or more execution units 110. However, it will be apparent to those skilled in the art that one or more of these units can be combined. For example, in other processors, the decoding and renaming unit 104 and one or more execution units 110 can be combined to form a single unit.

[0074] Instruction fetch unit 102 is configured to fetch instructions from a program (in program order) as indicated by the program counter (PC). Some instruction fetch units 102 are configured to fetch more than one instruction in a cycle, while others are configured to fetch only a single instruction in a cycle. When multiple instructions are fetched in a cycle, the instructions are configured to form an instruction bundle. The term "cycle" as used herein means a processing cycle of processor 100. In some cases, there is one processing cycle per clock cycle. However, in other cases, processing cycles may occur more or less frequently than per clock cycle.

[0075] The instruction fetch unit discussed herein is described as fetching a bundle of instructions (i.e., more than one instruction) per cycle; however, it will be apparent to those skilled in the art that the methods and principles described herein can also be applied to instruction fetch units that fetch only a single instruction per cycle. The term "a set of one or more instructions" as used herein includes both a single instruction and a bundle of instructions comprising two or more instructions.

[0076] Once the instruction bundle is extracted, the instructions contained therein are provided to the decoding and renaming unit 104, which is configured to interpret the instructions and perform register renaming. Specifically, each instruction may include: a register write operation; one or more register read operations; and / or arithmetic or logical operations. Register write operations write to a destination register, and register read operations read from a source register. During register renaming, each structure register mentioned in the instructions (e.g., each source and destination register) is replaced (or renamed) with a physical register.

[0077] After an instruction passes through the decoding and renaming unit 104, it is inserted into the reordering buffer 106 (ROB) and scheduled to the execution unit 110 for execution. The execution unit 110 to which an instruction is scheduled may be based on the type of instruction.

[0078] Reorder buffer 106 is a buffer that allows instructions to be executed out of order but submitted in an ordered manner. Reorder buffer 106 holds instructions inserted therein in program order, but instructions within ROB 106 can be executed out of order by execution unit 110. Instructions output from reorder buffer 106 are provided to submission unit 108, which submits the results of the instructions to registers / memory.

[0079] Each execution unit 110 is responsible for executing instructions and can be configured to execute specific types of instructions. Execution unit 110 may include one or more of an access unit, an integer unit, a floating-point unit (FPU), a digital signal processing (DSP) / single instruction multiple data (SIMD) unit, or a multiply-accumulate (MAC) unit. The access unit reads data into the L1 cache and other memory, and writes data from the L1 cache and other memory. The integer unit executes integer instructions, the FPU executes floating-point instructions, the DSP / SIMD unit has multiple processing elements that perform the same operation on multiple data points simultaneously, and the MAC unit calculates the product of two numbers and adds the product to an accumulator.

[0080] Processor 100 may also include, in addition to Figure 1 Other functional elements shown (e.g., cache, memory, register file, etc.). For example, processor 100 may also include a branch predictor configured to predict which direction the program flow will take given that an instruction (such as a branch instruction) is known to cause a possible change in flow. Branch prediction is useful because it allows instructions to be speculatively executed by processor 100 before the result of the branch instruction is known. When the branch predictor accurately predicts the program flow, this improves the performance of processor 100. However, if the branch predictor does not correctly predict the branch direction, misprediction will occur and needs to be corrected before the program can continue. To correct the misprediction, the speculative instruction sent to ROB 106 is discarded, and instruction fetch unit 102 begins fetching instructions from the correct program branch.

[0081] It should be recognized that other processors may not include Figure 1 All functional elements shown (i.e., can be omitted) Figure 1 (one or more of the functional elements shown), and in some examples, may include Figure 1 Additional functional elements not shown.

[0082] Programs that execute on a processor (e.g., processor 100) may include various types of instructions, such as subroutine calls and linking instructions.

[0083] Subroutine call and link instructions (which may also be referred to herein as call and link instructions; call instructions; branch and link instructions; or procedure call and link instructions) are instructions that jump to a subroutine (a piece of code that performs a specific task) at the destination address of the call and return to the calling point after the subroutine has been executed. Specifically, the last instruction of a subroutine is the subroutine return instruction, which directs the processor back to the calling point and begins execution of instructions. Therefore, a subroutine can only be called by storing the link instructions that return to the calling point.

[0084] The address of the instruction following the subroutine return instruction that the processor (e.g., processor 100) begins executing is referred to herein as the target address for the subroutine return instruction, but it may also be referred to as the return address. The target address of the subroutine return instruction is typically the first instruction in the program following the call and link instructions to be executed after the subroutine. For certain types of subroutine call and link instructions, the target address of the corresponding subroutine return instruction is the address of the instruction immediately following the subroutine call and link instruction in the program. Such subroutine call and link instructions are called compact subroutine call and link instructions. For other types of subroutine call and link instructions, the target address of the corresponding subroutine return instruction may be the address of another instruction following the subroutine call and link instruction. Specifically, some types of subroutine call and link instructions may always be followed by a slot instruction in the program. A slot instruction is an instruction that follows a branch instruction but is executed before that branch instruction. For these types of call and link instructions, the target address of the corresponding subroutine return instruction is the instruction immediately following the slot instruction.

[0085] Now for reference Figure 2 The diagram illustrates the main program 202, which includes two subroutine call and link instructions 204 and 206 that call the same subroutine 208. Execution of subroutine call and link instruction 204 or 206 causes (i) the target address for the corresponding subroutine return instruction to be stored in the return register; and (ii) a jump to the first instruction 210 of subroutine 208. The last instruction of the subroutine (subroutine return instruction 212) causes a jump back to the target instruction 214 or 216 at the target address (e.g., $31) specified by the return register.

[0086] The first subroutine call and link instruction 204 is a compact call and link instruction, and therefore the target instruction 214 for the corresponding subroutine return instruction is the instruction immediately following the first subroutine call and link instruction 204 in the main program 202. Therefore, the target address for the corresponding subroutine return instruction is the address of the target instruction 214 (e.g., address 4 of the main program 202). Conversely, the second subroutine call and link instruction 206 is a non-compact call and link instruction, and therefore is followed by a delay slot instruction 218. Therefore, the target instruction 216 for the corresponding subroutine return instruction is the instruction immediately following the delay slot instruction 218 in the main program 202. Therefore, the target address for the corresponding subroutine return instruction is the address of the target instruction 216 (e.g., address 11 of the main program 202).

[0087] Subroutine call and link instructions include, but are not limited to, those shown in Table 1. It will be apparent to those skilled in the art that these are merely examples and that the methods and techniques described herein can be applied to other subroutine call and link instructions.

[0088] Table 1

[0089]

[0090] Examples of subroutine return instructions are shown in Table 2. It will be apparent to those skilled in the art that these are merely examples and that the methods and techniques described herein can be used for other subroutine return instructions.

[0091] Table 2

[0092]

[0093]

[0094] As described above, the instruction fetch unit 102 of processor 100 fetches instructions from the program (in program order), as indicated by the program counter (PC). Instructions in a program are typically executed sequentially, unless there are control transfer instructions (CTIs) (instructions that change the direction of the program), such as branch instructions or jump instructions. When instructions are executed sequentially, the address of the next instruction can be easily calculated as the address of the current instruction plus a fixed offset (e.g., the instruction length). However, when executing control transfer instructions, the address of the next instruction often requires some time to calculate (e.g., one or more registers may need to be read), which can cause delays in fetching the next instruction for execution. To mitigate this problem, a branch predictor has been designed to predict the address of the instruction following a branch instruction.

[0095] As mentioned above, when the branch predictor accurately predicts the program flow, this will improve the performance of the processor 100. However, if the branch predictor does not correctly predict the branch direction, then mispredictions will occur that need to be corrected before the program can continue.

[0096] Since the target address of a subroutine return instruction can usually be determined from the addresses of the corresponding subroutine call and link instructions, it can be predicted by detecting subroutine call and link instructions and storing their target addresses in the return prediction stack (RPS). Specifically, when a call or link instruction is detected, the predicted target address of the corresponding subroutine return instruction is pushed onto the RPS, and then popped from the RPS when the subroutine return instruction is detected.

[0097] Now for reference Figure 3 The illustration shows an example instruction fetch unit 302, which can be used as... Figure 1 The instruction fetch unit 102 includes a return prediction stack 304 for storing the predicted target address of the subroutine return instruction.

[0098] The instruction fetch unit 302 is implemented as a three-stage pipeline – fetch (FE) stage 306, cache (FC) stage 308, and select (FS) stage 310.

[0099] During FE stage 306, program counter selector logic 312 sets the program counter (PC) to the address of the next instruction bundle to be fetched and generates and outputs a PC-based index that will be used by FC stage 308. In some cases, the index is a subset of the PC bits. Which PC bits form part of the index can be based on the size of the instruction cache. When the program is executing sequentially, program counter selector logic 312 increments the PC to the address of the next instruction bundle in the program (e.g., program counter selector logic 312 can increment the PC by an offset equal to the size of the instruction bundle). However, if a CTI is already present, program counter selector logic 312 can receive another address from another module (e.g., RPS 304) indicating that the instruction bundle at that other address should be fetched. Program counter selection logic 312 can be considered a multiplexer that selects the address of the program counter based on one or more inputs received from one or more other modules or logic blocks (e.g., RPS 304).

[0100] During FC stage 308, the index generated by FE stage 306 is used to fetch the next instruction bundle to be executed from instruction cache 314. For an index generated by program counter selection logic 312, if a match is found in instruction cache 314, the instruction bundle with the matching index is output to FS stage 310.

[0101] During FS level 310, the instruction bundle received from FC level 308 is decoded by partial decoding logic 316 to identify subroutine call and link instructions, as well as subroutine return instructions. If partial decoding logic 316 identifies a subroutine call or link instruction in the received instruction bundle, it predicts the target address of the corresponding subroutine return instruction based on the address and instruction type of the subroutine call or link instruction and pushes it onto RPS 304. If partial decoding logic 316 identifies a subroutine return instruction, the predicted target address most recently added to RPS 304 is popped and sent to FE level 306.

[0102] Now for reference Figure 4 It shows Figure 3 Example structure of RPS 304.

[0103] Stacks are typically used to provide a region for temporary storage and are implemented as Last-In-First-Out (LIFO) storage resources (which may optionally involve Last-In-First-Out (FILO), meaning that data is removed from the stack strictly in the reverse order in which it was added. A stack can be thought of growing or shrinking from its starting point; however, in either case, the top of the stack, which is the most recently added element, can be identified by a top pointer.

[0104] For the purposes described below, the stack, and in particular the Return Predicted Stack (RPS), is assumed to grow such that the stack pointer increases when data is pushed onto the stack and decreases when data is popped from the stack. However, it will be understood that the method described herein also applies if the stack and / or RPS are assumed to decrease (where the stack pointer decreases when data is pushed onto the stack and increases when data is popped from the stack).

[0105] exist Figure 4 In the example, RPS 304 is a LIFO buffer with a top pointer 402 that points to the most recently created entry on the stack. Each entry includes valid data 404 and destination address data 406. Valid data 404 indicates whether the destination address data is valid; and destination address data 406 is used to store the predicted destination address for a subroutine return instruction.

[0106] When partial decoding logic 316 detects subroutine call and link instructions, it predicts the target address of the corresponding subroutine return instruction based on the address and type of the call and link instructions. For example, partial decoding logic 316 can predict the target address of a subroutine return instruction corresponding to a compact subroutine call and link instruction as the address of the instruction immediately following the subroutine call and link instructions; and partial decoding logic 316 can predict the target address of a subroutine return instruction corresponding to a non-compact subroutine call and link instruction as the address of the instruction immediately following the delay slot instruction (i.e., the address of the second instruction immediately following the subroutine call and link instructions).

[0107] Once the target address of the corresponding subroutine return instruction has been predicted, it is pushed onto RPS 304. This may involve adjusting (e.g., incrementing) the top pointer 402 to the next free entry or slot of RPS 304, storing the predicted target address as target address data 406 of the entry or slot pointed to by the top pointer, and setting valid data 404 to indicate that the corresponding target address data 406 is valid.

[0108] When partial decoding logic 316 detects a subroutine return instruction, if the entry in the RPS pointed to by the top pointer has valid target address data 406 (e.g., valid data 404 indicates that target address data 406 is valid), then the predicted target address is popped from RPS 304. This may involve outputting the predicted target address, clearing valid data 404, and adjusting (e.g., decrementing) the top pointer 402 to point to the next valid entry or slot in RPS 304.

[0109] Now for reference Figure 5 It shows how to pass Figure 3 This is an example of how the instruction fetch unit 302 fetches instructions from the example program. Specifically, Figure 5 This shows which instruction bundle the output of each stage of instruction fetch unit 302 relates to in a given cycle. For example, in cycle A, the output of FE stage 306 (e.g., index / PC) relates to instruction bundle 1.

[0110] exist Figure 5 In the example shown, in cycle A, FE stage 306 sets the PC to the address of instruction bundle 1. In cycle B, FE stage 306 sets the PC to the address of the next instruction bundle (e.g., instruction bundle 2) and FC stage 308 fetches instruction bundle 1. In cycle C, FE stage 306 sets the PC to the address of the next instruction bundle (e.g., instruction bundle 3), FC stage 308 fetches instruction bundle 2, and FS stage 310 decodes instruction bundle 1. Therefore, in cycles A, B, and C, instructions are fetched and decoded sequentially.

[0111] However, in cycle D, FS stage 310 detects a subroutine call and link instruction (e.g., JAL) that indicates a change in the direction of the program. Specifically, it indicates that the next instruction bundle to be executed is not the one immediately following the current instruction bundle (e.g., instruction bundle 3). Therefore, FS stage 310 informs FE stage 306 of the target address of the subroutine call and link instruction, which causes FE stage 306 to set the PC to the target address of the call and link instruction (e.g., the address of instruction bundle 20). FS stage 310 also predicts the target address for the corresponding subroutine return address (in this case, the address of instruction bundle 3) and stores the predicted target address in RPS 304.

[0112] In cycle D, FC stage 308 has fetched instruction bundle 3, but instruction bundle 3 is no longer the next instruction bundle to be executed. Therefore, in the following cycle (e.g., cycle E), instruction bundle 3 is discarded by FS stage 310 and FS stage 310 does not produce any useful output. This is called CTI bubble.

[0113] The instruction fetch unit then continues to fetch instructions in program order (e.g., cycle F).

[0114] In cycle G, FS stage 310 detects a subroutine return instruction (e.g., JR$31) that indicates a change in the direction of the program. Specifically, it indicates that the next instruction bundle to be executed is not the one immediately following the current instruction bundle (e.g., instruction bundle 22). FS stage 310 then pops the most recently added valid target address from RPS (e.g., the target address generated and stored in cycle D) and provides that target address (in this case, the address of instruction bundle 3) to FE stage 306. This causes FE stage 306 to set the PC to the target address (i.e., the address of instruction bundle 3).

[0115] In cycle G, FC stage 308 has fetched instruction bundle 22, but instruction bundle 22 is no longer the next instruction bundle to be executed. Therefore, in the following cycle (e.g., cycle H), instruction bundle 22 is discarded by FS stage 310 and FS stage 310 does not produce any useful output. This is called CTI bubble – latency caused by control transfer instructions.

[0116] Only during period I, FS stage 310 receives and processes instruction bundle 3.

[0117] from Figure 5As can be seen, the instruction bundle immediately following the instruction bundle containing subroutine call and link instructions (e.g., instruction bundle 3) is extracted in FC stage 308 of cycle D, and again in FC stage 308 of cycle H after the subroutine instruction is identified. The inventors have recognized that, in some cases, if the instruction bundle immediately following the instruction bundle including subroutine call and link instructions is stored, then the cycle does not need to be wasted on re-retrieving the already extracted instruction bundle. Specifically, instead of cycle H being an empty cycle for FS stage 310, the stored instruction bundle can be fed to FS stage 310 after the subroutine return address has been detected, which eliminates the CTI bubble following the subroutine return instruction.

[0118] Figure 6-16 The improved instruction fetch unit will be described, which, in addition to storing the predicted target address for the subroutine return instruction, in some cases also stores the predicted target instruction bundle for the subroutine return instruction. The "target instruction bundle" for the subroutine return instruction is an instruction bundle that includes the target instructions for the subroutine instruction. As mentioned above, the target instructions are the instructions pointed to by the target address. Accordingly, the predicted target instruction bundle for the subroutine return instruction includes the instructions at the predicted target address.

[0119] Now for reference Figure 6 The illustration shows an example of a modified instruction fetch unit 602, which can be used as... Figure 1 The processor 100 has an instruction fetch unit 102. The modified instruction fetch unit 602 has an RPS 604 for storing modifications to the target instruction bundle predicted for a subroutine return instruction. As... Figure 3 The instruction fetch unit 302, and the modified instruction fetch unit 602 implement a three-stage pipeline—fetch (FE) stage 606, cache (FC) stage 608, and select (FS) stage 610. The FE stage 606 and FC stage 608 are typically configured with… Figure 3 The instruction fetch unit 302 operates in the same manner as the FE stage 306 and FC stage 308.

[0120] Specifically, during FE stage 606, program counter selector logic 612 sets the program counter (PC) to the address of the next instruction bundle to be fetched and generates and outputs an index based on it for use by FC stage 608 to fetch the instruction bundle. While the program is being executed sequentially, program counter selector logic 612 increments the PC to the address of the next instruction bundle in the program. However, if a CTI instruction (indicating a change in direction) has been detected, FS stage 610 can provide a replacement address as the next PC. For example, as described in more detail below, when FS stage 610 detects a subroutine return instruction and a valid target address is stored in the modified RPS 604, FS stage 610 can provide a new address to program counter selector logic 612 as the next PC based on the target address. As described above, program counter selector logic 612 can be considered a multiplexer that selects the address for the program counter based on one or more inputs received from one or more other modules or logic blocks (e.g., RPS 604).

[0121] During FC level 608, the index generated by FE level 606 is used to fetch the instruction bundle at the address indicated by the PC. Specifically, during FC level 608, the index is used to search instruction cache 614. If a match is found in instruction cache 614 for an index, the instruction bundle associated with that index is output to FS level 610.

[0122] During FS level 610, modified partial decoding logic 616 receives the instruction bundle output from FC level 608 and partially decodes the instructions contained therein to identify subroutine call and link instructions and subroutine return instructions. In some cases, modified partial decoding logic 616 can be configured to identify subroutine call and link instructions and / or subroutine return instructions by analyzing the operation (OP) codes of the instructions contained within the instruction bundle. However, it will be apparent to those skilled in the art that any mechanism for identifying a particular type of instruction can be used by modified partial decoding logic 616 to identify subroutine call and link instructions and subroutine return instructions.

[0123] as Figure 3 The decoding logic 316 of the instruction fetch unit 302, if Figure 6 The modified partial decoding logic 616 identifies an instruction in the received instruction bundle that includes a subroutine call and a link instruction. The modified partial decoding logic 616 then predicts the target address (i.e., the return address) for the corresponding subroutine return instruction and pushes the predicted target address onto the modified RPS 604. As described above, the target address of the corresponding subroutine return instruction can be predicted as an address offset from the address of the subroutine call and link instructions.

[0124] For example, the modified partial decoding logic 616 can be configured to predict the target address of a subroutine return instruction corresponding to a compact subroutine call and link instruction as the address of the instruction immediately following the compact subroutine call and link instruction (e.g., the address of the subroutine call and link instruction plus an offset equal to the size of the instruction); and the modified partial decoding logic 616 can be configured to predict the target address of a subroutine return instruction corresponding to a non-compact subroutine call and link instruction as the address of the instruction immediately following the delay slot instruction (e.g., the address of the subroutine call and link instruction plus an offset equal to the size of the two instructions).

[0125] However, with Figure 3 Unlike the partial decoding logic 316, if the modified partial decoding logic 616 identifies one of the instructions in the instruction bundle as a subroutine call or link instruction, then under certain conditions, the modified partial decoding logic 616 can also cause the subsequent instruction bundle (i.e., the instruction bundle currently fetched by the FC stage 608) to be stored together with the predicted target address as the predicted target instruction bundle. Specifically, during the cycle in which the FS stage 610 is decoding instruction bundle X, the FC stage 608 will typically fetch the instruction bundle immediately following instruction bundle X (e.g., instruction bundle X+1). If the predicted target address of the corresponding subroutine return instruction points to an instruction in instruction bundle X+1 (therefore, the target instruction bundle is instruction bundle X+1), then in response to the detection of the corresponding subroutine return instruction, time and resources can be saved by storing instruction bundle X+1 instead of re-fetching the instruction.

[0126] Therefore, if the modified partial decoding logic 616 identifies that the instruction bundle includes subroutine call and link instructions, the modified partial decoding logic 616 determines (i) whether the predicted target instruction bundle for the corresponding subroutine is the instruction bundle immediately following the current instruction bundle (e.g., the predicted target address for the corresponding subroutine return instruction points to an instruction in the instruction bundle immediately following the current instruction bundle (which includes the detected subroutine call and link instructions); and (ii) whether FC level 608 is active.

[0127] In some cases, the modified partial decoding logic 616 can be configured to determine whether the target instruction bundle for the corresponding subroutine return instruction is the immediately following instruction bundle based on the predicted target address. In other cases, the modified partial decoding logic 616 can be configured to determine whether the target instruction bundle is the immediately following instruction bundle based on the format of the current instruction bundle.

[0128] As described above, for compact subroutine call and link instructions, the target address for the corresponding return address can be predicted as the address of the instruction immediately following the subroutine call and link instruction. Therefore, if the compact subroutine call and link instruction is the last instruction in the current instruction bundle (i.e., the instruction bundle currently being decoded), the predicted target address for the corresponding subroutine return instruction will point to an instruction in the next instruction bundle; otherwise, the target address will point to an instruction in the same instruction bundle.

[0129] Conversely, for non-compact subroutine call and link instructions (i.e., subroutine call and link instructions followed by a delay slot instruction), the target address for the corresponding return address can be predicted as the address of the instruction immediately following the delay slot instruction. Therefore, if the non-compact subroutine call and link instruction is the last instruction in the current instruction bundle, or if the delay slot instruction is the last instruction in the current instruction bundle (i.e., the instruction bundle currently being decoded), then the predicted target address for the corresponding subroutine return instruction will point to an instruction in the following instruction bundle.

[0130] When each instruction bundle contains two instructions, the decision on whether to push the (X+1)th instruction bundle onto the modified RPS 604 when the Xth instruction bundle contains a subroutine call and a link instruction is summarized in Table 3.

[0131] Table 3

[0132]

[0133] As can be seen from Table 3, when each instruction bundle has two instructions and the subroutine call and link instructions are non-compact instructions, the target address for the corresponding subroutine call and return instructions will always point to the instruction in the following instruction bundle. Specifically, if the non-compact subroutine call and link instructions are the first instruction in a bundle of two instructions (e.g., instruction bundle X), then the target address for the corresponding subroutine return instruction is the first instruction in the immediately following instruction bundle (e.g., instruction bundle X+1). However, if the non-compact subroutine call and link instructions are the second instruction in a bundle of two instructions (e.g., instruction bundle X), then the target address for the corresponding subroutine return instruction is the second instruction in the immediately following instruction bundle (e.g., instruction bundle X+1). In either case, the target instruction bundle is thus the immediately following instruction bundle (e.g., instruction bundle X+1). Therefore, when the instruction bundles are of size two, when the modified partial decoding logic detects non-compact call and link instructions and FC level 608 is active, the modified partial decoding logic 616 can be simplified by always keeping the next instruction bundle in RPS 604.

[0134] Therefore, the modified decoding logic 616 can be configured to determine that the instruction bundle has a predetermined form if the identified subroutine call and link instruction is a compact subroutine call and link instruction that is the last instruction in the instruction bundle, or if the identified subroutine call and link instruction is a non-compact subroutine call and link instruction, wherein the non-compact subroutine call and link instruction or the corresponding delay slot instruction is the last instruction in the instruction bundle.

[0135] If the modified partial decoding logic 616 determines that the target instruction bundle for the corresponding subroutine return instruction is the instruction bundle immediately following the current instruction bundle, and the FC level 608 is active (indicating that it is currently fetching the instruction bundle immediately following the current instruction bundle), then the modified partial decoding logic 616 can store the instruction bundle currently being fetched by the FC level 608 as the target instruction bundle for the corresponding subroutine return instruction, along with the saved target address, in the modified RPS 604.

[0136] Since the instruction bundle currently being extracted in FC level 608 is not output until the next cycle, the modified partial decoding logic 616 can be configured to set an indicator (such as flag 618) that indicates that the instruction bundle received from FC level 608 should be stored in the modified RPS 604 in the subsequent cycle. Therefore, in the next cycle, the modified partial decoding logic 616 will first determine if flag 618 is set, and if so, will store the instruction bundle received from FC level 608 in the modified RPS 604 at the most recently saved address next to the target address of the modified RPS 604.

[0137] In certain situations, when the modified partial decoding logic 616 determines that the target instruction bundle for the corresponding return instruction is not the instruction bundle immediately following the current instruction bundle, the modified partial decoding logic 616 is configured to determine whether the target instruction for the corresponding subroutine instruction is the current instruction bundle. If it is determined that the target instruction bundle for the corresponding subroutine return instruction is the current instruction bundle, then the current instruction bundle is pushed onto the modified RPS 604. Since the current instruction bundle can be immediately stored in the RPS, no flag is set.

[0138] refer to Figure 9 This section will describe example methods for determining when to push data into a modified RPS 604 and what data to push into a modified RPS 604.

[0139] The modified partial decoding logic 616 is also configured to identify subroutine return instructions in the received instruction bundle. If the modified partial decoding logic 616 identifies a subroutine return instruction in the received instruction bundle and the top entry of the modified RPS 604 has a valid target address, then the target address is popped from the modified RPS 604 and used to generate the address of the next instruction bundle to be extracted.

[0140] If certain conditions are met, any predicted target instruction bundle is also popped from the modified RPS 604 and stored in the instruction storage module 619. In a subsequent cycle, the modified partial decoding logic 616 obtains the instruction bundle stored in the instruction storage module 619 and decodes it.

[0141] Specific conditions may include the modified RPS 604 having valid target instruction bundle data in its top entry, and the instruction bundle including the subroutine return instruction being of a specified form. For example, as described in more detail below, in certain circumstances, the instruction bundle may be considered to be of a specified form if the subroutine return instruction is a compact subroutine return instruction and is the last instruction in the instruction bundle; or if the subroutine return instruction is a non-compact subroutine return instruction (i.e., followed by a delay slot instruction) and is the last instruction in the instruction bundle.

[0142] When each instruction bundle contains two instructions, the decision on whether to pop the target instruction bundle from the modified RPS 604 when the Xth instruction bundle contains a subroutine return instruction is summarized in Table 4.

[0143] Table 4

[0144]

[0145] As described in more detail below, this eliminates the CTI bubble following the subroutine return instruction, which in some cases can significantly improve the performance of the modified instruction fetch unit 602 and the processor in which it forms a part.

[0146] When data is popped from the modified RPS 604, the next instruction bundle to be fetched depends on whether the target instruction bundle for the subroutine return instruction was popped from the modified RPS 604. Specifically, if the instruction bundle for the subroutine return instruction was popped from the modified RPS 604, the popped instruction bundle is provided to FS stage 610 in the next cycle, and the next instruction bundle to be fetched is the instruction bundle immediately following the stored instruction bundle. Since the target address stored in the modified RPS 604 is the address of the instruction bundle stored in the modified RPS 604, the address of the next instruction bundle to be fetched can be calculated by adding an offset (e.g., equal to the size of the instruction bundle) to the stored target address. Conversely, if the target instruction bundle for the subroutine return instruction was not popped from the modified RPS 604, the address of the next instruction bundle to be fetched is the target address that was popped from the modified RPS 604.

[0147] Therefore, FS level 610 may include next bundle logic 620, which is configured to calculate and output the address of the next instruction bundle to be fetched based on whether the corresponding instruction bundle is popped from the modified RPS 604. (See reference) Figure 15 This describes an example method for determining the address of the next instruction bundle to be fetched, which can be executed by the next bundle logic 620.

[0148] Now for reference Figure 7 It shows Figure 6 The modified RPS 604 example structure.

[0149] Figure 7 The modified RPS 604 in the example has a LIFO buffer with a top pointer 702 pointing to the most recently modified entry on the stack. Each entry may include address valid data 704, destination address data 706, bundle valid data 708, and / or destination bundle data 710. Address valid data 704 indicates whether the corresponding destination address data 706 is valid; destination address data 706 is used to store the predicted destination address for a subroutine return instruction; bundle valid data 708 indicates whether the corresponding destination bundle data 710 is valid; and destination bundle data 710 is used to store the predicted destination instruction bundle for a subroutine return instruction.

[0150] As described above, when the modified partial decoding logic 616 detects subroutine call and link instructions, it predicts the target address of the corresponding subroutine return instruction based on the address and type of the subroutine call and link instructions. For example, in some cases where the call and link instructions are compact call and link instructions, the target address of the corresponding subroutine return instruction can be predicted as the address of the instruction immediately following the call and link instructions; and in the case where the call and link instructions are non-compact call and link instructions, the target address of the corresponding subroutine return instruction can be predicted as the address of the instruction immediately following the delay slot instruction (e.g., the address of the second instruction immediately following the delay slot instruction).

[0151] Once the target address for the corresponding subroutine return instruction has been predicted, the modified decoding logic 616 pushes the predicted target address onto the modified RPS 604. Pushing the predicted target address onto the modified RPS 604 may involve adjusting (e.g., incrementing) the top pointer 702 to point to the next free entry in the modified RPS 604; storing the predicted target address as target address data 706 of the entry pointed to by the top pointer 702; and setting the corresponding address validity data 704 to indicate that the target address data is valid.

[0152] As described above, the modified partial decoding logic 616 can also determine whether a specific condition is met, indicating that the instruction bundle currently being fetched by FC level 608 should also be stored in the modified RPS 604 (e.g., the target instruction bundle for the corresponding subroutine return instruction is the instruction bundle immediately following the current instruction bundle; and FC level 608 is active). If the modified partial decoding logic 616 determines that the condition is met, then the modified partial decoding logic 616 indicates, for example, by setting flag 618, that the instruction bundle currently being fetched by FC level 608 should be stored in the modified RPS 604.

[0153] In the following cycle, the modified decoding logic 616 sees that flag 618 is set and then stores the received instruction bundle in the most recently modified entry in the modified RPS 604. This may involve storing the received instruction bundle as target bundle data 710 of the entry pointed to by top pointer 702, and setting the corresponding bundle valid data 708 to indicate that the target instruction bundle data is valid. Note that there is no incrementing of top pointer 702 at this time.

[0154] When the modified decoding logic 616 detects subroutine calls and link instructions, if the entry pointed to by the top pointer 702 in the modified RPS 604 has valid address data, then the target address data is popped from the modified RPS 604 and used to determine the address of the next instruction bundle to be fetched.

[0155] As described above, the modified partial decoding logic 616 can also determine whether a specific condition is met, indicating that any valid target instruction bundle is the next instruction bundle to be decoded. If the modified partial decoding logic 616 determines that the condition is met, then if the entry pointed to by the top pointer 702 in the modified RPS 604 has valid instruction bundle data, then the instruction bundle data is popped from the modified RPS 604 and decoded by the FS stage 610 in the next cycle.

[0156] Once the target address and / or target instruction bundle has been output, clear the valid data indicators (e.g., address valid data 704 and bundle valid data 708) to indicate that the corresponding data is not valid and decrement the top pointer 702.

[0157] Now for reference Figure 8 The illustration shows an example method 800 for pushing data onto and popping data from a modified RPS 604, which can be executed by FS level 610 each cycle. Method 800 begins at block 802, where, in response to identifying subroutine call and link instructions in a received instruction bundle, modified partial decoding logic 616 pushes the predicted target address and / or the predicted target instruction bundle onto the modified RPS 604. For example, as described above, in response to identifying subroutine call and link instructions in a received instruction bundle, modified partial decoding logic 616 stores the predicted target address of the corresponding return instruction in the modified RPS 604; and if certain conditions are met, the predicted target instruction bundle is also stored in the modified RPS 604. Reference Figure 9 An example method for implementing block 802 is described.

[0158] At block 804, in response to the detection of a subroutine return instruction, the modified partial decoding logic 616 pops the predicted target address and / or the predicted target instruction bundle from the modified RPS 604. For example, as described above, in response to the recognition of a subroutine return instruction in the received instruction bundle, the modified partial decoding logic 616 pops a first valid predicted target address from the modified RPS 604; and if a certain condition is met, any valid stored target instruction bundle is output and used as input to FS level 610 in the next cycle. Reference Figure 12 An example method for implementing block 804 is described.

[0159] At block 806, if data is popped and / or output from modified RPS 604 in block 804, then the next bundle logic 620 generates the address of the next instruction based on the predicted target address. For example, as described above, whenever the target address is output or popped from modified RPS 604, the next bundle logic 620 can be configured to set the address of the next instruction bundle to be fetched to the predicted target address. However, if both the predicted target address and the predicted target instruction bundle are output or popped from modified RPS 604, then the next bundle logic 620 can be configured to set the address of the next instruction bundle to be fetched to the instruction bundle immediately following the predicted target instruction bundle (i.e., predicted target address + 1 instruction bundle). Reference Figure 15 An example method for implementing block 806 is described.

[0160] Now for reference Figure 9 The diagram illustrates an example method 900 for pushing data onto a modified RPS 604, which can be executed each cycle by modified partial decoding logic 616. Method 900 begins at block 902, where modified partial decoding logic 616 determines whether flag 618 is set. As described above (and below with respect to blocks 912 through 918), if, in a particular cycle, modified partial decoding logic 616 identifies subroutine calls and link instructions and satisfies specific conditions for storing the instruction bundle currently being fetched, then flag 618 is set to notify modified partial decoding logic 616 that the instruction bundle received in the next cycle will be pushed onto modified RPS 604.

[0161] Therefore, if the modified partial decoding logic 616 determines that flag 618 has been set, then the modified partial decoding logic 616 knows that a subroutine call and link instruction were detected in the previous cycle and that the conditions for storing the received instruction bundle have been met. Thus, method 900 proceeds to blocks 904 and 906, where the received instruction bundle is pushed onto the modified RPS 604 and flag 618 is cleared. The method then ends at 908. However, if the modified partial decoding logic 616 determines that flag 618 has not been set, then method 900 proceeds to block 910.

[0162] At block 910, the modified partial decoding logic 616 partially decodes the instructions in the received instruction bundle to determine whether any instructions in the received instruction bundle are subroutine call and link instructions. As mentioned above, decoding instructions may include using OP codes to identify the type of instruction. However, it will be apparent to those skilled in the art that other methods and techniques can be used to partially decode instructions to identify subroutine call and link instructions. Once the instructions in the received instruction bundle have been partially decoded, method 900 proceeds to block 912.

[0163] At block 912, the modified decoding logic 616 determines whether any instruction in the received instruction bundle is a subroutine call or link instruction. If no instruction in the received instruction bundle is a subroutine call or link instruction, then method 900 ends at 908. However, if one of the instructions in the received instruction bundle is a subroutine call or link instruction, then method 900 proceeds to blocks 914 and 916, where it is determined whether the conditions for storing the instruction bundle currently being fetched by FC level 608 are met.

[0164] At block 914, the modified decoding logic 616 determines whether FC level 608 is active, indicating that FC level 608 is currently fetching instruction bundles. The modified partial decoding logic 616 can determine whether FC level 608 is active, for example, by querying the status of FC level 608 or by receiving an indication from FC level 608 indicating its status. If the modified partial decoding logic 616 determines that FC level 608 is not active and therefore is not currently fetching instruction bundles, the method proceeds to block 920. However, if the modified partial decoding logic 616 determines that FC level 608 is active and therefore is currently fetching instruction bundles, method 900 proceeds to block 916.

[0165] At method 916, the modified partial decoding logic 616 determines whether the predicted target instruction bundle for the corresponding subroutine return instruction is the instruction bundle immediately following the current instruction bundle. In some cases, the modified partial decoding logic 616 can be configured to predict the target address for the corresponding subroutine return instruction and determine whether the predicted target instruction bundle for the corresponding subroutine return instruction is the instruction bundle immediately following the current instruction bundle based on the predicted target address. For example, the modified partial decoding logic 616 can determine whether the predicted target instruction bundle for the corresponding subroutine return instruction is the instruction bundle immediately following the current instruction bundle based on whether the predicted target address points to an instruction in the instruction bundle immediately following the current instruction bundle.

[0166] In other cases, based on whether the current instruction bundle has a specific form, the modified partial decoding logic 616 can determine whether the predicted target instruction bundle for the corresponding subroutine return instruction is the instruction bundle immediately following the current instruction bundle. As described above, the modified partial decoding logic 616 can be configured to determine that the current instruction bundle has a specific form if either (a) or (b) the identified subroutine call and link instructions are compact call and link instructions located in the last slot of the instruction bundle; or (b) the identified call and link instructions are non-compact call and link instructions (i.e., followed by a delay slot instruction), and the non-compact call and link instruction or the corresponding delay slot instruction is in the last slot of the instruction bundle. If the instruction bundle is determined to have a specific form, then the conditions for storing the subsequent instruction bundle are satisfied and method 900 proceeds to block 918. However, if the bundle does not have a specific form, then the conditions for storing the subsequent instruction bundle in the modified RPS 604 are not satisfied and method 900 proceeds to block 920.

[0167] In some cases, if the modified partial decoding logic 616 determines that the target instruction bundle for the prediction of the corresponding return instruction is not the instruction bundle immediately following the current instruction bundle, then before proceeding to block 920, the modified partial decoding logic 616 can be configured to determine whether the target instruction bundle for the prediction of the corresponding subroutine instruction is the current instruction bundle. If it is determined that the target instruction bundle for the prediction of the corresponding subroutine return instruction is the current instruction bundle, then the modified partial decoding logic 616 can push the current instruction bundle onto the modified RPS 604 and set the target bundle valid data. Method 900 then continues to block 920.

[0168] At block 918, the modified partial decoding logic 616 sets flag 618 or other indicators, causing the modified partial decoding logic 616 to push the instruction bundle received in the next cycle onto the modified RPS 604. Once flag 618 or other indicators have been set, method 900 proceeds to block 920.

[0169] At block 920, the modified decoding logic 616 predicts the target address of the corresponding subroutine return instruction and then pushes the target address onto the modified RPS 604. As mentioned above, the target address of the corresponding subroutine return instruction can be based on the addresses of the subroutine call and link instructions identified in block 912, as well as the type of the instruction. For example, in some cases, for compact subroutine call and link instructions, the target address of the corresponding subroutine return instruction can be predicted as the address of the instruction immediately following the subroutine call and link instructions. However, for non-compact subroutine call and link instructions, the target address of the corresponding subroutine return instruction can be predicted as the address of the instruction immediately following the delay slot instruction.

[0170] Once the target address for the corresponding subroutine return instruction has been predicted, it is pushed onto the modified RPS 604. This may involve adjusting (e.g., incrementing) the top pointer to point to the next free entry or slot in the modified RPS 604, storing the predicted target address as target address data 706, and setting the valid address data to indicate that the target address data is valid. Once the target address has been pushed onto the modified RPS 604, method 900 ends at 908.

[0171] Now for reference Figure 10 and Figure 11 The illustration shows an example timing diagram that illustrates when... Figure 9 Method 900 is used to push data into the modified RPS 604. Figure 6 The modified state of instruction fetch unit 602 over several cycles. Specifically, Figure 10 The modified instruction fetch unit 602 is shown in its state when a call and link instruction move through the instruction fetch pipeline, satisfying the conditions for storing the next instruction bundle in the modified RPS 604; and Figure 11 The modified instruction fetch unit is shown in its state when subroutine calls and link instructions move through the fetch pipeline when the conditions for storing the next instruction bundle in the modified RPS 604 are not met. Figure 10 and Figure 11 In the example, each instruction bundle consists of two instructions.

[0172] First refer to Figure 10 For example, in the first cycle (cycle A), FE stage 606 sets the program counter (PC) to the address of bundle Z, which is a bundle that includes JAL instructions (which are non-compact subroutine calls and link instructions) followed by delay slot instructions. In the second cycle (cycle B), FE stage 606 increments the PC to point to the next instruction bundle (bundle Z+1), and FC stage 608 fetches bundle Z.

[0173] In the third cycle (cycle C), the FC stage fetches bundle Z+1 and the FS stage 610 decodes bundle Z. Since instruction bundle Z includes subroutine call and link instructions (JAL instructions), the FS stage 610 predicts the target address for the corresponding subroutine return instruction as the address of the instruction immediately following the delay slot instruction and pushes the predicted target address into the modified RPS 604. Specifically, the FS stage 610 increments the top pointer, saves the predicted target address as target address data, and sets the valid address data (e.g., sets the valid address bit to one) to indicate that the corresponding target address data is valid.

[0174] Additionally, since bundle Z is in a predetermined form (followed by a non-compact subroutine call and link instruction with a delay slot instruction) and FC level 608 is active, the condition for storing the bundle (bundle Z+1) currently being extracted in FC level 608 is met, and therefore FS level 610 sets flag 618.

[0175] Furthermore, since bundle Z includes CTI (e.g., the JAL instruction), the next bundle to be fetched is not bundle Z+1 but the bundle at the target address relative to the JAL instruction. If the target address is available, it is provided to FE level 606 so that the PC can be set to the target address.

[0176] In the fourth cycle (cycle D), FE stage 606 sets the PC to the next instruction bundle (target instruction bundle + 1) and FC stage 608 extracts the target instruction bundle for subroutine calls and link instructions (e.g., JAL instructions). FS stage 610 receives instruction bundle Z+1 from FC stage 608, but because flag 618 has been set, instruction bundle Z+1 is not decoded or output; it is simply pushed onto the modified RPS 604. FS stage 610 then clears flag 618.

[0177] Therefore, it can be seen in this example that the predicted target address and the predicted target instruction bundle for the corresponding subroutine return instruction are both stored in the modified RPS 604 for subsequent use.

[0178] Now for reference Figure 11 In the second example, in the first cycle (cycle A), FE stage 606 sets the program counter (PC) to the address of instruction bundle Y, which is a bundle that includes JIALC instructions (compact subroutine call and link instructions) followed by instructions. In the second cycle (cycle B), FE stage 606 increments the PC to point to the next instruction bundle (instruction bundle Y+1), and FC stage 608 fetches instruction bundle Y.

[0179] In the third cycle (cycle C), FC stage 608 fetches instruction bundle Y+1 and FS stage 610 decodes instruction bundle Y. Since instruction bundle Y includes compact subroutine call and link instructions (JIALC instructions), FS stage 610 predicts the target address for the corresponding subroutine return address as the address of the instruction immediately following the call and link instructions and pushes the predicted target address onto the modified RPS 604. Specifically, FS stage 610 increments the top pointer, saves the predicted target address as target address data 706, and sets valid address data 708 to indicate that target address data 706 is valid (e.g., sets the valid address bit to one).

[0180] However, on the contrary Figure 10In the example, instruction bundle Y does not meet the conditions for storing the next instruction bundle in the modified RPS604 because the predicted target address is the second instruction in instruction bundle Y, therefore flag 618 is not set. However, since the predicted target address points to an address in the current instruction bundle (instruction bundle Y), (and thus the current instruction bundle (instruction bundle Y) is the predicted target instruction bundle) the current instruction bundle is pushed onto the modified RPS604.

[0181] Furthermore, since instruction bundle Y includes CTI (e.g., the JAL instruction), the next bundle to be fetched is not bundle Y+2 but the bundle at the target address relative to the JAL instruction. If the target address is available, it is provided to FE level 606, so that the PC can be set to the target address.

[0182] In the fourth cycle (cycle D), FE stage 606 sets the PC to the next instruction bundle (target instruction bundle + 1) and FC stage 608 extracts the target instruction bundle for subroutine calls and link instructions (e.g., JIALC instructions). FS stage 610 receives bundle Y+1 from FC stage 608, but simply discards it because no flag is set.

[0183] Therefore, as can be seen in this example, like Figure 10 In the example above, the predicted target address and predicted instruction bundle for the corresponding subroutine return instruction are both stored in the modified RPS 604 for subsequent use. However, in this example, the predicted instruction bundle is the current instruction bundle, so it is immediately stored in the modified RPS 604 instead of having to wait for the cycle used to push the predicted target instruction bundle into the modified RPS 604.

[0184] Now for reference Figure 12 The diagram illustrates an example method 1200 for popping data from a modified RPS 604, which can be executed each cycle by modified partial decoding logic 616. Method 1200 begins at block 1202, where the modified partial decoding logic 616 partially decodes the received instruction bundle to determine whether it includes a subroutine return instruction. In some cases, the modified partial decoding logic 616 can be configured to analyze the OP code of the instructions in the received instruction bundle to determine whether any instruction in the instruction bundle is a subroutine return instruction. Once the instruction bundle has been partially decoded, method 1200 proceeds to block 1204.

[0185] At block 1204, the modified decoding logic 616 determines whether any instruction in the instruction bundle is a subroutine return instruction. If it is determined that no instruction in the instruction bundle is a subroutine return instruction, then method 1200 ends at block 1206. However, if it is determined that one of the instructions in the instruction bundle is a subroutine return instruction, then method 1200 proceeds to block 1208.

[0186] At block 1208, the modified partial decoding logic 616 determines whether the target address data 706 stored in the top entry of the modified RPS 604 is valid. In some cases, the modified partial decoding logic 616 can be configured to analyze the address valid data 704 to determine whether the corresponding target address data 706 is valid. If the address valid data 704 is implemented as a single bit, the modified partial decoding logic 616 can determine that the target address stored in the top entry of the modified RPS 604 is valid if the address valid bit is set. If the modified partial decoding logic 616 determines that the target address stored in the top entry of the modified RPS 604 is not valid, then method 1200 ends at 1206. However, if the modified partial decoding logic 616 determines that the target address data 706 is valid, then the method proceeds to block 1210.

[0187] At block 1210, the modified partial decoding logic 616 determines whether the instruction bundle has a specific form that indicates the next instruction bundle to be executed is the predicted target instruction bundle. For example, as described above, if the identified subroutine return instruction is a compact subroutine return instruction; or if the identified subroutine return instruction is a non-compact subroutine return instruction (i.e., followed by a delay slot instruction) and the corresponding delay slot instruction is in the same instruction bundle as the subroutine return instruction, then the modified partial decoding logic 616 can determine that the received instruction bundle has a specific form.

[0188] If the modified partial decoding logic 616 determines that the received instruction bundle does not have a specific form, then even if the predicted target instruction bundle is stored in the modified RPS 604, it will not be used. Thus, method 1200 proceeds to block 1212, where the address of the predicted target is popped from the modified RPS 604. However, if the modified partial decoding logic 616 determines that the received instruction bundle has a specific form, then if a validly predicted target instruction bundle is already stored in the modified RPS 604, the predicted target instruction bundle can be fed to FS stage 610 in the next cycle. Thus, method 1200 proceeds to block 1214.

[0189] At block 1214, the modified partial decoding logic 616 determines whether the top entry of the modified RPS 604 includes valid target bundle data 710. In some cases, the modified partial decoding logic 616 can be configured to analyze the bundle valid data 708 to determine whether the top entry of the modified RPS 604 includes valid target bundle data 710. If the bundle valid data 708 is implemented as a single bit, the modified partial decoding logic 616 can determine that the target bundle data stored in the top entry of the modified RPS 604 is valid if the bundle valid bit is set. If the modified partial decoding logic 616 determines that the target instruction bundle stored in the top entry of the modified RPS 604 is not valid, then method 1200 proceeds to block 1212, where the target address is popped from the modified RPS 604. However, if the modified partial decoding logic 616 determines that the target bundle data 710 is valid, then method 1200 proceeds to block 1216.

[0190] At block 1216, the modified partial decoding logic 616 pops the top target bundle data 710 from the modified RPS 604. This may involve outputting the top target bundle data 710 (the target bundle data 710 in the entry pointed to by the top pointer 702) and storing it in the instruction store module 619. Once the target bundle data 710 has been popped from the modified RPS 604, method 1200 proceeds to block 1212.

[0191] At block 1212, the modified partial decoding logic 616 pops the target address data 706 from the modified RPS 604. This may involve outputting the top target address data 706 to the next bundle logic 620, where the address of the next bundle to be extracted is determined based on the output target address data 706. The modified partial decoding logic 616 may also clear the valid data fields (i.e., address valid data 704 and bundle valid data 708) and adjust (e.g., decrement) the top pointer 702. Once the target address data 706 has been popped from the modified RPS 604, method 1200 ends at 1206.

[0192] Now for reference Figure 13 and Figure 14 The illustration shows an example timing diagram that illustrates when... Figure 12 Method 1200 is used to pop data from a modified RPS 604. Figure 6 The modified state of instruction fetch unit 602 over several cycles. Specifically, Figure 13 The modified instruction fetch unit 602 is shown in its state when a return instruction for a subroutine with a specific form and for which a target instruction bundle has been stored passes through the instruction fetch pipeline; and Figure 14The modified instruction fetch unit is shown in its state when a subroutine return instruction of a specific form, for which no target instruction bundle is stored, moves through the instruction fetch pipeline. Figure 13 and Figure 14 In the example, each instruction bundle consists of two instructions.

[0193] First refer to Figure 13 For example, in the first cycle (cycle A), FE stage 606 sets the program counter (PC) to the address of instruction bundle J, which includes the JR$31 instruction (a non-compact subroutine return instruction) followed by a delay slot instruction. In the second cycle (cycle B), FE stage 606 increments the PC to point to the next instruction bundle (instruction bundle J+1), and FC stage 608 fetches instruction bundle J.

[0194] In the third cycle (cycle C), the FC stage fetches instruction bundle J+1 and the FS stage 610 decodes instruction bundle J. Since instruction bundle J includes a subroutine return instruction (JR $31 instruction) and the instruction bundle is of a specific form (the subroutine instruction is a non-compact subroutine return instruction and the corresponding delay slot instruction is in the same instruction bundle), the FS stage 610 determines whether the modified RPS 604 includes a valid target address and a valid target bundle in its top entry. Since it does include them (all valid bits are set), the target address is used to generate the address of the next bundle to be fetched (which is the bundle immediately following the target bundle, in this case bundle Z+2), which is used by the FE stage 606 to set the PC to that address; and the target bundle from the modified RPS 604 (in this example, instruction bundle Z) is output to the instruction storage module 619 so that it can be used by the FS stage 610 in the next cycle.

[0195] Specifically, in the fourth cycle (cycle D), the FS stage 610 decodes the target instruction bundle (in this case, instruction bundle Z+1) stored in the instruction storage module 619.

[0196] Therefore, as can be seen in this example, in response to the detection of a subroutine return instruction, both the predicted target address and the predicted instruction bundle are popped from the modified RPS 604. The predicted target address is used to generate the address of the next instruction bundle to be fetched, and the predicted target instruction bundle is used by the FS stage 610 in subsequent cycles. As can be seen in this example, the CTI bubble caused by the subroutine return instruction has been eliminated.

[0197] Now for reference Figure 14For example, in the first cycle (cycle A), FE stage 606 sets the program counter (PC) to the address of instruction bundle L, which includes the instruction followed by JIC$31 (a compact subroutine return instruction). In the second cycle (cycle B), FE stage 606 increments the PC to point to the next instruction bundle (instruction bundle L+1), and FC stage 608 fetches instruction bundle L.

[0198] In the third cycle (cycle C), the FC stage fetches instruction bundle L+1 and the FS stage 610 decodes instruction bundle L. Since instruction bundle L includes a subroutine return instruction (JIC$31 instruction) and the instruction bundle is of a specific form (the subroutine instruction is a compact subroutine return instruction), the FS stage 610 determines whether the modified RPS 604 includes a valid target address and a valid target bundle in the top entry. Because the modified RPS 604 only includes a valid target address, this target address is used to generate the address of the next bundle to be executed (which in this case is instruction bundle Z+1), which is used by the FE stage 606 to set the PC to that address.

[0199] In the fourth cycle (cycle D), FC stage 608 fetches instruction bundle Z+1, and FS stage 610 discards it because instruction bundle L+1 is no longer the next instruction bundle to be executed.

[0200] Therefore, as can be seen in this example, in response to the detection of a subroutine return instruction, only the predicted target address is popped from the modified RPS 604. The predicted target address is used to generate the address of the next bundle to be extracted, and the FS stage 610 must wait one cycle to receive the next instruction bundle to be decoded.

[0201] Now for reference Figure 15 The diagram illustrates the method used to implement Figure 8 Example method 1500 of block 806 of method 800. Specifically, method 1500 is an example method for generating the address of the next instruction bundle to be extracted when the predicted target address is popped from the modified RPS 604, which can be executed by the next bundle logic 620 in each cycle.

[0202] Method 1500 begins at block 1502, where the next bundle logic 620 determines whether the target address has been popped from the modified RPS 604. The next bundle logic 620 can be configured to determine whether the target address has been popped from the modified RPS 604 if it receives the target address from the modified RPS 604. If the next bundle logic 620 determines that the target address has not been popped from the modified RPS 604, then method 1500 ends at block 1504. However, if the next bundle logic 620 determines that the target address has been popped from the modified RPS 604, then method 1500 proceeds to block 1506.

[0203] At block 1506, the next bundle logic 620 determines whether the target instruction bundle has also been popped from the modified RPS 604. The next bundle logic 620 can be configured to receive a notification from the modified partial decoding logic 616 that the target instruction bundle has been popped, and thus determine that the target instruction has also been popped from the modified RPS 604 upon receiving such a notification. Otherwise, the next bundle logic 620 can be configured to read the instruction storage module 619 to see if it contains valid data. If the next bundle logic 620 determines that the target instruction bundle has been popped from the modified RPS 604, method 1500 proceeds to block 1508. However, if the next bundle logic 620 determines that the target instruction bundle has not been popped from the modified RPS 604, method 1500 proceeds to block 1510.

[0204] At block 1508, the next bundle logic 620 sets the address of the next bundle to be fetched to the instruction bundle following the target instruction bundle. For example, the next bundle logic 620 can set the address of the next bundle to be fetched to the predicted target address popped from the modified RPS 604 plus an offset. Specifically, if the predicted target bundle is popped from the modified RPS 604, then the next bundle to be decoded and executed is already available, so FC level 608 can directly fetch the next instruction bundle following the predicted target instruction bundle. Once the next bundle logic 620 sets the address, method 1500 ends at 1504.

[0205] At block 1510, the next bundle logic 620 sets the address of the next bundle to be extracted to the address of the target bundle. For example, the next bundle logic 620 may set the address of the next bundle to be extracted to the predicted target address popped from the modified RPS 604. Specifically, since the target bundle is not immediately available for decoding and execution, it must be extracted by FC level 608 in the next cycle. Once the address is set by the next bundle logic 620, method 1500 ends at 1504.

[0206] Now for reference Figure 16 It shows an example timing diagram that illustrates Figure 6 The modified state of instruction fetch unit 602 over several cycles. As... Figure 5 The timing diagram, Figure 16 The timing diagram shows which instruction bundle the output of each stage of the fetch unit 602, modified in a specific cycle, relates to. For example, in cycle A, the output of FE stage 606 (e.g., index / PC) relates to instruction bundle 1.

[0207] Therefore, in cycle A, FE stage 606 sets the PC to the address of instruction bundle 1. In cycle B, FE stage 606 sets the PC to the address of the next instruction bundle (e.g., instruction bundle 2), and FC stage 608 fetches instruction bundle 1. In cycle C, FE stage 606 sets the PC to the address of the next instruction bundle (e.g., instruction bundle 3), FC stage 608 fetches instruction bundle 2, and FS stage 610 decodes instruction bundle 1. Thus, instructions are fetched sequentially in cycles A, B, and C.

[0208] However, in cycle D, FS stage 610 detects subroutine call and link instructions (e.g., JAL instructions). In response, FS stage 610 predicts the target address of the corresponding subroutine return instruction and pushes it onto the modified RPS 604. Additionally, if the conditions for storing the next instruction bundle in the modified RPS 604 are met (e.g., the next instruction bundle is predicted as the target instruction bundle, and FC stage 608 is active), then FS stage 610 indicates to FS stage 610, for example, by setting flag 618, that the instruction bundle received in a subsequent cycle should be pushed onto the modified RPS 604.

[0209] Then, in cycle E, FS stage 610 sees the flag set, and the instruction bundle 3 is stored in the modified RPS 604 as the predicted target instruction bundle data and the flag 618 is cleared.

[0210] Then, in cycle G, when FS stage 610 detects the corresponding subroutine return instruction (e.g., JR$31 instruction), FS stage 610 pops the stored predicted target instruction bundle (e.g., instruction bundle 3) to be decoded by FS stage 610 in the next cycle (cycle H), and FS stage 610 pops the stored predicted target address used to generate the address of the next instruction bundle to be extracted (in this case, instruction bundle 4).

[0211] In some cases, instruction bundles may be updated or invalidated after they have been stored or pushed onto the modified RPS 604. Therefore, in some cases, the instruction fetch unit 602 may also include an RPS controller that monitors changes to instruction bundles in the instruction cache and updates the modified RPS 604 accordingly. For example, in some cases, the RPS controller may be configured to automatically invalidate the predicted target instruction bundle in the modified RPS 604 (e.g., clear bundle valid data) if the RPS controller detects a change to the corresponding entry in the instruction cache.

[0212] Now for reference Figure 17 It shows an example FS level 610 including an instruction fetch unit with an RPS controller 1702. For simplicity, not all... Figure 6The components of the instruction fetch unit 602 are all in Figure 17 As shown, but will be apparent, the RPS controller 1702 described herein can be used as Figure 6 It is part of the FS stage 610 of the instruction fetch unit 602.

[0213] Processors typically do not have enough memory to store the entire program, so the Memory Management Unit (MMU) is used to map the virtual addresses of instructions (addresses used by the processor, such as the PC) to physical memory addresses. When searching for the instruction bundle corresponding to the PC in instruction cache 614 in FC level 608, instruction cache 614 can use an index (generated from the PC) and a tag (generated from the physical address) to search.

[0214] To reduce the number of accesses to the MMU 1704, the FC level 608 can maintain a miniature translation bypass buffer (TLB) 1706, which can be used to cache a predetermined number of virtual addresses to physical address maps. In these cases, the miniature TLB 1706 is then used to generate tags for instruction cache lookups.

[0215] To ensure that the data in the miniature TLB 1706 remains up-to-date, the MMU 1704 tracks the entries in the miniature TLB 1706. When the MMU 1704 receives an update on one of the entries in the miniature TLB 1706 (e.g., a change or invalidation of the entry), the MMU 1704 sends the corresponding update to the miniature TLB 1706. If appropriate, the miniature TLB 1706 then updates its instruction cache.

[0216] RPS controller 1702 can be configured to monitor updates sent from MMU 1704 to miniature TLB 1706 to determine if they relate to an instruction bundle entry in modified RPS 604. Since entries in miniature TLB 1706 are identified by virtual addresses (e.g., indexes) and physical addresses (tags), in some cases, modified partial decoding logic 616 can be configured to also store tags in modified RPS 604. In these cases, RPS controller 1702 can ultimately determine that if the index and tag specified in the update match (determined from the predicted target address) the stored index and stored tag, then the update to miniature TLB 1706 corresponds to a target instruction bundle entry in the RPS. In other cases, tags are not stored in modified RPS 604. In these cases, RPS controller 1702 can determine that if the index in the update matches the stored index (which can be determined from the predicted target address), then the update to miniature TLB 1706 may correspond to an entry in the RPS.

[0217] If the RPS controller 1702 detects that an update sent from the MMU 1704 to the micro TLB 1706 relates to or may relate to an entry in the modified RPS 604, then the RPS controller 1702 can invalidate the target bundle data by setting the bundle valid data 708 to indicate that the target bundle data 710 is invalid (e.g., this may involve clearing the bundle valid bit).

[0218] Because the miniature TLB 1706 has a finite number of entries, if the miniature TLB 1706 receives a request for conversion (e.g., for tag generation) and does not have a corresponding entry, then the miniature TLB 1706 requests the entry from the MMU 1704, and the MMU 1704 sends data about the requested entry, which is used to refill, replace, or evict the least recently used entry in the miniature TLB 1706. In some cases, when the RPS controller 1702 detects a refill signal or command from the MMU 1704, the RPS controller 1702 can be configured to invalidate all target bundle data stored in the modified RPS 604. In other cases, the modified partial decoding logic 616 can be configured to store the slot or number of entries corresponding to each entry in the miniature TLB 1706, and the corresponding target bundle data is only invalidated when that particular slot is refilled or evicted.

[0219] Typically, when a virtual address is remapped to another physical address, the MMU invalidates / updates the corresponding entries in the mini-TLB and instruction cache; and then the instruction bundle at the new address must subsequently be fetched. As described above, when the example RPS controller 1702 detects a change to the entry in the mini-TLB corresponding to the entry in the RPS, the RPS controller 1702 invalidates the corresponding entry in the RPS and does not attempt to update the entry in the RPS with the new instruction bundle data. This is because the instruction bundle at the new address will be fetched anyway, and therefore no time is saved by storing the instruction bundle when it is fetched.

[0220] It will be apparent to those skilled in the art that the above description of the RPS controller 1702 is merely an example, and the RPS controller 1702 may be otherwise configured to monitor updates to the instruction bundle and update the RPS 604 accordingly.

[0221] As used herein, the terms "processor" and "computer" refer to any device or part thereof that has processing power enabling it to execute instructions. The term "processor" can include, for example, a central processing unit (CPU), a graphics processing unit (GPU or VPU), a physical processing unit (PPU), a radio processing unit (RPU), a digital signal processor (DSP), a general-purpose processor (e.g., a general-purpose GPU), a microprocessor, any processing unit designed to accelerate tasks outside the CPU, and the like. Those skilled in the art will recognize that such processing power is incorporated into many different devices, and therefore, the term "computer" includes set-top boxes, media players, digital radios, PCs, servers, mobile phones, personal digital assistants, and many other devices.

[0222] Those skilled in the art will recognize that storage devices used to store program instructions can be distributed across a network. For example, a remote computer can store a described process instance as software. A local or terminal computer can access the remote computer and download part or all of the software to run the program. Alternatively, a local computer can download some software as needed, or execute certain software instructions at a local terminal and at a remote computer (or computer network). Those skilled in the art will also recognize that, by utilizing conventional techniques known to those skilled in the art, all or part of the software instructions can be executed by dedicated circuitry such as a DSP, a programmable logic array, etc.

[0223] The methods described herein can be executed by a computer configured with machine-readable software stored on a tangible storage medium. When the program is run on the computer and where the computer program can be embodied on a computer-readable storage medium, it takes the form of a computer program including computer-readable program code for configuring the computer to perform the components of the described methods, or as a computer program including computer program code means suitable for performing all steps of any of the methods described herein. Examples of tangible (or non-transitory) storage media include disks, thumb drives, memory cards, etc., and do not include propagated signals. The software can be adapted to execute on a parallel or serial processor, such that the method steps can be performed in any suitable order or simultaneously.

[0224] The hardware components described herein can be generated from a non-transitory computer-readable storage medium on which computer-readable program code is encoded.

[0225] This term is intended to encompass software that “describes” or defines a hardware configuration that implements the modules, functions, components, or logic described above, such as HDL (Hardware Description Language) software for designing integrated circuits or configuring programmable chips to perform desired functions. That is, a computer-readable storage medium may be provided on which computer-readable program code is encoded for generating processing units configured to perform any of the methods described herein or for generating processing units including any of the means described herein. In other words, a computer system may be configured to represent a digital circuit from definitions of circuit elements and data defining rules for combining those circuit elements, wherein a non-transitory computer-readable storage medium may store processor-executable instructions thereon that, when executed at such a computer system, cause the computer system to generate processing units as described herein. For example, a non-transitory computer-readable storage medium may store computer-readable instructions thereon that, when processed at a computer system used to generate the representation of an integrated circuit, cause that computer system to generate the representation of a processor including an instruction fetch unit as described in the examples herein, or to generate the representation of a processor configured to perform the methods described in the examples herein. The representation of the processor may be the processor itself, or a representation of the processor (e.g., a mask) that can be used to generate the processor.

[0226] Memory storing machine-executable data used to implement the disclosed aspects can be a non-transitory medium. A non-transitory medium can be volatile or non-volatile. Examples of volatile non-transitory media include semiconductor-based memories such as SRAM or DRAM. Examples of technologies that can be used to implement non-volatile memory include optical and magnetic storage technologies, flash memory, phase-change memory, and resistive RAM.

[0227] The specific reference to "logic" refers to a structure that performs one or more functions. Examples of logic include circuits arranged to perform these functions(s). For example, such circuits may include transistors and / or other hardware elements available during the manufacturing process. Such transistors and / or other elements may be used to form circuits or structures that implement and / or contain memory, by way of example, such as registers, flip-flops, or latches, logic units (e.g., Boolean operations), mathematical units (such as adders, multipliers, or shifters), and interconnects. Such elements may be provided as custom circuits or standard cell libraries, macros, or at other levels of abstraction. Such elements may be interconnected in a specific arrangement. Logic may include circuits with fixed functions, and the circuits may be programmed to perform one or more functions; such programming may be provided from firmware or software updates or control mechanisms. Logic that determines the performance of a function may also include logic that implements constituent functions or sub-processes. In one example, hardware logic has circuits that implement one or more fixed-function operations, state machines, or processes.

[0228] Any range or device values ​​given in this article can be extended or changed without losing the desired effect, as will be apparent to a technician.

[0229] It will be understood that the benefits and advantages described above may relate to one embodiment or several embodiments. The embodiments are not limited to those that solve any or all of the stated problems or have any or all of the stated benefits and advantages.

[0230] Any reference to an item “an” refers to one or more of those items. The term “comprising” as used herein is intended to include identified method blocks or elements, but such blocks or elements do not include an exclusive list and the apparatus may contain additional blocks or elements, and the method may contain additional operations or elements. Furthermore, blocks, elements, and operations are self-contained and not implicitly enclosed.

[0231] The steps of the method described herein can be performed in any suitable order or simultaneously when appropriate. The arrows between the boxes in the accompanying drawings indicate an example order of the method steps, but are not intended to exclude other orders or the parallel execution of multiple steps. Furthermore, individual blocks can be removed from any method without departing from the spirit and scope of the subject matter described herein. Aspects of any of the examples described above can be combined with aspects of any other examples described to form further examples without losing the desired effect. Where elements in the figures are shown connected by arrows, it will be understood that these arrows only illustrate an example flow of communication (including data and control messages) between elements. Flow between elements can occur in either direction or in both directions.

[0232] It is understood that the above description of preferred embodiments has been given by way of example only, and various modifications can be made by those skilled in the art. Although various embodiments have been described above with a degree of specificity or by reference to one or more individual embodiments, those skilled in the art can make many changes to the disclosed embodiments without departing from the spirit or scope of the invention.

Claims

1. A processor, comprising a multi-level instruction fetch unit, the multi-level instruction fetch unit comprising: Return to the prediction stack; as well as Partial decoding logic, which communicates with the return prediction stack, is configured periodically as follows: Receives a set of one or more instructions for execution; At least partially decode a received set of one or more instructions to determine whether the received set of one or more instructions includes subroutine call and link instructions or subroutine return instructions; In response to determining that the received set of one or more instructions includes subroutine call and link instructions: Predict the target address for the corresponding subroutine return instruction and store the predicted target address in the return prediction stack; as well as One or more instructions of the prediction target group for the corresponding subroutine return instruction are stored in the return prediction stack in the following manner: Determine whether one or more instructions of the predicted target group are a group of one or more instructions that immediately follow the received group of one or more instructions; Determine whether the cache level of the instruction fetch unit is fetching one or more instructions in the current cycle; as well as In response to determining that one or more instructions of the prediction target group are a group of one or more instructions immediately following the received group of one or more instructions, the received group of one or more instructions are stored in the return prediction stack; and in response to determining that the cache level of the instruction fetch unit is fetching one or more instructions in the current cycle, the received group of one or more instructions in the next cycle are stored in the return prediction stack. In response to determining that the received set of one or more instructions includes a subroutine return instruction, one or more instructions of the prediction target group stored in the return prediction stack become the received set of one or more instructions in the next cycle.

2. The processor according to claim 1, wherein, The decoding logic is configured to make one or more instructions of the prediction target group stored in the returned prediction stack become one or more instructions of the received group in the next cycle in the following manner: Determine whether the returned prediction stack includes one or more instructions for a valid prediction target group; and In response to determining that the return prediction stack includes one or more instructions of a valid prediction target group, the one or more instructions of the valid prediction target group in the return prediction stack become one or more instructions of a received group in the next cycle.

3. The processor of claim 2, further comprising next bundle logic configured to generate an address for the next set of one or more instructions to be extracted based on a predicted target address stored in the return prediction stack, in response to the partial decoding logic determining that the set of one or more instructions includes a subroutine return instruction.

4. The processor according to claim 3, wherein, The next beam logic is configured as follows: In response to the partial decoding logic determining that the return prediction stack includes one or more instructions of a valid prediction target group, the address of the next group of one or more instructions to be extracted is generated as an address offset from the target address of the prediction stored in the return prediction stack; as well as In response to the partial decoding logic determining that the return prediction stack does not include one or more instructions of a valid prediction target group, an address for the next group of one or more instructions to be extracted is generated as the target address of the prediction stored in the return prediction stack.

5. A method for retrieving instructions in a multi-level instruction fetch unit of a processor, the method comprising, in a cycle: Receive a set of one or more instructions for execution at part of the decoding logic; The received set of one or more instructions is at least partially decoded by the partial decoding logic to determine whether the received set of one or more instructions includes subroutine call and link instructions or subroutine return instructions; In response to determining that the received set of one or more instructions includes subroutine call and link instructions: Predict the target address of the corresponding subroutine return instruction and store the predicted target address in the return prediction stack; as well as One or more instructions of the prediction target group for the corresponding subroutine return instruction are stored in the return prediction stack in the following manner: Determine whether one or more instructions of the predicted target group are a group of one or more instructions that immediately follow the received group of one or more instructions; Determine whether the cache level of the instruction fetch unit is fetching one or more instructions in the current cycle; as well as In response to determining that one or more instructions of the prediction target group are a group of one or more instructions immediately following the received group of one or more instructions, the received group of one or more instructions are stored in the return prediction stack; and in response to determining that the cache level of the instruction fetch unit is fetching one or more instructions in the current cycle, the received group of one or more instructions in the next cycle are stored in the return prediction stack. In response to determining that the received set of one or more instructions includes a subroutine return instruction, one or more instructions of the prediction target group stored in the return prediction stack become the received set of one or more instructions in the next cycle.

6. The method according to claim 5, wherein, Making one or more instructions stored in the returned prediction stack become one or more instructions received in the next cycle includes: Determine whether the returned prediction stack includes one or more instructions for a valid prediction target group; and In response to determining that the return prediction stack includes one or more instructions of a valid prediction target group, the one or more instructions of the valid prediction target group in the return prediction stack become one or more instructions of a received group in the next cycle.

7. The method of claim 6, further comprising, in response to determining that the set of one or more instructions includes a subroutine return instruction, generating an address for the next set of one or more instructions to be extracted based on a target address of a prediction stored in the return prediction stack.

8. The method according to claim 7, wherein, Generating the address of the next set of one or more instructions to be extracted includes: In response to the partial decoding logic determining that the return prediction stack includes one or more instructions of a valid prediction target group, the address of the next group of one or more instructions to be extracted is generated as an address offset from the target address of the prediction stored in the return prediction stack; and In response to the partial decoding logic determining that the return prediction stack does not include one or more instructions of a valid prediction target group, an address for the next group of one or more instructions to be extracted is generated as the target address of the prediction stored in the return prediction stack.

9. A processor, comprising a multi-level instruction fetch unit, the multi-level instruction fetch unit comprising: Return to the prediction stack; logo; as well as Partial decoding logic, which communicates with the return prediction stack, is configured periodically as follows: Receives a set of one or more instructions for execution; At least partially decode a received set of one or more instructions to determine whether the received set of one or more instructions includes subroutine call and link instructions or subroutine return instructions; In response to determining that the received set of one or more instructions includes subroutine call and link instructions: Predict the target address for the corresponding subroutine return instruction and store the predicted target address in the return prediction stack; as well as One or more instructions of the prediction target group for the corresponding subroutine return instruction are stored in the return prediction stack in the following manner: Determine whether one or more instructions of the predicted target group are a group of one or more instructions that immediately follow the received group of one or more instructions; as well as In response to determining that one or more instructions of the prediction target group are a group of one or more instructions that immediately follow the received group of one or more instructions, the flag is set to store the received group of one or more instructions in the return prediction stack in the next cycle; In response to determining that the received set of one or more instructions includes a subroutine return instruction, one or more instructions of the prediction target group stored in the return prediction stack become the received set of one or more instructions in the next cycle.

10. The processor according to claim 9, wherein, The decoding logic is further configured to determine whether the flag is set, and in response to determining that the flag is set, to store the received set of one or more instructions in the return prediction stack.

11. The processor according to claim 9 or 10, wherein, The decoding logic is configured to make one or more instructions of the prediction target group stored in the returned prediction stack become one or more instructions of the received group in the next cycle in the following manner: Determine whether the returned prediction stack includes one or more instructions for a valid prediction target group; and In response to determining that the return prediction stack includes one or more instructions of a valid prediction target group, the one or more instructions of the valid prediction target group in the return prediction stack become one or more instructions of a received group in the next cycle.

12. The processor of claim 11, further comprising next bundle logic configured to generate an address for the next set of one or more instructions to be extracted based on a target address of a prediction stored in the return prediction stack, in response to the partial decoding logic determining that the set of one or more instructions includes a subroutine return instruction.

13. The processor according to claim 12, wherein, The next beam logic is configured as follows: In response to the partial decoding logic determining that the return prediction stack includes one or more instructions of a valid prediction target group, the address of the next group of one or more instructions to be extracted is generated as an address offset from the target address of the prediction stored in the return prediction stack; as well as In response to the partial decoding logic determining that the return prediction stack does not include one or more instructions of a valid prediction target group, an address for the next group of one or more instructions to be extracted is generated as the target address of the prediction stored in the return prediction stack.

14. A method for retrieving instructions in a multi-level instruction fetch unit of a processor, the method comprising, in a cycle: Receive a set of one or more instructions for execution at part of the decoding logic; The received set of one or more instructions is at least partially decoded by the partial decoding logic to determine whether the received set of one or more instructions includes subroutine call and link instructions or subroutine return instructions; In response to determining that the received set of one or more instructions includes subroutine call and link instructions: Predict the target address of the corresponding subroutine return instruction and store the predicted target address in the return prediction stack; as well as One or more instructions of the prediction target group for the corresponding subroutine return instruction are stored in the return prediction stack in the following manner: Determine whether one or more instructions of the predicted target group are a group of one or more instructions that immediately follow the received group of one or more instructions; as well as In response to determining that one or more instructions of the predicted target group are a group of one or more instructions that immediately follow the received group of one or more instructions, a flag is set to store the received group of one or more instructions in the return prediction stack. In response to determining that the received set of one or more instructions includes a subroutine return instruction, one or more instructions of the prediction target group stored in the return prediction stack become the received set of one or more instructions in the next cycle.

15. The method according to claim 14, wherein, Storing one or more sets of instructions received in the next cycle in the return prediction stack includes setting the flag.

16. The method according to claim 14 or 15, wherein, Making one or more instructions stored in the returned prediction stack become one or more instructions received in the next cycle includes: Determine whether the returned prediction stack includes one or more instructions for a valid prediction target group; and In response to determining that the return prediction stack includes one or more instructions of a valid prediction target group, the one or more instructions of the valid prediction target group in the return prediction stack become one or more instructions of a received group in the next cycle.

17. The method of claim 16, further comprising, in response to determining that the set of one or more instructions includes a subroutine return instruction, generating an address for the next set of one or more instructions to be extracted based on a target address of a prediction stored in the return prediction stack.

18. The method according to claim 17, wherein, Generating the address of the next set of one or more instructions to be extracted includes: In response to the partial decoding logic determining that the return prediction stack includes one or more instructions of a valid prediction target group, the address of the next group of one or more instructions to be extracted is generated as an address offset from the target address of the prediction stored in the return prediction stack; and In response to the partial decoding logic determining that the return prediction stack does not include one or more instructions of a valid prediction target group, an address for the next group of one or more instructions to be extracted is generated as the target address of the prediction stored in the return prediction stack.

19. A processor, comprising a multi-level instruction fetch unit, the multi-level instruction fetch unit comprising: Return to the prediction stack; as well as Partial decoding logic, which communicates with the return prediction stack, is configured periodically as follows: Receives a set of one or more instructions for execution; At least partially decode a received set of one or more instructions to determine whether the received set of one or more instructions includes subroutine call and link instructions or subroutine return instructions; In response to determining that the received set of one or more instructions includes subroutine call and link instructions, one or more instructions of the prediction target set for the corresponding subroutine return instructions are stored in the return prediction stack; as well as In response to determining that the received set of one or more instructions includes a subroutine return instruction, one or more instructions of the prediction target group stored in the return prediction stack become the received set of one or more instructions in the next cycle; and RPS controller, the RPS controller is configured as follows: Monitor updates to one or more sets of instructions in the instruction cache to determine whether the updates affect one or more instructions in one or more prediction target sets stored in the return prediction stack; as well as In response to determining that an update affects one or more prediction target groups stored in the return prediction stack, one or more instructions stored in the return prediction stack are invalidated.

20. The processor of claim 19, wherein, The decoding logic is configured to make one or more instructions of the prediction target group stored in the returned prediction stack become one or more instructions of the received group in the next cycle in the following manner: Determine whether the returned prediction stack includes one or more instructions for a valid prediction target group; and In response to determining that the return prediction stack includes one or more instructions of a valid prediction target group, the one or more instructions of the valid prediction target group in the return prediction stack become one or more instructions of a received group in the next cycle.

21. The processor of claim 20, further comprising next bundle logic configured to generate an address for the next set of one or more instructions to be extracted based on a target address of a prediction stored in the return prediction stack in response to the partial decoding logic determining that the set of one or more instructions includes a subroutine return instruction.

22. The processor according to claim 21, wherein, The next beam logic is configured as follows: In response to the partial decoding logic determining that the return prediction stack includes one or more instructions of a valid prediction target group, the address of the next group of one or more instructions to be extracted is generated as an address offset from the target address of the prediction stored in the return prediction stack; as well as In response to the partial decoding logic determining that the return prediction stack does not include one or more instructions of a valid prediction target group, an address for the next group of one or more instructions to be extracted is generated as the target address of the prediction stored in the return prediction stack.

23. A method for retrieving instructions in a multi-level instruction fetch unit of a processor, the method comprising, in a cycle: Receive a set of one or more instructions for execution at part of the decoding logic; The received set of one or more instructions is at least partially decoded by the partial decoding logic to determine whether the received set of one or more instructions includes subroutine call and link instructions or subroutine return instructions; In response to determining that the received set of one or more instructions includes subroutine call and link instructions, one or more instructions of the prediction target set for the corresponding subroutine return instruction are stored in the return prediction stack; as well as In response to determining that the received set of one or more instructions includes a subroutine return instruction, one or more instructions of the prediction target group stored in the return prediction stack become the received set of one or more instructions in the next cycle; Monitor updates to one or more sets of instructions in the instruction cache to determine whether the updates affect one or more instructions in one or more prediction target sets stored in the return prediction stack; as well as In response to determining that an update affects one or more prediction target groups stored in the return prediction stack, one or more instructions stored in the return prediction stack are invalidated.

24. The method according to claim 23, wherein, Making one or more instructions stored in the returned prediction stack become one or more instructions received in the next cycle includes: Determine whether the returned prediction stack includes one or more instructions for a valid prediction target group; and In response to determining that the return prediction stack includes one or more instructions of a valid prediction target group, the one or more instructions of the valid prediction target group in the return prediction stack become one or more instructions of a received group in the next cycle.

25. The method of claim 24, further comprising, in response to determining that the set of one or more instructions includes a subroutine return instruction, generating an address for the next set of one or more instructions to be extracted based on a target address of a prediction stored in the return prediction stack.

26. The method of claim 25, wherein, Generating the address of the next set of one or more instructions to be extracted includes: In response to the partial decoding logic determining that the return prediction stack includes one or more instructions of a valid prediction target group, the address of the next group of one or more instructions to be extracted is generated as an address offset from the target address of the prediction stored in the return prediction stack; and In response to the partial decoding logic determining that the return prediction stack does not include one or more instructions of a valid prediction target group, an address for the next group of one or more instructions to be extracted is generated as the target address of the prediction stored in the return prediction stack.

27. A multi-level instruction fetch unit for use in a processor, the multi-level instruction fetch unit comprising: Return to the prediction stack; as well as Partial decoding logic, which communicates with the return prediction stack, is configured periodically as follows: Receives a set of one or more instructions for execution; At least partially decode a received set of one or more instructions to determine whether the received set of one or more instructions includes subroutine call and link instructions or subroutine return instructions; In response to determining that the received set of one or more instructions includes subroutine call and link instructions, one or more instructions of the prediction target set for the corresponding subroutine return instruction are stored in the return prediction stack in such a way as follows: Determine whether one or more instructions of the predicted target group are a group of one or more instructions that immediately follow the received group of one or more instructions; as well as In response to determining that one or more instructions of the predicted target group are not a group of one or more instructions immediately following the received group of one or more instructions, the received group of one or more instructions in the next cycle are stored in the return prediction stack; In response to determining that the received set of one or more instructions includes a subroutine return instruction, one or more instructions of the prediction target group stored in the return prediction stack become the received set of one or more instructions in the next cycle, wherein the one or more instructions of the prediction target group are a set of one or more instructions that immediately follow the delay slot instruction.

28. The instruction fetching unit according to claim 27, further comprising a branch predictor, wherein, The branch predictor is configured to predict the target address for the corresponding subroutine return instruction and store the predicted target address in the return prediction stack.

29. A method for retrieving instructions in a multi-level instruction fetch unit of a processor, the method comprising, in a cycle: Receives a set of one or more instructions for execution; At least partially decode a received set of one or more instructions to determine whether the received set of one or more instructions includes subroutine call and link instructions or subroutine return instructions; In response to determining that the received set of one or more instructions includes subroutine call and link instructions, one or more instructions of the prediction target set for the corresponding subroutine return instruction are stored in the return prediction stack in such a way as follows: Determine whether one or more instructions of the predicted target group are a group of one or more instructions that immediately follow the received group of one or more instructions; as well as In response to determining that one or more instructions of the predicted target group are not a group of one or more instructions immediately following the received group of one or more instructions, the received group of one or more instructions in the next cycle are stored in the return prediction stack; In response to determining that the received set of one or more instructions includes a subroutine return instruction, one or more instructions of the prediction target group stored in the return prediction stack become the received set of one or more instructions in the next cycle, wherein the one or more instructions of the prediction target group are a set of one or more instructions that immediately follow the delay slot instruction.

30. The method of claim 29 further includes predicting the target address for the corresponding subroutine return instruction and storing the predicted target address in the return prediction stack.

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