Pipeline computer system and instruction processing method

Abstract

The present disclosure relates to a pipelined computer system and a method for processing instructions. The pipelined computer system includes a processor circuit and a memory circuit. The processor circuit is configured to obtain a first target address of a first branch instruction and a second address of a first prediction instruction according to a first address of the first branch instruction before executing the first branch instruction, and sequentially prefetch a first instruction corresponding to the first target address and the first prediction instruction when a prediction result of the first branch instruction is a branch taken, wherein an execution order of the first prediction instruction is later than an execution order of the first instruction. The memory circuit is configured to temporarily store the first instruction and the first prediction instruction.

Description

TECHNICAL FIELD

[0001] The present application relates to computer systems, and more particularly, to pipelined computer systems with branch prediction mechanisms and instruction processing methods thereof. BACKGROUND

[0002] Instruction pipelining can increase the number of instructions executed per unit time. To further improve the efficiency of instruction processing, a branch prediction mechanism can be used to predict the execution result of a branch instruction (e.g., a jump instruction, a return instruction, etc.) to process the subsequent instructions in advance. However, when the predicted result of a branch instruction is branch not-taken, the existing branch prediction mechanism still cannot eliminate most of the bubbles in the instruction processing process. SUMMARY

[0003] In some embodiments, a pipelined computer system includes a processor circuit and a memory circuit. The processor circuit is configured to, before executing a first branch instruction, obtain a first target address of the first branch instruction and a second address of a first prediction instruction according to a first address of the first branch instruction, and in sequence, pre-fetch a first instruction corresponding to the first target address and the first prediction instruction when a predicted result of the first branch instruction is branch taken, wherein the execution order of the first prediction instruction is later than that of the first instruction. The memory circuit is configured to temporarily store the first instruction and the first prediction instruction.

[0004] In some embodiments, an instruction processing method includes the following operations: before executing a first branch instruction, obtaining a first target address of the first branch instruction and a second address of a first prediction instruction according to a first address of the first branch instruction; and in sequence, pre-fetching a first instruction corresponding to the first target address and the first prediction instruction when a predicted result of the first branch instruction is branch taken, wherein the execution order of the first prediction instruction is later than that of the first instruction.

[0005] The features, implementations, and effects of the present application are described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0006] Figure 1 A schematic diagram of a pipelined computer system according to some embodiments of the present application is shown;

[0007] Figure 2 A flowchart of an instruction processing method according to some embodiments of the present application is shown;

[0008] Figure 3A A schematic diagram of a pipelined computer system according to some embodiments of the present application is shown; Figure 1A diagram illustrating how a pipelined computer system executes multiple instructions sequentially;

[0009] Figure 3B Drawing based on some embodiments of this case Figure 3A A flowchart illustrating the execution of multiple instructions;

[0010] Figure 4A Drawing based on some embodiments of this case Figure 1 A diagram illustrating how a pipelined computer system executes multiple instructions sequentially;

[0011] Figure 4B Drawing based on some embodiments of this case Figure 3A Flowcharts of the execution of multiple instructions; and

[0012] Figure 5 Drawing based on some embodiments of this case Figure 1 A diagram illustrating how a pipelined computer system executes multiple instructions sequentially. Detailed Implementation

[0013] All terms used herein have their common meanings. The definitions of the terms used in commonly used dictionaries, and any examples of the use of any term discussed herein, are merely illustrative and should not be construed as limiting the scope or meaning of this document. Similarly, this document is not limited to the various embodiments shown in this specification.

[0014] As used herein, "coupling" or "connection" can refer to two or more components making direct physical or electrical contact with each other, or indirectly making direct physical or electrical contact with each other, or to two or more components operating or moving together. As used herein, the term "circuit" can refer to a single system formed by at least one circuit, and the term "circuit" can refer to a device that processes signals by connecting at least one transistor and / or at least one active or passive component in a certain manner.

[0015] As used herein, the term "and / or" includes any combination of one or more of the listed related items. In this document, the terms first, second, third, etc., are used to describe and distinguish individual elements. Therefore, a first element in this document may also be referred to as a second element without departing from the intent of this case. For ease of understanding, similar elements in the various diagrams will be designated with the same reference numerals.

[0016] Figure 1FIG. 1 is a schematic diagram of a pipeline computer system 100 according to some embodiments. In some embodiments, the pipeline computer system 100 can be applied to general electronic products, such as including but not limited to personal computers, notebook computers, display cards, servers, tablet computers, smart phones, televisions, network devices, and the like. The pipeline computer system 100 includes a processor circuit 110, a main memory 120, and an input / output (I / O) device 130. The main memory 120 is used to store instructions and / or data. The I / O device 130 can receive (or output) instructions (or data).

[0017] In some embodiments, the processor circuit 110 is a pipeline processor circuit, which can allow multiple instructions to run in overlap. For example, the processor circuit 110 can include a program counter circuit (not shown), an instruction memory (not shown), at least one multiplexer circuit (not shown), at least one register circuit (not shown), and at least one data memory circuit (not shown), which form multiple data paths to process multiple instructions in parallel. The above-described arrangement of data paths of the processor circuit 110 is used for example, and the present disclosure is not limited thereto.

[0018] In some embodiments, a core portion of the processor circuit 110 includes an instruction fetch circuit 112, and the processor circuit 110 further includes a memory circuit 114. The instruction fetch circuit 112 can be used to determine a prediction result of a branch instruction as branch-taken or branch-untaken, and to prefetch corresponding instructions from the main memory 120 (or the memory circuit 114) in advance according to the prediction result. In some embodiments, the instruction fetch circuit 112 includes a branch prediction mechanism (not shown) to determine the above-mentioned prediction result and to store a lookup table (such as Tables 1 and 2 described later). In some embodiments, the branch prediction mechanism can determine the prediction result of a current branch instruction according to a history record of previous instruction execution, where the history record can be stored as the lookup table. In some embodiments, the branch prediction mechanism can perform a global-sharing (g-share) algorithm, or perform a tagged geometric history length branch prediction (TAGE) algorithm to determine the prediction result of a branch instruction. The above-mentioned algorithm types are used for example, and the present disclosure is not limited thereto. Various related algorithms that can be used for branch prediction are all within the scope of the present disclosure. The above-mentioned related operations of branch prediction and prefetching will be described in the following paragraphs.

[0019] In some embodiments, memory circuitry 114 may be a temporary register for temporarily storing instructions and / or data pre-fetched by instruction fetch circuitry 112. In some embodiments, memory circuitry 114 may be a cache, which may contain a complete cache hierarchy. For example, memory circuitry 114 may contain only L1 cache, or may contain L1 cache and L2 cache, or may contain L1 cache, L2 cache, and L3 cache. The above description of the types of memory circuitry 114 is for illustrative purposes only and is not intended to limit the scope of this invention.

[0020] Figure 2 A flowchart of an instruction processing method 200 is provided according to some embodiments of this case. In some embodiments, the instruction processing method 200 may be (but is not limited to) [the following methods]. Figure 1 The processor circuit 110 executes.

[0021] In operation S210, before executing the first branch instruction (e.g., branch instruction B), the first address of the first branch instruction (e.g., address ADDR in Table 1) is used. B Obtain the first target address of the first branch instruction (e.g., address ADDR3 in Table 1) and the second address of the first prediction instruction (e.g., branch instruction C) (e.g., address ADDR3 in Table 1). C In operation S220, when the prediction result of the first branch instruction is that the jump is true, the first instruction and the first predicted instruction corresponding to the first target address are retrieved in advance in sequence, wherein the execution order of the first predicted instruction is after the execution order of the first instruction.

[0022] The above operations are merely examples and are not intended to be performed in the order shown in these examples. Without departing from the operational methods and scope of the embodiments of this invention, various operations in instruction processing method 200 may be appropriately added, replaced, or omitted. Alternatively, one or more operations in instruction processing method 200 may be performed simultaneously or partially simultaneously.

[0023] To further explain instruction processing method 200, refer to Figure 3A and Figure 3B , Figure 3A Drawing based on some embodiments of this case Figure 1 A schematic diagram of a pipelined computer system 100 executing multiple instructions sequentially, and Figure 3B Drawing based on some embodiments of this case Figure 3A A flowchart illustrating the execution of multiple instructions.

[0024] like Figure 3AAs shown, the processor circuit 110 sequentially executes a series of instructions 1, A, 2, 3, B, C, 4, and D from top to bottom. In this example, assume that instruction A, instruction B, instruction C, and instruction D are branch instructions, instruction 2 is the instruction corresponding to the target address of instruction A, instruction 3 is the instruction corresponding to the target address of instruction B, and instruction 4 is the instruction corresponding to the target address of instruction C. In some embodiments, the branch instructions can be, but are not limited to, conditional branch instructions and / or unconditional branch instructions.

[0025] As mentioned above, the processor circuit 110 stores a lookup table. In some embodiments, the lookup table records the correspondence between the first address, the first target address, and the second address. For example, the lookup table can be represented as Table 1 below:

[0026] Address of branch instruction Target address of branch instruction Address of next predicted instruction ADDR A ]]> ADDR2 ADDR B ]]> ADDR B ]] ADDR3 ADDR C ]]> ADDR C ]]> ADDR4 ADDR D ]]> ADDR C' ]]> ADDR 4' ]]> ADDR D' ]]>

[0027] In Table 1 above, the address of the branch instruction (i.e., the first address) represents the storage address of the branch instruction in the main memory 120 (or the memory circuit 114). The target address of the branch instruction (i.e., the first target address) is the storage address of the instruction to be executed when the prediction result of the branch instruction is true. The execution order of the next predicted instruction is next to the execution order of the instruction corresponding to the target address. For example, the instruction corresponding to the target address ADDR2 is instruction 2, and the next predicted instruction is instruction B which is executed after instruction 2. Thus, when the processor circuit 110 executes the branch instruction A, the instruction fetch circuit 112 can obtain the target address ADDR2 and the address ADDR3 of the next predicted instruction (i.e., the branch instruction B) according to the storage address ADDR1 of the branch instruction A and the lookup table. A The lookup table is searched to obtain the target address ADDR2 and the address ADDR3 of the next predicted instruction (i.e., the branch instruction B). B In other words, the address of the branch instruction corresponds to the tag of the lookup table. If the tag in the lookup table is hit, it means that the processor circuit 110 is executing the branch instruction corresponding to the tag, and the processor circuit 110 can obtain the corresponding target address and the storage address (i.e., the second address) of the next predicted instruction. As shown, the instruction fetch circuit 112 can predict (as shown by the dashed line) the target address and the address of the next predicted instruction according to the address of the branch instruction. Figure 3A

[0028] In different embodiments, the address of the next predicted instruction in Table 1 above can be an offset value or an absolute address. If the address of the next predicted instruction is an offset value, the processor circuit 110 can add the corresponding target address and the corresponding relative offset to determine the actual storage address of the next predicted instruction.

[0029] In some embodiments, as shown in Table 2 below, the lookup table can record the correspondence between the first address, the first target address, and the second address.​Figure 3B As shown, the instruction processing of the pipelined computer system 100 can be divided into multiple levels, which sequentially include: instruction fetch (labeled 1_IF), instruction tag matching (labeled 2_IX), instruction buffer (3_IB), instruction decoding (labeled 4_ID), instruction sending (labeled 5_IS), operand fetch (labeled 6_OF), execution (labeled 7_EX), and write-back (labeled 8_WB). The above-described multiple levels of the instruction processing are for illustrative purposes and are not limited thereto. In some embodiments, before the processor circuit 110 processes a branch instruction (e.g., branch instruction B) in level 1 (i.e., 1_IF), the instruction fetch circuit 112 may begin to determine the prediction result of this branch instruction and search a lookup table (e.g., Table 1 above) based on the address of this branch instruction to obtain the target address of this branch instruction and the address of the next predicted instruction. If the prediction result indicates a jump is possible, processor circuit 110 can pre-fetch the instruction corresponding to the target address (e.g., instruction 3) at level 3 (i.e., 3_IB). Next, processor circuit 110 can pre-fetch the next predicted instruction (e.g., branch instruction C) at level 4 (i.e., 4_ID). It should be understood that, depending on the actual hardware architecture, processor circuit 110 (and / or instruction fetching circuit 112) can pre-fetch the instruction corresponding to the target address and the next predicted instruction at an earlier or later stage.

[0030] Specifically, at time T, processor circuit 110 begins processing instruction 1. At time T+1, processor circuit 110 begins processing branch instruction A, and instruction fetch circuit 112 begins determining the prediction result of branch instruction A. Simultaneously, instruction fetch circuit 112 determines the prediction result of branch instruction A based on address ADDR. A Read the lookup table to obtain the target address ADDR2 and the address ADDR of the next predicted instruction. B (Right now Figure 2 Operation S210).

[0031] At time T+2, since it has not yet been confirmed whether branch instruction A has successfully executed, processor circuit 110 begins processing the next instruction after branch instruction A (e.g., ...). Figure 5 In this example, the predicted result of branch instruction A is a jump, so processor circuit 110 flushes the next instruction. Under this condition, a pause (bubble) will occur during period T+2.

[0032] During period T+3, instruction fetch circuit 112 confirms that the predicted result of branch instruction A is a jump (denoted as 3_IB / direct2). In response to this prediction result, processor circuit 110 can pre-fetch instruction 2 (i.e., ...) based on the target address ADDR2. Figure 2 (Operation S220). Simultaneously, if address ADDR...B The corresponding next prediction instruction (i.e., instruction B) is a branch instruction. The instruction fetch circuit 112 can start to determine the prediction result of the branch instruction B, and according to the address ADDR B The lookup table is read to obtain the target address ADDR3 and the address ADDR C (i.e. Figure 2 of operation S210).

[0033] At time T+4, the processor circuit 110 starts to process the branch instruction B (i.e. Figure 2 of operation S220). In other words, the prediction result of the branch instruction B can be determined at a time (i.e., time T+3) before the branch instruction B is executed (i.e., time T+4).

[0034] At time T+5, the instruction fetch circuit 112 confirms that the prediction result of the branch instruction B is taken (denoted as 3_IB / direct3). In response to the prediction result, the processor circuit 110 can start to process (i.e., pre-fetch) instruction 3 (i.e. Figure 2 of operation S220) according to the target address ADDR3. In other words, after the execution of instruction B, the processor circuit 110 can pre-fetch instruction 3 without time delay (i.e., without causing stall). Meanwhile, since the address ADDR C The corresponding next prediction instruction is the branch instruction C. The instruction fetch circuit 112 can start to determine the prediction result of the branch instruction C, and according to the address ADDR C The lookup table is read to obtain the target address ADDR4 and the address ADDR D (i.e. Figure 2 of operation S210). At time T+6, the processor circuit 110 pre-fetches the branch instruction C corresponding to the address ADDR C to start to process the branch instruction C (i.e. Figure 2 of operation S220). In other words, during the operation from time T+4 to time T+6, the processor circuit 110 can sequentially execute the branch instruction B, instruction 2 and the branch instruction C without causing stall. By analogy, during time T+7 to time T+10, if the prediction results of the subsequent branch instructions C and D are both taken, the stalls in the instruction processing process will be eliminated.

[0035] In some related technologies, the branch prediction mechanism only fetches the target address when the jump is successful based on the address of the branch instruction. In the above technologies, even if the prediction result of the branch instruction is that the jump is successful, a pause will still occur before the instruction corresponding to the target address is executed. Compared with the above technologies, by using the setting method in Table 1 above, most pauses in the instruction processing process can be eliminated. In this way, the instruction processing efficiency of the processor circuit 110 can be improved.

[0036] Reference Figure 4A and Figure 4B , Figure 4A Drawing based on some embodiments of this case Figure 1 A schematic diagram of a pipelined computer system 100 executing multiple instructions sequentially, and Figure 4B Drawing based on some embodiments of this case Figure 4A A flowchart of the execution of multiple instructions.

[0037] In this example, the operations of processing instruction 1, branch instruction A, instruction 2, branch instruction B, and instruction 3 are the same as... Figure 3B Therefore, it will not be elaborated further here. During T+5, the instruction fetch circuit 112 begins to determine the prediction result of branch instruction C, and based on the address ADDR of branch instruction C... C Read the lookup table to obtain the target address ADDR4 and the address ADDR of the next predicted instruction. D (Right now Figure 2 (Operation S210). During T+6, processor circuit 110 begins processing branch instruction C. Simultaneously, instruction fetch circuit 112 begins determining the prediction result of branch instruction C' and, based on the address ADDR of branch instruction C'... C' Read the lookup table to obtain the target address ADDR. 4' and the address ADDR of the next prediction instruction (i.e., the branch instruction D'). D' (Right now Figure 2 (Operation S210). It should be understood that the execution order of branch instruction C' is after the execution order of branch instruction C, and the execution order of branch instruction D' is after the target address ADDR. 4' The execution order of the corresponding instruction 4'. During period T+7, the instruction fetching circuit 112 confirms that the predicted result of branch instruction C is that the jump is not valid. Therefore, the processor circuit 110 begins processing (i.e., sequentially fetching) branch instruction C' during period T+7. During period T+8, the instruction fetching circuit 112 confirms that the predicted result of branch instruction C' is that the jump is valid (marked as 3_IB / direct4'), and executes the branch instruction D' according to the address ADDR. D' Search the lookup table to obtain the corresponding target address and the address of the next predicted instruction (not shown). Figure 2(S210). Simultaneously, the instruction fetch circuit 112 can begin determining the prediction result of the branch instruction D' during period T+8, and the processor circuit 110 can pre-fetch instruction 4' during period T+8 and pre-fetch the branch instruction D' during period T+9. In other words, in this example, if the prediction result of the branch instruction C is that the jump is invalid, the processor circuit 110 can execute the branch instructions C', 4', and D' sequentially without causing a pause.

[0038] In the aforementioned related technologies, if the predicted branch instruction indicates a false jump, at least one pause will still occur. In other related technologies, the branch prediction mechanism obtains the target address of the next branch instruction (if the prediction result is a false jump) based on the target address of the branch instruction. In the above technologies, if the prediction result is a false jump, several pauses (e.g., four) will occur. Compared to the aforementioned related technologies, by using the configuration in Table 1 above, when the predicted branch instruction result is a false jump, the processor circuit 110 can execute multiple instructions without causing a pause.

[0039] Reference Figure 5 , Figure 5 Drawing based on some embodiments of this case Figure 1 A schematic diagram of a pipelined computer system 100 executing multiple instructions sequentially. In some embodiments, the processor circuit 110 is further configured to obtain the address of another predicted instruction (e.g., branch instruction A') based on the address of a branch instruction (e.g., branch instruction A), and to begin processing the other predicted instruction A' when the prediction result of branch instruction A is that the jump is not true. In other words, compared to Figure 3A or Figure 4A The instruction fetching circuit 112 can predict (as shown by the dashed line) the target address, the address of the next predicted instruction (if the jump is successful), and the address of the next predicted instruction (if the jump is not successful) based on the address of the branch instruction.

[0040] exist Figure 5 In the example, the aforementioned lookup table can be represented as Table 2 below:

[0041]

[0042] In other words, in this example, the lookup table (i.e., Table 2 above) is used to record the correspondence between the address of the branch instruction, the target address of the branch instruction, the address of the next predicted instruction (if the prediction result is a jump that is true), and the address of the next predicted instruction (if the prediction result is a jump that is not true).

[0043] For example, before the processor circuit 110 starts processing branch instruction A, the instruction fetching circuit 112 can fetch the instruction based on the address ADDR of branch instruction A. AThe processor circuit 110 (and the instruction fetch circuit 112) can start to determine the prediction result of the branch instruction A, and obtain the corresponding target address ADDR2, the address ADDR of the next predicted instruction B (if the prediction result is branch taken), and the address ADDR of the next predicted instruction A' (if the prediction result is branch not taken) from Table 2. B and the address ADDR of the next predicted instruction A' (if the prediction result is branch not taken). In this way, if the prediction result is branch not taken, the processor circuit 110 (and the instruction fetch circuit 112) can start to process (i.e., pre-fetch) the corresponding next predicted instruction to eliminate more stall. A' and the address ADDR of the next predicted instruction A' (if the prediction result is branch not taken). In this way, if the prediction result is branch not taken, the processor circuit 110 (and the instruction fetch circuit 112) can start to process (i.e., pre-fetch) the corresponding next predicted instruction to eliminate more stall. A' 2' and the address ADDR of the next predicted instruction A' (if the prediction result is branch not taken). In this way, if the prediction result is branch not taken, the processor circuit 110 (and the instruction fetch circuit 112) can start to process (i.e., pre-fetch) the corresponding next predicted instruction to eliminate more stall.

[0044] In summary, by the pipelined computer system and the instruction processing method according to some embodiments of the present application, the stall in the instruction processing process can be effectively eliminated to improve the overall instruction processing efficiency.

[0045] Although the embodiments of the present application are described above, the embodiments are not intended to limit the present application. Those skilled in the art can make changes to the technical features of the present application according to the explicit or implicit content of the present application, and such changes can all fall within the scope of the patent protection sought by the present application. In other words, the scope of the patent protection of the present application shall be subject to the scope of the patent application defined in the specification.

[0046]

Symbol Description

[0047] 100: pipelined computer system

[0048] 110: processor circuit

[0049] 112: instruction fetch circuit

[0050] 114: memory circuit

[0051] 120: main memory

[0052] 130: input / output device

[0053] 200: instruction processing method

[0054] S210, S220: operations

[0055] 1, 2, 2', 3, 4, 4': instructions

[0056] A, A', B, B', C, C', D, D': branch instructions ​

[0057] 1_IF: fetch instructions

[0058] 2_IX: instruction tag comparison

[0059] 3_IB: instruction buffer

[0060] 4_ID: instruction decode

[0061] 5_IS: instruction send

[0062] 6_OF: operand fetch

[0063] 7_EX: execute

[0064] 8_WB: write back

[0065] T, T+1, T+2, T+3, T+4, T+5, T+6, T+7, T+8, T+9, T+10: periods

Claims

1. A pipelined computer system, comprising: a processor circuit configured to obtain a first target address of a first branch instruction and a second address of a first prediction instruction based on a first address of the first branch instruction before execution of the first branch instruction, and to speculatively fetch a first instruction corresponding to the first target address and the first prediction instruction in sequence when a prediction result of the first branch instruction is a branch taken, wherein an execution order of the first prediction instruction is later than an execution order of the first instruction, and the first instruction and the first prediction instruction are executed consecutively; and a memory circuit configured to temporarily store the first instruction and the first prediction instruction.

2. The pipelined computer system of claim 1, wherein the processor circuit is configured to search a lookup table based on the first address to obtain the first target address and the second address, and the lookup table is configured to record a correspondence among the first address, the first target address, and the second address.

3. The pipelined computer system of claim 1, wherein the processor circuit is further configured to obtain a second target address of a second branch instruction and a fourth address of a second prediction instruction based on a third address of the second branch instruction, wherein an execution order of the second branch instruction is later than the execution order of the first branch instruction, and if the prediction result is a branch not taken, the processor circuit is further configured to start processing the second branch instruction.

4. The pipelined computer system of claim 1, wherein the prediction result of the first branch instruction is determined during a period before the first branch instruction is executed.

5. The pipelined computer system of claim 1, wherein the processor circuit is further configured to obtain a third address of a second prediction instruction based on the first address, and to start processing the second prediction instruction when the prediction result is a branch not taken.

6. The pipelined computer system of claim 5, wherein the processor circuit is configured to search a lookup table based on the first address to obtain the first target address, the second address, and the third address, and the lookup table is configured to record a correspondence among the first address, the first target address, the second address, and the third address.

7. An instruction processing method, comprising: obtaining a first target address of a first branch instruction and a second address of a first prediction instruction based on a first address of the first branch instruction before execution of the first branch instruction; and speculatively fetching a first instruction corresponding to the first target address and the first prediction instruction in sequence when a prediction result of the first branch instruction is a branch taken, wherein an execution order of the first prediction instruction is later than an execution order of the first instruction, and the first instruction and the first prediction instruction are executed consecutively.

8. The instruction processing method of claim 7, further comprising: obtaining a second target address of a second branch instruction and a fourth address of a second prediction instruction based on a third address of the second branch instruction, wherein an execution order of the second branch instruction is later than the execution order of the first branch instruction; and If the prediction result is not a branch taken, start processing the second branch instruction.

9. The instruction processing method of claim 8, wherein the second predicted instruction is executed after a instruction corresponding to the second target address.

10. The instruction processing method of claim 7, further comprising: obtaining a third address of a second predicted instruction according to the first address; and starting processing the second predicted instruction if the prediction result is not a branch taken.

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