Multi-bit vector-matrix product operator based on 8T-SRAM unit

Abstract

The present invention discloses a multi-bit vector-matrix product operator based on 8T-SRAM cells, comprising: a row multi-channel digital-to-analog converter, an operation array, an SRAM bit read-write circuit, an SRAM row selection circuit, a column multi-channel analog-to-digital converter and a post-processing circuit; the row multi-channel digital-to-analog converter is used to convert an input data binary number into a corresponding current; the operation array is composed of M rows and N×P columns of 8T-SRAM cells, and is used for the storage of a weight matrix and the product operation of an input current and a weight matrix; the column multi-channel analog-to-digital converter is used to convert an output current difference on a read bit line corresponding to the jth column into a binary number D j ; The post-processing circuit is used to j The corresponding left shift operation is performed, the corresponding column unit is given a corresponding binary weight, and the outputs of adjacent P channels after left shift are summed to obtain the final vector output. The present invention does not need to increase the unit area too much, avoids mutual interference of storage potentials, and can improve the forward propagation efficiency of the neural network.

Description

Technical Field

[0001] The present invention relates to the technical field of operators, and more specifically to a multi-bit vector-matrix product operator based on 8T-SRAM units. Background Art

[0002] The traditional computer architecture is dominated by the von Neumann architecture, which separates the computing unit and the data storage unit. When data needs to be calculated, the data will be moved from the data storage unit to the computing unit for the corresponding calculation, and then moved back to the data storage unit. The advantage of this architecture is that the division of labor of each functional module is clear. Each functional module can make special optimizations and technical evolutions according to its own positioning, so that the performance of each subsystem is continuously optimized to achieve the improvement of the entire computing system. The data storage unit has developed a hierarchical storage architecture according to different application requirements, such as registers, tightly coupled memories, caches at all levels, and various remote large-capacity storage, and uses different technical routes to optimize the above different types of storage requirements. The problem with the von Neumann architecture is that the back and forth movement of data between the storage unit and the computing unit in the system may become the performance bottleneck of the system, consuming a lot of power. The rise of new applications such as artificial intelligence involving large-scale data processing has exacerbated the above performance bottleneck.

[0003] A feasible solution to the "memory wall" problem of the above-mentioned von Neumann architecture is to introduce in-memory computing, that is, to give the storage unit a certain computing power so that some data can complete the corresponding computing operations without being moved to the computing unit, thereby reducing the energy consumption of moving data between the storage unit and the computing unit and improving system performance.

[0004] According to the different processes used by the memory, current in-memory computing can be roughly divided into SRAM-based in-memory computing, flash-based in-memory computing, and new NVM-based in-memory computing. SRAM memory is very common in digital systems because it does not require special processes and additional masks, so it is worth optimizing through in-memory computing technology.

[0005] The paper "A 64-Tile 2.4-Mb In-Memory-Computing CNN Accelerator Employing Charge-Domain Compute" introduces a method to accelerate CNN (convolutional neural network) operations based on SRAM in-memory computing. Figure 1As shown in the figure, in order to achieve the required in-memory computing operation, the article adds two transistors M7 and M8 on the basis of the traditional 6T-SRAM cell as the switches required for the in-memory computing operation, connecting the points Wnijk and Wbnijk storing the binary weights to a newly added capacitor in the cell. According to the potential stored in Wnijk and Wbnijk, and the different gate potentials of M7 and M8, it can be achieved Figure 1 The XNOR logic shown in the table on the right is the product operation of 1-bit input and 1-bit weight, and the result is temporarily stored on the capacitor in the unit. Then the capacitors of multiple units are connected to the bottom read bit line at the same time, and the multi-bit multiplication result is obtained. However, this structure has the following problems: 1. The storage unit circuit is complex. On the basis of the classic 6-transistor SRAM unit (6T-SRAM unit), more devices are added, even including devices with large area consumption such as capacitors, which greatly increases the unit area. 2. In-memory calculation operations usually connect the bit information storage point of the unit directly to the read bit line. Since the read bit line may be connected to the storage points of multiple storage units at the same time in the in-memory calculation operation, this operation may cause multiple storage potentials connected to the read bit line to interfere with each other and destroy the stored bit information. 3. In most in-memory calculation schemes based on SRAM units, each unit only undertakes binary multiplication operations, that is, both operands of the multiplication are 1 bit, which imposes restrictions on the neural network that can be applied, that is, the neural network needs to support 1-bit weight or network input.

[0006] Therefore, how to provide a multi-bit vector-matrix product operator based on 8T-SRAM cells that does not increase the cell area too much, avoids interference between storage potentials, and improves the forward propagation efficiency of the neural network is an urgent problem that technical personnel in this field need to solve. Summary of the invention

[0007] In view of this, the present invention provides a multi-bit vector-matrix product operator based on 8T-SRAM units, which does not require too much increase in unit area, avoids mutual interference of storage potentials, and can improve the forward propagation efficiency of the neural network.

[0008] In order to achieve the above object, the present invention adopts the following technical solution:

[0009] A multi-bit vector-matrix product operator based on an 8T-SRAM unit, comprising: a row multi-channel digital-to-analog converter, an operation array, an SRAM bit read-write circuit, an SRAM row selection circuit, a column multi-channel analog-to-digital converter and a post-processing circuit; the write bit line and the select word line of the operation array are connected to the SRAM bit read-write circuit; the select word line of the operation array is connected to the SRAM row selection circuit; the read word line of the operation array is connected to the row multi-channel digital-to-analog converter; the read bit line of the operation array is connected to the column multi-channel analog-to-digital converter;

[0010] The row multi-channel digital-to-analog converter is composed of M digital-to-analog converters, which are used to convert the input data B i The K-bit binary number is converted into the corresponding current I i and through the read word line RWL of the operation array i Enter into the corresponding i-th row;

[0011] The operation array consists of M rows and N×P columns of 8T-SRAM cells, which are used to store the weight matrix and the input current I i The product operation of the weight matrix is ​​performed, and the SRAM bit read and write circuit and the SRAM row selection circuit complete the write and read operations on the 8T-SRAM unit;

[0012] The column multi-channel analog-to-digital converter is composed of N×P analog-to-digital converters, each of which corresponds to a column of the operation array and is used to convert the output current I on the read bit lines RBL and RBLN of the corresponding j-th column op,j and I on,j The difference is converted to binary number D j ;

[0013] The post-processing circuit is used to j The corresponding left shift operation is performed to give the corresponding column unit an additional binary weight, and the outputs of the adjacent P channels after left shift are summed to obtain the final vector output.

[0014] Preferably, in the above-mentioned multi-bit vector-matrix product operator based on 8T-SRAM unit, the 8T-SRAM unit is composed of 8 transistors M0-M7, a selection word line WL, write bit lines BL and BLN, a read word line RWL, and read bit lines RBL and RBLN; wherein the transistors M0-M5 constitute a 6T-SRAM unit for bit storage of the weight matrix; the transistor M6 is respectively connected to the storage potential Q, the read word line RWL, and the read bit line RBL; the transistor M7 is respectively connected to the storage potential QN, the read word line RWL, and the read bit line RBLN;

[0015] Transistors M6 and M7 provide a set of differential current paths according to the stored bit pair Q-QN, and direct the current given by the read word line RWL to the read bit line RBL or RBLN; when Q=1 and QN=0, transistor M6 is turned on and M7 is turned off, and the current on the read word line RWL flows to the read bit line RBL through M6; when Q=0 and QN=1, transistor M6 is turned off and M7 is turned on, and the current on the read word line RWL flows to the read bit line RBL through M7; the word line WL is selected to drive transistors M4 and M5, so that the storage potentials Q and QN are connected to the write bit lines BL and BLN, and the SRAM bit read and write circuit performs 0-1 binary information read and write operations on the storage potentials Q and QN through the write bit lines BL and BLN.

[0016] Preferably, in the above-mentioned multi-bit vector-matrix product operator based on 8T-SRAM units, the current flowing through each of the 8T-SRAM units is I u，i =I i / (NP), indicating that the row input current will be evenly divided among N×P row cells.

[0017] Preferably, in the above-mentioned multi-bit vector-matrix product operator based on 8T-SRAM unit, the analog-to-digital converter includes two sampling capacitors C P and C N , switches S0 to S5 and a differential quantizer; wherein one end of switch S0, one end of switch S1 and one end of switch S2 are connected to each other and connected to the sampling capacitor C p One end of the sampling capacitor C p The other end of switch S0 is connected to the reference potential V REF The other end of switch S1 is connected to the read bit line RBL j The other end of switch S2 is connected to the positive electrode of the differential quantizer; one end of switch S3, one end of switch S4 and one end of switch S5 are connected to each other and connected to the sampling capacitor C N One end of the sampling capacitor C N The other end of switch S3 is connected to the reference potential V REF The other end of switch S4 is connected to the read bit line RBLN j The other end of the switch S5 is connected to the negative electrode of the differential quantizer; the differential quantizer is used to connect the sampling capacitor C P and C N The potential difference is quantized into a binary digital output D j .

[0018] Preferably, in the above-mentioned multi-bit vector-matrix product operator based on 8T-SRAM unit, the analog-to-digital converter includes three working stages: a pre-charging stage, a sampling stage and a quantization stage;

[0019] In the pre-charging stage, switches S0 and S3 are closed, S1, S2, S4, and S5 are disconnected, and the sampling capacitor C P and C N The upper plate will be charged or discharged to a reference potential V during the precharge phase. REF ;

[0020] During the sampling phase, switches S1 and S4 are closed, switches S0, S2, S3, and S5 are open, and the sampling capacitor C P and C N They are connected to read bit lines RBL and RBLN respectively. The read bit line current is the sum of the differential output currents of each cell on the column. The read bit line current charges or discharges the sampling capacitor. After the sampling phase, the potential value of the sampling capacitor is linearly related to the read bit line current.

[0021] In the quantization stage, switches S2 and S5 are closed, S0, S1, S3, and S4 are disconnected, and the sampling capacitor C P and C N Connected to the two ends of the differential quantizer, the potential difference between the two capacitors V CP -V CN Quantized into binary digital output D j .

[0022] Preferably, in the above-mentioned multi-bit vector-matrix product operator based on 8T-SRAM cells, the post-processing circuit is used to divide the 8T-SRAM cells into N groups, and each group contains P columns of adjacent 8T-SRAM cells, and assigns different binary weights to each group of P D j The final output O is obtained by binary weighted summation. n .

[0023] Preferably, in the above-mentioned multi-bit vector-matrix product operator based on 8T-SRAM units, the final output O corresponding to the nth group of 8T-SRAM units n The expression is as follows:

[0024]

[0025] The above formula indicates that the output D of the qth column in each group of 8T-SRAM cells is q Shift left by q bits, and then add the left-shifted output to get the corresponding output O n ; Wherein, q=j modP, indicating that q is obtained by performing a modulo operation on P by j; n=0~N-1, j is the column number of the qth column in each group of 8T-SRAM cells in the entire array, j=0~N×P-1.

[0026] Preferably, in the above-mentioned multi-bit vector-matrix product operator based on 8T-SRAM unit, the read bit line RWLi The connected digital-to-analog converter is a multi-bit current-type digital-to-analog converter.

[0027] Preferably, in the above-mentioned multi-bit vector-matrix product operator based on 8T-SRAM cells, when the operation array performs an in-memory operation read operation, the driving current on the read bit line RWL is proportional to the multi-bit binary input of the digital-to-analog converter, and is evenly divided in the 8T-SRAM cells in the same row, and is allocated to the RBL corresponding to the 8T-SRAM cell according to the 0-1 information stored in the 8T-SRAM cell. i or RBLN i The output current of all 8T-SRAM cells in the same column is on the corresponding read bit line BL i and RBLN i Add up on.

[0028] It can be seen from the above technical solution that, compared with the prior art, the present invention discloses a multi-bit vector-matrix product operator based on 8T-SRAM unit, which has the following beneficial effects:

[0029] 1. The present invention converts input data into current through a multi-channel digital-to-analog converter connected by a read word line (RWL). When performing an in-memory operation read operation, the driving current on the read word line RWL is proportional to the multi-bit binary input of the digital-to-analog converter, and the current is distributed and accumulated on the corresponding read word line through the 8T-SRAM unit, which can more efficiently support the multiplication operation of the multi-bit binary input vector.

[0030] 2. The gates of the two transistors M6 and M7 in the 8T-SRAM unit involved in the in-memory operation read operation of the present invention are connected to the unit's weight storage potentials Q and QN. Since the transistor gate is high impedance, when performing in-memory operation read operations, the storage potentials Q and QN are well isolated from the read word lines RBL and RBLN, ensuring that the in-memory operation does not affect the storage of weights. At the same time, M6 and M7 are used as switch tubes, and the minimum size allowed by the process can be used, which is smaller than the area increased by the traditional 6T-SRAM.

[0031] 3. The present invention groups P adjacent SRAM cells into a group and assigns different binary weights to represent the P-bit binary weights. Accordingly, the output values ​​(D i ) with the corresponding binary weights, weighted summation can be used to obtain the result of multi-bit vector-matrix product O n , achieving the purpose of supporting multiplication operations of multi-bit binary weight matrices. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0033] Figure 1 It is a structural schematic diagram of an SRAM unit in the prior art;

[0034] Figure 2 The overall structural diagram of the multi-bit vector-matrix product operator based on 8T-SRAM unit provided by the present invention;

[0035] Figure 3 A schematic diagram of the structure of a single 8T-SRAM unit in the computing array provided by the present invention;

[0036] Figure 4 This is a schematic diagram of the structure of a single analog-to-digital converter in the multi-channel analog-to-digital converter provided by the present invention. DETAILED DESCRIPTION

[0037] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0038] like Figure 2 As shown, the embodiment of the present invention discloses a multi-bit vector-matrix product operator based on an 8T-SRAM unit, comprising: a row multi-channel digital-to-analog converter, an operation array, an SRAM bit read-write circuit, an SRAM row selection circuit, a column multi-channel analog-to-digital converter and a post-processing circuit; the write bit lines (BL and BLN) of the operation array are connected to the SRAM bit read-write circuit; the select word lines (WL) of the operation array are connected to the SRAM row selection circuit; the read word lines (RWL) of the operation array are connected to the row multi-channel digital-to-analog converter; the read bit lines (RBL and RBLN) of the operation array are connected to the column multi-channel analog-to-digital converter;

[0039] The multi-channel digital-to-analog converter is composed of M digital-to-analog converters, which are used to convert the input data B i The K-bit binary number is converted into the corresponding current I i and through the read word line RWL of the operation array i Enter into the corresponding i-th row;

[0040] The operation array consists of M rows and N×P columns of 8T-SRAM cells, which are used to store the weight matrix and the input current I i The product operation of the weight matrix is ​​performed, and the SRAM bit read and write circuit and the SRAM row selection circuit complete the write and read operations on the 8T-SRAM unit;

[0041] The column multi-channel analog-to-digital converter is composed of N×P analog-to-digital converters, each of which corresponds to a column of the operation array and is used to convert the output current I on the read bit lines RBL and RBLN of the corresponding j-th column into op,j and I on,j The difference is converted to binary number D j ;

[0042] The post-processing circuit is used to j The corresponding left shift operation is performed to give the corresponding column unit an additional binary weight, and the outputs of the adjacent P channels after left shift are summed to obtain the final vector output.

[0043] Among them, the SRAM read and write circuit adopts a traditional SRAM bit read and write circuit and a traditional SRAM row selection circuit. The traditional SRAM bit read and write circuit is connected to the write bit lines BL and BLN in the operation array, and the traditional SRAM row selection circuit is connected to the selection word line WL in the operation array.

[0044] The whole operation process can be expressed by the following formula:

[0045]

[0046] Among them, the input data B i (i=0~M-1) is a K-bit binary number, and the weight matrix unit W n，i (n=0~N-1, i=0~M-1) is a P-bit binary number. The vector-matrix product operator is used in the forward propagation in a neural network, especially in the forward propagation in a fully connected network.

[0047] In a specific embodiment, the operation array is composed of Mx(NxP) 8T-SRAM cells arranged in M ​​rows and NxP columns, such as Figure 3 As shown, the 8T-SRAM cell is composed of 8 transistors M0-M7, a selection word line WL, write bit lines BL and BLN, a read word line RWL, and read bit lines RBL and RBLN; wherein, transistors M0-M5 constitute a 6T-SRAM cell for bit storage of the weight matrix; transistor M6 is respectively connected to the storage potential Q, the read word line RWL, and the read bit line RBL; transistor M7 is respectively connected to the storage potential QN, the read word line RWL, and the read bit line RBLN;

[0048] Transistors M6 and M7 provide a set of differential current paths according to the stored bit pair Q-QN, directing the current given by the read word line RWL to the read bit line RBL or RBLN; when Q=1, QN=0, transistor M6 is turned on, M7 is turned off, and the current on the read word line RWL flows to the read bit line RBL through M6; when Q=0, QN=1, transistor M6 is turned off, M7 is turned on, and the current on the read word line RWL flows to the read bit line RBLN through M7.

[0049] The word line WL is selected to drive transistors M4 and M5, so that the storage potentials Q and QN are connected to the write bit lines BL and BLN, and the SRAM bit read and write circuit performs 0-1 binary information read and write operations on the storage potentials Q and QN through the write bit lines BL and BLN, so that the column SRAM bit read and write circuit can complete the traditional SRAM bit read and write circuit bit write and read operations on Q and QN. Specifically, the traditional SRAM row selection circuit will select a row in the SRAM array according to the given address information, that is, drive the WL of the selected row to a high potential, so that M4 and M5 in all SRAM cells in the row are turned on, and the storage points Q and QN are connected to BL and BLN; and the traditional SRAM bit read and write circuit performs 0-1 binary information read or write operations on Q and QN through BL and BLN.

[0050] The current flowing through each 8T-SRAM cell is I u，i =I i / (NP), indicating that the row input current will be evenly divided among N×P row cells.

[0051] When the operation array performs an in-memory operation read operation, the driving current on the read bit line RWL is proportional to the multi-bit binary input of the digital-to-analog converter. After being evenly divided among the 8T-SRAM cells in the same row, it is allocated to the RBL corresponding to the 8T-SRAM cell according to the 0-1 information stored in the 8T-SRAM cell. i or RBLN i The output current of all 8T-SRAM cells in the same column is on the corresponding read bit line BL i and RBLN i Add up on.

[0052] In a specific embodiment, Figure 4 As shown, the analog-to-digital converter includes two sampling capacitors C P and C N , switches S0 to S5 and a differential quantizer; wherein one end of switch S0, one end of switch S1 and one end of switch S2 are connected to each other and connected to the sampling capacitor C p One end of the sampling capacitor C p The other end of switch S0 is connected to the reference potential VREF The other end of switch S1 is connected to the read bit line RBL j The other end of switch S2 is connected to the positive electrode of the differential quantizer; one end of switch S3, one end of switch S4 and one end of switch S5 are connected to each other and connected to the sampling capacitor C N One end of the sampling capacitor C N The other end of switch S3 is connected to the reference potential V REF The other end of switch S4 is connected to the read bit line RBLN j The other end of the switch S5 is connected to the negative electrode of the differential quantizer; the differential quantizer is used to connect the sampling capacitor C P and C N The potential difference is quantized into a binary digital output D j .

[0053] The analog-to-digital converter includes three working stages: pre-charging stage, sampling stage and quantization stage;

[0054] In the pre-charging stage, switches S0 and S3 are closed, S1, S2, S4, and S5 are disconnected, and the sampling capacitor C P and C N The upper plate will be charged or discharged to a reference potential V during the precharge phase. REF ;

[0055] During the sampling phase, switches S1 and S4 are closed, switches S0, S2, S3, and S5 are open, and the sampling capacitor C P and C N They are connected to read bit lines RBL and RBLN respectively. The read bit line current is the sum of the differential output currents of each cell on the column. The read bit line current charges or discharges the sampling capacitor. After the sampling phase, the potential value of the sampling capacitor is linearly related to the read bit line current.

[0056] In the quantization stage, switches S2 and S5 are closed, S0, S1, S3, and S4 are disconnected, and the sampling capacitor C P and C N Connected to the two ends of the differential quantizer, the potential difference between the two capacitors (V CP -V CN ) is quantized into a binary digital output D j .

[0057] In a specific embodiment, the post-processing circuit is used to divide NxP columns of 8T-SRAM cells into N groups, and each group includes P columns of adjacent 8T-SRAM cells, and assigns different binary weights, that is, each P weight unit in the same row constitutes a P-bit binary weight number, and each group of P D j The final output O is obtained by binary weighted summation. n .

[0058] The final output O corresponding to the nth group of 8T-SRAM cells n The expression is as follows:

[0059]

[0060] The above formula indicates that the output D of the qth column in each group of 8T-SRAM cells is q Shift left by q bits, and then add the left-shifted output to get the corresponding output O n ; Wherein, q=j modP, indicating that q is obtained by performing a modulo operation on P by j; n=0~N-1, j is the column number of the qth column in each group of 8T-SRAM cells in the entire array, j=0~N×P-1.

[0061] More advantageously, with the read bit line RWL i The connected digital-to-analog converter is a multi-bit current-type digital-to-analog converter.

[0062] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0063] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A multi-bit vector-matrix product operator based on 8T-SRAM cells, characterized in that: include: A row multi-channel digital-to-analog converter, an operation array, an SRAM bit read-write circuit, an SRAM row selection circuit, a column multi-channel analog-to-digital converter and a post-processing circuit; the write bit line of the operation array is connected to the SRAM bit read-write circuit; the select word line of the operation array is connected to the SRAM row selection circuit; the read word line of the operation array is connected to the row multi-channel digital-to-analog converter; the read bit line of the operation array is connected to the column multi-channel analog-to-digital converter; The row multi-channel digital-to-analog converter is composed of M digital-to-analog converters, which are used to convert the input data B i The K-bit binary number is converted into the corresponding current I i and through the read word line RWL of the operation array i Enter into the corresponding i-th row; The operation array consists of M rows and N×P columns of 8T-SRAM cells, which are used to store the weight matrix and the input current I i The product operation of the weight matrix is ​​performed, and the SRAM bit read and write circuit and the SRAM row selection circuit complete the write and read operations on the 8T-SRAM unit; The column multi-channel analog-to-digital converter is composed of N×P analog-to-digital converters, each of which corresponds to a column of the operation array and is used to convert the output current I on the read bit lines RBL and RBLN of the corresponding j-th column op,j and I on,j The difference is converted to binary number D j ; The post-processing circuit is used to j Perform the corresponding left shift operation, give the corresponding column unit an additional binary weight, and sum the left-shifted outputs of adjacent P channels to obtain the final vector output; The analog-to-digital converter includes two sampling capacitors C P and C N , switches S0 to S5 and a differential quantizer; wherein one end of switch S0, one end of switch S1 and one end of switch S2 are connected to each other and connected to the sampling capacitor C p One end of the sampling capacitor C p The other end of switch S0 is connected to the reference potential V REF The other end of switch S1 is connected to the read bit line RBL j The other end of switch S2 is connected to the positive electrode of the differential quantizer; one end of switch S3, one end of switch S4 and one end of switch S5 are connected to each other and connected to the sampling capacitor C N One end of the sampling capacitor C N The other end of switch S3 is connected to the reference potential V REF The other end of switch S4 is connected to the read bit line RBLN j The other end of the switch S5 is connected to the negative electrode of the differential quantizer; the differential quantizer is used to connect the sampling capacitor C P and C N The potential difference is quantized into a binary digital output D j .

2. A multi-bit vector-matrix product operator based on 8T-SRAM unit according to claim 1, characterized in that: The 8T-SRAM cell is composed of 8 transistors M0-M7, a selection word line WL, write bit lines BL and BLN, a read word line RWL, and read bit lines RBL and RBLN; wherein the transistors M0-M5 constitute a 6T-SRAM cell for storing bits of the weight matrix; the transistor M6 is respectively connected to the storage potential Q, the read word line RWL, and the read bit line RBL; the transistor M7 is respectively connected to the storage potential QN, the read word line RWL, and the read bit line RBLN; Transistors M6 and M7 provide a set of differential current paths according to the stored bit pair Q-QN, and direct the current given by the read word line RWL to the read bit line RBL or RBLN; when Q=1 and QN=0, transistor M6 is turned on and M7 is turned off, and the current on the read word line RWL flows to the read bit line RBL through M6; when Q=0 and QN=1, transistor M6 is turned off and M7 is turned on, and the current on the read word line RWL flows to the read bit line RBL through M7; the word line WL is selected to drive transistors M4 and M5, so that the storage potentials Q and QN are connected to the write bit lines BL and BLN, and the SRAM bit read and write circuit performs 0-1 binary information read and write operations on the storage potentials Q and QN through the write bit lines BL and BLN.

3. A multi-bit vector-matrix product operator based on 8T-SRAM unit according to claim 2, characterized in that: The current flowing through each of the 8T-SRAM cells is I u，i =I i / (NP), indicating that the row input current will be evenly divided among N×P row cells.

4. The multi-bit vector-matrix product operator based on 8T-SRAM unit according to claim 1, characterized in that: The analog-to-digital converter includes three working stages: a pre-charging stage, a sampling stage, and a quantization stage; In the pre-charging stage, switches S0 and S3 are closed, S1, S2, S4, and S5 are disconnected, and the sampling capacitor C P and C N The upper plate will be charged or discharged to a reference potential V during the precharge phase. REF ; During the sampling phase, switches S1 and S4 are closed, switches S0, S2, S3, and S5 are open, and the sampling capacitor C P and C N They are connected to read bit lines RBL and RBLN respectively. The read bit line current is the sum of the differential output currents of each cell on the column. The read bit line current charges or discharges the sampling capacitor. After the sampling phase, the potential value of the sampling capacitor is linearly related to the read bit line current. In the quantization stage, switches S2 and S5 are closed, S0, S1, S3, and S4 are disconnected, and the sampling capacitor C P and C N Connected to the two ends of the differential quantizer, the potential difference between the two capacitors V CP -V CN Quantized into binary digital output D j .

5. The multi-bit vector-matrix product operator based on 8T-SRAM unit according to claim 1, characterized in that: The post-processing circuit is used to divide the 8T-SRAM cells into N groups, each group including P columns of adjacent 8T-SRAM cells, and assign different binary weights to each group of P D j The final output O is obtained by binary weighted summation. n .

6. A multi-bit vector-matrix product operator based on 8T-SRAM unit according to claim 5, characterized in that: The final output O corresponding to the nth group of 8T-SRAM cells n The expression is as follows: The above formula indicates that the output D of the qth column in each group of 8T-SRAM cells is q Shift left by q bits, and then add the left-shifted output to get the corresponding output O n ; Wherein, q=j modP, indicating that q is obtained by performing a modulo operation on P by j; n=0~N-1, j is the column number of the qth column in each group of 8T-SRAM cells in the entire array, j=0~N×P-1.

7. The multi-bit vector-matrix product operator based on 8T-SRAM unit according to claim 1, characterized in that: and the read bit line RWL i The connected digital-to-analog converter is a multi-bit current-type digital-to-analog converter.

8. The multi-bit vector-matrix product operator based on 8T-SRAM unit according to claim 1, characterized in that: When the operation array performs an in-memory operation read operation, the driving current on the read bit line RWL is proportional to the multi-bit binary input of the digital analog converter, and is evenly divided in the 8T-SRAM cells in the same row, and is allocated to the RBL corresponding to the 8T-SRAM cell according to the 0-1 information stored in the 8T-SRAM cell. i or RBLN i The output current of all 8T-SRAM cells in the same column is on the corresponding read bit line RBL. i and RBLN i Add up on.

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