Signal detection method and device

Abstract

The disclosed embodiment provides a signal detection method and device. The signal detection device defines the information of the correct output waveform of the signal to be tested in the stimulus file, and uses a setting simulator to simulate the chip to be tested to generate a simulation file, which includes the information of the simulation waveform of the signal to be tested, and filters out the noise in the simulation waveform to obtain a file to be compared, and compares the file to be compared with the stimulus file to generate a detection result file; or, compares the correct output waveform with the simulation waveform to obtain a candidate detection result, and filters out the result of the noise point in the candidate detection result to generate a detection result file. This method improves the correctness of the simulation result and the signal detection efficiency by automatically comparing the correct output waveform of the signal to be tested with the information of the simulation waveform and filtering out false error points.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and more particularly to a signal detection method and device. Background Art

[0002] In the process of developing, designing and debugging memory, it is necessary to simulate and verify the function of the memory, and simulation software can be used to simulate and verify the memory. The memory is, for example, a dynamic random access memory (DRAM), and the simulation software is, for example, Finesim, which is a high-performance accelerated universal analog circuit simulator (Simulation program with integrated circuit emphasis, SPICE for short), which has been widely used for its speed and accuracy.

[0003] In the simulation verification of memory, a large number of signals need to be simulated and verified, which will generate thousands of waveform result files. At present, these simulation results are mainly checked manually, but manual inspection of simulation results has the problems of low efficiency and low accuracy. Summary of the invention

[0004] The embodiments of the present disclosure provide a signal detection method and device, which can realize automatic detection of a simulation waveform obtained by simulation by a simulator.

[0005] In some embodiments, the first aspect of the present disclosure provides a signal detection method, the method comprising:

[0006] Obtaining an excitation file, wherein the excitation file includes information of a correct output waveform of a signal to be tested;

[0007] Using a set simulator to simulate the chip to be tested to generate a simulation file, wherein the simulation file includes information of a simulation waveform of the signal to be tested;

[0008] Screening out noise in the simulation waveform to obtain a file to be compared, wherein the file to be compared includes information on a valid simulation waveform of the signal to be tested;

[0009] The file to be compared is compared with the stimulus file to generate a detection result file.

[0010] In some embodiments, the simulation waveform includes a simulation waveform of a data signal and a simulation waveform of a data strobe signal, and filtering out noise in the simulation waveform to obtain a file to be compared includes:

[0011] Acquire a voltage reference line of the data strobe signal, wherein the voltage reference line is a straight line in the same dimension as the data strobe signal simulation waveform, and a voltage value corresponding to the voltage reference line is between a maximum voltage value and a minimum voltage value of the data strobe signal;

[0012] Determining a data strobe signal change point according to an intersection of a simulation waveform of the data strobe signal and the voltage reference line;

[0013] Invalid change points among the data selection signal change points are deleted to obtain the file to be compared.

[0014] In some embodiments, the step of acquiring a voltage reference line of the data strobe signal includes:

[0015] Determine half of the sum of the maximum voltage value and the minimum voltage value of the data strobe signal as a voltage reference value;

[0016] The voltage reference line is generated according to the voltage reference value and the simulation waveform of the data selection signal. The voltage reference line is a straight line in the same dimension as the simulation waveform of the data selection signal and the corresponding voltage value is equal to the voltage reference value.

[0017] In some embodiments, the invalid change point includes one or more of the following change points:

[0018] a change point of the data strobe signal within a first time period, wherein the state of the data strobe signal is not to select the data signal within the first time period;

[0019] The first signal edge of the data selection signal in the second time period changes and the intersection point with the voltage reference line. In the second time period, the state of the data selection signal is to select the data signal.

[0020] In some embodiments, the information of the correct output waveform of the signal to be tested is the correct logic voltage value of the data signal at each time, and comparing the file to be compared with the stimulus file to generate a test result file includes:

[0021] Calculating an average voltage value of the data signal according to a data signal simulation waveform corresponding to adjacent valid data strobe signal change points;

[0022] Converting the average voltage value of the data signal into a logic voltage value;

[0023] The logic voltage value is compared with the correct logic voltage value of the data signal in the excitation file to obtain the detection result file.

[0024] In some embodiments, before deleting the invalid change points in the data strobe signal change points, the method further includes:

[0025] Check the correctness of the data strobe signal simulation waveform.

[0026] In some embodiments, checking the correctness of the data strobe signal simulation waveform includes:

[0027] Obtaining the correct number of transitions of the data strobe signal within a data strobe cycle;

[0028] Calculating the number of simulated transitions of the data strobe signal in each data strobe cycle according to the simulated waveform of the data strobe signal;

[0029] The simulated transition times of the data strobe signal in the data strobe period are compared with the correct transition times, and a check result file of the data strobe signal is generated according to the comparison result.

[0030] In some embodiments, comparing the simulated transition number of the data strobe signal in the data strobe period with the correct transition number includes:

[0031] When the simulated transition number of the data strobe signal in the data strobe period is the same as the correct transition number, determining that the simulated waveform of the data strobe signal in the data strobe period is normal;

[0032] When the simulated transition number of the data strobe signal in the data strobe period is different from the correct transition number, it is determined that the simulated waveform of the data strobe signal in the data strobe period is abnormal.

[0033] In some embodiments, the second aspect of the present disclosure provides a signal detection method, including:

[0034] Obtaining an excitation file, wherein the excitation file includes information of a correct output waveform of a signal to be tested;

[0035] Using a set simulator to simulate the chip to be tested to generate a simulation file, wherein the simulation file includes information of a simulation waveform of the signal to be tested;

[0036] Comparing the correct output waveform with the simulation waveform to obtain a candidate detection result;

[0037] The noise points in the candidate detection results are screened out to generate a detection result file.

[0038] In some embodiments, comparing the correct output waveform with the simulation waveform to obtain a candidate detection result includes:

[0039] The output waveform and the simulation waveform are sampled under the same sampling conditions, and the voltage values ​​of the output waveform and the simulation waveform at each sampling time point are compared.

[0040] In some embodiments, the same sampling condition includes a sampling frequency, and the sampling frequency is N times the frequency of a clock signal of the chip, where N is greater than or equal to 2.

[0041] In some embodiments, the comparing the voltage values ​​of the correct output waveform and the simulation waveform at each sampling time point includes:

[0042] When the voltage values ​​of the correct output waveform and the simulation waveform at each sampling time point within half a cycle of the chip clock signal are different, it is determined that the simulation waveform of the signal to be tested has an error within half a cycle of the chip clock signal;

[0043] When the correct output waveform and the simulation waveform have the same voltage value at at least one sampling time point within half a cycle of the chip clock signal, it is determined that the simulation waveform of the signal to be tested has no error within half a cycle of the chip clock signal.

[0044] In some embodiments, the step of filtering out the noise points in the candidate detection results to generate a detection result file includes:

[0045] When the logic voltage value of at least one sampling time point in a half cycle of the clock signal of the chip is the same, determining the target sampling time points with different logic voltage values ​​in the half cycle as the noise points;

[0046] The sampling results of the noise points are screened out to generate a detection result file.

[0047] In some embodiments, the signal to be tested is an external output signal of the chip to be tested.

[0048] In some embodiments, the third aspect of the present disclosure provides a signal detection device, including:

[0049] An acquisition module, used for acquiring an excitation file, wherein the excitation file includes information of a correct output waveform of a signal to be tested;

[0050] A simulation module, used to simulate the chip to be tested by using a set simulator to generate a simulation file, wherein the simulation file includes information of a simulation waveform of the signal to be tested;

[0051] A screening module, used for screening out noise in the simulation waveform to obtain a file to be compared, wherein the file to be compared includes information on a valid simulation waveform of the signal to be tested;

[0052] A comparison module is used to compare the file to be compared with the stimulus file to generate a detection result file.

[0053] In some embodiments, the fourth aspect of the present disclosure provides a signal detection device, including:

[0054] An acquisition module, used for acquiring an excitation file, wherein the excitation file includes information of a correct output waveform of a signal to be tested;

[0055] A simulation module, used to simulate the chip to be tested by using a set simulator to generate a simulation file, wherein the simulation file includes a simulation waveform of the signal to be tested;

[0056] A comparison module, used for comparing the output waveform with the simulation waveform to obtain a candidate detection result;

[0057] The screening module is used to screen out the noise points in the candidate detection results to generate a detection result file. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0059] Figure 1 A flow chart of a signal detection method provided in Embodiment 1 of the present disclosure;

[0060] Figure 2 A flow chart of a signal detection method provided in Embodiment 2 of the present disclosure;

[0061] Figure 3 It is a schematic diagram of the simulation waveform and voltage reference line of DQS;

[0062] Figure 4 A flowchart of a signal detection method provided in Embodiment 3 of the present disclosure;

[0063] Figure 5 A flowchart of a signal detection method provided in Embodiment 4 of the present disclosure;

[0064] Figure 6 A schematic diagram of a chip clock signal;

[0065] Figure 7 A schematic diagram of the structure of a signal detection device provided in Embodiment 5 of the present disclosure;

[0066] Figure 8 A schematic diagram of the structure of a signal detection device provided in Embodiment 6 of the present disclosure;

[0067] Fig. 9This is a schematic diagram of the structure of the signal detection device provided in Example 7 of the present disclosure.

[0068] The above drawings show clear embodiments of the present disclosure, which will be described in more detail below. These drawings and text descriptions are not intended to limit the scope of the present disclosure in any way, but to illustrate the concepts of the present disclosure to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0069] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. Instead, they are merely examples of devices and methods consistent with some aspects of the present disclosure as detailed in the appended claims.

[0070] The disclosed embodiment provides a signal detection method, which can detect the result obtained by simulating a set simulator to automatically determine whether the simulation result is correct. The set simulator is used to simulate the chip to be tested to generate a simulation file, and the simulation file includes information on the simulation waveform of the signal to be tested. The set simulator can be Finesim, which has the advantages of fast speed and high accuracy in DRAM simulation verification, but there is no corresponding mechanism or language for the generated waveform result file to conveniently determine whether the result is correct or not, and it can only be checked manually. On the one hand, manual inspection has the risk of missing or wrong inspection, and on the other hand, the inspection speed is slow.

[0071] Figure 1 This is a flow chart of a signal detection method provided in the first embodiment of the present disclosure. The method of this embodiment can be executed by a signal detection device, which can be integrated in a simulator or can be an independent device. The signal detection device is used to detect the simulation results of the chip to be tested, which includes but is not limited to DRAM. This embodiment is described by taking the chip to be tested as DRAM as an example. Figure 1 As shown, the method of this embodiment includes the following steps.

[0072] S101 , obtaining an excitation file, wherein the excitation file includes information on a correct output waveform of a signal to be tested.

[0073] The stimulus file can be obtained through the model developed by the verification personnel. The stimulus file defines the information of the correct output waveform of the signal to be tested. The information of the correct output waveform of the signal to be tested includes the voltage value or logic voltage value that the signal to be tested should have at each time. The voltage value is an analog quantity, such as 0.746V, 0.5V, etc., and the logic voltage value is a digital quantity, which can be represented in the form of 0 / 1, where 0 can represent a low level and 1 represents a high level. The voltage value and the logic voltage value can be converted. For example, when the voltage value is 0.746V, if the reference voltage is 0.7V, the corresponding logic voltage value is 1.

[0074] The signal to be tested includes but is not limited to a data signal (i.e., DQ), which is used to write data into DRAM and read data from DRAM. The data strobe signal (DQS) is used for signal synchronization between the memory controller and the memory (i.e., DRAM). When the memory controller writes data into DRAM (i.e., a write operation), the memory controller generates DQS, and the rising edge or falling edge (collectively referred to as the edge) of DQS is aligned with the edge of DQ. The DRAM determines when to receive the written data based on the edge of DQS. When the memory controller reads data from DRAM (i.e., a read operation), the DRAM generates DQS, and the edge of DQS is aligned with the edge of DQ. The memory controller determines when to receive the read data based on the edge of DQS.

[0075] S102 , using a set simulator to simulate the chip to be tested to generate a simulation file, wherein the simulation file includes information of a simulation waveform of the signal to be tested.

[0076] Taking Finesim as an example, the designer can write a corresponding measurement file based on the signal to be tested by measuring the simulation waveform through Finesim, and add the measurement file when simulating with Finesim. Correspondingly, after executing the measurement file, a measurement result file will be automatically generated.

[0077] The information of the simulated waveform of the signal to be tested corresponds to the information of the correct output waveform of the signal to be tested. When the information of the correct output waveform of the signal to be tested is the voltage value that the signal to be tested should have at each moment, the information of the simulated waveform of the signal to be tested is the measured voltage value of the simulated waveform of the signal to be tested at each moment. When the signal to be tested is DQ, the simulated waveform includes the simulated waveform of DQ and the simulated waveform of DQS.

[0078] S103 , filtering out noise in the simulation waveform to obtain a file to be compared, wherein the file to be compared includes information on a valid simulation waveform of the signal to be tested.

[0079] There are some noises in the simulation waveform, which may produce erroneous detection results and reduce the accuracy of the detection results of the signal to be tested, so these noises need to be eliminated. In this embodiment, noise refers to all factors that may cause errors in the detection results.

[0080] It can be understood that when the signal to be tested is different, the type of noise in the simulation waveform may be different. Taking DQ as an example, the noise of the simulation waveform includes DQS invalid change points, and the DQS change point refers to the time point corresponding to the rising edge or falling edge of DQS, or the time point when DQS changes from a high level to a low level and the time point when DQS changes from a low level to a high level. Among them, the rising edge is the band where the level of the waveform changes from a low level to a high level, and the falling edge is the band where the level of the waveform changes from a high level to a low level.

[0081] The DQS invalid change point includes one or more of the following change points: a DQS change point in the first time period, in which the DQS state is not selected for DQ. A DQS first signal edge change in the second time period and the intersection of the voltage reference line, in which the DQS state is selected for DQ.

[0082] S104: Compare the file to be compared with the stimulus file to generate a detection result file.

[0083] The stimulus file defines the correct output waveform information of the signal to be tested, and the comparison file includes the effective simulation waveform information of the signal to be tested. The correct output waveform information and the effective simulation waveform information are compared to obtain the test result. For example, the correct logic voltage value of DQ at each time is compared with the simulated logic voltage value of DQ at each time to obtain whether the logic voltage value of the simulation waveform of DQ at each time is correct.

[0084] Optionally, the test result file can be displayed to the user through a display screen so that the user can intuitively understand the test result of the signal. Further, the error points of the signal can be displayed to the user in the form of a waveform or table, or a matrix can be used to indicate whether the simulation result is correct.

[0085] In some embodiments, the signal detection device defines the correct output waveform information of the signal to be tested in the stimulus file, and uses a setting simulator to simulate the chip to be tested to generate a simulation file, which includes the simulation waveform information of the signal to be tested, and then screens out the noise in the simulation waveform to obtain a file to be compared, which includes the effective simulation waveform information of the signal to be tested, and compares the file to be compared with the stimulus file to generate a detection result file. This method automatically detects whether the simulation result of the signal is correct by automatically comparing the correct output waveform of the signal to be tested with the effective simulation waveform information, and the signal detection efficiency is high.

[0086] On the basis of the first embodiment, the second embodiment of the present disclosure takes the signal to be tested as DQ as an example to illustrate the detection method of DQ. In the memory design verification, the correctness of DQ is the basic condition for judging the correctness of the memory design. Figure 2 This is a flow chart of a signal detection method provided in Embodiment 2 of the present disclosure, such as Figure 2 As shown, the method provided in this embodiment includes the following steps.

[0087] S201 , obtaining a stimulus file, wherein the stimulus file includes the correct logic voltage of DQ at each time.

[0088] S202 , using a set simulator to simulate the chip to be tested to generate a simulation file, wherein the simulation file includes information of simulation waveforms of DQ and DQS.

[0089] S203 , obtaining a voltage reference line of DQS.

[0090] The voltage reference line is a straight line in the same dimension as the DQS simulation waveform, and a voltage value corresponding to the voltage reference line is between a maximum voltage value and a minimum voltage value of the DQS.

[0091] Exemplarily, half of the sum of the maximum voltage value and the minimum voltage value of DQS is determined as the voltage reference value, and a voltage reference line is generated according to the voltage reference value and the simulation waveform of DQS. The voltage reference line is a straight line in the same dimension as the simulation waveform of DQS, and the corresponding voltage value is equal to the voltage reference value. Here, the voltage reference value is taken as half of the sum of the maximum voltage value and the minimum voltage value of DQS as an example. It can be understood that the voltage reference value can also float up and down based on half of the sum of the maximum voltage value and the minimum voltage value of DQS.

[0092] S204 . Determine a DQS change point according to an intersection of the DQS simulation waveform and the voltage reference line.

[0093] Figure 3 The schematic diagram of the simulation waveform and voltage reference line of DQS is shown in FIG. Figure 3 As shown in FIG. 1 , the maximum voltage value of DQS is 1.2V, and the minimum voltage value of DQS is 0.4V. The dotted line in the figure represents the voltage reference line, and the voltage reference value is 0.8V, which is half of the maximum voltage value and the minimum voltage value of DQS.

[0094] The DQS change point is the intersection of the DQS simulation waveform and the voltage reference line. From the figure, it can be seen that within one cycle (i.e., the first time period + the second time period), the DQS simulation waveform and the voltage reference line have 10 intersections (i.e., DQS change points), which are recorded as D9, D10...D19 respectively. The intersection points are generated by the rising edge and falling edge of DQS. Each DQS change point corresponds to a change in the voltage value of DQS. In the figure, r1-r9 represent the rising edge, and f1-f9 represent the falling edge.

[0095] S205: Delete invalid change points in the DQS change points to obtain a file to be compared.

[0096] The DQS invalid change point includes one or more of the following change points: a DQS change point in the first time period, in which the DQS state is not selected for DQ. A DQS first signal edge change in the second time period and the intersection of the voltage reference line, in which the DQS state is selected for DQ.

[0097] by Figure 3 For example, the first time period may be the time period between D9 and D10, excluding D9 and D10, and DQS is not gated during this time period, that is, the change points where the signal jump occurs during this time period are considered to be invalid change points. The second time period is the time period between D10 and D19, including D10 and D19, and the DQS state during this time period is gated DQ. During the gated process, the intersection D10 of the first signal edge change of DQS and the voltage reference line is an invalid change point, because during the data gated process, the first signal edge change of DQS does not gate the DQ data.

[0098] The noise in the DQS simulation waveform is screened out through steps S203 - S205 .

[0099] S206 , calculating the average voltage value of DQ according to the DQ simulation waveforms corresponding to adjacent valid DQS change points in the file to be compared.

[0100] by Figure 3 For example, D11 to D19 are valid DQS change points, then determine the DQ simulation waveforms corresponding to eight time periods, namely D11-D12, D12-D13, ... D17-D18, and D18-D19, respectively, and calculate the average voltage value of DQ in each time period based on the voltage value of the DQ simulation waveform corresponding to the time period, and obtain the average voltage value of DQ in eight time periods in total.

[0101] S207 , converting the average voltage value of DQ into a logic voltage value.

[0102] The average voltage value of DQ in each time period calculated in step S206 is an analog voltage, and the analog voltage is converted into a logic voltage value according to the average voltage value of DQ and the reference voltage.

[0103] S208. Compare the logic voltage value with the correct logic voltage value of DQ in the stimulus file to obtain a test result file.

[0104] The calculated logic voltage value of DQ in each time period is compared with the correct logic voltage value of DQ set in the same time period in the stimulus file. When the logic voltage value of DQ calculated in the same time period is the same as the correct logic voltage value, it is determined that the DQ simulated in the time period is correct. When the logic voltage value of DQ calculated in the same time period is different from the correct logic voltage value, it is determined that the DQ simulated in the time period is wrong.

[0105] In this embodiment, after obtaining the simulation waveform of DQ and the simulation waveform of DQS, the DQS change point is determined, and the invalid DQS change point is deleted. According to the simulation waveform of the data signal corresponding to the adjacent valid DQS change point, the average voltage value of DQ is calculated, and the average voltage value of DQ is converted into a logical voltage value. The logical voltage value is compared with the correct logical voltage value of DQ in the stimulus file to obtain the test result file. This method can automatically detect whether the simulation result of DQ is correct, and excludes invalid DQS, so that the test result is more accurate.

[0106] Based on the second embodiment, in a possible embodiment, before deleting the invalid change points in the DQS change points, the correctness of the DQS simulation waveform is checked. The third embodiment of the present disclosure introduces in detail a method for checking the correctness of the DQS simulation waveform. Figure 4 This is a flow chart of a signal detection method provided in Embodiment 3 of the present disclosure, such as Figure 4 As shown, the method provided in this embodiment includes the following steps.

[0107] S301, obtaining the correct transition times of DQS in a data strobe cycle.

[0108] The transition of DQS refers to the voltage of DQS changing from high level to low level or from low level to high level. The number of transitions of DQS in a data strobe cycle includes the number of times DQS changes from high level to level and the number of times DQS changes from low level to high level in a data strobe cycle. Each transition corresponds to a rising edge or falling edge of DQS, so the correct number of transitions of DQS in a data strobe cycle can also be the sum of the number of rising edges and the number of falling edges of DQS in a data strobe cycle.

[0109] The correct number of jumps may be included in the excitation file, and the signal detection device may read the correct number of jumps from the excitation file.

[0110] S302 , calculating the number of simulated transitions of DQS in each data strobe cycle according to the simulated waveform of DQS.

[0111] The DQS simulation waveform can reflect the voltage change of DQS. According to the change of the voltage amplitude of the DQS simulation waveform, the number of simulated jumps of DQS can be obtained. Figure 3 Taking the DQS shown in FIG. 1 as an example, the number of DQS transitions in one data strobe cycle is 10.

[0112] S303 , comparing the simulated transition times of DQS in the data strobe period with the correct transition times, and generating a DQS inspection result file according to the comparison result.

[0113] When the simulated transition times of DQS in the data strobe cycle are the same as the correct transition times, it is determined that the simulated waveform of DQS in the data strobe cycle is normal. When the simulated transition times of DQS in the data strobe cycle are different from the correct transition times, it is determined that the simulated waveform of DQS in the data strobe cycle is abnormal.

[0114] by Figure 3 Taking the DQS shown in the figure as an example, the correct jump number of DQS in the data strobe period is 10 times. When the simulated jump number of DQS in the data strobe period is less than 10 times or greater than 10 times, it is determined that the simulated waveform of DQS in the data strobe period is abnormal. For example, when the simulated jump number of DQS in the data strobe period is 8 times or 11 times, it is determined that the simulated waveform of DQS in the data strobe period is abnormal.

[0115] Figure 5 This is a flow chart of a signal detection method provided in Embodiment 4 of the present disclosure. The method in this embodiment and the method in Embodiment 1 are respectively used to detect different signals. Figure 5 As shown, the method of this embodiment includes the following steps.

[0116] S401 , obtaining an excitation file, wherein the excitation file includes information on a correct output waveform of a signal to be tested.

[0117] S402 , using a set simulator to simulate the chip to be tested to generate a simulation file, wherein the simulation file includes information of a simulation waveform of the signal to be tested.

[0118] The specific implementation of S401-S402 refers to the relevant description of steps S101-102 in the first embodiment, and the specific principles are similar, except that the signal to be tested is different. In this embodiment, the signal to be tested can be an external output signal of the chip to be tested.

[0119] S403: Compare the correct output waveform with the simulation waveform to obtain a candidate detection result.

[0120] Exemplarily, the correct output waveform and the simulation waveform are sampled under the same sampling conditions, and then the voltage values ​​of the correct output waveform and the simulation waveform at each sampling time point are compared to obtain the candidate detection result.

[0121] The same sampling condition includes but is not limited to the sampling frequency, wherein the sampling frequency is N times the frequency of the chip clock signal, and N is greater than or equal to 2. This is because, if the sampling frequency is equal to the frequency of the chip clock signal, when the sampling point is located at the edge of the correct output waveform or simulation waveform, the sampled voltage value is likely to be wrong due to the jump of the signal, thereby causing an error in the detection result. Therefore, the sampling frequency should be at least twice the frequency of the clock signal, so as to ensure that the sampled voltage value includes the correct voltage value and improve the accuracy of the detection result.

[0122] When comparing the voltage values ​​of the correct output waveform and the simulated waveform at each sampling time point, if the voltage values ​​of the correct output waveform and the simulated waveform at each sampling time point within half a cycle of the chip's clock signal are all different, it is determined that the simulated waveform of the signal to be tested has an error within half a cycle of the chip's clock signal. When the voltage values ​​of the correct output waveform and the simulated waveform at at least one sampling time point within half a cycle of the chip's clock signal are the same, it is determined that the simulated waveform of the signal to be tested has no error within half a cycle of the chip's clock signal.

[0123] Since the simulation waveform and the correct output waveform will not jump within half a cycle of the clock signal, that is, the voltage values ​​of the simulation waveform and the correct output waveform will not jump from a high level to a low level, nor from a low level to a high level, so as long as the voltage value at one sampling time point within half a cycle of the clock signal is correct, the simulation waveform of the signal to be tested will be correct within half a cycle of the chip's clock signal, and no errors will occur.

[0124] Similarly, when an error occurs in the simulation waveform, the entire waveform of the simulation waveform within half a cycle of the clock signal is flipped. For example, the voltage value of the simulation waveform changes from a low level to a high level or from a high level to a low level within half a cycle of the clock signal. Correspondingly, the voltage values ​​collected at each sampling time point will be flipped. Therefore, when the voltage values ​​of the correct output waveform and the simulation waveform at each sampling time point within half a cycle of the chip clock signal are different, it is determined that the simulation waveform of the signal to be tested has an error within half a cycle of the chip clock signal.

[0125] S404: Screen out the noise points in the candidate detection results to generate a detection result file.

[0126] There are some noises in the candidate detection results, and these noises need to be screened out. In this embodiment, noise refers to all factors that may cause errors in the detection results. By screening out the noise points, an accurate detection result file can be obtained.

[0127] Exemplarily, the candidate detection results include the detection results of the simulation waveform in multiple clock signals of the chip and the voltage values ​​of each sampling point in each clock signal. Among them, the detection result of the simulation waveform in half a cycle of the chip clock signal is used to indicate whether the waveform of the simulation waveform in half a cycle of the chip clock signal is correct. Correct can be represented by true, and error can be represented by fause, or correct can be represented by 1 and error can be represented by 0. This is just an example.

[0128] Accordingly, when the noise point is determined from the candidate detection results, when the voltage value of at least one sampling time point is the same within half a cycle of the chip's clock signal, the target sampling time points with different voltage values ​​are determined as noise points, and the sampling results of the noise points are screened out to generate a detection result file. The detection result file includes the detection results of the simulation waveform within half a cycle of multiple clock signals of the chip and the voltage value of the correct sampling point within half a cycle of each chip clock signal.

[0129] Within half a cycle of the chip's clock signal, some sampling time points may be located at the transition edge of the chip's clock signal cycle. The voltage collected at the sampling time points at the clock signal edge may be erroneous due to the clock edge signal transition. Therefore, the voltage values ​​of the simulation waveforms collected at these sampling time points may be different from the voltage values ​​of the correct output waveforms. Therefore, the sampling points that are usually located at the transition edge of the chip's clock signal cycle are noise points and need to be excluded.

[0130] Figure 6 A schematic diagram of the chip's clock signal, such as Figure 6 As shown, we do not need to pay attention to whether the voltage values ​​of the sampling points at the rising and falling edges of the chip's clock signal are correct, but only need to pay attention to whether the voltage values ​​of the sampling points during the signal stability period are correct. Therefore, the sampling points at the rising and falling edges of the chip's clock signal are noise points. It can be understood that Figure 6 The rising edge, falling edge and stable period of the chip clock signal are only schematic diagrams. The switching time of the rising edge and falling edge of the signal in different devices may be different, and the switching time of the rising edge may be less than the switching time of the falling edge. In some cases, the switching time of the rising edge or the switching time of the falling edge may be 0 or very small and can be ignored.

[0131] In this embodiment, the signal detection device defines the information of the correct output waveform of the signal to be tested in the stimulus file, and uses a setting simulator to simulate the chip to be tested to generate a simulation file, which includes the information of the simulation waveform of the signal to be tested, and then compares the correct output waveform and the simulation waveform to obtain candidate detection results, and screens out the results of noise points in the candidate detection results to generate a detection result file. This method automatically detects whether the simulation result of the signal is correct by automatically comparing the information of the correct output waveform of the signal to be tested and the effective simulation waveform, and the signal detection efficiency is high. After obtaining the candidate detection results, the results of noise points in the candidate detection results are screened out, which improves the accuracy of the detection results.

[0132] Figure 7 This is a schematic diagram of the structure of the signal detection device provided in Embodiment 5 of the present disclosure, such as Figure 7 As shown, the signal detection device 100 comprises:

[0133] An acquisition module 11 is used to acquire an excitation file, wherein the excitation file includes information of a correct output waveform of a signal to be tested;

[0134] The simulation module 12 is used to use a set simulator to simulate the chip to be tested to generate a simulation file, wherein the simulation file includes a simulation waveform of the signal to be tested;

[0135] A screening module 13, used for screening out noise in the simulation waveform to obtain a file to be compared, wherein the file to be compared includes information on a valid simulation waveform of the signal to be tested;

[0136] The comparison module 14 is used to compare the file to be compared with the stimulus file to generate a detection result file.

[0137] In one embodiment, the simulation waveform includes a simulation waveform of a data signal and a simulation waveform of a data strobe signal, and the screening module 14 is specifically used for:

[0138] Acquire a voltage reference line of the data strobe signal, wherein the voltage reference line is a straight line in the same dimension as the data strobe signal simulation waveform, and a voltage value corresponding to the voltage reference line is between a maximum voltage value and a minimum voltage value of the data strobe signal;

[0139] Determining a data strobe signal change point according to an intersection of a simulation waveform of the data strobe signal and the voltage reference line;

[0140] Invalid change points among the data selection signal change points are deleted to obtain the file to be compared.

[0141] In one embodiment, the voltage reference line for obtaining the data strobe signal is specifically:

[0142] Determine half of the sum of the maximum voltage value and the minimum voltage value of the data strobe signal as a voltage reference value;

[0143] The voltage reference line is generated according to the voltage reference value and the simulation waveform of the data selection signal. The voltage reference line is a straight line in the same dimension as the simulation waveform of the data selection signal and the corresponding voltage value is equal to the voltage reference value.

[0144] In one embodiment, the invalid change point includes one or more of the following change points: a change point of the data enable signal within a first time period, during which the state of the data enable signal is not to enable the data signal; an intersection point where the first signal edge of the data enable signal within a second time period changes and intersects with the voltage reference line, during which the state of the data enable signal is to enable the data signal.

[0145] In one embodiment, the comparison module 1 is specifically used to: calculate the average voltage value of the data signal based on the data signal simulation waveform corresponding to the adjacent valid data selection signal change points, convert the average voltage value of the data signal into a logic voltage value, compare the logic voltage value with the correct logic voltage value of the data signal in the excitation file, and obtain the detection result file.

[0146] In one embodiment, a checking module is further included, for checking the correctness of the simulation waveform of the data strobe signal.

[0147] In one embodiment, the inspection module is specifically used to: obtain the correct number of jumps of the data selection signal in a data selection cycle; calculate the simulated number of jumps of the data selection signal in each data selection cycle based on the simulation waveform of the data selection signal; compare the simulated number of jumps of the data selection signal in the data selection cycle with the correct number of jumps, and generate an inspection result file of the data selection signal based on the comparison result.

[0148] In one embodiment, the comparison of the simulated transition number of the data enable signal within the data enable cycle and the correct transition number is specifically as follows: when the simulated transition number of the data enable signal within the data enable cycle is the same as the correct transition number, it is determined that the simulated waveform of the data enable signal within the data enable cycle is normal; when the simulated transition number of the data enable signal within the data enable cycle is different from the correct transition number, it is determined that the simulated waveform of the data enable signal within the data enable cycle is abnormal.

[0149] The device of this embodiment can be used to execute the method described in any one of the above embodiments 1 to 3. The specific implementation method and technical effects are similar and will not be described in detail here.

[0150] Figure 8 This is a schematic diagram of the structure of a signal detection device provided in Embodiment 6 of the present disclosure, such as Figure 8 As shown, the signal detection device 200 includes:

[0151] An acquisition module 21 is used to acquire an excitation file, wherein the excitation file includes information of a correct output waveform of a signal to be tested;

[0152] The simulation module 22 is used to use a set simulator to simulate the chip to be tested to generate a simulation file, wherein the simulation file includes a simulation waveform of the signal to be tested;

[0153] A comparison module 23, used for comparing the output waveform with the simulation waveform to obtain a candidate detection result;

[0154] The screening module 24 is used to screen out the noise points in the candidate detection results to generate a detection result file.

[0155] In one embodiment, the comparison module 23 is specifically used to: sample the output waveform and the simulation waveform under the same sampling conditions, and compare the voltage values ​​of the output waveform and the simulation waveform at each sampling time point.

[0156] In one embodiment, the same sampling condition includes a sampling frequency, and the sampling frequency is N times the frequency of a clock signal of the chip, where N is greater than or equal to 2.

[0157] In one embodiment, the comparison of the voltage values ​​of the correct output waveform and the simulation waveform at each sampling time point is specifically as follows: when the voltage values ​​of the correct output waveform and the simulation waveform at each sampling time point within half a cycle of the chip clock signal are all different, it is determined that the simulation waveform of the signal to be measured has an error within half a cycle of the chip clock signal; when the voltage values ​​of the correct output waveform and the simulation waveform at at least one sampling time point within half a cycle of the chip clock signal are the same, it is determined that the simulation waveform of the signal to be measured has no error within half a cycle of the chip clock signal.

[0158] In one embodiment, the screening module 24 is specifically used to: determine the target sampling time points with different voltage values ​​as the noise points within a half cycle of the clock signal of the chip; and screen out the sampling results of the noise points to generate a detection result file.

[0159] In one embodiment, the signal to be tested is an external output signal of the chip to be tested.

[0160] The device of this embodiment can be used to execute the method described in the fourth embodiment above. The specific implementation method and technical effects are similar and will not be described in detail here.

[0161] It should be noted that when the device provided in the above embodiment executes the signal detection method, only the division of the above-mentioned functional modules is used as an example. In actual applications, the above-mentioned functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0162] Fig. 9 This is a structural diagram of a signal detection device provided in Embodiment 7 of the present disclosure, such as Fig. 9 As shown, the signal detection device 300 includes: at least one processor 31 and a memory 32; the memory 32 stores computer execution instructions; the at least one processor 31 executes the computer execution instructions stored in the memory 32, so that the at least one processor 31 executes the method described in any one of Embodiments 1 to 4 of the present disclosure, and the specific implementation methods and technical effects are similar, which will not be repeated here.

[0163] The embodiments of the present disclosure also provide a computer program product, including a computer program. When the computer program is executed by a processor, the method described in any one of the above embodiments 1 to 4 is implemented. The specific implementation method and technical effect are similar and will not be repeated here.

[0164] The embodiments of the present disclosure also provide a computer-readable storage medium, in which computer-executable instructions are stored. When the computer-executable instructions are executed by a processor, they are used to implement the method described in any one of the above embodiments 1 to 4. The specific implementation methods and technical effects are similar and will not be repeated here.

[0165] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. The present disclosure is intended to cover any variations, uses or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The description and examples are to be considered exemplary only, and the true scope and spirit of the present disclosure are indicated by the following claims.

[0166] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A signal detection method, characterized in that: include: Obtaining an excitation file, wherein the excitation file includes information of a correct output waveform of a signal to be tested; Using a set simulator to simulate the chip to be tested to generate a simulation file, wherein the simulation file includes information of a simulation waveform of the signal to be tested; Screening out noise in the simulation waveform to obtain a file to be compared, wherein the file to be compared includes information on a valid simulation waveform of the signal to be tested; Comparing the file to be compared with the stimulus file to generate a detection result file; The simulation waveform includes a simulation waveform of a data signal and a simulation waveform of a data strobe signal, and filtering out noise in the simulation waveform to obtain a file to be compared includes: Acquire a voltage reference line of the data strobe signal, wherein the voltage reference line is a straight line in the same dimension as the data strobe signal simulation waveform, and a voltage value corresponding to the voltage reference line is between a maximum voltage value and a minimum voltage value of the data strobe signal; Determining a data strobe signal change point according to an intersection of a simulation waveform of the data strobe signal and the voltage reference line; Invalid change points among the data selection signal change points are deleted to obtain the file to be compared.

2. The signal detection method according to claim 1, characterized in that: The voltage reference line for obtaining the data strobe signal comprises: Determine half of the sum of the maximum voltage value and the minimum voltage value of the data strobe signal as a voltage reference value; The voltage reference line is generated according to the voltage reference value and the simulation waveform of the data selection signal. The voltage reference line is a straight line in the same dimension as the simulation waveform of the data selection signal and the corresponding voltage value is equal to the voltage reference value.

3. The signal detection method according to claim 2, characterized in that: The invalid change points include one or more of the following change points: a change point of the data strobe signal within a first time period, wherein the state of the data strobe signal is not to select the data signal within the first time period; The first signal edge of the data selection signal in the second time period changes and the intersection point with the voltage reference line. In the second time period, the state of the data selection signal is to select the data signal.

4. The signal detection method according to claim 3, characterized in that: The information of the correct output waveform of the signal to be tested is the correct logic voltage value of the data signal at each time, and the file to be compared is compared with the stimulus file to generate a test result file, including: Calculating an average voltage value of the data signal according to a data signal simulation waveform corresponding to adjacent valid data strobe signal change points; Converting the average voltage value of the data signal into a logic voltage value; The logic voltage value is compared with the correct logic voltage value of the data signal in the excitation file to obtain the detection result file.

5. The signal detection method according to any one of claims 1 to 4, characterized in that: Before deleting the invalid change points in the data strobe signal change points, the method further includes: Check the correctness of the data strobe signal simulation waveform.

6. The signal detection method according to claim 5, characterized in that: The checking of the correctness of the data strobe signal simulation waveform comprises: Obtaining the correct number of transitions of the data strobe signal within a data strobe cycle; Calculating the number of simulated transitions of the data strobe signal in each data strobe cycle according to the simulated waveform of the data strobe signal; The simulated transition times of the data strobe signal in the data strobe period are compared with the correct transition times, and a check result file of the data strobe signal is generated according to the comparison result.

7. The signal detection method according to claim 6, characterized in that: The comparing the simulated transition number of the data strobe signal in the data strobe period with the correct transition number includes: When the simulated transition number of the data strobe signal in the data strobe period is the same as the correct transition number, determining that the simulated waveform of the data strobe signal in the data strobe period is normal; When the simulated transition number of the data strobe signal in the data strobe period is different from the correct transition number, it is determined that the simulated waveform of the data strobe signal in the data strobe period is abnormal.

8. A signal detection method, characterized in that: include: Obtaining an excitation file, wherein the excitation file includes information of a correct output waveform of a signal to be tested; Using a set simulator to simulate the chip to be tested to generate a simulation file, wherein the simulation file includes information of a simulation waveform of the signal to be tested; Comparing the correct output waveform with the simulation waveform to obtain a candidate detection result; Screening out the noise points in the candidate detection results to generate a detection result file; The step of filtering out the noise points in the candidate detection results to generate a detection result file includes: When the logic voltage value of at least one sampling time point is the same within a half cycle of the clock signal of the chip, determining the target sampling time points with different logic voltage values ​​within the half cycle as the noise points; The sampling results of the noise points are screened out to generate a detection result file.

9. The signal detection method according to claim 8, characterized in that: The comparing the correct output waveform with the simulation waveform to obtain a candidate detection result includes: The output waveform and the simulation waveform are sampled under the same sampling conditions, and the voltage values ​​of the output waveform and the simulation waveform at each sampling time point are compared.

10. The signal detection method according to claim 9, characterized in that: The same sampling condition includes a sampling frequency, and the sampling frequency is N times the frequency of the clock signal of the chip, where N is greater than or equal to 2.

11. The signal detection method according to claim 10, characterized in that: The comparing the voltage values ​​of the correct output waveform and the simulation waveform at each sampling time point includes: When the voltage values ​​of the correct output waveform and the simulation waveform at each sampling time point within half a cycle of the chip clock signal are different, it is determined that the simulation waveform of the signal to be tested has an error within half a cycle of the chip clock signal; When the correct output waveform and the simulation waveform have the same voltage value at at least one sampling time point within half a cycle of the chip clock signal, it is determined that the simulation waveform of the signal to be tested has no error within half a cycle of the chip clock signal.

12. The signal detection method according to any one of claims 8 to 11, characterized in that: The signal to be tested is an external output signal of the chip to be tested.

13. A signal detection device, characterized in that: include: An acquisition module, used for acquiring an excitation file, wherein the excitation file includes information of a correct output waveform of a signal to be tested; A simulation module, used to simulate the chip to be tested by using a set simulator to generate a simulation file, wherein the simulation file includes information of a simulation waveform of the signal to be tested; A screening module, used for screening out noise in the simulation waveform to obtain a file to be compared, wherein the file to be compared includes information on a valid simulation waveform of the signal to be tested; A comparison module, used for comparing the file to be compared with the stimulus file to generate a detection result file; The simulation waveform includes a simulation waveform of a data signal and a simulation waveform of a data strobe signal, and the screening module is configured as follows: Acquire a voltage reference line of the data strobe signal, wherein the voltage reference line is a straight line in the same dimension as the data strobe signal simulation waveform, and a voltage value corresponding to the voltage reference line is between a maximum voltage value and a minimum voltage value of the data strobe signal; Determining a data strobe signal change point according to an intersection of a simulation waveform of the data strobe signal and the voltage reference line; Invalid change points among the data selection signal change points are deleted to obtain the file to be compared.

14. A signal detection device, characterized in that: include: An acquisition module, used for acquiring an excitation file, wherein the excitation file includes information of a correct output waveform of a signal to be tested; A simulation module, used to simulate the chip to be tested by using a set simulator to generate a simulation file, wherein the simulation file includes a simulation waveform of the signal to be tested; A comparison module, used for comparing the output waveform with the simulation waveform to obtain a candidate detection result; A screening module, used to screen out the noise points in the candidate detection results to generate a detection result file; Wherein, the screening module is configured as follows: When the logic voltage value of at least one sampling time point is the same within a half cycle of the clock signal of the chip, determining the target sampling time points with different logic voltage values ​​within the half cycle as the noise points; The sampling results of the noise points are screened out to generate a detection result file.

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