Display panel, display device, and method for detecting crack of display panel

Abstract

A display panel, a display device, and a method for detecting cracks in a display panel. The display panel includes: a display area and a second border area located on one side of the display area. The display area includes a plurality of detection display unit groups, and each detection display unit group includes a plurality of sub-pixels; the second border area includes a plurality of chamfered areas; the display panel includes at least two first crack detection lines and a plurality of detection units. At least one first crack detection line passes through one or two chamfered areas, and different first crack detection lines pass through different chamfered areas; one end of the first crack detection line passing through one chamfered area is electrically connected to a detection display unit group through a detection unit. Under the control of the detection unit, a first detection signal transmitted by the first crack detection line in the chamfered area is provided to the detection display unit group, so as to determine whether there is a crack in the chamfered area through which the first crack detection line passes according to the display result of the detection display unit group. Different chamfered areas correspond to different detection display unit groups.

Description

Technical Field

[0001] This document relates to, but is not limited to, display technologies, and particularly to a display panel, a display device, and a method for detecting cracks in a display panel. Background Art

[0002] For some electronic products, such as electronic wearable products, since relevant electronic signals need to be provided to a display panel, a wiring area for connecting the display panel and an electronic signal provider needs to be set up. This area is commonly known as the "watch neck". During preparation, chamfering needs to be performed on multiple areas on the "watch neck", and cracks may be generated in these areas, affecting the product quality. In some technologies, only a rough detection can be performed on whether there are cracks in the chamfered area, and the specific location of the cracks needs to be determined by relying on manual microscopy. The detection results obtained in this way have low accuracy, consume manpower, and microscopy may cause damage to the product. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail in this document. This overview is not intended to limit the scope of protection of the claims.

[0004] Embodiments of the present disclosure provide a display panel, a display device, and a method for detecting cracks in a display panel to solve the problem of inaccurate detection of cracks in the chamfered area of existing products.

[0005] In a first aspect, embodiments of the present disclosure provide a display panel, including: a display area and a second border area located on one side of the display area along a second direction. The display area includes a plurality of detection display unit groups, and each detection display unit group includes a plurality of sub-pixels. The second border area includes a plurality of chamfered areas; the display panel includes: at least two first crack detection lines and a plurality of detection units, where: at least one first crack detection line passes through one or two chamfered areas, and different first crack detection lines pass through different chamfered areas. One end of the first crack detection line passing through one chamfered area is electrically connected to a detection display unit group through the detection unit, and is configured to provide, under the control of the detection unit, a first detection signal transmitted by the first crack detection line in the chamfered area to the detection display unit group, so as to determine whether there is a crack in the chamfered area passed through by the first crack detection line according to the display result of the detection display unit group. Different chamfered areas correspond to different detection display unit groups.

[0006] In some exemplary embodiments, the two chamfered areas passed through by the first crack detection line are arranged along a first direction, and the first direction intersects with the second direction.

[0007] In some exemplary embodiments, the detection unit is electrically connected to a test control line and is configured to conduct the connected first crack detection line and the corresponding detection display unit group under the control of the test control line.

[0008] In some exemplary embodiments, the detection unit includes: a detection transistor, a control electrode of the detection transistor is electrically connected to the test control line, a first pole of the detection transistor is electrically connected to the first crack detection line, and a second pole of the detection transistor is electrically connected to the detection display unit group.

[0009] In some exemplary embodiments, the detection transistor is a P-type transistor.

[0010] In some exemplary embodiments, the first crack detection line is electrically connected to a first detection signal terminal, the first detection signal terminal is configured to provide the first detection signal to the first crack detection line, and a connection position between the first crack detection line and the first detection signal terminal is located between two chamfered areas through which the first crack detection line passes.

[0011] In some exemplary embodiments, the plurality of chamfered areas include: a first chamfered area, a second chamfered area, a third chamfered area, and a fourth chamfered area; the third chamfered area is located on a side of the first chamfered area away from the display area in the second direction, and the fourth chamfered area is located on a side of the second chamfered area away from the display area in the second direction; one of the first crack detection lines passes through one of the first chamfered area and the third chamfered area and one of the second chamfered area and the fourth chamfered area, and the other first crack detection line passes through the remaining two chamfered areas.

[0012] In some exemplary embodiments, two detection units connected to one of the first crack detection lines are located on a side of the display area close to the second border area, and two detection units connected to the other first crack detection line are located on a side of the display area away from the second border area.

[0013] In some exemplary embodiments, two detection units connected to one of the first crack detection lines, and one detection unit connected to the other first crack detection line are located on a side of the display area close to the second border area, and the other detection unit connected to the other first crack detection line is located on a side of the display area away from the second border area.

[0014] In some exemplary embodiments, the second border area includes a bent area; the plurality of chamfered areas are respectively located on a side of the bent area close to the display area and a side away from the display area.

[0015] In some exemplary embodiments, the display panel further includes: at least one second crack detection line disposed around the display area, configured to transmit a second detection signal to a corresponding detection display unit group under the control of the detection unit, so as to determine whether there is a crack in the display panel where the second crack detection line corresponding to the detection display unit group is located according to the display result of the detection display unit group; the second crack detection line is connected to different detection display unit groups through different detection units, the detection unit connected to the second crack detection line is different from the detection unit connected to the first crack detection line, and the detection display unit group corresponding to the second crack detection line is different from the detection display unit group corresponding to the first crack detection line.

[0016] In a second aspect, an embodiment of the present disclosure further provides a display device, including the display panel as described above.

[0017] In a third aspect, an embodiment of the present disclosure further provides a method for detecting cracks in a display panel, which is applied to detect the display panel as described above. The method includes: inputting a first detection signal to at least two first crack detection lines, and providing, under the control of the detection unit, the first detection signal transmitted by the crack detection line in the chamfered area to the detection display unit group corresponding to the chamfered area; determining whether there is a crack in the chamfered area through which the first crack detection line passes according to the display result of the detection display unit group.

[0018] In some exemplary embodiments, the method further includes: pre-configuring the correspondence between the chamfered area of the display panel and the detection display unit group.

[0019] In some exemplary embodiments, the method further includes: inputting a second detection signal to at least one second crack detection line, and transmitting the second detection signal to a corresponding detection display unit group under the control of the detection unit; determining whether there is a crack in the display panel where the second crack detection line is located according to the display result of the detection display unit group.

[0020] In the display panel provided by the embodiment of the present disclosure, at least two first crack detection lines are provided. Each first crack detection line passes through one or two chamfered areas. One end passing through one chamfered area is electrically connected to the detection display unit group on the display area. Different chamfered areas correspond to different detection display unit groups. According to the display result of the detection display unit group, it can be determined which chamfered area has a crack. The problem of inaccurate crack detection in the chamfered area of existing products is solved.

[0021] Other features and advantages of the present disclosure will be set forth in the following description, and in part will be obvious from the description, or can be learned by practicing the present disclosure. Other advantages of the present disclosure can be realized and obtained by the solutions described in the description and the drawings.

[0022] Other aspects will be apparent after reading and understanding the drawings and the detailed description. Brief Description of the Drawings

[0023] The drawings are used to provide an understanding of the technical solutions of the present disclosure, and constitute a part of the description. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure, and do not constitute a limitation to the technical solutions of the present disclosure.

[0024] Figure 1 A schematic structural diagram of a display device;

[0025] Figure 2 A schematic plan view of a display substrate;

[0026] Figure 3 A schematic equivalent circuit diagram of a pixel driving circuit;

[0027] Figure 4 A working timing diagram of a pixel driving circuit;

[0028] Figure 5 A schematic structural diagram of a display panel in an exemplary embodiment;

[0029] Figure 6 A schematic diagram of the line layout of a display panel in an exemplary embodiment;

[0030] Figure 7 A schematic diagram of the line layout of a display panel in another exemplary embodiment;

[0031] Figure 8 A schematic diagram of the line layout of a display panel in still another exemplary embodiment;

[0032] Figure 9 A schematic diagram of the line layout of a display panel in another exemplary embodiment;

[0033] Figure 10 A schematic diagram of the line layout of a display panel including a second crack detection line in an exemplary embodiment. Detailed Description of the Embodiments

[0034] The present disclosure describes multiple embodiments, but the description is exemplary rather than restrictive, and it will be apparent to those of ordinary skill in the art that there can be more embodiments and implementation solutions within the scope encompassed by the embodiments described in the present disclosure. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically restricted, any feature or element of any embodiment can be used in combination with any other feature or element in any other embodiment, or can replace any other feature or element in any other embodiment.

[0035] The present disclosure includes and contemplates combinations with features and elements known to those of ordinary skill in the art. The embodiments, features, and elements already disclosed in the present disclosure can also be combined with any conventional features or elements to form unique inventive solutions defined by the claims. Any feature or element of any embodiment can also be combined with features or elements from other inventive solutions to form another unique inventive solution defined by the claims. Therefore, it should be understood that any feature shown and / or discussed in the present disclosure can be implemented alone or in any suitable combination. Therefore, the embodiments are not subject to other limitations except those made in accordance with the appended claims and their equivalents. In addition, various modifications and changes can be made within the scope of the appended claims.

[0036] Furthermore, when describing representative embodiments, the specification may have presented the method and / or process as a specific sequence of steps. However, to the extent that the method or process does not depend on the specific order of the steps described herein, the method or process should not be limited to the specific order of steps described. As will be understood by those of ordinary skill in the art, other step orders are possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation on the claims. In addition, the claims directed to the method and / or process should not be limited to performing their steps in the order written, and those skilled in the art can readily understand that these orders can vary and still remain within the spirit and scope of the embodiments of the present disclosure.

[0037] In the drawings, sometimes for clarity, the size of one or more constituent elements, the thickness of layers, or regions are exaggerated. Therefore, one aspect of the present disclosure is not necessarily limited to that size, and the shape and size of one or more components in the drawings do not reflect the true scale. In addition, the drawings schematically show ideal examples, and one aspect of the present disclosure is not limited to the shapes or values shown in the drawings, etc.

[0038] The ordinal numbers such as "first", "second", "third", etc. in this specification are set to avoid confusion of components, rather than to limit the quantity. "Plurality" in the present disclosure means two or more quantities.

[0039] In this specification, for convenience, terms indicating orientation or positional relationship such as "middle part", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are used to describe the positional relationship of components with reference to the accompanying drawings. This is only for the convenience of describing this specification and simplifying the description, rather than indicating or implying that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to the present disclosure. The positional relationship of the components is appropriately changed according to the direction of the described components. Therefore, it is not limited to the terms described in the specification and can be appropriately replaced according to the situation.

[0040] In this specification, unless otherwise clearly specified and limited, the terms "mount", "connect", and "couple" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be directly connected, or indirectly connected through an intermediate member, or the internal communication of two components. For those of ordinary skill in the art, the meanings of the above terms in the present disclosure can be understood according to the situation.

[0041] In this specification, a transistor refers to an element including at least three terminals: a gate electrode (control electrode), a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain) and the source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region where current mainly flows.

[0042] In this specification, the first pole can be the drain electrode, the second pole can be the source electrode, or the first pole can be the source electrode, and the second pole can be the drain electrode. In the case of using transistors with opposite polarities or when the current direction changes during circuit operation, etc., the functions of the "source electrode" and "drain electrode" sometimes switch with each other. Therefore, in this specification, the "source electrode" and "drain electrode" can be switched with each other.

[0043] In this specification, "electrically connected" includes the case where components are connected together through an element having a certain electrical effect. There is no particular limitation on the "element having a certain electrical effect" as long as it can transfer electrical signals between the components to be connected. Examples of the "element having a certain electrical effect" include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0044] The following describes the solutions of the embodiments of the present disclosure with reference to the accompanying drawings.

[0045] Figure 1 It is a schematic structural diagram of a display device. As Figure 1 shown, the OLED display device may include a timing controller, a data signal driver, a scan signal driver, a light emission signal driver, and a pixel array. The pixel array may include a plurality of scan signal lines (S1 to Sm), a plurality of data signal lines (D1 to Dn), a plurality of light emission signal lines (E1 to Eo), and a plurality of sub-pixels Pxij. In an exemplary embodiment, the timing controller may provide a gray value and a control signal suitable for the specification of the data signal driver to the data signal driver, may provide a clock signal, a scan start signal, etc. suitable for the specification of the scan signal driver to the scan signal driver, and may provide a clock signal, an emission stop signal, etc. suitable for the specification of the light emission signal driver to the light emission signal driver. The data signal driver may use the gray value and the control signal received from the timing controller to generate data voltages to be provided to the data signal lines D1, D2, D3, ……, and Dn. For example, the data signal driver may sample the gray value using a clock signal and apply the data voltage corresponding to the gray value to the data signal lines D1 to Dn in units of pixel rows, and n may be a natural number. The scan signal driver may generate scan signals to be provided to the scan signal lines S1, S2, S3, ……, and Sm by receiving a clock signal, a scan start signal, etc. from the timing controller. For example, the scan signal driver may sequentially provide scan signals having conductive level pulses to the scan signal lines S1 to Sm. For example, the scan signal driver may be configured in the form of a shift register and may generate scan signals in such a way that the scan start signal provided in the form of a conductive level pulse is sequentially transmitted to the next-stage circuit under the control of the clock signal, and m may be a natural number. The light emission signal driver may generate emission signals to be provided to the light emission signal lines E1, E2, E3, ……, and Eo by receiving a clock signal, an emission stop signal, etc. from the timing controller. For example, the light emission signal driver may sequentially provide emission signals having cut-off level pulses to the light emission signal lines E1 to Eo. For example, the light emission signal driver may be configured in the form of a shift register and may generate light emission signals in such a way that the light emission stop signal provided in the form of a cut-off level pulse is sequentially transmitted to the next-stage circuit under the control of the clock signal, and o may be a natural number. The pixel array may include a plurality of sub-pixels Pxij. Each sub-pixel Pxij may be connected to a corresponding data signal line, a corresponding scan signal line, and a corresponding light emission signal line, and i and j may be natural numbers. The sub-pixel Pxij may refer to a sub-pixel in which a transistor is connected to the i-th scan signal line and the j-th data signal line.

[0046] Figure 2 It is a schematic plan view of a display substrate. As Figure 2 shown, the display substrate may include a plurality of pixel units P arranged in a matrix. At least one of the plurality of pixel units P includes a first sub-pixel P1 that emits light rays of a first color, a second sub-pixel P2 that emits light rays of a second color, and a third sub-pixel P3 that emits light rays of a third color. The first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 each include a pixel driving circuit and a light-emitting device. The pixel driving circuits in the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 are respectively connected to a scan signal line, a data signal line, and a light-emitting signal line. The pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting device. The light-emitting devices in the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 are respectively connected to the pixel driving circuits of the corresponding sub-pixels, and the light-emitting devices are configured to emit light of corresponding brightness in response to the current output by the pixel driving circuits of the corresponding sub-pixels.

[0047] In an exemplary embodiment, the pixel unit P may include a red (R) sub-pixel, a green (G) sub-pixel, and a blue (B) sub-pixel, or may include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel. The present disclosure does not make a limitation herein. In an exemplary embodiment, the shape of the sub-pixels in the pixel unit may be rectangular, rhombic, pentagonal, or hexagonal. When the pixel unit includes three sub-pixels, the three sub-pixels may be arranged in a horizontal side-by-side, vertical side-by-side, or triangular pyramid manner. When the pixel unit includes four sub-pixels, the four sub-pixels may be arranged in a horizontal side-by-side, vertical side-by-side, or square manner. The present disclosure does not make a limitation herein.

[0048] In an exemplary embodiment, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, or 7T1C structure. Figure 3 It is a schematic equivalent circuit diagram of a pixel driving circuit. As Figure 3 shown, the pixel driving circuit may include seven transistors (a first transistor T1 to a seventh transistor T7), one storage capacitor C, and seven signal lines (a data signal line D, a first scan signal line S1, a second scan signal line S2, a light-emitting signal line E, an initial signal line INIT, a first power supply line VDD, and a second power supply line VSS).

[0049] In an exemplary embodiment, a first end of the storage capacitor C is connected to the first power supply line VDD, and a second end of the storage capacitor C is connected to a second node N2, that is, the second end of the storage capacitor C is connected to a control electrode of the third transistor T3.

[0050] The control electrode of the first transistor T1 is connected to the second scan signal line S2, the first electrode of the first transistor T1 is connected to the initial signal line INIT, and the second electrode of the first transistor is connected to the second node N2. When a conduction-level scan signal is applied to the second scan signal line S2, the first transistor T1 transfers an initialization voltage to the control electrode of the third transistor T3 to initialize the charge amount at the control electrode of the third transistor T3.

[0051] The control electrode of the second transistor T2 is connected to the first scan signal line S1, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the third node N3. When a conduction-level scan signal is applied to the first scan signal line S1, the second transistor T2 connects the control electrode and the second electrode of the third transistor T3.

[0052] The control electrode of the third transistor T3 is connected to the second node N2, that is, the control electrode of the third transistor T3 is connected to the second end of the storage capacitor C. The first electrode of the third transistor T3 is connected to the first node N1, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 can be referred to as a driving transistor. The third transistor T3 determines the amount of driving current flowing between the first power supply line VDD and the second power supply line VSS according to the potential difference between its control electrode and the first electrode.

[0053] The control electrode of the fourth transistor T4 is connected to the first scan signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the first node N1. The fourth transistor T4 can be referred to as a switching transistor, a scan transistor, etc. When a conduction-level scan signal is applied to the first scan signal line S1, the fourth transistor T4 inputs the data voltage of the data signal line D into the pixel driving circuit.

[0054] The control electrode of the fifth transistor T5 is connected to the light-emitting signal line E, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1. The control electrode of the sixth transistor T6 is connected to the light-emitting signal line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light-emitting device. The fifth transistor T5 and the sixth transistor T6 can be referred to as light-emitting transistors. When a conduction-level light-emitting signal is applied to the light-emitting signal line E, the fifth transistor T5 and the sixth transistor T6 cause the light-emitting device to emit light by forming a driving current path between the first power supply line VDD and the second power supply line VSS.

[0055] The control electrode of the seventh transistor T7 is connected to the first scan signal line S1, the first electrode of the seventh transistor T7 is connected to the initial signal line INIT, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light-emitting device. When a conductive-level scan signal is applied to the first scan signal line S1, the seventh transistor T7 transfers an initialization voltage to the first electrode of the light-emitting device to initialize the electric charge accumulated in the first electrode of the light-emitting device or release the electric charge accumulated in the first electrode of the light-emitting device.

[0056] In an exemplary embodiment, the second electrode of the light-emitting device is connected to the second power supply line VSS, the signal of the second power supply line VSS is a low-level signal, and the signal of the first power supply line VDD is a continuously provided high-level signal. The first scan signal line S1 is a scan signal line in the pixel driving circuit of the current display row, and the second scan signal line S2 is a scan signal line in the pixel driving circuit of the previous display row. That is, for the nth display row, the first scan signal line S1 is S(n), and the second scan signal line S2 is S(n - 1). The second scan signal line S2 of the current display row and the first scan signal line S1 in the pixel driving circuit of the previous display row are the same signal line, which can reduce the signal lines of the display panel and achieve a narrow border of the display panel.

[0057] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 can be P-type transistors, or can be N-type transistors. Using transistors of the same type in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementation manners, the first transistor T1 to the seventh transistor T7 can include P-type transistors and N-type transistors.

[0058] In an exemplary embodiment, the first scan signal line S1, the second scan signal line S2, the light-emitting signal line E, and the initial signal line INIT extend in the horizontal direction, and the second power supply line VSS, the first power supply line VDD, and the data signal line D extend in the vertical direction.

[0059] In an exemplary embodiment, the light-emitting device can be an organic light-emitting diode (OLED), including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode).

[0060] Figure 4 It is a timing diagram of the operation of a pixel driving circuit. The following uses Figure 3 the operation process of the exemplary pixel driving circuit to illustrate the exemplary embodiments of the present disclosure. Figure 3The pixel driving circuit therein includes seven transistors (a first transistor T1 to a sixth transistor T7), one storage capacitor C, and seven signal lines (a data signal line D, a first scan signal line S1, a second scan signal line S2, a light-emitting signal line E, an initial signal line INIT, a first power supply line VDD, and a second power supply line VSS). All seven transistors are P-type transistors.

[0061] In an exemplary embodiment, the operation process of the pixel driving circuit may include:

[0062] A first stage A1, called a reset stage, in which the signal of the second scan signal line S2 is a low-level signal, and the signals of the first scan signal line S1 and the light-emitting signal line E are high-level signals. The low-level signal of the second scan signal line S2 turns on the first transistor T1, and the signal of the initial signal line INIT is provided to the second node N2 to initialize the storage capacitor C and clear the original data voltage in the storage capacitor. The high-level signals of the first scan signal line S1 and the light-emitting signal line E turn off the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7. In this stage, the OLED does not emit light.

[0063] A second stage A2, called a data writing stage or a threshold compensation stage, in which the signal of the first scan signal line S1 is a low-level signal, and the signals of the second scan signal line S2 and the light-emitting signal line E are high-level signals, and the data signal line D outputs a data voltage. In this stage, since the second end of the storage capacitor C is at a low level, the third transistor T3 is turned on. The low-level signal of the first scan signal line S1 turns on the second transistor T2, the fourth transistor T4, and the seventh transistor T7. The conduction of the second transistor T2 and the fourth transistor T4 causes the data voltage output by the data signal line D to be provided to the second node N2 through the first node N1, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2, and the difference between the data voltage output by the data signal line D and the threshold voltage of the third transistor T3 is charged into the storage capacitor C. The voltage at the second end (the second node N2) of the storage capacitor C is Vd - |Vth|, where Vd is the data voltage output by the data signal line D and Vth is the threshold voltage of the third transistor T3. The conduction of the seventh transistor T7 provides the initial voltage of the initial signal line INIT to the first electrode of the OLED to initialize (reset) the first electrode of the OLED, empty the pre-stored voltage inside it, complete the initialization, and ensure that the OLED does not emit light. The high-level signal of the second scan signal line S2 turns off the first transistor T1. The high-level signal of the light-emitting signal line E turns off the fifth transistor T5 and the sixth transistor T6.

[0064] The third stage A3, known as the light-emitting stage, has a low-level signal on the light-emitting signal line E, and high-level signals on the first scan signal line S1 and the second scan signal line S2. The low-level signal on the light-emitting signal line E turns on the fifth transistor T5 and the sixth transistor T6. The power supply voltage output from the first power supply line VDD provides a driving voltage to the first electrode of the OLED through the turned-on fifth transistor T5, third transistor T3, and sixth transistor T6, driving the OLED to emit light.

[0065] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the second node N2 is Vdata - |Vth|, the driving current of the third transistor T3 is:

[0066] I = K * (Vgs - Vth) 2 = K * [(Vdd - Vd + |Vth|) - Vth] 2 = K * [(Vdd - Vd] 2

[0067] Wherein, I is the driving current flowing through the third transistor T3, which is also the driving current for driving the OLED, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vd is the data voltage output from the data signal line D, and Vdd is the power supply voltage output from the first power supply line VDD.

[0068] Embodiments of the present disclosure provide a display panel, including: a display area and a second border area located on one side of the display area along the second direction. The display area includes a plurality of detection display unit groups, and each detection display unit group includes a plurality of sub-pixels. The second border area includes a plurality of chamfered areas; the display panel includes: at least two first crack detection lines and a plurality of detection units, wherein:

[0069] At least one first crack detection line passes through one or two chamfered areas, and different first crack detection lines pass through different chamfered areas. One end of the first crack detection line passing through one chamfered area is electrically connected to a detection display unit group through the detection unit, and is configured to provide, under the control of the detection unit, a first detection signal transmitted by the first crack detection line in the chamfered area to the detection display unit group, so as to determine whether there is a crack in the chamfered area passed through by the first crack detection line according to the display result of the detection display unit group. Different chamfered areas correspond to different detection display unit groups.

[0070] In an embodiment of the present disclosure, a detection display unit group includes a plurality of sub-pixels. The plurality of sub-pixels can form a certain pattern in the display area. For example, the plurality of sub-pixels can be a plurality of sub-pixels arranged along a second direction. When the detection display unit group emits light, a bright line is formed on the display substrate. Alternatively, a detection display unit group can form other patterns in the display area, such as one or more straight lines extending in any direction, one or more triangles, one or more polygons, one or more circles, or any other arbitrary shape, and the present disclosure does not limit this.

[0071] In an embodiment of the present disclosure, when a first crack detection line passes through a chamfered area, one end of the first crack detection line can be used to receive a first detection signal, and the other end can be electrically connected to a detection display unit group through a detection unit. When a first crack detection line passes through two chamfered areas, one end of the first crack detection line can be electrically connected to a detection display unit group through a detection unit after passing through one chamfered area, and the other end of the first crack detection line can be electrically connected to another detection display unit group through another detection unit after passing through another chamfered area. The first crack detection line located between the two passed chamfered areas can be configured to receive the first detection signal, so that the first detection signal can be transmitted to the detection display unit groups corresponding to the two passed chamfered areas respectively after passing through the two passed chamfered areas.

[0072] In the first crack detection line display panel provided by the embodiment of the present disclosure, at least two first crack detection lines are provided. Each first crack detection line passes through one or two chamfered areas. One end passing through one chamfered area is electrically connected to a detection display unit group on the display area. Different chamfered areas correspond to different detection display unit groups. According to the display result of the detection display unit group, it can be determined which chamfered area has a crack. The detection result is accurate, and manual microscopy is not required, saving manpower and avoiding damage to the product that may be caused by manual operation.

[0073] In some exemplary embodiments, the first crack detection line can be a panel crack detect (PCD) signal line.

[0074] In some exemplary embodiments, the two chamfered areas passed through by the first crack detection line are arranged along a first direction, and the first direction intersects with the second direction.

[0075] In some exemplary embodiments, the detection unit is electrically connected to a test control line and is configured to conduct the connected first crack detection line and the corresponding detection display unit group under the control of the test control line.

[0076] In some exemplary embodiments, the detection unit includes: a detection transistor, a control electrode of the detection transistor is electrically connected to the test control line, a first pole of the detection transistor is electrically connected to the first crack detection line, and a second pole of the detection transistor is electrically connected to the detection display unit group.

[0077] In some exemplary embodiments, the detection transistor is a P-type transistor.

[0078] In some exemplary embodiments, the first crack detection line is electrically connected to a first detection signal terminal, the first detection signal terminal is configured to provide the first detection signal to the first crack detection line, and a connection position between the first crack detection line and the first detection signal terminal is located between two chamfered areas through which the first crack detection line passes.

[0079] In some exemplary embodiments, the plurality of chamfered areas include: a first chamfered area, a second chamfered area, a third chamfered area, and a fourth chamfered area; the third chamfered area is located on a side of the first chamfered area away from the display area in the second direction, and the fourth chamfered area is located on a side of the second chamfered area away from the display area in the second direction. One of the first crack detection lines passes through one of the first chamfered area and the third chamfered area and one of the second chamfered area and the fourth chamfered area, and the other first crack detection line passes through the remaining two chamfered areas.

[0080] In some exemplary embodiments, two detection units connected by one of the first crack detection lines are located on a side of the display area close to the second border area, and two detection units connected by the other first crack detection line are located on a side of the display area away from the second border area.

[0081] In some exemplary embodiments, two detection units connected by one of the first crack detection lines, and one detection unit connected by the other first crack detection line are located on a side of the display area close to the second border area, and the other detection unit connected by the other first crack detection line is located on a side of the display area away from the second border area.

[0082] In some exemplary embodiments, the second border area includes a bending area, the bending area is configured to bend a display panel on a side away from the display area to the back side of the display area; the plurality of chamfered areas are respectively located on a side of the bending area close to the display area and a side away from the display area.

[0083] In some exemplary embodiments, the display panel further includes: at least one second crack detection line disposed around the display area, configured to transmit a second detection signal to a corresponding detection display unit group under the control of the detection unit, so as to determine whether there is a crack in the display panel where the second crack detection line corresponding to the detection display unit group is located according to the display result of the detection display unit group. The second crack detection line is connected to different detection display unit groups through different detection units, the detection unit connected to the second crack detection line is different from the detection unit connected to the first crack detection line, and the detection display unit group corresponding to the second crack detection line is different from the detection display unit group corresponding to the first crack detection line.

[0084] The display panel provided by the embodiments of the present disclosure will be described below through exemplary embodiments.

[0085] Figure 5 It is a schematic structural diagram of a display panel in an exemplary embodiment. As Figure 5 shown, the display panel includes: a display area 10, a first border area 22 surrounding the display area 10, and a second border area on one side of the display area 10. The display area 10 includes a plurality of pixels and a plurality of data signal lines connected to the plurality of pixels. The second border area includes a routing area (table neck) S1 and a signal access area 23 arranged in sequence along the direction away from the display area 10 (i.e., the second direction Y). The routing area S1 is located on the side of the first border area 22 away from the display area 10. The routing area S1 communicates with the first border area 22. A bending area 202 is provided in the routing area S1. The signal access area 23 is located on the side of the routing area S1 away from the display area 10. The signal access area 23 communicates with the routing area S1. The signal access area 23 includes: a circuit area 204 and a bonding pin area 205 arranged in sequence along the direction away from the display area 10 (i.e., the second direction Y).

[0086] In this exemplary embodiment, the bending region 202 is configured such that a part of the wiring region S1 and the signal access region 23 away from the display region 10 are bent to the back surface of the display region 10. The circuit region 204 is configured to provide a corresponding integrated circuit. The bonding pin region 205 is configured to provide a plurality of bonding pins, and the plurality of bonding pins can bond a flexible printed circuit (FPC) such that a plurality of signal leads (e.g., driving control lines, power lines, first crack detection lines, test control lines, second crack detection lines, etc.) are connected to an external control device through the plurality of bonding pins. After passing through the wiring region S1, the plurality of signal leads are connected to corresponding positions of the display region 10 along the first border region 22. In some examples, the integrated circuit provided in the circuit region 204 may be a touch and display driver integrated circuit (TDDI). However, the present disclosure is not limited thereto.

[0087] In this exemplary embodiment, as Figure 5 shown, the wiring region S1 includes a chamfered region A (first chamfered region), a chamfered region B (second chamfered region) on the side close to the display region 10, and a chamfered region C (third chamfered region), a chamfered region D (fourth chamfered region) on the side away from the display region 10. Among them, the chamfered regions A and B are distributed at both ends of the wiring region S1 along the first direction X and are located on the side of the bending region 202 close to the display region 10. The chamfered regions C and D are distributed at both ends of the wiring region S1 along the first direction X and are located on the side of the bending region 202 away from the display region 10. In actual production, the wiring region S1 is relatively narrow, and cracks are likely to occur in the generated chamfered regions. Detecting whether there are cracks and the accurate positions of the cracks is very important for the production process. The first direction X and the second direction Y intersect, and the first direction X and the second direction Y may be perpendicular to each other.

[0088] Figure 5 The display region 10 shown is circular. However, the present disclosure is not limited thereto. For example, the display region 10 may be rectangular, oval, or other shapes. Figure 5 illustrates the case where there are four chamfered regions in the display panel. The shape of the wiring region S1 and the number of chamfered regions can be designed according to actual needs. For example: the wiring region S1 can be designed as a polygonal shape, and a plurality of chamfered regions can be provided. The present disclosure is not limited thereto.

[0089] Figure 6 is a schematic diagram of the circuit layout of a display panel in an exemplary embodiment. Figure 6 Taking Figure 5 the display panel with the structure shown as an example for illustration, Figure 6Figure 0 schematically shows the position of the display area 10 and the positions of four chamfered areas, with the first border area exaggerated and the other structures omitted. As Figure 6 shown, two first crack detection lines, namely the first crack detection line 31 and the first crack detection line 32, are provided on the display panel. In this embodiment, each first crack detection line passes through two different chamfered areas. In other embodiments, the first crack detection line can be set to pass through one chamfered area as needed. As Figure 6 shown, the first crack detection line 31 passes through the chamfered area C and the chamfered area B. The first crack detection line 31 between the chamfered area C and the chamfered area B is set to be connected to a first detection signal terminal (not shown in the figure) for receiving a first detection signal V1. The first crack detection line 32 passes through the chamfered area A and the chamfered area D. The first crack detection line 32 between the chamfered area A and the chamfered area D is set to be connected to the first detection signal terminal for receiving the first detection signal V1. The two ends of the first crack detection line 31 and the first crack detection line 32 are respectively connected to different detection units 50. The different detection units 50 can be electrically connected to the detection and display unit group of the display area 10 for transmitting the first detection signal V1 passing through different chamfered areas to different detection and display unit groups. The detection unit 50 can control the on / off of the signal transmission between the first crack detection line and the detection and display unit group. As Figure 6 shown, one end of the first crack detection line 32 passing through the chamfered area A of the different detection units 50 can be connected to the detection and display unit group 13, one end of the first crack detection line 31 passing through the chamfered area C can be connected to the data signal line 11, one end of the first crack detection line 31 passing through the chamfered area B can be connected to the detection and display unit group 12, and one end of the first crack detection line 32 passing through the chamfered area D can be connected to the detection and display unit group 14. By setting the connection position with the first detection signal terminal on the first crack detection line and at a position between the chamfered areas passed through, the first detection signal V1 can pass through different chamfered areas and be transmitted to different data signal lines, realizing that even when one first crack detection line passes through two chamfered areas, these two chamfered areas can also be detected separately. In other embodiments, the connection relationship between the line end of the first crack detection line and the detection and display unit group can be set as needed, which chamfered area or which two chamfered areas the first crack detection line passes through can be set as needed, and the shape and position of the detection and display unit group can be set as needed. The present disclosure does not limit this.

[0090] In the embodiment of the present disclosure, the detection and display unit group can be set as Figure 6A column of sub-pixels arranged in the second direction as shown is used to detect whether there are cracks in the chamfered area through bright line testing or dark line testing. Bright line testing means controlling the detection display unit group corresponding to the chamfered area with cracks to emit light, so that bright lines appear on the completely black screen. Since the bright lines formed by the detection display unit group correspond to different chamfered areas, the position of the bright lines on the screen can be used to determine which chamfered area has cracks. Dark line testing means controlling the detection display unit group corresponding to the chamfered area with cracks not to emit light, so that dark lines appear on the bright screen. Since the dark lines formed by the detection display unit group correspond to different chamfered areas, the position of the dark lines on the screen can be used to determine which chamfered area has cracks. The implementation details of bright line testing and dark line testing will not be elaborated here.

[0091] In some technologies, it is only possible to distinguish whether there are cracks in the chamfered area located on the left or right side of the wiring area, but it is not possible to specifically locate which one or which several chamfered areas have cracks, and the detection accuracy is not high. When cracks are detected, manual microscopy is required to determine the position of the cracks, which results in high labor costs and may affect the product quality due to manual operations. In addition, after the product is bent along the bending area 202, the chamfered area A and the chamfered area B will be blocked, so that it is impossible to perform microscopy on the chamfered area A and the chamfered area B, and there is a risk of missed detection, which may bring product quality risks. However, for the display panel provided by the embodiments of the present disclosure, by connecting the line ends of the first crack detection lines passing through different chamfered areas to different detection display unit groups, the display results of the detection display unit groups correspond one-to-one to the chamfered areas, and it is possible to intuitively show which chamfered area has cracks, thus well solving the above problems.

[0092] Figure 7 It is a schematic diagram of the circuit layout of the display panel in another exemplary embodiment. Figure 7 Take Figure 5 the display panel with the structure shown as an example for illustration. Figure 7 The position of the display area 10 and four chamfered areas is schematically shown, the first border area is exaggeratedly shown, and the rest of the structure is omitted schematically. As Figure 7As shown, the detection unit is electrically connected to the test control line 51. The test control line 51 can be arranged to surround the display area 10 and is used to receive the test control signal VC. The detection unit can include a detection transistor. The detection transistor can be a P-type transistor. The control electrode of the P-type transistor is connected to the test control line 51. The first electrode of the P-type transistor is connected to the first crack detection line, and the second electrode is connected to the detection display unit group. In this embodiment, the detection transistors corresponding to the chamfered areas A can include: the third switching transistor P3, the detection transistors corresponding to the chamfered area B can include: the second switching transistor P2, the detection transistors corresponding to the chamfered area C can include: the first switching transistor P1, and the detection transistors corresponding to the chamfered area D can include: the fourth switching transistor P4. One end of the first crack detection line 32 passing through the chamfered area A can be connected to the detection display unit group 13 through the third switching transistor P3, one end of the first crack detection line 31 passing through the chamfered area C can be connected to the detection display unit group 11 through the first switching transistor P1, one end of the first crack detection line 31 passing through the chamfered area B can be connected to the detection display unit group 12 through the second switching transistor P2, and one end of the first crack detection line 32 passing through the chamfered area D can be connected to the detection display unit group 14 through the fourth switching transistor P4. In other embodiments, multiple test control lines can be set to control different detection transistors respectively. The detection transistors can be set as N-type transistors or other elements with switching functions. The present disclosure does not limit this. In this embodiment, P-type transistors can be used in the pixel driving circuit. The first detection signal V1 can be a high-level signal, and the test control signal VC can be a low-level signal. When performing a bright line test, taking the first switching transistor P1 as an example, for example: the second electrode of the first switching transistor P1 can be connected to the gate of the fourth transistor T4 in each sub-pixel of the detection display unit group 11. The first switching transistor P1 conducts after receiving the test control signal VC. When there is no crack in the chamfered area C, the first detection signal V1 is introduced into the gate of the fourth transistor T4. Since the fourth transistor T4 is a P-type transistor, it will not conduct after receiving the first detection signal V1 (high-level signal). Therefore, the detection display unit group 11 will not be lit. However, when there is a crack in the chamfered area C, the first detection signal V1 will not be introduced into the detection display unit group 11, and the fourth transistor T4 can be conducted, and the detection display unit group 11 will be lit, forming a bright line on the screen. The detection principles of the remaining switching transistors are similar to that of the first switching transistor P1 and will not be elaborated here. The chamfered area with a crack can be determined according to the position of the bright line on the screen.

[0093] Figure 8 FIG. is a schematic diagram of the circuit layout of the display panel in yet another exemplary embodiment. Figure 8 And Figure 7The circuit layouts are basically the same, except that: the chamfered areas through which the first crack detection line 31 and the first crack detection line 32 pass are different. In this embodiment, after one end of the first crack detection line 31 passes through the chamfered area C, it is connected to the detection and display unit group 11 through the first switching transistor P1. After the other end of the first crack detection line 31 passes through the chamfered area D, it is connected to the detection and display unit group 12 through the second switching transistor P2. One end of the first crack detection line 32 passes through the chamfered area A and is connected to the detection and display unit group 13 through the third switching transistor P3. The other end of the first crack detection line 32 passes through the chamfered area B and is connected to the detection and display unit group 14 through the fourth switching transistor P4. In other embodiments, the number of the first crack detection lines and the ways in which the first crack detection lines pass through the chamfered areas can be set as needed, and the present disclosure does not limit this.

[0094] In Figure 7 and Figure 8 the routing settings of, the chamfered areas through which the first crack detection line 31 and the first crack detection line 32 pass are both chamfered areas that are not adjacent in the second direction Y. In other embodiments, a crack detection line can be set to pass through chamfered areas that are adjacent in the second direction Y. For example: the first crack detection line 31 can pass through the chamfered area A and the chamfered area C, and the second crack detection line 32 can pass through the chamfered area B and the chamfered area D. The present disclosure does not limit this.

[0095] In Figure 7 and Figure 8 the routing settings of, one end of the first crack detection line 31 surrounds the left side of the display area 10 and then is connected to the first switching transistor P1, and the other end of the first crack detection line 31 surrounds the right side of the display area 10 and then is connected to the second switching transistor P2. That is, the two detection units connected by the first crack detection line 31 are located on one side of the display area 10 close to the second border area, and the two detection units connected by the first crack detection line 32 are located on the side of the display area 10 far from the second border area. This setting makes the area bypassed by the first crack detection line 31 larger, can detect cracks in the peripheral area of the display panel, and makes it easier to find product defects. In other embodiments, the routing method of the first crack detection line 32 can also be adopted, so that the first crack detection line 31 is connected to the switching transistor immediately after passing through the chamfered area, or other winding methods can be adopted, and the present disclosure does not limit this.

[0096] Figure 9 is a schematic diagram of the circuit layout of the display panel in another exemplary embodiment. Figure 9 With Figure 7The circuit layouts are basically the same, except that: the connection position of the first crack detection line 31 passing through one end of the chamfered area B to the second switching transistor P2 is changed. That is, the two detection units connected by the first crack detection line 32, and one detection unit (P2) connected by the first crack detection line 31 are located on the side of the display area 10 close to the second border area, and the other detection unit (P1) connected by the first crack detection line 31 is located on the side of the display area 10 far from the second border area. In this connection mode, the first crack detection line 31 surrounding the left side of the display area 10 can continue to extend to the right after being connected to the first switching transistor P1, and partially surround the right side of the display area 10. This design makes the detection area of the first crack detection line 31 larger, and it is easier to detect whether there are cracks in the display product. The routing mode of the first crack detection line can be set as needed, and the present disclosure does not limit this.

[0097] Figure 10 It is a schematic diagram of the circuit layout of a display panel including a second crack detection line in an exemplary embodiment. Figure 10 The first crack detection line in Figure 7 has the same circuit layout and will not be described in detail here. Figure 10 The difference from Figure 7 is that Figure 10 the display panel of Figure 10 includes a second crack detection line 33 and related settings. As shown in Figure 10The detection unit includes a first switching transistor P5 and a second switching transistor P6. The first switching transistor P5 is connected to the second crack detection line 33 and the detection display unit group 15, and the second switching transistor P6 is connected to the second crack detection line 33 and the detection display unit group 16. The second detection signal V2 can be set as a high-level signal, and the first detection signal V1 and the second detection signal V2 can be the same signal. In other embodiments, one or more separate control lines can be provided for the detection units connected to the second crack detection line 33 to control the detection units to transmit the second detection signal to the corresponding detection display unit group, that is, the detection units connected to the second crack detection line 33 do not have to be controlled by the test control line 51. The detection unit can be set as an N-type transistor or other elements with a switching function, and the number and position of the detection units can be set as needed to detect cracks in the edge area of the display panel. The present disclosure does not limit this. In a display panel including a second crack detection line, the wiring arrangement of the first crack detection line can be adopted as Figure 8 or Figure 9 shown, or other wiring forms can be adopted. The present disclosure does not limit the wiring arrangements of the first crack detection line and the second crack detection line. The principle of panel crack detection can refer to the description of the principle of crack detection in the chamfer area above, and will not be elaborated here. Through the wiring arrangement of this embodiment, panel crack detection and chamfer area crack detection can be performed simultaneously, saving the wiring space, saving the test time, and improving the test efficiency.

[0098] An embodiment of the present disclosure provides a display device, including the display panel described in any of the above embodiments.

[0099] An embodiment of the present disclosure provides a method for detecting cracks in a display panel, which is applied to detect the above display panel. The method includes: inputting a first detection signal to at least two first crack detection lines, and providing, under the control of the detection unit, the first detection signal transmitted by the crack detection line in the chamfer area to the detection display unit group corresponding to the chamfer area. Determine whether there are cracks in the chamfer area passed through by the first crack detection line according to the display result of the detection display unit group.

[0100] In some exemplary embodiments, the method further includes: pre-configuring the correspondence between the chamfer area of the display panel and the detection display unit group.

[0101] In some exemplary embodiments, the method further includes: inputting a test control signal to at least one test control line.

[0102] In some exemplary embodiments, the method further includes: inputting a second detection signal to at least one second crack detection line, and under the control of the detection unit, transmitting the second detection signal to the corresponding detection and display unit group. Determine whether there is a crack in the display panel where the second crack detection line is located according to the display result of the detection and display unit group.

[0103] For other detailed settings of this embodiment, reference may be made to the description of the above embodiments, which will not be elaborated here.

Claims

1. A display panel, characterized in that, Comprising: A display area and a second border area located on one side of the display area along a second direction, the display area including a plurality of detection display unit groups, each detection display unit group including a plurality of sub-pixels; the second border area including a plurality of chamfered areas; the display panel including: at least two first crack detection lines and a plurality of detection units, wherein: At least one first crack detection line passes through two chamfered areas, and a middle position of the first crack detection line located in the two chamfered areas is set to receive a first detection signal, and the chamfered areas passed through by different first crack detection lines are different; one end of the first crack detection line passing through one chamfered area is electrically connected to a detection display unit group through the detection unit, and is configured to provide, under the control of the detection unit, the first detection signal transmitted by the first crack detection line in the chamfered area to the detection display unit group, so as to determine whether there is a crack in the chamfered area passed through by the first crack detection line according to the display result of the detection display unit group, and each different chamfered area corresponds to a different detection display unit group; The plurality of chamfered areas include: a first chamfered area, a second chamfered area, a third chamfered area, and a fourth chamfered area; the third chamfered area is located on one side of the first chamfered area away from the display area in the second direction, and the fourth chamfered area is located on one side of the second chamfered area away from the display area in the second direction; one first crack detection line passes through one of the first chamfered area and the third chamfered area and one of the second chamfered area and the fourth chamfered area, and the other first crack detection line passes through the remaining two chamfered areas; The display panel further includes: at least one second crack detection line disposed around the display area, configured to transmit a second detection signal to a corresponding detection display unit group under the control of the detection unit, so as to determine whether there is a crack in the display panel where the second crack detection line corresponding to the detection display unit group is located according to the display result of the detection display unit group; the second crack detection line is located on a side of the first crack detection line close to the display area; The second crack detection line is connected to different detection display unit groups through different detection units, and the detection unit connected to the second crack detection line is different from the detection unit connected to the first crack detection line, and the detection display unit group corresponding to the second crack detection line is different from the detection display unit group corresponding to the first crack detection line.

2. The display panel according to claim 1, wherein The detection unit is electrically connected to a test control line, and is configured to conduct the connected first crack detection line and the corresponding detection display unit group under the control of the test control line.

3. The display panel according to claim 2, wherein The detection unit includes: a detection transistor, a control electrode of the detection transistor is electrically connected to the test control line, a first electrode of the detection transistor is electrically connected to the first crack detection line, and a second electrode of the detection transistor is electrically connected to the detection display unit group.

4. The display panel according to claim 3, characterized in that, The detection transistor is a P-type transistor.

5. The display panel according to claim 1, wherein The first crack detection line is electrically connected to the first detection signal terminal, and the first detection signal terminal is configured to provide the first detection signal to the first crack detection line. The connection position between the first crack detection line and the first detection signal terminal is located between two chamfered areas through which the first crack detection line passes.

6. The display panel according to claim 1, wherein Two detection units connected to one of the first crack detection lines are located on one side of the display area close to the second border area, and two detection units connected to the other first crack detection line are located on the side of the display area far from the second border area.

7. The display panel according to claim 1, wherein Two detection units connected to one of the first crack detection lines, and one detection unit connected to the other first crack detection line are located on one side of the display area close to the second border area, and the other detection unit connected to the other first crack detection line is located on the side of the display area far from the second border area.

8. The display panel according to claim 1, wherein The second border area includes a bent area; the plurality of chamfered areas are respectively located on one side of the bent area close to the display area and on the side far from the display area.

9. A display device, characterized in that, A display panel according to any one of the above claims 1 to 8.

10. A method for detecting cracks in a display panel, characterized in that, Applied to detect a display panel according to any one of claims 1 to 8, the method includes: Input a first detection signal to at least two first crack detection lines, and under the control of the detection unit, provide the first detection signal transmitted by the crack detection line in the chamfered area to the corresponding detection display unit group corresponding to the chamfered area; Determine whether there is a crack in the chamfered area through which the first crack detection line passes according to the display result of the detection display unit group; Input a second detection signal to at least one second crack detection line, and under the control of the detection unit, transmit the second detection signal to the corresponding detection display unit group; Determine whether there is a crack in the display panel where the second crack detection line is located according to the display result of the detection display unit group.

11. The crack detection method according to claim 10, characterized in that, The method further includes: Pre-configure the corresponding relationship between the chamfered area of the display panel and the detection display unit group.

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