Disposal of reinforcing material structures

Abstract

A method of forming a high-k dielectric cap layer on a semiconductor structure formed on a substrate includes the steps of depositing a high-k dielectric cap layer on the semiconductor structure; forming a sacrificial silicon cap layer on the high-k dielectric cap layer; performing a post-cap anneal process to harden and densify the deposited high-k dielectric cap layer; and removing the sacrificial silicon cap layer.

Description

Technical Field

[0001] The various embodiments described herein generally relate to semiconductor device fabrication, and in particular, to systems and methods for forming high-quality, high-k dielectric material layers and metal gate structures in semiconductor structures. Background Technology

[0002] As metal-oxide-semiconductor field-effect transistors (MOSFETs) have shrunk in size to achieve high device performance and low power consumption, the thickness of traditional silicon dioxide (SiO2) gate dielectrics has been reduced to its physical limit. Therefore, replacing the silicon dioxide gate dielectric with a high-k dielectric material is inevitable for further scaling. Among various high-k dielectric materials, hafnium oxide (HfO2) has been used since the 45nm MOSFET technology node due to its high dielectric constant and superior thermal stability on silicon substrates. However, for further reductions in equivalent oxide thickness (EOT) at the 32nm MOSFET technology node and beyond, simply reducing the thickness of the high-k dielectric layer is problematic because it increases leakage current flowing through it.

[0003] Furthermore, traditional polycrystalline silicon (polysilicon) gates have been replaced by metal gates formed from metal layers (e.g., titanium (Ti), tantalum (Ta), tungsten (W)) and metal-containing conductive compound layers (e.g., titanium nitride (TiN), tantalum nitride (TaN)) to reduce the undesirable voltage drop associated with the polycrystalline silicon depletion effect and to improve the drive current performance and operating speed of MOSFETs. However, such metal gates are typically formed using a furnace-based process that uses metal-containing precursors (e.g., titanium chloride, TiCl4) and nitrogen-containing precursors (e.g., ammonia, NH3). This process can involve high oxygen concentrations, and therefore may not be ideal for future scalability.

[0004] Therefore, there is a need for systems and methods to form thin (e.g., EOT less than 1 nm) high-κ dielectric material layers and to form metal gates without high oxygen concentrations, such material layers having chemical structures that can be controlled to ensure desired structural and electrical properties. Summary of the Invention

[0005] Several embodiments of this disclosure provide a method for forming a high-k dielectric cap layer on a semiconductor structure formed on a substrate. The method includes the steps of: depositing the high-k dielectric cap layer on the semiconductor structure; depositing a sacrificial silicon cap layer on the high-k dielectric cap layer; performing a post-cap annealing process to harden and densify the deposited high-k dielectric cap layer; and removing the sacrificial silicon cap layer.

[0006] Several embodiments of this disclosure also provide a method for forming a high-k dielectric cap layer on a semiconductor structure formed on a substrate. The method includes the steps of: depositing the high-k dielectric cap layer on the semiconductor structure; depositing a sacrificial silicon cap layer on the high-k dielectric cap layer; performing a post-cap annealing process to harden and densify the deposited high-k dielectric cap layer; and removing the sacrificial silicon cap layer.

[0007] Several embodiments of this disclosure further provide a processing system. The processing system includes a first processing chamber, a second processing chamber, a third processing chamber, a fourth processing chamber, and a system controller. The system controller is configured to: deposit a high-k dielectric cap layer on the high-k gate dielectric layer in the first processing chamber; deposit a sacrificial silicon cap layer on the high-k dielectric cap layer in the second processing chamber; perform a post-cap annealing process in the third processing chamber to harden and densify the deposited high-k dielectric cap layer; and remove the sacrificial silicon cap layer in the fourth processing chamber. The substrate is transferred between the first, second, third, and fourth processing chambers without disrupting the vacuum environment in the processing system. Attached Figure Description

[0008] To gain a more detailed understanding of the features described above, this disclosure can be described in more detail by referring to several embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings illustrate only typical embodiments of this disclosure and should not be construed as limiting the scope of this disclosure, as other equivalent embodiments are permissible.

[0009] Figure 1 This is a schematic top view of an example multi-chamber processing system according to one embodiment.

[0010] Figure 2 This is a process flow diagram of a method for forming a semiconductor structure according to one embodiment.

[0011] Figure 3A and Figure 3BThis is a schematic diagram of a semiconductor structure according to one embodiment.

[0012] Figure 4 This is a process flow diagram of a method for forming a semiconductor structure according to one embodiment.

[0013] Figure 5A , Figure 5B and Figure 5C This is a schematic diagram of a semiconductor structure according to one embodiment.

[0014] For ease of understanding, the same reference numerals are used to refer to common elements in all figures whenever possible. It is understood that elements and features of one embodiment can be advantageously incorporated into other embodiments without further declaration. Detailed Implementation

[0015] As gate structures shrink to smaller dimensions, new material structures are constantly being sought to provide improvements. The use of high-κ dielectric materials increases the dielectric constant of the gate structure compared to traditional gate structures utilizing materials such as silicon oxide. However, similar to silicon oxide, leakage current increases as the thickness of the gate structure decreases. For example, gate leakage increases with decreasing effective oxide thickness. Therefore, the inverse relationship between gate leakage and effective oxide thickness can limit the performance of the manufactured devices and transistors.

[0016] Compared to silicon oxide of similar physical thickness, high-κ dielectric materials offer greater electrostatic control over the channel. As the industry continues to seek lower effective oxide thicknesses without increasing gate leakage, efforts to maximize the dielectric constant (also known as the "κ value") of known high-κ materials are reaching their limits due to morphological characteristics. Conventional techniques have already struggled to overcome the inherent properties of high-κ materials (which may set an upper limit on the κ value), and subsequent device modifications have attempted to incorporate new films.

[0017] In addition, typical furnace-based processes that use metal layers and metal-conductive compounds to form metal gates that replace polysilicon can involve high oxygen concentrations during the process, which may not be ideal for future scalability.

[0018] The various embodiments described herein provide systems and methods for forming thin (e.g., EOT less than 1 nm) high-k dielectric material layers and forming metal gates. By producing high-k dielectric materials exhibiting specific morphologies or grain structures, higher dielectric constants and consequently improved device performance can be achieved. To control the in-film morphology in exemplary devices, treatment can be performed to provide an activated substrate surface capable of inducing specific film morphologies, and the film can be stabilized post-formation, which can result in higher dielectric constants. Forming the metal gate without a high oxygen concentration allows for further reduction in the equivalent oxide thickness (EOT).

[0019] Figure 1 This is a schematic top view of an example of a multi-chamber processing system 100 according to some examples of the present disclosure. The processing system 100 generally includes: a fab interface 102; loading and locking chambers 104, 106; transfer chambers 108, 110 with corresponding transfer manipulators 112, 114; holding chambers 116, 118; and processing chambers 120, 122, 124, 126, 128, 130. As detailed herein, wafers in the processing system 100 can be processed in various chambers and transferred between various chambers without exposing the wafers to the surrounding environment outside the processing system 100 (e.g., the atmospheric environment that may exist in a wafer fab). For example, the wafers can be processed in various chambers and transferred between various chambers in a low-pressure (e.g., less than or equal to about 300 Torr) or vacuum environment without disrupting the low-pressure or vacuum environment between the various processes performed on the wafers in the processing system 100. Therefore, the processing system 100 can provide integrated solutions for some processing of the chip.

[0020] Examples of processing systems that can be appropriately modified based on the teachings provided herein include those commercially available from Applied Materials, Inc., located in Santa Clara, California, USA. or An integrated processing system or other suitable processing system. Other processing systems (including those from other manufacturers) are expected to be suitable for benefiting from the various aspects described herein.

[0021] exist Figure 1In the illustrated example, factory interface 102 includes a docking station 140 and factory interface robots 142 to assist in wafer transfer. The docking station 140 is configured to receive one or more front-opening standard bays (FOUPs) 144. In some examples, each factory interface robot 142 generally includes blades 148 disposed at one end of the respective robot, configured to transfer wafers from factory interface 102 to loading and locking chambers 104, 106.

[0022] Loading and locking chambers 104 and 106 have corresponding ports 150 and 152 coupled to factory interface 102 and corresponding ports 154 and 156 coupled to transfer chamber 108. Transfer chamber 108 also has corresponding ports 158 and 160 coupled to holding chambers 116 and 118 and corresponding ports 162 and 164 coupled to processing chambers 120 and 122. Similarly, transfer chamber 110 has corresponding ports 166 and 168 coupled to holding chambers 116 and 118 and corresponding ports 170, 172, 174, and 176 coupled to processing chambers 124, 126, 128, and 130. Ports 154, 156, 158, 160, 162, 164, 166, 168, 170, 172, 174, and 176 can be, for example, slit valve openings with slit valves, for allowing wafers to pass through by means of transfer robots 112 and 114 and for providing a seal between the respective chambers to prevent gas from passing between the chambers. Typically, any port is open for transferring wafers through it. Otherwise, the port is closed.

[0023] Loading and locking chambers 104, 106, transfer chambers 108, 110, holding chambers 116, 118, and processing chambers 120, 122, 124, 126, 128, 130 can be fluidly coupled to a gas and pressure control system (not specifically shown). The gas and pressure control system may include one or more gas pumps (e.g., turbopumps, cryogenic pumps, roughing pumps), gas sources, various valves, and conduits fluidly coupled to the various chambers. In operation, the factory interface robot 142 transfers wafers from FOUP 144 to loading and locking chambers 104 or 106 via ports 150 or 152. The gas and pressure control system then pumps down loading and locking chambers 104 or 106. The gas and pressure control system further maintains transfer chambers 108, 110, and holding chambers 116, 118 in an internal low-pressure or vacuum environment (which may include an inert gas). Therefore, the pump-drying of the locking chamber 104 or 106 facilitates the transfer of wafers between, for example, the atmospheric environment of the factory interface 102 and the low-pressure or vacuum environment of the transfer chamber 108.

[0024] With the wafer already emptied from the loading lock chamber 104 or 106, the transfer robot 112 transfers the wafer from the loading lock chamber 104 or 106 to the transfer chamber 108 via port 154 or 156. The transfer robot 112 is then able to transfer the wafer to any of the processing chambers 120, 122 and holding chambers 116, 118 and / or between any of these chambers, transferring the wafer to the processing chambers 120, 122 for processing via corresponding ports 162, 164, and transferring the wafer to the holding chambers 116, 118 for holding in anticipation of further transfer via corresponding ports 158, 160. Similarly, the transfer robot 114 is capable of picking up wafers from holding chambers 116 or 118 via ports 166 or 168, and is capable of transferring wafers to any of the processing chambers 124, 126, 128, 130 and holding chambers 116, 118 and / or transferring wafers between any of these chambers. Wafers are transferred to processing chambers 124, 126, 128, 130 for processing via corresponding ports 170, 172, 174, 176, and to holding chambers 116, 118 for holding pending further transfer via corresponding ports 166, 168. The transfer and holding of wafers within and between the various chambers can be performed in a low-pressure or vacuum environment provided by a gas and pressure control system.

[0025] Processing chambers 120, 122, 124, 126, 128, and 130 can be any suitable chamber for processing wafers. In some examples, processing chamber 122 can perform cleaning processes, processing chamber 120 can perform etching processes, and processing chambers 124, 126, 128, and 130 can perform corresponding epitaxial growth processes. Processing chamber 122 can be made of SiCoNi available from Applied Materials, Inc., Santa Clara, California, USA. TM Pre-cleaning chamber. The treatment chamber 120 can be a Selectra product available from Applied Materials, Santa Clara, California, USA. TM Etching chamber.

[0026] System controller 190 is coupled to processing system 100 and is used to control processing system 100 or its components. For example, system controller 190 can control the operation of processing system 100 by directly controlling chambers 104, 106, 108, 116, 118, 110, 120, 122, 124, 126, 128, and 130, or by controlling controllers associated with chambers 104, 106, 108, 116, 118, 110, 120, 122, 124, 126, 128, and 130. In operation, system controller 190 can collect data and receive feedback from the respective chambers to coordinate the operation of processing system 100.

[0027] System controller 190 generally includes a central processing unit (CPU) 192, memory 194, and support circuitry 196. CPU 192 can be one of any type of general-purpose processor capable of use in an industrial setting. Memory 194, or a non-transitory computer-readable medium, is accessible by CPU 192 and can be one or more memories such as random access memory (RAM), read-only memory (ROM), floppy disk, hard disk, or any other form of local or remote digital storage device. Support circuitry 196 is coupled to CPU 192 and may include cache, clock circuitry, input / output subsystems, power supply, and similar devices. The various methods disclosed herein can generally be implemented under the control of CPU 192 by executing computer instruction code stored in memory 194 (or memory of a specific process chamber) as, for example, software routines. When the computer instruction code is executed by CPU 192, CPU 192 controls these chambers to perform the process according to various methods.

[0028] Other processing systems may employ different configurations. For example, more or fewer processing chambers may be coupled to a transfer device. In the illustrated example, the transfer device includes transfer chambers 108, 110 and holding chambers 116, 118. In other examples, more or fewer transfer chambers (e.g., one transfer chamber) and / or more or fewer holding chambers (e.g., no holding chambers) may be implemented as transfer devices in a processing system.

[0029] Figure 2 This is a process flow diagram of a method 200 for forming a semiconductor structure 300 according to one or more embodiments of the present disclosure. Figure 3A and Figure 3B This is a cross-sectional view of a portion of the semiconductor structure 300 corresponding to various states of method 200. It should be understood that... Figure 3A and Figure 3BOnly a partial schematic diagram of the semiconductor structure 300 is shown, but the semiconductor structure 300 may include any number of transistor portions and additional materials having the various aspects shown in the figure. It should also be noted that, although... Figure 2 The method steps shown are described in sequence, but other process sequences that include one or more method steps that have been omitted and / or added, and / or rearranged in another desired order also fall within the scope of the various embodiments of this disclosure provided herein.

[0030] Method 200 begins with the pre-cleaning process in block 210 to pre-clean the surface of substrate 302. This pre-cleaning process may include etching the surface of substrate 302 by a dry etching process or a wet etching process using an etching solution, such as a Standard Clean 1 (SC1) etching solution containing NH4OH (ammonium hydroxide), H2O2 (hydrogen peroxide), and H2O (water). The dry etching process may be, for example, SiConi... TM A remote plasma-assisted dry etching process is used, in which the surface of substrate 302 is exposed to N2, NF3, and NH3 plasma byproducts. This can be achieved in applications such as... Figure 1 The pre-cleaning process is performed in a pre-cleaning chamber such as processing chamber 122 or 120 shown.

[0031] In box 220, an interface formation process is performed to form an interface layer 304 on the pre-cleaned surface of substrate 302, such as... Figure 3A As shown in the diagram. The interface formation process may include a suitable thermal oxidation process, such as an enhanced in-situ steam generation (eISSG) process utilizing nitrous oxide (N₂O) gas. The interface layer 304 formed in block 220 is a thin amorphous silicon oxide (SiO₂) layer with a density between approximately With the agreement The thickness between, for example, approximately This corresponds to one or more monolayers of silicon oxide. In some embodiments, the interface layer 304 can be formed by an in-situ vapor generation (ISSG) process using H2 and O2 gases or by a rapid thermal oxidation (RTO) process using NH3 and O2 gases. The interface layer 304 can serve as a nucleation layer for the high-k dielectric material layer to be deposited on the interface layer 304, and improve the quality of the interface between the substrate 302 and the high-k dielectric material layer (e.g., interface state density, accumulation capacitance, frequency dispersion, and leakage current). It can be used in, for example... Figure 1 The interface forming process is performed in a processing chamber such as processing chamber 120, 122, 124, 126, 128 or 130 shown.

[0032] In some embodiments, the interface formation process in block 220 is omitted, and the interface layer 304 is not formed before the high-κ dielectric material layer is deposited on the substrate 302. In this case, the interface layer 304 is formed by the thermal oxidation process in block 250 or block 290 described below, which thermally oxidizes the substrate 302 via the high-κ dielectric material layer deposited on the substrate 302. Having a thickness between about 0.3 nm and about 1 nm, for example, about 0.5 nm, the interface layer 304 formed by the thermal oxidation process in block 250 or block 290 can be thick enough to ensure reliable device characteristics (e.g., such as interface state density, accumulated capacitance, dispersion, and leakage current) and reduce atomic diffusion from the high-κ dielectric material layer to the substrate 302.

[0033] In block 230, a deposition process is performed to deposit material on the exposed surface of the semiconductor structure 300 (i.e., in the case of forming interface layer 304 in block 220, such as...). Figure 3BAs shown, a high-κ gate dielectric layer 306 is deposited on substrate 302 without forming interface layer 304 in box 220. The high-κ gate dielectric layer 306 can be formed from a high-κ dielectric material (such as hafnium dioxide (HfO2), zirconium dioxide (ZrO2), ytterbium oxide (Y2O3), aluminum oxide (Al2O3)) or a ternary high-κ dielectric film (such as HfZrO, HfLaOx, HfTiO) having a third element incorporated into an existing metal oxide high-κ dielectric host material. This deposition process can include atomic layer deposition (ALD) processes, in which metal-containing precursors and oxygen-containing precursors are alternately delivered to the exposed surfaces of the semiconductor structure 300. In some embodiments, the metal-containing precursor is purged before the oxygen-containing precursor is delivered. The metal can be a transition metal such as hafnium (Hf), zirconium (Zr), or titanium (Ti), a rare earth metal such as lanthanum (La), ytterbium (Yb), or yttrium (Y), an alkaline earth metal such as strontium (Sr), or another metal such as aluminum (Al). For the oxidant, any oxygen-containing precursor that can react with the metal can be used. For example, the oxygen-containing precursor can be or contain water, diatomic oxygen, ozone, a hydroxyl-containing precursor or alcohol, a nitrogen- and oxygen-containing precursor, plasma-enhanced oxygen containing locally or remotely enhanced oxygen, or any other oxygen-containing material that can combine with the metal to produce a layer of metal oxides on substrate 302. In one example, the metal-containing precursor is hafnium tetrachloride (HfCl4) and the oxidant is water (H2O) to form a hafnium dioxide (HfO2) layer. The ALD process can be performed at a temperature between 200°C and about 400°C (e.g., about 270°C). As deposited by the ALD process, the high-κ gate dielectric layer 306 can be amorphous and has a temperature between approximately 400°C and 270°C. With the agreement The thickness between. It can be in, for example... Figure 1 The deposition process is performed in processing chambers such as processing chambers 120, 122, 124, 126, 128, or 130 shown.

[0034] In block 240, an optional post-deposition annealing process is performed to harden and densify the deposited high-κ gate dielectric layer 306. Crystallization of the deposited amorphous high-κ gate dielectric layer 306 may occur. This post-deposition annealing process may include a thermal annealing process performed in an inert environment (such as nitrogen (N2) and argon (Ar) environment) within a rapid thermal processing (RTP) chamber, such as a RADOX chamber available from Applied Materials, Inc., Santa Clara, California, USA. TM A chamber. This RTP chamber can be... Figure 1 Any of the processing chambers 120, 122, 124, 126, 128, and 130 shown. This post-deposition annealing process can be used to thermally harden and densify the interface layer 304 and the high-κ dielectric layer 306.

[0035] The post-deposition annealing process can be performed at a temperature between approximately 500°C and approximately 800°C and a pressure between approximately 0.01 Torr and 100 Torr for a time between approximately 1 second and approximately 60 seconds.

[0036] In block 250, instead of the post-deposition annealing process in block 240, an optional re-oxidation process is performed to thermally oxidize substrate 302. This re-oxidation process may include a thermal annealing process performed in an oxygen (O2), nitrous oxide (N2O), and H2 environment within a rapid thermal processing (RTP) chamber, such as a RADOX chamber available from Applied Materials, Inc., Santa Clara, California, USA. TM A chamber. This RTP chamber can be... Figure 1 Any of the processing chambers 120, 122, 124, 126, 128, and 130 shown. The re-oxidation process in block 250 can be performed via thermal oxidation of the underlying layer via the high-κ gate dielectric layer 306, thus thickening the interface layer 304 to between approximately With the agreement The thickness between, while without forming an interface layer 304 in block 220, an interface layer 304 is formed in the substrate 302 near the junction with the high-κ dielectric layer 306.

[0037] The re-oxidation process can be performed at a temperature between approximately 400°C and approximately 900°C and a pressure between approximately 0.01 Torr and 100 Torr for a time between approximately 1 second and approximately 30 seconds.

[0038] In block 260, a plasma nitridation process is performed to insert nitrogen atoms into voids and defects in the high-κ gate dielectric layer 306. This plasma nitridation process can be a DPN process performed in a decoupled plasma nitridation (DPN) chamber, such as those available from Applied Materials, Inc., located in Santa Clara, California, USA. DPN chamber. This DPN chamber can be... Figure 1 Any of the processing chambers 120, 122, 124, 126, 128, and 130 shown. This plasma nitriding process exposes the high-κ gate dielectric layer 306 to nitrogen plasma, which allows nitrogen radicals, or nitrogen atoms, to be incorporated into the high-κ gate dielectric layer 306 throughout its entire thickness. During this plasma nitriding process, nitrogen atoms can form metastable bonds with oxygen (O). Gases that can be used in this plasma process include nitrogen-containing gases, such as nitrogen (N2), ammonia (NH3), or mixtures of these gases. In one example, this nitrogen-containing gas is ammonia (NH3) mixed with about 3% to about 8% nitrogen (N2). As a result of nitrogen incorporation into the voids and defects of the deposited high-κ gate dielectric layer 306, the plasma nitriding process can maintain the thickness of the high-κ gate dielectric layer 306.

[0039] The nitriding process can be performed at a temperature between approximately 0°C and approximately 500°C for a time between approximately 10 seconds and approximately 300 seconds.

[0040] In block 270, an optional thermal nitriding process is performed to further insert nitrogen atoms into voids and defects in the plasma-nitrided high-κ gate dielectric layer 306. This thermal nitriding process may include a thermal annealing process performed in an ammonia (NH3) environment within a rapid thermal processing (RTP) chamber, such as a RADOX chamber available from Applied Materials, Inc., Santa Clara, California, USA. TM A chamber. This RTP chamber can be... Figure 1 Any of the processing chambers 120, 122, 124, 126, 128 and 130 shown.

[0041] The thermal nitriding process can be performed at a temperature between approximately 700°C and approximately 900°C and a pressure between approximately 10 Torr and 740 Torr for a time between approximately 10 seconds and approximately 300 seconds.

[0042] In block 280, a post-nitridation anneal process is performed to passivate the remaining chemical bonds in the plasma-nitrided high-κ gate dielectric layer 306. This post-nitridation anneal process may include a spike thermal anneal process performed in a nitrogen (N2) and argon (Ar) environment within a rapid thermal processing (RTP) chamber, such as a RADOX chamber available from Applied Materials, Inc., Santa Clara, California, USA. TM A chamber. This RTP chamber can be... Figure 1 Any of the processing chambers 120, 122, 124, 126, 128, and 130 shown. This post-nitriding annealing process can passivate the metastable nitrogen bonds formed in the plasma nitriding process in block 240, and may cause crystallization of the amorphous high-κ gate dielectric layer 306.

[0043] Peak heat annealing processes can be performed at temperatures between approximately 700°C and approximately 850°C and pressures between approximately 10 Torr and 740 Torr for periods between approximately 1 second and approximately 30 seconds.

[0044] In block 290, instead of the post-nitriding annealing process in block 280, a post-nitriding annealing and re-oxidation process is performed to simultaneously passivate the remaining chemical bonds in the high-κ gate dielectric layer 306 as in block 280 and thermally oxidize the substrate 302 as in block 250. The post-nitriding annealing and re-oxidation process in block 290 is the same as the re-oxidation process in block 250. Therefore, details of the post-nitriding annealing and re-oxidation process in block 290 are omitted here.

[0045] Figure 4 This is a process flow diagram of a method 400 for forming a metal gate structure 500 above a gate dielectric layer 306 in a semiconductor structure 300 according to one or more embodiments of the present disclosure. Figure 5A , Figure 5B and Figure 5C This is a cross-sectional view of a portion of the metal gate structure 500 in the semiconductor structure 300 corresponding to various states of method 400. It should be understood that... Figure 5A , Figure 5B and Figure 5C Only a partial schematic diagram of the semiconductor structure 300 is shown, but the semiconductor structure 300 may include any number of transistor portions and additional materials having the various aspects shown in the figure. It should also be noted that, although... Figure 4The method steps shown are described in sequence, but other process sequences that include one or more method steps that have been omitted and / or added, and / or rearranged in another desired order also fall within the scope of the various embodiments of this disclosure provided herein.

[0046] Method 400 begins with a deposition process in block 410 to deposit a high-k dielectric cap layer 502 on the gate dielectric layer 306 of the semiconductor structure 300, such as Figure 5AAs shown. The high-κ dielectric cap layer 502 can be formed from a metal nitride material comprising titanium (Ti) or tantalum (Ta) doped with silicon (Si), aluminum (Al), gallium (Ga), germanium (Ge), indium (In), or hafnium (Hf), such materials include TiSiN, TaSiN, TiAlN, TaAlN, TiGaN, TaGaN, TiGeN, TaGeN, TiInN, TaInN, TiHfN, or TaHfN. The high-κ dielectric cap layer 502 formed from such doped metal nitride material can prevent silicon (Si) migration during subsequent silicon deposition processes in block 430. The deposition process in block 410 can include an atomic layer deposition (ALD) process in which a metal-containing precursor, a nitrogen-containing precursor, and a doped precursor comprising titanium (Ti) or tantalum (Ta) are delivered to the surface of the gate dielectric layer 306. Examples of metallic precursors containing titanium (Ti) or tantalum (Ta) and examples of nitrogen-containing precursors are listed in the description of box 420. Doped precursors include aluminum (Al), gallium (Ga), germanium (Ge), hafnium (Hf), indium (In), or silicon (Si). Examples of aluminum (Al) doped precursors include inorganic compounds of aluminum (Al) and organometallic compounds of aluminum (Al). Inorganic compounds of aluminum (Al) include aluminum chloride (AlCl3) and aluminum bromide (AlBr3). Organometallic compounds of aluminum (Al) include trimethylaluminum (TMA, (CH3)3Al), dimethylaluminum hydride (DMAH, (CH3)2AlH), tris(diethylamino)aluminum (TDEAA, Al(N(C2H5)2)3), trimethylamine alane (TMAA, AlH3-N(CH3)3), triethylamine alane (TEAA, AlH3-N(C2H5)3), and dimethylethylamine. alane, (AlH3-C2H5N(CH3)2), triisobutylaluminum (TiBA, [Al(CH3)2CHCH2]3), triethylaluminum (TEAl, Al(C2H5)3), dimethylaluminum hydride (DMAH, (CH3)2AlH) and diethylaluminum chloride (DEAC, (C2H5)2AlCl).Examples of gallium (Ga) doped precursors include inorganic compounds of gallium (Ga) and organometallic compounds of gallium (Ga). Inorganic compounds of gallium (Ga) include gallium tribromide (GaBr3) and gallium trichloride (GaCl3). Organometallic compounds of gallium (Ga) include trimethylgallium (Ga(CH3)3), triethylgallium (Ga(C2H5)3), triisopropylgallium (Ga(CH(CH3)2)3), tris(dimethylamido)gallium (Ga(N(CH3)2)3), and tri-tert-butylgallium (Ga(C(CH3)3)3). Examples of precursors containing germanium (Ge) dopants include inorganic compounds of germanium (Ge) and organometallic compounds of germanium (Ge). Inorganic compounds of germanium (Ge) include digermane (Ge2H6) and germane (GeH4), while organometallic compounds of germanium (Ge) include tetramethylgermanium ((CH3)4Ge). Examples of precursors containing hafnium (Hf) dopants include inorganic compounds of hafnium (Hf) and organometallic compounds of hafnium (Hf). Inorganic compounds of hafnium (Hf) include hafnium(IV) chloride (HfCl4), while organometallic compounds of hafnium (Hf) include hafnium(IV) tert-butoxide (Hf[OC(CH3)3]4) and tetrakis(diethylamide)hafnium(IV) (tetrakis( diethylamido)hafnium(IV),[(CH2CH3)2N]4Hf), tetrakis(dimethylamido)hafnium(IV),[(CH3)2N]4Hf), and tetrakis(ethylmethylamido)hafnium(IV),TEMAH,[(CH3)(C2H5)N]4Hf).Examples of doped precursors containing indium (In) include inorganic compounds of indium (In) and organometallic compounds of indium (In). Inorganic compounds of indium (In) include indium trichloride (InCl3) and indium(I)iodide (InI), while organometallic compounds of indium (In) include triethylindium (In(CH2CH3)3) and indium(III)acetylacetonate (In(OCCH3CHOCCH3)3). Examples of silicon (Si) doped precursors include inorganic compounds of silicon (Si) and organometallic compounds of silicon (Si). Inorganic compounds of silicon (Si) include silane (SiH4) and disilane (Si2H6), while organometallic compounds of silicon (Si) include trimethylsilane ((CH3)3SiH) and neoopentasilane ((SiH3)4Si).

[0047] The order in which the metal-containing precursor, nitrogen-containing precursor, and doped precursor are delivered can be varied. In some embodiments, the metal-containing precursor, nitrogen-containing precursor, and doped precursor are delivered alternately. In some embodiments, the metal-containing precursor and the doped precursor are delivered simultaneously, and after purification, the nitrogen-containing precursor is delivered. Table 1 below shows several non-limiting changes in the order.

[0048] Table 1

[0049]

[0050]

[0051] The ALD process in block 410 can be performed at a temperature between about 200°C and about 700°C (e.g., between about 300°C and about 600°C). As deposited by the ALD process in block 410, the high-κ dielectric cap layer 502 can be amorphous and has a temperature between about 200°C and about 700°C. With the agreement The thickness between. It can be in, for example... Figure 1 The deposition process is performed in processing chambers such as processing chambers 120, 122, 124, 126, 128, or 130 shown.

[0052] In block 420, an optional metal cap annealing process is performed to harden and densify the deposited high-k dielectric cap layer 502. Crystallization of the deposited high-k dielectric cap layer 502 may occur. This optional metal cap annealing process in block 420 may include a thermal annealing process performed in an inert environment (such as in nitrogen (N2) and argon (Ar) environments) within a rapid thermal processing (RTP) chamber, such as a RADOX chamber available from Applied Materials, Inc., located in Santa Clara, California, USA. TM A chamber. This RTP chamber can be... Figure 1 Any of the processing chambers 120, 122, 124, 126, 128 and 130 shown.

[0053] The optional metal cap annealing process in block 420 can be performed at a temperature between about 700°C and about 850°C and a pressure between about 0.1 Torr and 100 Torr for a time between about 1 second and about 10 seconds.

[0054] In box 430, a deposition process is performed to deposit a sacrificial silicon cap 504 on the high-κ dielectric cap 502, as follows: Figure 5B As shown. The sacrificial silicon cap layer 504 can physically and chemically protect the underlying high-κ gate dielectric layer 306 and high-κ dielectric cap layer 502 during subsequent annealing processes in block 440. The sacrificial silicon cap layer 504 is formed of amorphous silicon, such as hydrogenated amorphous silicon (a-Si:H). Compared to polycrystalline silicon, which contains grain boundaries leading path for diffusion, amorphous silicon can provide less atomic diffusion. The deposition process in block 430 can be an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process, in which the semiconductor structure 300 on which the high-κ dielectric cap layer 502 is formed is exposed to a silicon precursor. Examples of silicon precursors are polysilanes (Si... x H y For example, polysilanes include disilane (Si2H6), trisilane (Si3H8), and tetrasilane (Si4H6). 10 Isotetrasilane, neoopentasilane (Si5H) 12 ), cyclopentasilane (Si5H) 10 hexasilane (C6H) 14 ), cyclohexane (Si6H)12 Or, in general, Si x H y (where x = 2 or greater), and their combinations.

[0055] The sacrificial silicon cap layer 504 can have a value between approximately With the agreement The thickness between. The deposition process in box 430 can be performed in, for example... Figure 1 It is performed in a processing chamber such as 120, 122, 124, 126, 128 or 130 shown.

[0056] In block 440, a post-cap anneal (PCA) process is performed to harden and densify the deposited high-k dielectric cap layer 502. Crystallization of the deposited high-k dielectric cap layer 502 and the deposited sacrificial silicon cap layer 504 may occur. The PCA process in block 440 may include a thermal annealing process performed in an inert environment (such as in nitrogen (N2) and argon (Ar) environments) within a rapid thermal processing (RTP) chamber, such as a RADOX chamber available from Applied Materials, Inc., located in Santa Clara, California, USA. TM A chamber. This RTP chamber can be... Figure 1 Any of the processing chambers 120, 122, 124, 126, 128 and 130 shown.

[0057] The PCA process in block 440 can be performed at a temperature between about 900°C and about 1000°C (e.g., about 900°C) and a pressure between about 0.1 Torr and 100 Torr for a time between about 1 second and about 10 seconds.

[0058] In box 450, a removal process is performed to strip the sacrificial silicon cap layer 504. This removal process may include a dry plasma etching process.

[0059] Following the removal process in block 460, a deposition process is performed in block 460 to deposit a metal layer 506 on the hardened and densified high-k dielectric cap layer 502, as follows. Figure 5C As shown in the diagram. Metal layer 506 can be formed of tungsten (W) or cobalt (Co). Metal layer 506 can be p-type doped or n-type doped. The deposition process in block 450 can include chemical vapor deposition (CVD) using a cobalt-containing precursor or a tungsten-containing precursor such as WF6.

[0060] The high-κ dielectric cap layer 502 formed from doped metal nitride materials described herein can be effectively used as a fluorine barrier, for example, in a deposition process using fluorine-containing precursors such as WF6 in block 460. The high-κ dielectric cap layer 502 formed from doped metal nitride materials described herein also prevents aluminum (Al) migration, thus eliminating the need for an aluminum barrier, whereas conventional high-κ dielectric cap layers formed from metal nitride materials such as titanium nitride (TiN) allow aluminum migration. The high-κ dielectric cap layer 502 formed from doped metal nitride materials described herein can also be used as a work function layer to increase the effective work function at the interface between the high-κ dielectric cap layer 502 and the metal layer 506.

[0061] In some implementations, the deposition processes in block 410 for depositing the high-k dielectric cap layer 502 and in block 430 for depositing the sacrificial silicon cap layer 504 are performed without disrupting the low-pressure or vacuum environment of the processing system, such as processing system 100. Processes that do not disrupt the low-pressure or vacuum environment can reduce contamination caused by moisture introduced from the atmosphere.

[0062] In some implementations, the deposition process in block 410 for depositing the high-k dielectric cap layer 502, the deposition process in block 430 for depositing the sacrificial silicon cap layer 504, and the post-cap annealing (PCA) process in block 440 are performed without disrupting the low-pressure or vacuum environment of the processing system, such as processing system 100. Processes that do not disrupt the low-pressure or vacuum environment can reduce contamination caused by moisture introduced from the atmosphere and further prevent the thickening of the high-k gate dielectric layer 306.

[0063] In several embodiments described herein, systems and methods are provided for forming high-quality, thin, high-κ dielectric material layers and metal gate structures. The properties of such high-κ dielectric material layers can be well controlled. For example, the nitriding processes in blocks 260 and 270 can be controlled to provide nitrogen bonding in the high-κ gate dielectric layer 306 between about 3 atomic% and about 20 atomic%, thereby achieving a higher κ value compared to cases with higher nitrogen bonding and better structural stability compared to cases with lower nitrogen bonding. The annealing processes in blocks 240, 270, 280, and 290 can also be controlled to provide a high κ value greater than about 3 atomic% in the high-κ gate dielectric layer 306. The size of the grains reduces leakage current flowing through the high-κ gate dielectric layer 306.

[0064] The metal gate structure described herein exhibits reduced equivalent oxide thickness (EOT), reduced leakage current through it, and increased effective work function. The metal gate structure also exhibits aluminum (A) barrier properties, enabling the direct formation of aluminum layers on the metal gate structure. This metal gate structure can be advantageously used in any barrier application and / or any metal gate application in flash memory, dynamic random access memory (DRAM), and MOSFETs.

[0065] Although the foregoing relates to various embodiments of this disclosure, other and further embodiments of this disclosure may be devised without departing from the basic scope of this disclosure, and the scope of this disclosure is determined by the appended claims.

Claims

1. A method of forming a semiconductor structure, the method comprising the steps of: forming the semiconductor structure on a substrate, including: pre-cleaning a surface of the substrate; forming an interface layer on the pre-cleaned surface of the substrate; depositing a high-k gate dielectric layer on the interface layer; performing a plasma nitridation process to intercalate nitrogen atoms in the deposited high-k gate dielectric layer; and performing a post-nitridation anneal process to passivate chemical bonds in the plasma-nitrided high-k gate dielectric layer, wherein crystallization of the plasma-nitrided high-k gate dielectric layer occurs; and forming a high-k dielectric cap layer on the semiconductor structure formed on the substrate, including: depositing the high-k dielectric cap layer on the semiconductor structure; depositing a sacrificial silicon cap layer on the high-k dielectric cap layer; performing a post-cap anneal process to harden and densify the deposited high-k dielectric cap layer; and removing the sacrificial silicon cap layer.

2. The method of claim 1, wherein the step of forming the high-k dielectric cap layer is performed in a processing system without breaking vacuum.

3. The method of claim 1, wherein the interface layer comprises silicon oxide (SiO2), and The step of forming the interface layer includes: the substrate is thermally oxidized with nitrous oxide (N2O) gas.

4. The method of claim 1, wherein the high-k gate dielectric layer comprises hafnium oxide (HfO2).

5. The method of claim 1, wherein the plasma nitridation process comprises: exposing the deposited high-k gate dielectric layer to a nitrogen plasma using a mixture of nitrogen (N2) and ammonia (NH3).

6. The method of claim 1, wherein the post-nitridation anneal process comprises: spike annealing the deposited high-k gate dielectric layer at a temperature between 700 °C and 850 °C in a nitrogen (N2) and argon (Ar) ambient.

7. The method of claim 1, further comprising the step of: performing a post-deposition anneal process to harden and densify the deposited high-k gate dielectric layer prior to the plasma nitridation process, wherein the post-deposition anneal process comprises annealing the deposited high-k gate dielectric layer at a temperature between 500 °C and 800 °C in a nitrogen (N2) and argon (Ar) ambient.

8. The method of claim 1, further comprising: performing a thermal nitridation process to further intercalate nitrogen atoms in the plasma-nitrided high-k gate dielectric layer prior to the post-nitridation anneal process, wherein the thermal nitridation process comprises annealing the plasma-nitrided high-k gate dielectric layer at a temperature between 700 °C and 900 °C in an ammonia (NH3) ambient.

9. The method of claim 1, wherein the high-k dielectric cap layer comprises TiSiN.

10. The method of claim 1, further comprising: performing a metal cap anneal process to harden and densify the deposited high-k dielectric cap layer at a temperature between 700 °C and 850 °C in a nitrogen (N2) ambient prior to the step of depositing the sacrificial silicon cap layer.

11. The method of claim 1, wherein the post cap anneal process comprises: annealing the high-k dielectric cap layer at a temperature between 900 °C and 1000 °C in a nitrogen (N2) ambient.

12. A method of forming a semiconductor structure, the method comprising the steps of: forming the semiconductor structure on a substrate, including: pre-cleaning a surface of the substrate; depositing a high-k gate dielectric layer on the substrate; and performing a plasma nitridation process to insert nitrogen atoms in the deposited high-k gate dielectric layer; prior to the plasma nitridation process, performing a re-oxidation process to thermally oxidize the substrate; and after the plasma nitridation process, performing a post-nitridation anneal process to passivate chemical bonds in the plasma-nitrided high-k gate dielectric layer, wherein crystallization of the plasma-nitrided high-k gate dielectric layer occurs; and forming a high-k dielectric cap layer on the semiconductor structure formed on the substrate, including: depositing the high-k dielectric cap layer on the semiconductor structure; depositing a sacrificial silicon cap layer on the high-k dielectric cap layer; performing a post-cap anneal process to harden and densify the deposited high-k dielectric cap layer; and removing the sacrificial silicon cap layer.

13. The method of claim 12, wherein the step of forming the high-k dielectric cap layer is performed in a processing system without breaking vacuum.

14. The method of claim 12, further comprising the step of: forming an interface layer on the pre-cleaned surface of the substrate, including: thermally oxidizing the substrate with nitrous oxide (N20) gas, wherein the interface layer comprises silicon oxide (Si02).

15. The method of claim 12, wherein the high-k gate dielectric layer comprises hafnium oxide (Hf02).

16. The method of claim 12, wherein the plasma nitridation process comprises: exposing the deposited high-k gate dielectric layer to a nitrogen plasma using a mixture of nitrogen gas (N2) and ammonia gas (NH3).

17. The method of claim 12, wherein The re-oxidation process comprises: annealing the high-k gate dielectric layer at a temperature between 400 °C and 900 °C in an environment of oxygen (02), nitrous oxide (N20), and H2; and the post-nitridation anneal process comprises spike annealing the plasma-nitrided high-k gate dielectric layer at a temperature between 700 °C and 850 °C in an environment of nitrogen (N2) and argon (Ar).

18. The method of claim 12, further comprising the step of: after the plasma nitridation process, performing a re-oxidation process to passivate remaining chemical bonds in the plasma-nitrided high-k gate dielectric layer and to thermally oxidize the substrate, wherein the re-oxidation process comprises annealing the high-k gate dielectric layer at a temperature between 400 °C and 900 °C in an environment of oxygen (02), nitrous oxide (N20), and H2.

19. The method of claim 12, wherein the high-k dielectric cap layer comprises TiSiN.

20. The method of claim 12, further comprising: prior to the step of depositing the sacrificial silicon cap layer, performing a metal cap anneal process to harden and densify the deposited high-k dielectric cap layer at a temperature between 700 °C and 850 °C in a nitrogen (N2) environment.

21. The method of claim 12, wherein the post cap anneal process comprises: annealing the high-k dielectric cap layer at a temperature between 900 °C and 1000 °C and in a nitrogen (N2) ambient.

22. A processing system comprising: a first processing chamber; a second processing chamber; a third processing chamber; a fourth processing chamber; a fifth processing chamber; a sixth processing chamber; a seventh processing chamber; an eighth processing chamber; a ninth processing chamber; and a system controller configured to: in the first processing chamber, pre-clean a surface of a substrate; in the second processing chamber, form an interface layer on the pre-cleaned surface of the substrate; in the third processing chamber, deposit a high-k dielectric layer on the interface layer; in the fourth processing chamber, perform a plasma nitridation process to insert nitrogen atoms in the deposited high-k dielectric layer; and after the plasma nitridation process, in the fifth processing chamber, perform a post-nitridation anneal process to passivate chemical bonds in the plasma-nitrided high-k dielectric layer, wherein crystallization of the plasma-nitrided high-k gate dielectric layer occurs; in the sixth processing chamber, deposit a high-k dielectric cap layer on the plasma-nitrided high-k dielectric layer; in the seventh processing chamber, deposit a sacrificial silicon cap layer on the high-k dielectric cap layer; in the eighth processing chamber, perform a post-cap anneal process to harden and densify the deposited high-k dielectric cap layer; and in the ninth processing chamber, remove the sacrificial silicon cap layer, wherein the substrate is transferred between the first processing chamber, the second processing chamber, the third processing chamber, and the fourth processing chamber without breaking a vacuum environment in the processing system.

23. The processing system of claim 22, wherein: the substrate is transferred between the fifth processing chamber, the sixth processing chamber, the seventh processing chamber, the eighth processing chamber, and the ninth processing chamber without breaking a vacuum environment in the processing system.

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