A chip or chip module detection method and device

Abstract

The present invention provides a method and device for detecting a chip or chip module. The method includes: determining physical information of the chip or chip module, and / or determining design information of the chip or chip module; comparing the physical information with the design information, and / or verifying the design information; and determining the autonomy and / or controllability of the chip or chip module based on the comparison result and / or verification result.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a method and device for detecting a chip or a chip module. Background Art

[0002] Chip design is the core and source of the chip industry chain, and its degree of autonomy and controllability plays a crucial role in the overall chip industry. The degree of autonomy and controllability in chip design is typically assessed based on a grading system, such as fully independent design, partially independent design, or fully outsourced. Evidence collection typically occurs through investigations and reviews.

[0003] The implementation plans for relevant autonomous and controllable ratings are mostly conducted through investigation and review. The accuracy of this assessment method depends on the authenticity, verifiability, and completeness of the relevant materials, as well as the experience and level of the experts. To a certain extent, its objectivity and comprehensiveness cannot be guaranteed. Summary of the Invention

[0004] In view of this, embodiments of the present invention are intended to provide a method and apparatus for detecting a chip or a chip module.

[0005] To achieve the above-mentioned purpose, the technical solution of the embodiment of the present invention is implemented as follows:

[0006] An embodiment of the present invention provides a method for detecting a chip or a chip module, the method comprising:

[0007] Determining physical information of the chip or chip module, and / or determining design information of the chip or chip module;

[0008] Comparing the physical object information with the design information, and / or verifying the design information;

[0009] Based on the comparison result and / or verification result, the autonomy and / or controllability of the chip or chip module is determined.

[0010] An embodiment of the present invention further provides a device for detecting a chip or a chip module, the device comprising:

[0011] an information determination module, configured to determine physical information of the chip or chip module, and / or design information of the chip or chip module;

[0012] an information processing module, configured to compare the physical object information with the design information, and / or verify the design information;

[0013] The determination module is used to determine the degree of autonomy and / or controllability of the chip or chip module based on the comparison result and / or verification result.

[0014] An embodiment of the present invention further provides a chip or chip module detection device, the device comprising: a processor and a memory for storing a computer program that can be run on the processor,

[0015] Wherein, the processor is used to execute the steps of the above method when running the computer program.

[0016] The chip or chip module detection method and device provided by the embodiment of the present invention determine the physical information of the chip or chip module and / or determine the design information of the chip or chip module; compare the physical information with the design information and / or verify the design information; and determine the autonomy and / or controllability of the chip or chip module based on the comparison result and / or verification result. It can be seen that the embodiment of the present invention provides a simple and objective detection basis for the evaluation of the autonomy and / or controllability of the chip or chip module, improves the objectivity, practicality and comprehensiveness of the evaluation of the autonomy and / or controllability of the chip or chip module, and can serve as a basis for supporting the authenticity of the evidence materials collected for the evaluation of the autonomy and / or controllability of the chip or chip module, and can serve as a strong support for the evaluation of the autonomy and / or controllability of the chip or chip module. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 Schematic diagram of the process of detecting a chip or chip module according to an embodiment of the present invention;

[0018] Figure 2 This is a schematic structural diagram of a detection device for a chip or chip module according to an embodiment of the present invention;

[0019] Figure 3 This is a flow chart of the detection method described in Example 1 of the present invention (for clarity, only the numbers of each operation are given in the figure);

[0020] Figure 4 This is a flow chart of the detection method described in Example 2 of the present invention (for clarity, only the numbers of each operation are given in the figure. In addition, the and / or relationships in 2.5 cannot be displayed one by one in the figure, and only one case is shown - verifying the second design information in Article 1.7 with the third design information in Article 1.8). DETAILED DESCRIPTION

[0021] The present invention will be described below with reference to the accompanying drawings and embodiments.

[0022] The embodiment of the present invention provides a method for detecting a chip or a chip module, such as Figure 1 As shown, the method includes:

[0023] Step 101: Determine physical information of a chip or chip module, and / or determine design information of the chip or chip module;

[0024] Step 102: Comparing the physical object information with the design information, and / or verifying the design information;

[0025] Step 103: Based on the comparison result and / or verification result, determine the degree of autonomy and / or controllability of the chip or chip module.

[0026] The embodiments of the present invention provide a simple and objective detection basis for the evaluation of the autonomy and / or controllability of a chip or chip module, improve the objectivity, practicality and comprehensiveness of the evaluation of the autonomy and / or controllability of a chip or chip module, and can serve as supporting evidence for the authenticity of evidence collected for the evaluation of the autonomy and / or controllability of a chip or chip module, and can serve as a strong support for the evaluation of the autonomy and / or controllability of a chip or chip module.

[0027] In the embodiment of the present invention, the chip includes but is not limited to one or more of the following:

[0028] A chip that encapsulates one or more bare dies (bare die is also called bare crystal or die);

[0029] Unpackaged die.

[0030] In the embodiment of the present invention, the chip module includes but is not limited to one or more of the following:

[0031] A die in a chip that packages one or more dies;

[0032] Functional module in a die (also called functional unit, unit, etc.).

[0033] (It should be noted that from the perspective of classification, the chips and chip modules here are a general term, including but not limited to integrated circuits (ICs), microsystems (MEMS), microelectromechanical systems (MEMS), semiconductor devices, discrete devices, sensors, actuators, and other categories.)

[0034] In the embodiment of the present invention, the physical information includes but is not limited to one or more of the following (it should be noted that the type of physical information can be selected based on the type of comparison required to determine the degree of autonomy and / or controllability of the chip or chip module, so that the selection of physical information is more targeted):

[0035] The physical connection relationship between the chip or chip module and the packaging substrate, and / or the physical connection relationship between the chip or chip module and other chips or chip modules, including but not limited to one or more of the following forms of expression: physical connection relationship, physical diagram describing the connection relationship, table describing the physical connection relationship, physical pin names describing the physical connection relationship, and physical connection relationship expressed by name;

[0036] Physical information of the package substrate, including but not limited to one or more of the following: the physical package substrate, the physical circuit or circuit diagram of the package substrate, the physical layout or layout diagram of the package substrate, the physical wiring or wiring diagram of the package substrate, and the physical circuit or circuit diagram of the package substrate;

[0037] Physical information of the chip or chip module, including but not limited to one or more of the following: the physical chip or chip module, the physical layout of the chip or chip module, the physical layout of the chip or chip module, the physical layout and wiring of the chip or chip module or the layout and wiring diagram, the physical circuit of the chip or chip module or the circuit diagram;

[0038] Among them, the physical information includes but is not limited to one or more of the following physical information: all layers, some layers, one layer, and the method of selecting the layer number includes but is not limited to one or more of the following: random selection, selection according to rules, and setting; for one of the layers, the physical information includes but is not limited to one or more of the following physical information: the entire area, multiple local areas, one local area, and the method of selecting the area includes but is not limited to one or more of the following: random selection, selection according to rules, and setting.

[0039] In the embodiment of the present invention, the method for obtaining the physical object information includes, but is not limited to, one or more of the following:

[0040] Directly obtain one or more chips or chip modules to be tested and obtain physical information;

[0041] Randomly or according to rules, select one or more chips or chip modules to be tested and obtain physical information;

[0042] Directly obtain physical information through one or more of the following methods, including but not limited to: computerized tomography (CT), X-rays, radiography, ultrasound, and non-destructive testing (also known as non-destructive observation); (e.g., for a packaged chip, directly obtain information inside the chip through CT)

[0043] Open the packaged chip (referred to as open the cover) and obtain the physical information;

[0044] In the case where the physical connection relationship between the chip or chip module and the packaging substrate, and / or the physical connection relationship between the chip or chip module and other chips or chip modules is blocked, the physical connection relationship is obtained by one or more of the following methods, including but not limited to: CT, X-ray, X-ray, radiation, ultrasound, non-destructive testing, delamination (also known as de-layering, layer removal, layer removal), flat grinding, grinding, lapping, polishing, corrosion, etching, sectioning (also known as chip dissection), dissection, and staining; the case where the physical connection relationship is blocked includes but is not limited to the physical connection relationship being blocked in a flip-chip chip; (for example, for a flip-chip chip, flat grinding to the flip-chip interface is performed, and the physical connection relationship is obtained at this interface)

[0045] Separating the chip or chip module from the packaging substrate, and / or separating the chip or chip module from other chips or chip modules, wherein the separation method includes but is not limited to one or more of the following: disconnecting or removing or removing connecting wires, corroding, etching, heating, delaminating, flat grinding, grinding, lapping, polishing, slicing, dissecting, and removing the chip;

[0046] Obtaining one or more layers of physical information by one or more of the following methods, including but not limited to: directly obtaining, obtaining through a microscope (including but not limited to one or more of the following: optical microscope, electron microscope) and / or microscopic imaging instrument and / or CT and / or X-ray and / or X-ray and / or radiation and / or ultrasound and / or non-destructive testing, delamination, flat grinding, grinding, lapping, polishing, corroding, etching, sectioning, dissecting, staining, disconnecting or removing or removing connecting lines;

[0047] Obtain and record the physical image, video or video corresponding to the physical object information through a microscope and / or microscopic imaging instrument and / or CT and / or X-ray and / or X-ray and / or radiation and / or ultrasound and / or non-destructive testing, in combination with photography and / or image acquisition and / or video recording, or directly through photography and / or image acquisition and / or video recording; the physical image, video or video is a single file, or multiple files, or a single file composed of multiple files;

[0048] Obtain physical object information and corresponding physical object images and videos through microscopes and / or microscopic imaging instruments and / or CT and / or X-rays and / or X-rays and / or radiation and / or ultrasound and / or non-destructive testing, combined with naked eye observation, or directly through naked eye observation.

[0049] In the embodiment of the present invention, obtaining or selecting multiple chips or chip modules to be tested and acquiring physical information includes, but is not limited to, one or more of the following:

[0050] To obtain multiple samples, perform statistical analysis on physical information, or / and comparison of physical information with design information, or / and the degree of autonomy and / or controllability of the chip or chip module, obtain or select multiple chips or chip modules of the same model, and obtain the same physical information from each chip or chip module;

[0051] In cases where destructive operations are required to obtain physical information or / and only partial physical information can be obtained from a chip or chip module, obtain or select multiple chips or chip modules of the same model and obtain different physical information from each chip or chip module, or obtain the same and different physical information simultaneously;

[0052] In order to determine the autonomy and / or controllability of a chip composed of multiple chip modules, the physical information of each of the multiple chip modules in the chip is obtained respectively, and the autonomy and / or controllability is determined, and the autonomy and / or controllability of the chip is determined based on the results.

[0053] In the embodiment of the present invention, the design information includes but is not limited to one or more of the following (it should be noted that the type of design information can be selected based on the type of comparison and / or verification required to determine the degree of autonomy and / or controllability of the chip or chip module, so that the selection of design information is more targeted):

[0054] The designed connection relationship between a chip or chip module and a packaging substrate, and / or the designed connection relationship between a chip or chip module and other chips or chip modules, the designed connection relationship including but not limited to one or more of the following forms of expression: a design drawing describing the connection relationship, a table describing the designed connection relationship, a pin design name describing the designed connection relationship, and the designed connection relationship expressed by the name; the design information including but not limited to one or more of the following design information: all layers, some layers, one layer, the layer number selection method including but not limited to one or more of the following: random selection, selection according to rules, and setting; for one layer, the design information including but not limited to one or more of the following design information: the entire area, multiple local areas, one local area, the area selection method including but not limited to one or more of the following: random selection, selection according to rules, and setting; the format of the designed connection relationship including but not limited to one or more formats;

[0055] Design information of a packaging substrate, the design information including but not limited to one or more of the following: a packaging substrate design circuit or circuit diagram, a packaging substrate design layout or layout diagram, a packaging substrate design wiring or wiring diagram, a packaging substrate design circuit or circuit diagram; the design information including but not limited to one or more of the following design information: all layers, some layers, one layer, and the layer number selection method including but not limited to one or more of the following: random selection, selection according to a rule, and setting; for one layer, the design information including but not limited to one or more of the following design information: the entire area, multiple local areas, one local area, and the area selection method including but not limited to one or more of the following: random selection, selection according to a rule, and setting; the format of the packaging substrate design information including but not limited to one or more formats;

[0056] The first design information of the chip or chip module, the first design information includes but is not limited to one or more of the following: chip or chip module design layout, chip or chip module design layout, chip or chip module design layout wiring or layout wiring diagram; the first design information includes but is not limited to one or more of the following design information: all layers, part of the layers, one layer, the layer number selection method includes but is not limited to one or more of the following: random selection, selection according to rules, setting; for one of the layers, the first design information includes but is not limited to one or more of the following design information: the entire area, multiple local areas, one local area, the area selection method includes but is not limited to one or more of the following: random selection, selection according to rules, setting; the first design information used for comparison is all the design information or part of the design information in the first design information; the first design information used for verification is the All or part of the design information in the first design information; the first design information used for comparison and the first design information used for verification are the same or different design information (for example, the first design information is determined to be a combination of all-layer design information and part-layer or one-layer design information, and the part-layer or one-layer design information is part of all-layer design information; when the physical information of the chip or chip module is the physical information of part-layer or one-layer, the first design information used for comparison is the design information of the part-layer or one-layer corresponding to the physical information; when the second design information is the second design information of the entire chip, the first design information used for verification is the design information of all layers, and is verified with the second design information); the format of the first design information includes but is not limited to one or more formats; the format of the first design information used for comparison and the format of the first design information used for verification are the same or different formats;

[0057] Second design information of the chip or chip module, the second design information includes but is not limited to a schematic diagram and / or a netlist of the chip or chip module, the schematic diagram and / or netlist includes but is not limited to one or more of the following: a schematic diagram, a netlist corresponding to the schematic diagram, a transistor-level netlist (it should be noted that a transistor-level netlist refers to a description of the transistor level and has various forms, such as a CDL netlist, an SCS netlist, a SPICE netlist, etc.), a gate-level netlist for the final design of the digital chip or digital chip module, and a gate-level netlist corresponding to the first design information of the digital chip or digital chip module; the second design information includes but is not limited to all or part of the design information; the second design information used for verification with the first design information is all or part of the design information in the second design information; the second design information used for verification with the first design information is all or part of the design information in the second design information; The second design information for verification of the third design information is all or part of the design information in the second design information; the second design information used for verification with the fourth design information is all or part of the design information in the second design information; any two of the second design information used for verification with the first design information, the second design information used for verification with the third design information, and the second design information used for verification with the fourth design information may be the same or different design information; the format of the second design information includes but is not limited to one or more formats; any two of the format of the second design information used for verification with the first design information, the format of the second design information used for verification with the third design information, and the format of the second design information used for verification with the fourth design information may be the same or different formats;

[0058] Third design information of a chip or chip module, the third design information including but not limited to a gate-level netlist synthesized from register transfer level RTL code of the digital chip or digital chip module; the third design information including but not limited to all or part of the design information; the third design information used for verification with the second design information is all or part of the design information in the third design information; the third design information used for verification with the fourth design information is all or part of the design information in the third design information; the third design information used for verification with the second design information and the third design information used for verification with the fourth design information are the same or different design information; the format of the third design information includes but is not limited to one or more formats; the format of the third design information used for verification with the second design information and the format of the third design information used for verification with the fourth design information are the same or different formats;

[0059] The fourth design information of the chip or chip module includes but is not limited to the RTL code of the digital chip or digital chip module; the fourth design information includes but is not limited to all or part of the design information; the fourth design information used for verification with the second design information is all or part of the design information in the fourth design information; the fourth design information used for verification with the third design information is all or part of the design information in the fourth design information; the fourth design information used for verification with the second design information and the fourth design information used for verification with the third design information are the same or different design information; the format of the fourth design information includes but is not limited to one or more formats; the format of the fourth design information used for verification with the second design information and the format of the fourth design information used for verification with the third design information are the same or different formats.

[0060] In the embodiment of the present invention, the comparing of the physical object information with the design information includes, but is not limited to, one or more of the following:

[0061] Comparing the physical connection relationship between the chip or chip module and the packaging substrate, and / or the physical connection relationship between the chip or chip module and other chips or chip modules, with the corresponding designed connection relationship to check whether the two are consistent;

[0062] Compare the physical information of the package substrate with the design information of the corresponding package substrate to check whether the two are consistent;

[0063] Comparing the physical information of the chip or chip module with the first design information of the corresponding chip or chip module to check whether the two are consistent;

[0064] The comparison includes but is not limited to one or more of the following comparisons: all layers, part of the layers, one layer, and the layer number selection method includes but is not limited to one or more of the following: random selection, selection according to rules, and setting; for one of the layers, the comparison includes but is not limited to one or more of the following comparisons: the entire area, multiple local areas, one local area, and the area selection method includes but is not limited to one or more of the following: random selection, selection according to rules, and setting.

[0065] In one embodiment of the present invention, before comparing the physical object information with the design information, the method further includes:

[0066] Confirm the accuracy of the acquired design information.

[0067] In the embodiment of the present invention, the comparison method includes but is not limited to one or more of the following: automatic comparison by a detection device, manual comparison;

[0068] When the comparison method is automatic comparison by a detection device, it is necessary to determine whether the format of the physical information is a format that can be recognized and / or used by the detection device; when the format of the physical information is not a format that can be recognized and / or used by the detection device, it is necessary to adjust the format of the physical information to a format that can be recognized and / or used by the detection device; the method of adjusting the format of the physical information to a format that can be recognized and / or used by the detection device includes but is not limited to one or more of the following: recording the physical information as a physical image, converting the physical connection relationship into a table that describes the physical connection relationship;

[0069] When the comparison method is automatic comparison by a detection device, it is necessary to determine whether the format of the design information is a format that can be recognized and / or used by the detection device; when the format of the design information is not a format that can be recognized and / or used by the detection device, it is necessary to adjust the format of the design information to a format that can be recognized and / or used by the detection device; the method of adjusting the format of the design information to a format that can be recognized and / or used by the detection device includes but is not limited to one or more of the following: converting the design information into a design image, converting the design connection relationship into a table that describes the design connection relationship; the design image includes but is not limited to an image in which the design information is saved or / and converted or / and recorded as an image format;

[0070] The method of determining whether the format of the physical information and / or the design information is a format that can be recognized and / or used by the detection device includes but is not limited to one or more of the following: automatic determination by the detection device, manual determination;

[0071] The method of adjusting the format of the physical information and / or the design information to a format that can be recognized and / or used by the detection device includes but is not limited to one or more of the following: automatic adjustment by the detection device and manual adjustment.

[0072] In the embodiment of the present invention, when the physical object information is compared with the design information, the correspondence between the physical object information and the design information includes, but is not limited to, one or more of the following:

[0073] Correspondence between the same layers;

[0074] Correspondence between the same areas;

[0075] The correspondence between the same positions;

[0076] The corresponding relationship of the same position ratio includes, but is not limited to, one or more of the following: if the ratio of the position in the physical information and / or physical image and the distance between each point in the entire physical information and / or physical image are the same as the ratio of the position in the design information and / or design image and the distance between each point in the entire design information and / or design image, then the position of the physical information and / or physical image and the position of the design information and / or design image are in a corresponding relationship; if the position in the physical information and / or physical image and the position in the design information and / or design image, after the entire physical information and / or the entire physical image and / or the entire design information and / or the entire design image are scaled proportionally, and the entire physical information and / or the entire physical image and / or the entire design image coincide with the entire design information and / or the entire design image, then the position of the physical information and / or physical image and the position of the design information and / or design image are in a corresponding relationship;

[0077] The corresponding relationship between the same pin names.

[0078] In an embodiment of the present invention, when comparing the physical object information or physical object image with the design information or design image, the method further includes: splitting the physical object information or physical object image and the corresponding design information or design image into one or more sections, maintaining a corresponding relationship between the sections of the physical object information or physical object image and the sections of the design information or design image, performing a comparison on each section separately, and analyzing the comparison results of each section based on the comparison results of each section;

[0079] The situations in which the splitting into one or more sections may be performed include but are not limited to one or more of the following: the physical information or physical image, and the comparison content with the design information or design image, are concentrated in one or more local areas, and the physical information or physical image, and the comparison content with the design information or design image, are split into one or more sections according to the concentrated areas; the physical information or physical image, and the comparison content with the design information or design image, have large differences in graphic sizes in different areas, and the physical information or physical image, and the comparison content with the design information or design image, are split into one or more sections according to different graphic sizes or different size ranges;

[0080] Among them, after splitting into sections, if some sections do not have the required comparison content, the comparison of this section may be omitted or not omitted. When the comparison of this section is omitted, this section will not be included in the analysis of the comparison results of the comprehensive comparison results of each section (for example, the comparison content of the physical information or physical image and the design information or design image is concentrated in one or more local areas, and it is split into one or more sections according to the concentrated areas. If there is no comparison content in the part outside the concentrated local area, then this part of the section can be omitted for comparison, and this part of the section will no longer be considered when analyzing the comparison results).

[0081] In the embodiment of the present invention, the physical object information or physical object image is compared with the design information or design image, and / or the physical object information plate or physical image plate is compared with the design information plate or design image plate. The comparison method includes but is not limited to one or more of the following: overall comparison, detailed comparison, and sampling comparison;

[0082] The comparison contents include but are not limited to one or more of the following: connection relationship, geometric shape, geometric shape features;

[0083] The degree of comparison fineness of the comparison is expressed using granularity, which is related to the comparison mode, method, content and purpose. The granularity includes but is not limited to the degree of accuracy of the comparison content. The minimum limit of the granularity includes but is not limited to one or more of the following: the minimum graphic in the corresponding information and / or image, the minimum size in the corresponding information and / or image, the minimum area in the corresponding information and / or image, the graphic set according to the corresponding information and / or image, the size set according to the corresponding information and / or image, and the area set according to the corresponding information and / or image.

[0084] In an embodiment of the present invention, the method of comparing the physical object information or physical object image with the design information or design image, and / or comparing the physical object information plate or physical object image plate with the design information plate or design image plate, further includes but is not limited to one or more of the following:

[0085] Adjusting the resolution and / or number of pixels of the physical image and / or the design image and / or the physical image plate and / or the design image plate to be compared, and performing a comparison between the physical image and the design image, and / or the physical image plate and the design image plate based on the adjustment result;

[0086] When the comparison method is automatic comparison by a detection device, with respect to the granularity of the planned comparison, the resolution and / or the number of pixels of the physical image and / or the design image and / or the physical image plate and / or the design image plate are adjusted according to the resolution of the physical image and / or the design image and / or the physical image plate and / or the design image plate, and / or the number of pixels of the granularity of the planned comparison contained in the physical image and / or the design image and / or the physical image plate and / or the design image plate, as well as the comparison capability of the detection device. Based on the adjustment result, the physical image and the design image, and / or the physical image plate and the design image plate are compared;

[0087] The comparison capability of the detection device includes but is not limited to: the minimum resolution required by the detection device for completing the comparison at the granularity, for the physical image and / or the design image and / or the physical image plate and / or the design image plate, and / or the minimum number of pixels required to be included in the granularity;

[0088] The adjustment method includes but is not limited to: with respect to the granularity of the planned comparison, on the premise of ensuring the accuracy of the comparison, reducing the resolution and / or number of pixels of the physical image and / or the design image and / or the physical image plate and / or the design image plate, so that the resolution of the physical image and / or the design image and / or the physical image plate and / or the design image plate is reduced, and / or the number of pixels contained in the granularity in the physical image and / or the design image and / or the physical image plate and / or the design image plate is reduced, and is greater than or equal to the comparison capability of the detection device.

[0089] In the embodiment of the present invention, the overall comparison method includes but is not limited to one or more of the following:

[0090] Comparison of the entire object information or image with the design information or image, and / or comparison of the entire object information panel or image panel with the design information panel or image panel;

[0091] The overall alignment includes but is not limited to one or more of the following: overall fine alignment, overall rough alignment;

[0092] During the overall fine comparison, the granularity of the comparison has reached the minimum limit;

[0093] During a rough overall comparison, the granularity of the comparison is greater than the minimum limit, and the comparison content includes but is not limited to one or more of the following: connection relationship, chip area, chip outline, package substrate area, package substrate outline, graphic overview, graphic distribution characteristics, and module structure;

[0094] Applicable situations for the overall fine comparison of the entire physical information or physical image with the design information or design image include but are not limited to one or more of the following: the time required to complete the overall fine comparison is less than or equal to a first preset threshold; the number of pixels of the physical image is less than or equal to a second preset threshold; the number of pixels of the design image is less than or equal to a third preset threshold; the resolution of the physical image is less than or equal to a fourth preset threshold; the resolution of the design image is less than or equal to a fifth preset threshold; the area of ​​the physical information and / or physical image and / or design information and / or design image is less than or equal to a sixth preset threshold; the area of ​​the smallest graphic in the physical information and / or physical image and / or design information and / or design image is greater than or equal to a seventh preset threshold;

[0095] Applicable situations for the overall fine comparison of the entire physical information plate or physical image plate with the design information plate or design image plate include but are not limited to one or more of the following: the time required to complete the overall fine comparison of the plates is less than or equal to the eighth preset threshold; the number of pixels of the physical image plate is less than or equal to the ninth preset threshold; the number of pixels of the design image plate is less than or equal to the tenth preset threshold; the resolution of the physical image plate is less than or equal to the eleventh preset threshold; the resolution of the design image plate is less than or equal to the twelfth preset threshold; the area of ​​the physical information plate and / or physical image plate and / or design information plate and / or design image plate is less than or equal to the thirteenth preset threshold; the area of ​​the smallest graphic in the physical information plate and / or physical image plate and / or design information plate and / or design image plate is greater than or equal to the fourteenth preset threshold;

[0096] Applicable situations for the overall rough comparison of the entire physical information or physical image with the design information or design image include but are not limited to one or more of the following: the time required to complete the overall fine comparison is greater than or equal to the fifteenth preset threshold; the number of pixels of the physical image is greater than or equal to the sixteenth preset threshold; the number of pixels of the design image is greater than or equal to the seventeenth preset threshold; the resolution of the physical image is greater than or equal to the eighteenth preset threshold; the resolution of the design image is greater than or equal to the nineteenth preset threshold; the area of ​​the physical information and / or physical image and / or design information and / or design image is greater than or equal to the twentieth preset threshold; the area of ​​the smallest figure in the physical information and / or physical image and / or design information and / or design image is less than or equal to the twenty-first preset threshold; the overall rough comparison is combined with the other comparison methods;

[0097] The applicable situations for the overall rough comparison of the entire physical information plate or physical image plate with the design information plate or design image plate include but are not limited to one or more of the following: the time required to complete the overall fine comparison of the plates is greater than or equal to the twenty-second preset threshold; the number of pixels of the physical image plate is greater than or equal to the twenty-third preset threshold; the number of pixels of the design image plate is greater than or equal to the twenty-fourth preset threshold; the resolution of the physical image plate is greater than or equal to the twenty-fifth preset threshold; the resolution of the design image plate is greater than or equal to the twenty-sixth preset threshold; the area of ​​the physical information plate and / or physical image plate and / or design information plate and / or design image plate is greater than or equal to the twenty-seventh preset threshold; the area of ​​the smallest graphic in the physical information plate and / or physical image plate and / or design information plate and / or design image plate is less than or equal to the twenty-eighth preset threshold; and the overall rough comparison is combined with the other comparison methods.

[0098] In the embodiment of the present invention, the detailed comparison method includes but is not limited to one or more of the following:

[0099] For the comparison of the physical object information or physical object image with the design information or design image, and / or the comparison of the physical object information plate or physical image plate with the design information plate or design image plate, one or more comparisons are conducted by gradually narrowing the comparison area and / or reducing the granularity for one or more of the following areas, including but not limited to: areas that failed the overall comparison, areas of interest or considered critical after the overall comparison passed, areas with complex implementation, areas with critical functions, and the entire area;

[0100] When performing one or more comparisons, the refinement limit is that the comparison area has been reduced to the minimum graphic and / or minimum size, and / or granularity in the corresponding information and / or image and / or information plate and / or image plate has reached the minimum limit, and the refined comparison needs to reach or not reach the refinement limit.

[0101] In the embodiment of the present invention, the sampling and comparison methods include, but are not limited to, one or more of the following:

[0102] For comparison between the physical object information or physical object image and the design information or design image, and / or comparison between the physical object information plate or physical object image plate and the design information plate or design image plate, calculate and / or set an area that can be used for comparison (i.e., this area can be obtained by calculation and / or set);

[0103] Selecting a number of sampling blocks from the object information or the object image or the object information plate or the object image plate based on the area available for comparison, wherein the sum of the areas of the sampling blocks shall not exceed the area available for comparison;

[0104] Selecting a number of sampling blocks from the design information or design image or design information plate or design image plate based on the area available for comparison, wherein the sum of the areas of the sampling blocks shall not exceed the area available for comparison;

[0105] The sampling blocks selected from the physical object information or physical object image or physical object information plate or physical image plate maintain a corresponding relationship with the sampling blocks selected from the design information or design image or design information plate or design image plate;

[0106] The sampling block selection method includes but is not limited to one or more of the following: random sampling, sampling according to a rule, allocating the number of sampling blocks proportional to the density and / or complexity of the graphics, allocating the area of ​​the sampling blocks proportional to the density and / or complexity of the graphics, setting;

[0107] Comparing the sample blocks in the physical object information or physical object image or physical object information plate or physical image plate with the sample blocks in the corresponding design information or design image or design information plate or design image plate;

[0108] Analyze the results of this sampling comparison by combining the comparison results of each sampling block;

[0109] The fine limit of sampling comparison is that the granularity has reached the minimum limit, and the sampling comparison needs to reach or not reach the said fine limit.

[0110] In the embodiment of the present invention, the area that can be used for comparison is calculated, including but not limited to one or more of the following:

[0111] For the physical object information or physical object image or physical object information plate or physical image plate, and the design information or design image or design information plate or design image plate, calculate the area available for comparison based on the time required to complete the comparison per unit area and the expected completion time of this comparison;

[0112] The calculation method includes but is not limited to: area available for comparison = unit area * expected completion time of this comparison / time required to complete the comparison per unit area.

[0113] In the embodiment of the present invention, the method for obtaining the minimum figure and / or minimum size and / or minimum area includes but is not limited to one or more of the following:

[0114] Obtaining a minimum size from corresponding design information and / or physical information and / or design information plate and / or physical information plate, wherein the obtaining method includes but is not limited to obtaining one or more of the following information: minimum line width, feature size, process technology, gate length, and channel length;

[0115] Further analysis is performed based on the minimum size to obtain the minimum figure and / or minimum area;

[0116] The minimum graphic and / or the minimum size and / or the minimum area are identified in the corresponding design image and / or the actual product image and / or the design image panel and / or the actual product image panel.

[0117] In an embodiment of the present invention, in one or more of the following situations, the method further includes adjusting the corresponding resolution and / or number of pixels before comparing:

[0118] Before image comparison begins and / or after splitting the panels and / or during overall comparison, adjust the resolution and / or pixel count of the physical image and / or design image and / or physical image panels and / or design image panels before comparison;

[0119] After narrowing the comparison area and / or reducing the granularity, the resolution and / or number of pixels of the corresponding images are adjusted for the narrowed and / or granularity-reduced areas before re-comparison;

[0120] After selecting the sampling blocks, the resolution and / or pixel count of the corresponding image are adjusted for each sampling block before comparison.

[0121] In one embodiment of the present invention, the method further includes:

[0122] Adjust the comparison implementation algorithm for one or more of the following situations, including but not limited to: different comparison purposes, different comparison contents, different comparison methods, different comparison modes, and different working stages of the comparison.

[0123] In the embodiment of the present invention, the verification of the design information includes, but is not limited to, one or more of the following:

[0124] Verifying the first design information of the chip or chip module with the corresponding second design information, wherein the verification method includes but is not limited to LVS inspection or verification;

[0125] Verifying the second design information of the chip or chip module with the corresponding third design information, and / or verifying the second design information of the chip or chip module with the corresponding fourth design information, wherein the verification method includes but is not limited to formal verification;

[0126] The third design information of the chip or chip module is verified with the corresponding fourth design information, and the verification method includes but is not limited to formal verification.

[0127] In one embodiment of the present invention, before verifying the design information, the method further includes:

[0128] Confirm the accuracy of the acquired design information.

[0129] In the embodiment of the present invention, the method for confirming the accuracy of the acquired design information includes but is not limited to one or more of the following:

[0130] For the first design information obtained for comparison and the first design information obtained for verification, confirming that the design information of the overlapping parts and / or repeated parts therein are identical and / or consistent; the method for confirming that the design information of the overlapping parts and / or repeated parts are identical and / or consistent includes, but is not limited to, one or more of the following: unifying the format of the first design information obtained for comparison and the format of the first design information obtained for verification, performing image comparison on the overlapping parts and / or repeated parts, performing graphic comparison on the overlapping parts and / or repeated parts, performing similarity comparison on the overlapping parts and / or repeated parts, determining that the similarity is greater than or equal to a twenty-ninth preset threshold, and determining that all or part of the information of one of the first design information obtained for comparison and the first design information obtained for verification is obtained by extracting all or part of the information from the other information, and / or all or part of the information of one of the information is obtained by converting the format of the other information into another information and extracting all or part of the information therefrom;

[0131] unifying the format of the first design information obtained for comparison with the format of the first design information obtained for verification; the method of unifying the formats of the two includes but is not limited to one or more of the following: converting one of the two formats into the other format, converting both formats into a third format; the third format refers to a format other than the format of the first design information obtained for comparison and the format of the first design information obtained for verification;

[0132] For the second design information obtained for verification with the first design information, the second design information obtained for verification with the third design information, and the second design information obtained for verification with the fourth design information, for any and / or set one or more combinations of two of the three, and / or between the three, confirm that the design information of the overlapping parts and / or repeated parts is the same and / or remains consistent; the method for confirming that the design information of the overlapping parts and / or repeated parts is the same and / or remains consistent, includes but is not limited to one or more of the following: unifying the design information format; performing image comparison on the overlapping parts and / or repeated parts; performing graphic comparison on the overlapping parts and / or repeated parts; performing similarity comparison on the overlapping parts and / or repeated parts; determining that the similarity is greater than or equal to the thirtieth preset threshold; determining that the obtained Among the second design information used for verification with the first design information, the second design information obtained for verification with the third design information, and the second design information obtained for verification with the fourth design information, all or part of one or more of the information is obtained by extracting all or part of the information from another one or more of the information, and / or all or part of the information is obtained by extracting all or part of the information from another one or more of the information after format conversion. Application scenarios of the method for confirming that the design information of the overlapping and / or repeated parts is the same and / or consistent include, but are not limited to: for an analog-digital hybrid chip, confirming that the gate-level netlist of the digital chip module therein, after the format is converted into a transistor-level netlist, its content is the same as or consistent with the digital chip module part in the chip transistor-level netlist;

[0133] For the second design information obtained for verification with the first design information, the second design information obtained for verification with the third design information, and the second design information obtained for verification with the fourth design information, for any and / or set one or more pairwise combinations of the three, and / or between the three, the design information formats are unified; the method for unifying the design information formats includes but is not limited to one or more of the following: for the pairwise combinations, converting one of the two formats into another format, for the pairwise combinations, converting both formats into a third format, for the pairwise combinations, the third format refers to a format other than the design information format in the combination, for the three, unifying the formats into one of the three formats, for the three, converting all the three formats into a fourth format, for the three, the fourth format refers to a format other than the design information format among the three;

[0134] confirming that the design information of the overlapping and / or repeated parts of the third design information obtained for verification with the second design information and the third design information obtained for verification with the fourth design information are identical and / or consistent; methods for confirming that the design information of the overlapping and / or repeated parts are identical and / or consistent include, but are not limited to, one or more of the following: unifying the format of the third design information obtained for verification with the second design information and the format of the third design information obtained for verification with the fourth design information, performing image comparison on the overlapping and / or repeated parts, performing graphic comparison on the overlapping and / or repeated parts, and performing similarity comparison on the overlapping and / or repeated parts to determine that the similarity is greater than or equal to a thirty-first preset threshold, and determining that, between the third design information obtained for verification with the second design information and the third design information obtained for verification with the fourth design information, all or part of the information of one of the information is obtained by extracting all or part of the information from the other information, and / or all or part of the information of one of the information is obtained by converting the format of the other information into another information and extracting all or part of the information therefrom;

[0135] unifying the format of the third design information obtained for verification with the second design information and the format of the third design information obtained for verification with the fourth design information; the method of unifying the formats of the two includes but is not limited to one or more of the following: converting one of the two formats into the other format, converting both formats into a third format; the third format refers to a format other than the format of the third design information obtained for verification with the second design information and the format of the third design information obtained for verification with the fourth design information;

[0136] confirming that the design information of the overlapping and / or repeated parts of the fourth design information obtained for verification with the second design information and the fourth design information obtained for verification with the third design information are identical and / or consistent; methods for confirming that the design information of the overlapping and / or repeated parts are identical and / or consistent include, but are not limited to, one or more of the following: unifying the format of the fourth design information obtained for verification with the second design information and the format of the fourth design information obtained for verification with the third design information, performing image comparison on the overlapping and / or repeated parts, performing graphic comparison on the overlapping and / or repeated parts, and performing similarity comparison on the overlapping and / or repeated parts to determine that the similarity is greater than or equal to a thirty-second preset threshold, and determining that, between the fourth design information obtained for verification with the second design information and the fourth design information obtained for verification with the third design information, all or part of the information of one of the information is obtained by extracting all or part of the information from the other information, and / or all or part of the information of one of the information is obtained by converting the format of the other information into another information and extracting all or part of the information therefrom;

[0137] unifying the obtained fourth design information format for verification with the second design information and the obtained fourth design information format for verification with the third design information; the method of unifying the formats of the two includes but is not limited to one or more of the following: converting one of the two formats into the other format, converting both formats into a third format; the third format refers to a format other than the obtained fourth design information format for verification with the second design information and the obtained fourth design information format for verification with the third design information;

[0138] Confirming that the gate-level netlist in the acquired second design information is a back-end netlist and / or a non-front-end netlist;

[0139] confirming that the gate-level netlist in the acquired third design information is a front-end netlist and / or a non-back-end netlist;

[0140] The method for confirming that the gate-level netlist in the obtained second design information is a back-end netlist and / or a non-front-end netlist, and / or confirming that the gate-level netlist in the obtained third design information is a front-end netlist and / or a non-back-end netlist, includes but is not limited to one or more of the following: keyword search; performing a similarity comparison between the gate-level netlist in the obtained second design information and the gate-level netlist in the obtained third design information, and / or determining that the similarity is less than or equal to a thirty-third preset threshold;

[0141] Confirming that the acquired RTL code is a register transfer level description and / or not a description at another level, wherein the description at another level includes but is not limited to a gate level description;

[0142] The accuracy of the obtained design information is confirmed by the file suffix of the obtained design information.

[0143] In an embodiment of the present invention, when the design information is verified, the correspondence between the design information includes but is not limited to one or more of the following: correspondence of the same modules, correspondence of the same units, correspondence of the same functions, correspondence of the same logic, and correspondence of the same connections.

[0144] In an embodiment of the present invention, when performing the verification, the verification settings and / or conditions are confirmed. The method of confirming the verification settings and / or conditions includes, but is not limited to, one or more of the following:

[0145] When the verification is LVS verification, the settings and / or conditions of the LVS verification are confirmed by analyzing the design information targeted by the LVS verification, or / and checking the design specifications corresponding to the design information targeted by the LVS verification; the settings and / or conditions of the LVS verification include but are not limited to one or more of the following: top-level design, top-level unit, top-level logic, and top-level module;

[0146] When the verification is formal verification, the settings and / or conditions of the formal verification are confirmed by analyzing the design information targeted by the formal verification and / or viewing the design specifications corresponding to the design information targeted by the formal verification; the settings and / or conditions of the formal verification include but are not limited to one or more of the following: top-level design, top-level unit, top-level logic, top-level module, and constant settings;

[0147] The top-level design and / or top-level unit and / or top-level logic and / or top-level module in the verification settings and / or conditions are related to the design information targeted by the verification, and are all or part of the design information of the chip or chip module; the top-level design and / or top-level unit and / or top-level logic and / or top-level module in the verification settings are application scenarios of part of the design information of the chip, including but not limited to: for a mixed analog-digital chip, the top-level design and / or top-level unit and / or top-level logic and / or top-level module in the formal verification settings and / or conditions are digital chip modules in the mixed analog-digital chip.

[0148] In an embodiment of the present invention, when conducting the verification, a comprehensive analysis is performed on one or more verification results and / or reports to determine whether the verification is passed; when the verification is a formal verification, the verification results and / or reports include but are not limited to one or more of the following: comparison point matching check results, verification results, and verification reports.

[0149] In the embodiment of the present invention, the determination of the autonomy and / or controllability of the chip or chip module based on the comparison result and / or verification result includes, but is not limited to, one or more of the following:

[0150] Determining, based on the characteristics of the chip or chip module, the type of comparison and / or verification required to determine the degree of autonomy and / or controllability of the chip or chip module;

[0151] For the required comparison and / or verification types, assign scores corresponding to the required comparisons and / or verifications according to the difficulty and / or criticality of the steps represented by the types;

[0152] For each of the required comparisons and / or verifications, when the comparisons and / or verifications are actually performed and passed, the chip or chip module obtains a score corresponding to the comparison and / or verification;

[0153] For each of the required comparisons and / or verifications, if the comparisons and / or verifications are not actually performed or are not actually performed, the chip or chip module does not obtain a score corresponding to the comparison and / or verification;

[0154] Based on the results of various comparisons and / or verifications actually carried out, invalid scores are sorted out from the scores corresponding to the various comparisons and / or verifications obtained for the chip or chip module;

[0155] Among the scores corresponding to various comparisons and / or verifications obtained for the chip or chip module, invalid scores are removed, and the remaining scores are valid scores, the valid scores are summed, and the summed result is used as the final score of the chip or chip module;

[0156] The degree of autonomy and / or controllability of the chip or chip module is determined based on the final score of the chip or chip module.

[0157] In the embodiment of the present invention, the results of the various comparisons and / or verifications actually performed are comprehensively analyzed, and invalid scores are sorted out from the scores corresponding to the various comparisons and / or verifications obtained by the chip or chip module, including but not limited to one or more of the following:

[0158] When the physical information of the chip or chip module fails the comparison with the corresponding first design information, the corresponding scores obtained by the chip or chip module for each of the required verifications when actually carried out and passed are invalid scores;

[0159] When the verification between the first design information of the chip or chip module and the corresponding second design information fails, the corresponding score obtained when the verification between the second design information of the chip or chip module and the corresponding third design information is actually carried out and passes is an invalid score;

[0160] When the verification between the first design information of the chip or chip module and the corresponding second design information fails, the corresponding score obtained when the verification between the second design information of the chip or chip module and the corresponding fourth design information is actually carried out and passes is an invalid score;

[0161] When the verification between the first design information of the chip or chip module and the corresponding second design information fails, the corresponding score obtained when the verification between the third design information of the chip or chip module and the corresponding fourth design information is actually carried out and passes is an invalid score;

[0162] When the second design information of the chip or chip module and the corresponding third design information fail to be verified, and the second design information of the chip or chip module and the corresponding fourth design information fail to be verified, the corresponding score obtained when the verification of the third design information of the chip or chip module and the corresponding fourth design information is actually carried out and passed is an invalid score.

[0163] In the embodiment of the present invention, for a chip composed of one or more chip modules, the determination of the autonomy and / or controllability of the chip includes, but is not limited to, one or more of the following:

[0164] For each chip module in the chip, a corresponding weight is assigned according to the difficulty and / or criticality of each chip module. The chip score is the weighted sum of the scores of each chip module. The chip's autonomy and / or controllability is determined based on the weighted sum.

[0165] The allocation of corresponding weights needs to ensure that when a chip with a given function is composed of one or more chip modules under different solutions, the scores corresponding to the same degree of autonomy and / or controllability are the same; the implementation method of ensuring the same scores corresponding to the same degree of autonomy and / or controllability includes but is not limited to one or more of the following: weight allocation normalization, in which the sum of the weights of the chip modules of the chip with the given function is the same under different solutions, and when it is determined that the autonomy and / or controllability of each chip module is the highest, the scores of each chip module are the same, and the full scores of each chip module are the same;

[0166] For each chip module in the chip, when determining the physical information of each chip module, ensure that the physical information of each chip module does not overlap and / or repeat, and that the sum of the physical information of each chip module is the physical information of the entire chip;

[0167] For each chip module in the chip, when determining the design information of each chip module, ensure that the design information of each chip module does not overlap and / or repeat, and that the sum of the design information of each chip module is the design information of the entire chip;

[0168] The physical information of each chip module corresponds to the design information.

[0169] (One of the purposes of ensuring that the physical information of each chip module does not overlap and / or does not repeat, and / or ensuring that the design information of each chip module does not overlap and / or does not repeat, is to avoid repeated scoring for the same comparison content and / or verification content. For example: in one or more of the following situations, when determining the physical information of each chip module and / or determining the design information of each chip module, it is ensured that the physical information of each chip module does not overlap and / or does not repeat, and / or ensuring that the design information of each chip module does not overlap and / or does not repeat: When multiple chip modules are placed on the same packaging substrate, the physical information and corresponding design information of the packaging substrate are divided according to their relationship with each chip module, ensuring that each chip module The physical information of the assigned packaging substrates does not overlap, and the sum is exactly the total physical information of the packaging substrates, ensuring that the design information of the packaging substrates assigned to each chip module does not overlap, and the sum is exactly the total design information of the packaging substrates; when multiple chip modules are connected, the physical connection relationships and corresponding design connection relationships between the chip modules are divided according to their relationships with each chip module, ensuring that the physical connection relationships between the chip modules assigned to each chip module do not overlap, and the sum is exactly the total physical connection relationships between the chip modules, ensuring that the design connection relationships between the chip modules assigned to each chip module do not overlap, and the sum is exactly the total design connection relationships between the chip modules.)

[0170] In an embodiment of the present invention, when the chip modules constituting the chip have the same model, the chip modules of the same model are uniformly treated as a single integrated chip module for detection, and scores are uniformly calculated and weights are assigned. Methods for uniformly treating the chip modules of the same model as a single integrated chip module for detection include, but are not limited to, one or more of the following:

[0171] Determining the sum of the physical information of the chip modules of the same model as the physical information of the entire chip module under test, determining the sum of the design information of the chip modules of the same model as the design information of the entire chip module under test, and calculating a score for the entire chip module under test;

[0172] Randomly or according to a rule, select a chip module from the chip modules of the same model, and use the score of the chip module as the score of the entire chip module tested;

[0173] For the chip modules of the same model, all or part of the chip modules are selected, scores of the selected chip modules are calculated respectively, and the average of the scores of the selected chip modules is used as the score of the entire chip module detected.

[0174] In the embodiment of the present invention, the scope of application of the method for determining the autonomy and / or controllability of a chip composed of one or more chip modules includes, but is not limited to, one or more of the following:

[0175] An analog-digital hybrid chip composed of a digital chip module and an analog chip module;

[0176] A multi-chip module (MCM) (i.e., one of the chips) formed by packaging multiple bare chips (i.e., one of the chip modules);

[0177] RF front-end module.

[0178] In order to implement the above method embodiment, the embodiment of the present invention further provides a detection device for a chip or chip module, such as Figure 2 As shown, the device includes:

[0179] Information determination module 201, used to determine physical information of a chip or chip module, and / or determine design information of the chip or chip module;

[0180] An information processing module 202 is configured to compare the physical object information with the design information and / or verify the design information;

[0181] The determination module 203 is configured to determine the degree of autonomy and / or controllability of the chip or chip module based on the comparison result and / or verification result.

[0182] In the embodiment of the present invention, the chip includes but is not limited to one or more of the following:

[0183] A chip that packages one or more dies;

[0184] Unpackaged die.

[0185] In the embodiment of the present invention, the chip module includes but is not limited to one or more of the following:

[0186] A die in a chip that packages one or more dies;

[0187] Functional modules in a die.

[0188] In the embodiment of the present invention, the physical information includes but is not limited to one or more of the following:

[0189] The physical connection relationship between the chip or chip module and the packaging substrate, and / or the physical connection relationship between the chip or chip module and other chips or chip modules, including but not limited to one or more of the following forms of expression: physical connection relationship, physical diagram describing the connection relationship, table describing the physical connection relationship, physical pin names describing the physical connection relationship, and physical connection relationship expressed by name;

[0190] Physical information of the package substrate, including but not limited to one or more of the following: the physical package substrate, the physical circuit or circuit diagram of the package substrate, the physical layout or layout diagram of the package substrate, the physical wiring or wiring diagram of the package substrate, and the physical circuit or circuit diagram of the package substrate;

[0191] Physical information of the chip or chip module, including but not limited to one or more of the following: the physical chip or chip module, the physical layout of the chip or chip module, the physical layout of the chip or chip module, the physical layout and wiring of the chip or chip module or the layout and wiring diagram, the physical circuit of the chip or chip module or the circuit diagram;

[0192] Among them, the physical information includes but is not limited to one or more of the following physical information: all layers, some layers, one layer, and the method of selecting the layer number includes but is not limited to one or more of the following: random selection, selection according to rules, and setting; for one of the layers, the physical information includes but is not limited to one or more of the following physical information: the entire area, multiple local areas, one local area, and the method of selecting the area includes but is not limited to one or more of the following: random selection, selection according to rules, and setting.

[0193] In the embodiment of the present invention, the method for obtaining the physical object information includes, but is not limited to, one or more of the following:

[0194] Directly obtain one or more chips or chip modules to be tested and obtain physical information;

[0195] Randomly or according to rules, select one or more chips or chip modules to be tested and obtain physical information;

[0196] Directly obtain physical information through one or more of the following methods, including but not limited to: computerized tomography (CT), X-rays, radiography, ultrasound, and non-destructive testing;

[0197] Uncap the packaged chip and obtain physical information;

[0198] In the case where the physical connection relationship between the chip or chip module and the packaging substrate, and / or the physical connection relationship between the chip or chip module and other chips or chip modules is obscured, the physical connection relationship is obtained through one or more of the following methods, including but not limited to: CT, X-ray, X-ray, radiation, ultrasound, non-destructive testing, delamination, flat grinding, grinding, lapping, polishing, corrosion, etching, sectioning, dissection, and staining; the case where the physical connection relationship is obscured includes but is not limited to the physical connection relationship being obscured in a flip-chip chip;

[0199] Separating the chip or chip module from the packaging substrate, and / or separating the chip or chip module from other chips or chip modules, wherein the separation method includes but is not limited to one or more of the following: disconnecting or removing or removing connecting wires, corroding, etching, heating, delaminating, flat grinding, grinding, lapping, polishing, slicing, dissecting, and removing the chip;

[0200] Obtaining one or more layers of physical information by one or more of the following methods, including but not limited to: directly obtaining, obtaining through a microscope and / or microscopic imaging instrument and / or CT and / or X-ray and / or X-ray and / or radiology and / or ultrasound and / or non-destructive testing, delamination, flat grinding, grinding, lapping, polishing, corroding, etching, sectioning, dissecting, staining, disconnecting or removing or removing connecting lines;

[0201] Obtain and record the physical image, video or video corresponding to the physical object information through a microscope and / or microscopic imaging instrument and / or CT and / or X-ray and / or X-ray and / or radiation and / or ultrasound and / or non-destructive testing, in combination with photography and / or image acquisition and / or video recording, or directly through photography and / or image acquisition and / or video recording; the physical image, video or video is a single file, or multiple files, or a single file composed of multiple files;

[0202] Obtain physical object information and corresponding physical object images and videos through microscopes and / or microscopic imaging instruments and / or CT and / or X-rays and / or X-rays and / or radiation and / or ultrasound and / or non-destructive testing, combined with naked eye observation, or directly through naked eye observation.

[0203] In the embodiment of the present invention, the information determination module 201 obtains or selects multiple chips or chip modules to be tested and acquires physical information, including but not limited to one or more of the following:

[0204] To obtain multiple samples, perform statistical analysis on physical information, or / and comparison of physical information with design information, or / and the degree of autonomy and / or controllability of the chip or chip module, obtain or select multiple chips or chip modules of the same model, and obtain the same physical information from each chip or chip module;

[0205] In cases where destructive operations are required to obtain physical information or / and only partial physical information can be obtained from a chip or chip module, obtain or select multiple chips or chip modules of the same model and obtain different physical information from each chip or chip module, or obtain the same and different physical information simultaneously;

[0206] In order to determine the autonomy and / or controllability of a chip composed of multiple chip modules, the physical information of each of the multiple chip modules in the chip is obtained respectively, and the autonomy and / or controllability is determined, and the autonomy and / or controllability of the chip is determined based on the results.

[0207] In the embodiment of the present invention, the design information includes but is not limited to one or more of the following:

[0208] The designed connection relationship between a chip or chip module and a packaging substrate, and / or the designed connection relationship between a chip or chip module and other chips or chip modules, the designed connection relationship including but not limited to one or more of the following forms of expression: a design drawing describing the connection relationship, a table describing the designed connection relationship, a pin design name describing the designed connection relationship, and the designed connection relationship expressed by the name; the design information including but not limited to one or more of the following design information: all layers, some layers, one layer, the layer number selection method including but not limited to one or more of the following: random selection, selection according to rules, and setting; for one layer, the design information including but not limited to one or more of the following design information: the entire area, multiple local areas, one local area, the area selection method including but not limited to one or more of the following: random selection, selection according to rules, and setting; the format of the designed connection relationship including but not limited to one or more formats;

[0209] Design information of a packaging substrate, the design information including but not limited to one or more of the following: a packaging substrate design circuit or circuit diagram, a packaging substrate design layout or layout diagram, a packaging substrate design wiring or wiring diagram, a packaging substrate design circuit or circuit diagram; the design information including but not limited to one or more of the following design information: all layers, some layers, one layer, and the layer number selection method including but not limited to one or more of the following: random selection, selection according to a rule, and setting; for one layer, the design information including but not limited to one or more of the following design information: the entire area, multiple local areas, one local area, and the area selection method including but not limited to one or more of the following: random selection, selection according to a rule, and setting; the format of the packaging substrate design information including but not limited to one or more formats;

[0210] First design information of a chip or chip module, the first design information includes but is not limited to one or more of the following: a chip or chip module design layout, a chip or chip module design layout, a chip or chip module design layout wiring or layout wiring diagram; the first design information includes but is not limited to one or more of the following design information: all layers, part of the layers, one layer, and the layer number selection method includes but is not limited to one or more of the following: random selection, selection according to rules, and setting; for one layer, the first design information includes but is not limited to one or more of the following design information: the entire area, multiple local areas, one local area, and the area selection method includes but is not limited to one or more of the following: random selection, selection according to rules, and setting; the first design information used for comparison is all or part of the design information in the first design information; the first design information used for verification is all or part of the design information in the first design information; the first design information used for comparison and the first design information used for verification are the same or different design information; the format of the first design information includes but is not limited to one or more formats; the format of the first design information used for comparison and the format of the first design information used for verification are the same or different formats;

[0211] Second design information of the chip or chip module, the second design information includes but is not limited to a schematic diagram and / or a netlist of the chip or chip module, the schematic diagram and / or netlist includes but is not limited to one or more of the following: a schematic diagram, a netlist corresponding to the schematic diagram, a transistor-level netlist, a gate-level netlist of the final design of the digital chip or digital chip module, a gate-level netlist corresponding to the first design information of the digital chip or digital chip module; the second design information includes but is not limited to all or part of the design information; the second design information used for verification with the first design information is all or part of the design information in the second design information; the second design information used for verification with the third design information is all design information or part of the design information; the second design information used for verification with the fourth design information is all the design information or part of the design information in the second design information; any two of the second design information used for verification with the first design information, the second design information used for verification with the third design information, and the second design information used for verification with the fourth design information are the same or different design information; the format of the second design information includes but is not limited to one or more formats; any two of the format of the second design information used for verification with the first design information, the format of the second design information used for verification with the third design information, and the format of the second design information used for verification with the fourth design information are the same or different formats;

[0212] Third design information of a chip or chip module, the third design information including but not limited to a gate-level netlist synthesized from register transfer level RTL code of the digital chip or digital chip module; the third design information including but not limited to all or part of the design information; the third design information used for verification with the second design information is all or part of the design information in the third design information; the third design information used for verification with the fourth design information is all or part of the design information in the third design information; the third design information used for verification with the second design information and the third design information used for verification with the fourth design information are the same or different design information; the format of the third design information includes but is not limited to one or more formats; the format of the third design information used for verification with the second design information and the format of the third design information used for verification with the fourth design information are the same or different formats;

[0213] The fourth design information of the chip or chip module includes but is not limited to the RTL code of the digital chip or digital chip module; the fourth design information includes but is not limited to all or part of the design information; the fourth design information used for verification with the second design information is all or part of the design information in the fourth design information; the fourth design information used for verification with the third design information is all or part of the design information in the fourth design information; the fourth design information used for verification with the second design information and the fourth design information used for verification with the third design information are the same or different design information; the format of the fourth design information includes but is not limited to one or more formats; the format of the fourth design information used for verification with the second design information and the format of the fourth design information used for verification with the third design information are the same or different formats.

[0214] In the embodiment of the present invention, the information processing module 202 compares the physical information with the design information, including but not limited to one or more of the following:

[0215] Comparing the physical connection relationship between the chip or chip module and the packaging substrate, and / or the physical connection relationship between the chip or chip module and other chips or chip modules, with the corresponding designed connection relationship to check whether the two are consistent;

[0216] Compare the physical information of the package substrate with the design information of the corresponding package substrate to check whether the two are consistent;

[0217] Comparing the physical information of the chip or chip module with the first design information of the corresponding chip or chip module to check whether the two are consistent;

[0218] The comparison includes but is not limited to one or more of the following comparisons: all layers, part of the layers, one layer, and the layer number selection method includes but is not limited to one or more of the following: random selection, selection according to rules, and setting; for one of the layers, the comparison includes but is not limited to one or more of the following comparisons: the entire area, multiple local areas, one local area, and the area selection method includes but is not limited to one or more of the following: random selection, selection according to rules, and setting.

[0219] In the embodiment of the present invention, before the information processing module 202 compares the physical object information with the design information, the information determining module 201 is further configured to confirm the accuracy of the acquired design information.

[0220] In the embodiment of the present invention, the comparison method adopted by the information processing module 202 includes but is not limited to one or more of the following: automatic comparison by a detection device, manual comparison;

[0221] When the comparison method is automatic comparison by a detection device, it is necessary to determine whether the format of the physical information is a format that can be recognized and / or used by the detection device; when the format of the physical information is not a format that can be recognized and / or used by the detection device, it is necessary to adjust the format of the physical information to a format that can be recognized and / or used by the detection device; the method of adjusting the format of the physical information to a format that can be recognized and / or used by the detection device includes but is not limited to one or more of the following: recording the physical information as a physical image, converting the physical connection relationship into a table that describes the physical connection relationship;

[0222] When the comparison method is automatic comparison by a detection device, it is necessary to determine whether the format of the design information is a format that can be recognized and / or used by the detection device; when the format of the design information is not a format that can be recognized and / or used by the detection device, it is necessary to adjust the format of the design information to a format that can be recognized and / or used by the detection device; the method of adjusting the format of the design information to a format that can be recognized and / or used by the detection device includes but is not limited to one or more of the following: converting the design information into a design image, converting the design connection relationship into a table that describes the design connection relationship; the design image includes but is not limited to an image in which the design information is saved or / and converted or / and recorded as an image format;

[0223] The method of determining whether the format of the physical information and / or the design information is a format that can be recognized and / or used by the detection device includes but is not limited to one or more of the following: automatic determination by the detection device, manual determination;

[0224] The method of adjusting the format of the physical information and / or the design information to a format that can be recognized and / or used by the detection device includes but is not limited to one or more of the following: automatic adjustment by the detection device and manual adjustment.

[0225] In the embodiment of the present invention, when the information processing module 202 compares the physical information with the design information, the correspondence between the physical information and the design information includes but is not limited to one or more of the following:

[0226] Correspondence between the same layers;

[0227] Correspondence between the same areas;

[0228] The correspondence between the same positions;

[0229] The corresponding relationship of the same position ratio includes, but is not limited to, one or more of the following: if the ratio of the position in the physical information and / or physical image and the distance between each point in the entire physical information and / or physical image are the same as the ratio of the position in the design information and / or design image and the distance between each point in the entire design information and / or design image, then the position of the physical information and / or physical image and the position of the design information and / or design image are in a corresponding relationship; if the position in the physical information and / or physical image and the position in the design information and / or design image, after the entire physical information and / or the entire physical image and / or the entire design information and / or the entire design image are scaled proportionally, and the entire physical information and / or the entire physical image and / or the entire design image coincide with the entire design information and / or the entire design image, then the position of the physical information and / or physical image and the position of the design information and / or design image are in a corresponding relationship;

[0230] The corresponding relationship between the same pin names.

[0231] In the embodiment of the present invention, when comparing the physical object information or physical object image with the design information or design image, the information processing module 202 is further configured to: split the physical object information or physical object image and the corresponding design information or design image into one or more sections, maintain a corresponding relationship between the sections of the physical object information or physical image and the sections of the design information or design image, perform a comparison on each section separately, and analyze the comparison result based on the comparison results of each section;

[0232] The situations in which the splitting into one or more sections may be performed include but are not limited to one or more of the following: the physical information or physical image, and the comparison content with the design information or design image, are concentrated in one or more local areas, and the physical information or physical image, and the comparison content with the design information or design image, are split into one or more sections according to the concentrated areas; the physical information or physical image, and the comparison content with the design information or design image, have large differences in graphic sizes in different areas, and the physical information or physical image, and the comparison content with the design information or design image, are split into one or more sections according to different graphic sizes or different size ranges;

[0233] Among them, after splitting into sections, if some sections do not have the required comparison content, the comparison of this section may be omitted or not omitted. When the comparison of this section is omitted, this section will not be included in the analysis of the comparison results of the comprehensive comparison results of each section.

[0234] In the embodiment of the present invention, the information processing module 202 compares the physical object information or physical object image with the design information or design image, and / or compares the physical object information plate or physical image plate with the design information plate or design image plate. The comparison method includes but is not limited to one or more of the following: overall comparison, detailed comparison, and sampling comparison;

[0235] The comparison contents include but are not limited to one or more of the following: connection relationship, geometric shape, geometric shape features;

[0236] The degree of comparison fineness of the comparison is expressed using granularity, which is related to the comparison mode, method, content and purpose. The granularity includes but is not limited to the degree of accuracy of the comparison content. The minimum limit of the granularity includes but is not limited to one or more of the following: the minimum graphic in the corresponding information and / or image, the minimum size in the corresponding information and / or image, the minimum area in the corresponding information and / or image, the graphic set according to the corresponding information and / or image, the size set according to the corresponding information and / or image, and the area set according to the corresponding information and / or image.

[0237] In the embodiment of the present invention, the information processing module 202 compares the physical object information or physical object image with the design information or design image, and / or compares the physical object information plate or physical object image plate with the design information plate or design image plate, and is further configured to perform, but not limited to, one or more of the following:

[0238] Adjusting the resolution and / or number of pixels of the physical image and / or the design image and / or the physical image plate and / or the design image plate to be compared, and performing a comparison between the physical image and the design image, and / or the physical image plate and the design image plate based on the adjustment result;

[0239] When the comparison method is automatic comparison by a detection device, with respect to the granularity of the planned comparison, the resolution and / or the number of pixels of the physical image and / or the design image and / or the physical image plate and / or the design image plate are adjusted according to the resolution of the physical image and / or the design image and / or the physical image plate and / or the design image plate, and / or the number of pixels of the granularity of the planned comparison contained in the physical image and / or the design image and / or the physical image plate and / or the design image plate, as well as the comparison capability of the detection device. Based on the adjustment result, the physical image and the design image, and / or the physical image plate and the design image plate are compared;

[0240] The comparison capability of the detection device includes but is not limited to: the minimum resolution required by the detection device for completing the comparison at the granularity, for the physical image and / or the design image and / or the physical image plate and / or the design image plate, and / or the minimum number of pixels required to be included in the granularity;

[0241] The adjustment method includes but is not limited to: with respect to the granularity of the planned comparison, on the premise of ensuring the accuracy of the comparison, reducing the resolution and / or number of pixels of the physical image and / or the design image and / or the physical image plate and / or the design image plate, so that the resolution of the physical image and / or the design image and / or the physical image plate and / or the design image plate is reduced, and / or the number of pixels contained in the granularity in the physical image and / or the design image and / or the physical image plate and / or the design image plate is reduced, and is greater than or equal to the comparison capability of the detection device.

[0242] In the embodiment of the present invention, the information processing module 202 adopts the overall comparison method, including but not limited to one or more of the following:

[0243] Comparison of the entire object information or image with the design information or image, and / or comparison of the entire object information panel or image panel with the design information panel or image panel;

[0244] The overall alignment includes but is not limited to one or more of the following: overall fine alignment, overall rough alignment;

[0245] During the overall fine comparison, the granularity of the comparison has reached the minimum limit;

[0246] During a rough overall comparison, the granularity of the comparison is greater than the minimum limit, and the comparison content includes but is not limited to one or more of the following: connection relationship, chip area, chip outline, package substrate area, package substrate outline, graphic overview, graphic distribution characteristics, and module structure;

[0247] Applicable situations for the overall fine comparison of the entire physical information or physical image with the design information or design image include but are not limited to one or more of the following: the time required to complete the overall fine comparison is less than or equal to a first preset threshold; the number of pixels of the physical image is less than or equal to a second preset threshold; the number of pixels of the design image is less than or equal to a third preset threshold; the resolution of the physical image is less than or equal to a fourth preset threshold; the resolution of the design image is less than or equal to a fifth preset threshold; the area of ​​the physical information and / or physical image and / or design information and / or design image is less than or equal to a sixth preset threshold; the area of ​​the smallest graphic in the physical information and / or physical image and / or design information and / or design image is greater than or equal to a seventh preset threshold;

[0248] Applicable situations for the overall fine comparison of the entire physical information plate or physical image plate with the design information plate or design image plate include but are not limited to one or more of the following: the time required to complete the overall fine comparison of the plates is less than or equal to the eighth preset threshold; the number of pixels of the physical image plate is less than or equal to the ninth preset threshold; the number of pixels of the design image plate is less than or equal to the tenth preset threshold; the resolution of the physical image plate is less than or equal to the eleventh preset threshold; the resolution of the design image plate is less than or equal to the twelfth preset threshold; the area of ​​the physical information plate and / or physical image plate and / or design information plate and / or design image plate is less than or equal to the thirteenth preset threshold; the area of ​​the smallest graphic in the physical information plate and / or physical image plate and / or design information plate and / or design image plate is greater than or equal to the fourteenth preset threshold;

[0249] Applicable situations for the overall rough comparison of the entire physical information or physical image with the design information or design image include but are not limited to one or more of the following: the time required to complete the overall fine comparison is greater than or equal to the fifteenth preset threshold; the number of pixels of the physical image is greater than or equal to the sixteenth preset threshold; the number of pixels of the design image is greater than or equal to the seventeenth preset threshold; the resolution of the physical image is greater than or equal to the eighteenth preset threshold; the resolution of the design image is greater than or equal to the nineteenth preset threshold; the area of ​​the physical information and / or physical image and / or design information and / or design image is greater than or equal to the twentieth preset threshold; the area of ​​the smallest figure in the physical information and / or physical image and / or design information and / or design image is less than or equal to the twenty-first preset threshold; the overall rough comparison is combined with the other comparison methods;

[0250] The applicable situations for the overall rough comparison of the entire physical information plate or physical image plate with the design information plate or design image plate include but are not limited to one or more of the following: the time required to complete the overall fine comparison of the plates is greater than or equal to the twenty-second preset threshold; the number of pixels of the physical image plate is greater than or equal to the twenty-third preset threshold; the number of pixels of the design image plate is greater than or equal to the twenty-fourth preset threshold; the resolution of the physical image plate is greater than or equal to the twenty-fifth preset threshold; the resolution of the design image plate is greater than or equal to the twenty-sixth preset threshold; the area of ​​the physical information plate and / or physical image plate and / or design information plate and / or design image plate is greater than or equal to the twenty-seventh preset threshold; the area of ​​the smallest graphic in the physical information plate and / or physical image plate and / or design information plate and / or design image plate is less than or equal to the twenty-eighth preset threshold; and the overall rough comparison is combined with the other comparison methods.

[0251] In the embodiment of the present invention, the information processing module 202 adopts the detailed comparison method, including but not limited to one or more of the following:

[0252] For the comparison of the physical object information or physical object image with the design information or design image, and / or the comparison of the physical object information plate or physical image plate with the design information plate or design image plate, one or more comparisons are conducted by gradually narrowing the comparison area and / or reducing the granularity for one or more of the following areas, including but not limited to: areas that failed the overall comparison, areas of interest or considered critical after the overall comparison passed, areas with complex implementation, areas with critical functions, and the entire area;

[0253] When performing one or more comparisons, the refinement limit is that the comparison area has been reduced to the minimum graphic and / or minimum size, and / or granularity in the corresponding information and / or image and / or information plate and / or image plate has reached the minimum limit, and the refined comparison needs to reach or not reach the refinement limit.

[0254] In the embodiment of the present invention, the information processing module 202 adopts the sampling and comparison method, including but not limited to one or more of the following:

[0255] Calculating and / or setting an area available for comparison between the physical object information or physical object image and the design information or design image, and / or comparing the physical object information plate or physical object image plate and the design information plate or design image plate;

[0256] Selecting a number of sampling blocks from the object information or the object image or the object information plate or the object image plate based on the area available for comparison, wherein the sum of the areas of the sampling blocks shall not exceed the area available for comparison;

[0257] Selecting a number of sampling blocks from the design information or design image or design information plate or design image plate based on the area available for comparison, wherein the sum of the areas of the sampling blocks shall not exceed the area available for comparison;

[0258] The sampling blocks selected from the physical object information or physical object image or physical object information plate or physical image plate maintain a corresponding relationship with the sampling blocks selected from the design information or design image or design information plate or design image plate;

[0259] The sampling block selection method includes but is not limited to one or more of the following: random sampling, sampling according to a rule, allocating the number of sampling blocks proportional to the density and / or complexity of the graphics, allocating the area of ​​the sampling blocks proportional to the density and / or complexity of the graphics, setting;

[0260] Comparing the sample blocks in the physical object information or physical object image or physical object information plate or physical image plate with the sample blocks in the corresponding design information or design image or design information plate or design image plate;

[0261] Analyze the results of this sampling comparison by combining the comparison results of each sampling block;

[0262] The fine limit of sampling comparison is that the granularity has reached the minimum limit, and the sampling comparison needs to reach or not reach the said fine limit.

[0263] In the embodiment of the present invention, the information processing module 202 calculates the area that can be used for comparison, including but not limited to one or more of the following:

[0264] For the physical object information or physical object image or physical object information plate or physical image plate, and the design information or design image or design information plate or design image plate, calculate the area available for comparison based on the time required to complete the comparison per unit area and the expected completion time of this comparison;

[0265] The calculation method includes but is not limited to: area available for comparison = unit area * expected completion time of this comparison / time required to complete the comparison per unit area.

[0266] In the embodiment of the present invention, the method for obtaining the minimum figure and / or minimum size and / or minimum area includes but is not limited to one or more of the following:

[0267] Obtaining a minimum size from corresponding design information and / or physical information and / or design information plate and / or physical information plate, wherein the obtaining method includes but is not limited to obtaining one or more of the following information: minimum line width, feature size, process technology, gate length, and channel length;

[0268] Further analysis is performed based on the minimum size to obtain the minimum figure and / or minimum area;

[0269] The minimum graphic and / or the minimum size and / or the minimum area are identified in the corresponding design image and / or the actual product image and / or the design image panel and / or the actual product image panel.

[0270] In the embodiment of the present invention, in one or more of the following situations, the information processing module 202 is further configured to adjust the corresponding resolution and / or number of pixels before comparison:

[0271] Before image comparison begins and / or after splitting the panels and / or during overall comparison, adjust the resolution and / or pixel count of the physical image and / or design image and / or physical image panels and / or design image panels before comparison;

[0272] After narrowing the comparison area and / or reducing the granularity, the resolution and / or number of pixels of the corresponding images are adjusted for the narrowed and / or granularity-reduced areas before re-comparison;

[0273] After selecting the sampling blocks, the resolution and / or pixel count of the corresponding image are adjusted for each sampling block before comparison.

[0274] In an embodiment of the present invention, the information processing module 202 is further used to adjust the comparison implementation algorithm according to one or more of the following situations, including but not limited to: different comparison purposes, different comparison contents, different comparison methods, different comparison modes, and different working stages in the comparison.

[0275] In the embodiment of the present invention, the information processing module 202 verifies the design information, including but not limited to one or more of the following:

[0276] Verifying the first design information of the chip or chip module with the corresponding second design information, wherein the verification method includes but is not limited to LVS inspection or verification;

[0277] Verifying the second design information of the chip or chip module with the corresponding third design information, and / or verifying the second design information of the chip or chip module with the corresponding fourth design information, wherein the verification method includes but is not limited to formal verification;

[0278] The third design information of the chip or chip module is verified with the corresponding fourth design information, and the verification method includes but is not limited to formal verification.

[0279] In the embodiment of the present invention, before the information processing module 202 verifies the design information, the information determining module 201 is further configured to confirm the accuracy of the acquired design information.

[0280] In the embodiment of the present invention, the method by which the information determination module 201 confirms the accuracy of the acquired design information includes but is not limited to one or more of the following:

[0281] For the first design information obtained for comparison and the first design information obtained for verification, confirming that the design information of the overlapping parts and / or repeated parts therein are identical and / or consistent; the method for confirming that the design information of the overlapping parts and / or repeated parts are identical and / or consistent includes, but is not limited to, one or more of the following: unifying the format of the first design information obtained for comparison and the format of the first design information obtained for verification, performing image comparison on the overlapping parts and / or repeated parts, performing graphic comparison on the overlapping parts and / or repeated parts, performing similarity comparison on the overlapping parts and / or repeated parts, determining that the similarity is greater than or equal to a twenty-ninth preset threshold, and determining that all or part of the information of one of the first design information obtained for comparison and the first design information obtained for verification is obtained by extracting all or part of the information from the other information, and / or all or part of the information of one of the information is obtained by converting the format of the other information into another information and extracting all or part of the information therefrom;

[0282] unifying the format of the first design information obtained for comparison with the format of the first design information obtained for verification; the method of unifying the formats of the two includes but is not limited to one or more of the following: converting one of the two formats into the other format, converting both formats into a third format; the third format refers to a format other than the format of the first design information obtained for comparison and the format of the first design information obtained for verification;

[0283] For the second design information obtained for verification with the first design information, the second design information obtained for verification with the third design information, and the second design information obtained for verification with the fourth design information, for any and / or set one or more combinations of two of the three, and / or between the three, confirm that the design information of the overlapping parts and / or repeated parts is the same and / or remains consistent; the method for confirming that the design information of the overlapping parts and / or repeated parts is the same and / or remains consistent, includes but is not limited to one or more of the following: unifying the design information format; performing image comparison on the overlapping parts and / or repeated parts; performing graphic comparison on the overlapping parts and / or repeated parts; performing similarity comparison on the overlapping parts and / or repeated parts; determining that the similarity is greater than or equal to the thirtieth preset threshold; determining that the obtained Among the second design information used for verification with the first design information, the second design information obtained for verification with the third design information, and the second design information obtained for verification with the fourth design information, all or part of one or more of the information is obtained by extracting all or part of the information from another one or more of the information, and / or all or part of the information is obtained by extracting all or part of the information from another one or more of the information after format conversion. Application scenarios of the method for confirming that the design information of the overlapping and / or repeated parts is the same and / or consistent include, but are not limited to: for an analog-digital hybrid chip, confirming that the gate-level netlist of the digital chip module therein, after the format is converted into a transistor-level netlist, its content is the same as or consistent with the digital chip module part in the chip transistor-level netlist;

[0284] For the second design information obtained for verification with the first design information, the second design information obtained for verification with the third design information, and the second design information obtained for verification with the fourth design information, for any and / or set one or more pairwise combinations of the three, and / or between the three, the design information formats are unified; the method for unifying the design information formats includes but is not limited to one or more of the following: for the pairwise combinations, converting one of the two formats into another format, for the pairwise combinations, converting both formats into a third format, for the pairwise combinations, the third format refers to a format other than the design information format in the combination, for the three, unifying the formats into one of the three formats, for the three, converting all the three formats into a fourth format, for the three, the fourth format refers to a format other than the design information format among the three;

[0285] confirming that the design information of the overlapping and / or repeated parts of the third design information obtained for verification with the second design information and the third design information obtained for verification with the fourth design information are identical and / or consistent; methods for confirming that the design information of the overlapping and / or repeated parts are identical and / or consistent include, but are not limited to, one or more of the following: unifying the format of the third design information obtained for verification with the second design information and the format of the third design information obtained for verification with the fourth design information, performing image comparison on the overlapping and / or repeated parts, performing graphic comparison on the overlapping and / or repeated parts, and performing similarity comparison on the overlapping and / or repeated parts to determine that the similarity is greater than or equal to a thirty-first preset threshold, and determining that, between the third design information obtained for verification with the second design information and the third design information obtained for verification with the fourth design information, all or part of the information of one of the information is obtained by extracting all or part of the information from the other information, and / or all or part of the information of one of the information is obtained by converting the format of the other information into another information and extracting all or part of the information therefrom;

[0286] unifying the format of the third design information obtained for verification with the second design information and the format of the third design information obtained for verification with the fourth design information; the method of unifying the formats of the two includes but is not limited to one or more of the following: converting one of the two formats into the other format, converting both formats into a third format; the third format refers to a format other than the format of the third design information obtained for verification with the second design information and the format of the third design information obtained for verification with the fourth design information;

[0287] confirming that the design information of the overlapping and / or repeated parts of the fourth design information obtained for verification with the second design information and the fourth design information obtained for verification with the third design information are identical and / or consistent; methods for confirming that the design information of the overlapping and / or repeated parts are identical and / or consistent include, but are not limited to, one or more of the following: unifying the format of the fourth design information obtained for verification with the second design information and the format of the fourth design information obtained for verification with the third design information, performing image comparison on the overlapping and / or repeated parts, performing graphic comparison on the overlapping and / or repeated parts, and performing similarity comparison on the overlapping and / or repeated parts to determine that the similarity is greater than or equal to a thirty-second preset threshold, and determining that, between the fourth design information obtained for verification with the second design information and the fourth design information obtained for verification with the third design information, all or part of the information of one of the information is obtained by extracting all or part of the information from the other information, and / or all or part of the information of one of the information is obtained by converting the format of the other information into another information and extracting all or part of the information therefrom;

[0288] unifying the obtained fourth design information format for verification with the second design information and the obtained fourth design information format for verification with the third design information; the method of unifying the formats of the two includes but is not limited to one or more of the following: converting one of the two formats into the other format, converting both formats into a third format; the third format refers to a format other than the obtained fourth design information format for verification with the second design information and the obtained fourth design information format for verification with the third design information;

[0289] Confirming that the gate-level netlist in the acquired second design information is a back-end netlist and / or a non-front-end netlist;

[0290] confirming that the gate-level netlist in the acquired third design information is a front-end netlist and / or a non-back-end netlist;

[0291] The method for confirming that the gate-level netlist in the obtained second design information is a back-end netlist and / or a non-front-end netlist, and / or confirming that the gate-level netlist in the obtained third design information is a front-end netlist and / or a non-back-end netlist, includes but is not limited to one or more of the following: keyword search; performing a similarity comparison between the gate-level netlist in the obtained second design information and the gate-level netlist in the obtained third design information, and / or determining that the similarity is less than or equal to a thirty-third preset threshold;

[0292] Confirming that the acquired RTL code is a register transfer level description and / or not a description at another level, wherein the description at another level includes but is not limited to a gate level description;

[0293] The accuracy of the obtained design information is confirmed by the file suffix of the obtained design information.

[0294] In an embodiment of the present invention, when the information processing module 202 verifies the design information, the correspondence between the design information includes but is not limited to one or more of the following: correspondence of the same modules, correspondence of the same units, correspondence of the same functions, correspondence of the same logic, and correspondence of the same connections.

[0295] In the embodiment of the present invention, when the information processing module 202 performs the verification, it confirms the settings and / or conditions of the verification. The method of confirming the settings and / or conditions of the verification includes, but is not limited to, one or more of the following:

[0296] When the verification is LVS verification, the settings and / or conditions of the LVS verification are confirmed by analyzing the design information targeted by the LVS verification, or / and checking the design specifications corresponding to the design information targeted by the LVS verification; the settings and / or conditions of the LVS verification include but are not limited to one or more of the following: top-level design, top-level unit, top-level logic, and top-level module;

[0297] When the verification is formal verification, the settings and / or conditions of the formal verification are confirmed by analyzing the design information targeted by the formal verification and / or viewing the design specifications corresponding to the design information targeted by the formal verification; the settings and / or conditions of the formal verification include but are not limited to one or more of the following: top-level design, top-level unit, top-level logic, top-level module, and constant settings;

[0298] The top-level design and / or top-level unit and / or top-level logic and / or top-level module in the verification settings and / or conditions are related to the design information targeted by the verification, and are all or part of the design information of the chip or chip module; the top-level design and / or top-level unit and / or top-level logic and / or top-level module in the verification settings are application scenarios of part of the design information of the chip, including but not limited to: for a mixed analog-digital chip, the top-level design and / or top-level unit and / or top-level logic and / or top-level module in the formal verification settings and / or conditions are digital chip modules in the mixed analog-digital chip.

[0299] In an embodiment of the present invention, when the information processing module 202 carries out the verification, it performs a comprehensive analysis of one or more verification results and / or reports to determine whether the verification is passed; when the verification is a formal verification, the verification results and / or reports include but are not limited to one or more of the following: comparison point matching check results, verification results, and verification reports.

[0300] In the embodiment of the present invention, the determination module 203 determines the autonomy and / or controllability of the chip or chip module based on the comparison result and / or verification result, including but not limited to one or more of the following:

[0301] Determining, based on the characteristics of the chip or chip module, the type of comparison and / or verification required to determine the degree of autonomy and / or controllability of the chip or chip module;

[0302] For the required comparison and / or verification types, assign scores corresponding to the required comparisons and / or verifications according to the difficulty and / or criticality of the steps represented by the types;

[0303] For each of the required comparisons and / or verifications, when the comparisons and / or verifications are actually performed and passed, the chip or chip module obtains a score corresponding to the comparison and / or verification;

[0304] For each of the required comparisons and / or verifications, if the comparisons and / or verifications are not actually performed or are not actually performed, the chip or chip module does not obtain a score corresponding to the comparison and / or verification;

[0305] Based on the results of various comparisons and / or verifications actually carried out, invalid scores are sorted out from the scores corresponding to the various comparisons and / or verifications obtained for the chip or chip module;

[0306] Among the scores corresponding to various comparisons and / or verifications obtained for the chip or chip module, invalid scores are removed, and the remaining scores are valid scores, the valid scores are summed, and the summed result is used as the final score of the chip or chip module;

[0307] The degree of autonomy and / or controllability of the chip or chip module is determined based on the final score of the chip or chip module.

[0308] In the embodiment of the present invention, the determination module 203 integrates the results of various comparisons and / or verifications actually performed and sorts out invalid scores from the scores corresponding to the various comparisons and / or verifications obtained by the chip or chip module, including but not limited to one or more of the following:

[0309] When the physical information of the chip or chip module fails the comparison with the corresponding first design information, the corresponding scores obtained by the chip or chip module for each of the required verifications when actually carried out and passed are invalid scores;

[0310] When the verification between the first design information of the chip or chip module and the corresponding second design information fails, the corresponding score obtained when the verification between the second design information of the chip or chip module and the corresponding third design information is actually carried out and passes is an invalid score;

[0311] When the verification between the first design information of the chip or chip module and the corresponding second design information fails, the corresponding score obtained when the verification between the second design information of the chip or chip module and the corresponding fourth design information is actually carried out and passes is an invalid score;

[0312] When the verification between the first design information of the chip or chip module and the corresponding second design information fails, the corresponding score obtained when the verification between the third design information of the chip or chip module and the corresponding fourth design information is actually carried out and passes is an invalid score;

[0313] When the second design information of the chip or chip module and the corresponding third design information fail to be verified, and the second design information of the chip or chip module and the corresponding fourth design information fail to be verified, the corresponding score obtained when the verification of the third design information of the chip or chip module and the corresponding fourth design information is actually carried out and passed is an invalid score.

[0314] In the embodiment of the present invention, for a chip composed of one or more chip modules, the determination of the autonomy and / or controllability of the chip includes, but is not limited to, one or more of the following:

[0315] For each chip module in the chip, a corresponding weight is assigned according to the difficulty and / or criticality of each chip module. The chip score is the weighted sum of the scores of each chip module. The chip's autonomy and / or controllability is determined based on the weighted sum.

[0316] The allocation of corresponding weights needs to ensure that when a chip with a given function is composed of one or more chip modules under different solutions, the scores corresponding to the same degree of autonomy and / or controllability are the same; the implementation method of ensuring the same scores corresponding to the same degree of autonomy and / or controllability includes but is not limited to one or more of the following: weight allocation normalization, in which the sum of the weights of the chip modules of the chip with the given function is the same under different solutions, and when it is determined that the autonomy and / or controllability of each chip module is the highest, the scores of each chip module are the same, and the full scores of each chip module are the same;

[0317] For each chip module in the chip, when determining the physical information of each chip module, ensure that the physical information of each chip module does not overlap and / or repeat, and that the sum of the physical information of each chip module is the physical information of the entire chip;

[0318] For each chip module in the chip, when determining the design information of each chip module, ensure that the design information of each chip module does not overlap and / or repeat, and that the sum of the design information of each chip module is the design information of the entire chip;

[0319] The physical information of each chip module corresponds to the design information.

[0320] In an embodiment of the present invention, when the chip modules constituting the chip have the same model, the chip modules of the same model are uniformly regarded as a single integrated chip module for detection, and a score is uniformly calculated and a weight is assigned. The processing method for the determination module 203 to uniformly regard the chip modules of the same model as a single integrated chip module for detection includes, but is not limited to, one or more of the following:

[0321] Determining the sum of the physical information of the chip modules of the same model as the physical information of the entire chip module under test, determining the sum of the design information of the chip modules of the same model as the design information of the entire chip module under test, and calculating a score for the entire chip module under test;

[0322] Randomly or according to a rule, select a chip module from the chip modules of the same model, and use the score of the chip module as the score of the entire chip module tested;

[0323] For the chip modules of the same model, all or part of the chip modules are selected, scores of the selected chip modules are calculated respectively, and the average of the scores of the selected chip modules is used as the score of the entire chip module detected.

[0324] In the embodiment of the present invention, the scope of application of the method for determining the autonomy and / or controllability of a chip composed of one or more chip modules includes, but is not limited to, one or more of the following:

[0325] An analog-digital hybrid chip composed of a digital chip module and an analog chip module;

[0326] A multi-chip module (MCM) is a package of multiple dies.

[0327] RF front-end module.

[0328] An embodiment of the present invention further provides a chip or chip module detection device, the device comprising: a processor and a memory for storing a computer program that can be run on the processor,

[0329] Wherein, when the processor is used to run the computer program, it executes:

[0330] Determining physical information of the chip or chip module, and / or determining design information of the chip or chip module;

[0331] Comparing the physical object information with the design information, and / or verifying the design information;

[0332] Based on the comparison result and / or verification result, the autonomy and / or controllability of the chip or chip module is determined.

[0333] In the embodiment of the present invention, when the processor is used to run the computer program, it also executes the contents described in the above method embodiment, which will not be described in detail here.

[0334] It should be noted that the apparatus provided in the above embodiments, when performing chip or chip module detection, is illustrated only by the division of the aforementioned program modules. In actual applications, the aforementioned processing can be assigned to different program modules as needed, that is, the internal structure of the device can be divided into different program modules to complete all or part of the aforementioned processing. In addition, the apparatus provided in the above embodiments and the corresponding method embodiments are based on the same concept. The specific implementation process is detailed in the method embodiments and will not be repeated here.

[0335] The present invention is described below with reference to scenario embodiments.

[0336] This embodiment provides a method for detecting a chip or chip module, which checks the degree of autonomy and controllability of the chip by tracing the design process of the chip or chip module and comparing and verifying the outputs of each link of the chip or chip module. Through comparison and / or verification, the total score is calculated according to certain rules and logic. The higher the score obtained, the higher the degree of autonomy and / or controllability of the chip design process, and the higher the corresponding degree of autonomy and / or controllability. This embodiment provides a simple and objective detection basis for the evaluation of the autonomy and / or controllability of the chip or chip module, and improves the objectivity, practicality and comprehensiveness of the evaluation of the autonomy and / or controllability of the chip or chip module.

[0337] Scenario Example 1:

[0338] For a certain model of chip that encapsulates a bare die and does not contain a digital module, an embodiment is provided, which can be performed according to the following process (see the flowchart for details). Figure 3 , for clarity, only the numbers of the operations are given in the figure) to determine the degree of autonomy and / or controllability of the chip:

[0339] 1. Determine the physical and design information of the chip:

[0340] 1.1, Determine the physical connection relationship between the chip and the package substrate (a type of physical information):

[0341] Determine the physical connection relationship between the chip (including the internal bare die) and the package substrate. In this embodiment, it is determined to be the physical diagram describing the connection relationship - Figure A;

[0342] Here, it is assumed that all physical connections are concentrated in one layer, and the physical diagram of that layer represents the entire physical connection relationship. If the physical connection relationship has multiple layers, the connection relationship of all layers, some layers, or one layer can be recorded according to the actual situation to obtain a physical diagram describing the connection relationship.

[0343] 1.2, determine the physical information of the package substrate (a type of physical information):

[0344] Determine the physical information of the package substrate. In this embodiment, it is determined to be the physical package substrate and recorded as the physical package substrate images - images Bi and Bj (i and j are selected layer numbers);

[0345] Determine the physical object of the package substrate as the physical information of the package substrate. If the package substrate circuit has multiple layers, randomly select layer i and layer j (or other methods such as selection according to rules or settings), and record them as images using a combination of microscopy and photography to obtain images Bi and Bj.

[0346] This assumes that the package substrate circuitry has multiple layers, and that some layers (here, two layers, but three, four, or other numbers are also possible) are selected as physical information and recorded as images. For multi-layer package substrate circuitry, all layers can be selected as physical information and recorded as images, or a single layer can be selected as physical information and recorded as images. For package substrate circuitry with only one layer, the image of that layer can be directly recorded.

[0347] 1.3, Determine the physical information of the chip (a type of physical information):

[0348] Determine the physical information of the chip. In this embodiment, it is determined to be the physical layout of the chip, and recorded as the physical layout of the chip - Figure Cp, Figure Cq (p, q are selected layer numbers);

[0349] Determine the physical layout of the chip as the physical information of the chip. If the chip layout has multiple layers, set (or select randomly, according to a rule, or other methods) the p layer and the q layer as the physical information, and record them as images by combining microscopy and photography to obtain graphs Cp and Cq;

[0350] Here, we assume that the chip layout has multiple layers, and we select some layers (here, two layers, but it could be three, four, or any other number of layers) as physical information and record the image. If the chip layout has multiple layers, we can select all layers as physical information and record the image, or select one layer as physical information and record the image. If the chip layout has only one layer, we can directly record the image of that layer.

[0351] 1.4, Determine the design connection relationship between the chip and the package substrate (a type of design information):

[0352] Confirm the design connection relationship between the chip (including the internal bare die) and the package substrate. In this embodiment, it is determined to be the design diagram describing the connection relationship - Figure a;

[0353] The selection of layer numbers in the design drawing describing the connection relationship corresponds to the physical drawing describing the connection relationship.

[0354] 1.5, Determine the design information of the package substrate (a type of design information):

[0355] Determine the design information of the package substrate. In this embodiment, the design information is determined to be the package substrate design circuit diagrams - Figure bi and Figure bj (i and j are selected layer numbers);

[0356] The selection of layer numbers in the package substrate design circuit diagram corresponds to the actual diagram of the package substrate.

[0357] 1.6, determine the first design information of the chip (a type of design information):

[0358] Determine the first design information of the chip. In this embodiment, the first design information is determined to be the design layout of the chip - Figure c (the entire design layout of the chip), Figure cp, and Figure cq (where p and q are selected layer numbers);

[0359] Figure c is the entire design layout of the chip, that is, the layout of the entire area of ​​all layers, which is convenient for subsequent verification with the second design information. It is the first design information used for verification; Figure cp and Figure cq are the layouts of the p layer and q layer in the chip design layout, that is, the partial layout of Figure c. The selection of layer numbers corresponds to the physical layout of the chip, which is convenient for subsequent comparison with the physical layout of the chip. It is the first design information used for comparison.

[0360] 1.7, Determine the second design information of the chip (a type of design information):

[0361] The second design information of the chip is determined. In this embodiment, the second design information is determined to be a schematic diagram of the chip.

[0362] 2. Compare the physical information with the design information and verify the design information:

[0363] 2.1. Compare the physical connection between the chip and the package substrate with the corresponding design connection to check whether they are consistent (a type of comparison):

[0364] Compare the connection relationship between the pins in Figure A with the connection relationship between the pins in Figure a to see if they are consistent.

[0365] 2.2. Compare the physical information of the package substrate with the design information of the corresponding package substrate to check whether the two are consistent (a type of comparison):

[0366] Compare Figure Bi with Figure bi, and Figure Bj with Figure bj, to check whether the geometric shapes, geometric shape features, etc. of the lines in the figures are consistent.

[0367] 2.3. Compare the physical information of the chip with the first design information of the corresponding chip to check whether the two are consistent (a type of comparison):

[0368] Compare Figure Cp with Figure cp, and compare Figure Cq with Figure cq, and check whether the geometric shapes, geometric shape features, etc. of the layouts in the figures are consistent.

[0369] 2.4. Verify the first design information of the chip and the corresponding second design information (a type of verification). The verification method includes but is not limited to LVS inspection or verification:

[0370] Perform LVS verification on the chip design layout (Figure c) and the chip schematic.

[0371] 3. Based on the comparison and verification results, determine the chip's autonomy and / or controllability:

[0372] Based on the comparison and verification results, the chip's autonomy and / or controllability is determined, including but not limited to one or more of the following:

[0373] Based on the characteristics of the chip, the types of comparison and / or verification required to determine the degree of autonomy and / or controllability of the chip are determined. In this embodiment, the types of comparison required are: comparison of the physical connection relationship between the chip and the packaging substrate with the corresponding design connection relationship (item 2.1), comparison of the physical information of the packaging substrate with the corresponding design information of the packaging substrate (item 2.2), and comparison of the physical information of the chip with the corresponding first design information of the chip (item 2.3). The type of verification required is: verification of the first design information of the chip with the corresponding second design information (item 2.4).

[0374] For the required comparison and / or verification types, scores are assigned to the required comparisons and / or verifications based on the difficulty and / or criticality of the steps represented by the types. In this embodiment, scores are assigned to the following comparisons and verifications: comparison of the physical connection relationship between the chip and the packaging substrate with the corresponding design connection relationship (item 2.1), comparison of the physical information of the packaging substrate with the corresponding design information of the packaging substrate (item 2.2), comparison of the physical information of the chip with the corresponding first design information of the chip (item 2.3), and verification of the first design information of the chip with the corresponding second design information (item 2.4).

[0375] For each of the required comparisons and / or verifications, when the comparisons and / or verifications are actually performed and passed, the chip obtains a score corresponding to the comparison and / or verification; when the comparisons and / or verifications are actually performed and failed or not actually performed, the chip does not obtain a score corresponding to the comparison and / or verification;

[0376] Based on the results of various comparisons and / or verifications actually carried out, invalid scores are sorted out from the scores corresponding to the various comparisons and / or verifications obtained by the chip;

[0377] Among the scores corresponding to various comparisons and verifications obtained by the chip, invalid scores are removed, and the remaining scores are valid scores, the valid scores are summed, and the summed result is used as the final score of the chip;

[0378] The autonomy and / or controllability of the chip is determined based on the final score of the chip.

[0379] Scenario Example 2:

[0380] For a certain model of a digital chip that is packaged with a bare die, an embodiment is provided, which can be carried out according to, but not limited to, the following process (see the flowchart for details). Figure 4 For clarity, only the numbers of the operations are given in the figure. Furthermore, the and / or relationships in 2.5 cannot be shown one by one in the figure. Only one case is shown - verifying the second design information in 1.7 with the third design information in 1.8 to determine the autonomy and / or controllability of this chip:

[0381] 1. Determine the physical and design information of the chip:

[0382] 1.1, Determine the physical connection relationship between the chip and the package substrate (a type of physical information):

[0383] Determine the physical connection relationship between the chip (including the internal bare die) and the package substrate. In this embodiment, it is determined to be the physical diagram describing the connection relationship - Figure A;

[0384] Here, it is assumed that all physical connections are concentrated in one layer, and the physical diagram of that layer represents the entire physical connection relationship. If the physical connection relationship has multiple layers, the connection relationship of all layers, some layers, or one layer can be recorded according to the actual situation to obtain a physical diagram describing the connection relationship.

[0385] 1.2, determine the physical information of the package substrate (a type of physical information):

[0386] Determine the physical information of the package substrate. In this embodiment, it is determined to be the physical package substrate and recorded as the physical package substrate images - images Bi and Bj (i and j are selected layer numbers);

[0387] Determine the physical object of the package substrate as the physical information of the package substrate. If the package substrate circuit has multiple layers, randomly select layer i and layer j (or other methods such as selection according to rules or settings), and record them as images using a combination of microscopy and photography to obtain images Bi and Bj.

[0388] This assumes that the package substrate circuitry has multiple layers, and that some layers (here, two layers, but three, four, or other numbers are also possible) are selected as physical information and recorded as images. For multi-layer package substrate circuitry, all layers can be selected as physical information and recorded as images, or a single layer can be selected as physical information and recorded as images. For package substrate circuitry with only one layer, the image of that layer can be directly recorded.

[0389] 1.3, Determine the physical information of the chip (a type of physical information):

[0390] Determine the physical information of the chip. In this embodiment, it is determined to be the physical layout of the chip, and recorded as the physical layout of the chip - Figure Cp, Figure Cq (p, q are selected layer numbers);

[0391] Determine the physical layout of the chip as the physical information of the chip. If the chip layout has multiple layers, set (or select randomly, according to a rule, or other methods) the p layer and the q layer as the physical information, and record them as images by combining microscopy and photography to obtain graphs Cp and Cq;

[0392] Here, we assume that the chip layout has multiple layers, and we select some layers (here, two layers, but it could be three, four, or any other number of layers) as physical information and record the image. If the chip layout has multiple layers, we can select all layers as physical information and record the image, or select one layer as physical information and record the image. If the chip layout has only one layer, we can directly record the image of that layer.

[0393] 1.4, Determine the design connection relationship between the chip and the package substrate (a type of design information):

[0394] Confirm the design connection relationship between the chip (including the internal bare die) and the package substrate. In this embodiment, it is determined to be the design diagram describing the connection relationship - Figure a;

[0395] The selection of layer numbers in the design drawing describing the connection relationship corresponds to the physical drawing describing the connection relationship.

[0396] 1.5, Determine the design information of the package substrate (a type of design information):

[0397] Determine the design information of the package substrate. In this embodiment, the design information is determined to be the package substrate design circuit diagrams - Figure bi and Figure bj (i and j are selected layer numbers);

[0398] The selection of layer numbers in the package substrate design circuit diagram corresponds to the actual diagram of the package substrate.

[0399] 1.6, determine the first design information of the chip (a type of design information):

[0400] Determine the first design information of the chip. In this embodiment, the first design information is determined to be the design layout of the chip - Figure c (the entire design layout of the chip), Figure cp, and Figure cq (where p and q are selected layer numbers);

[0401] Figure c is the entire design layout of the chip, that is, the layout of the entire area of ​​all layers, which is convenient for subsequent verification with the second design information. It is the first design information used for verification; Figure cp and Figure cq are the layouts of the p layer and q layer in the chip design layout, that is, the partial layout of Figure c. The selection of layer numbers corresponds to the physical layout of the chip, which is convenient for subsequent comparison with the physical layout of the chip. It is the first design information used for comparison.

[0402] 1.7, Determine the second design information of the chip (a type of design information):

[0403] Determine the second design information of the chip. In this embodiment, the second design information is determined to be a gate-level netlist of the final design of the chip (this embodiment uses this as an example, and it can also be other content such as the gate-level netlist corresponding to the first design information).

[0404] It should be noted that the above determination that the second design information is the gate-level netlist of the final chip design is for the case where the LVS verification software can take the gate-level netlist format as input. If the LVS software cannot take the gate-level netlist format as input, one or more of the following processing can be performed:

[0405] Convert the final chip design gate-level netlist into an input format acceptable to LVS software, such as a transistor-level netlist format like a CDL netlist (to confirm the accuracy of the acquired design information). Use the final chip design gate-level netlist and the converted CDL netlist or other transistor-level netlist as the second design information. The former is used to verify with the third design information, and the latter is used to verify with the first design information.

[0406] Determine and obtain the gate-level netlist of the final chip design, obtain the chip CDL netlist and other transistor-level netlists, confirm that the gate-level netlist is the same or consistent with the obtained CDL netlist and other transistor-level netlists after conversion (confirm the accuracy of the obtained design information), and use the gate-level netlist of the final chip design, the chip CDL netlist and other transistor-level netlists as the second design information, the former is used to verify with the third design information, and the latter is used to verify with the first design information.

[0407] 1.8, Determine the third design information of the chip (a type of design information):

[0408] The third design information of the chip is determined. In this embodiment, the third design information is determined to be a gate-level netlist synthesized from the chip RTL code.

[0409] 1.9, determine the fourth design information of the chip (a type of design information):

[0410] The fourth design information of the chip is determined. In this embodiment, the fourth design information is determined to be the RTL code of the chip.

[0411] 2. Compare the physical information with the design information and verify the design information:

[0412] 2.1. Compare the physical connection between the chip and the package substrate with the corresponding design connection to check whether they are consistent (a type of comparison):

[0413] Compare the connection relationship between the pins in Figure A with the connection relationship between the pins in Figure a to see if they are consistent.

[0414] 2.2. Compare the physical information of the package substrate with the design information of the corresponding package substrate to check whether the two are consistent (a type of comparison):

[0415] Compare Figure Bi with Figure bi, and Figure Bj with Figure bj, to check whether the geometric shapes, geometric shape features, etc. of the lines in the figures are consistent.

[0416] 2.3. Compare the physical information of the chip with the first design information of the corresponding chip to check whether the two are consistent (a type of comparison):

[0417] Compare Figure Cp with Figure cp, and compare Figure Cq with Figure cq, and check whether the geometric shapes, geometric shape features, etc. of the layouts in the figures are consistent.

[0418] 2.4. Verify the first design information of the chip and the corresponding second design information (a type of verification). The verification method includes but is not limited to LVS inspection or verification:

[0419] The chip design layout (Figure c) and the gate-level netlist of the final chip design are verified by LVS.

[0420] 2.5. Verify the second chip design information with the corresponding third design information, and / or verify the second chip design information with the corresponding fourth design information (a type of verification). Verification methods include but are not limited to formal verification:

[0421] In this embodiment, the gate-level netlist of the final chip design and the chip RTL code are formally verified, and / or the gate-level netlist of the final chip design and the chip RTL code are formally verified.

[0422] 2.6. Verify the third design information of the chip with the corresponding fourth design information (a type of verification). The verification method includes but is not limited to formal verification:

[0423] In this embodiment, a gate-level netlist synthesized from the chip RTL code is formally verified together with the chip RTL code.

[0424] 3. Based on the comparison and verification results, determine the chip's autonomy and / or controllability:

[0425] Based on the comparison and verification results, the chip's autonomy and / or controllability is determined, including but not limited to one or more of the following:

[0426] Based on the characteristics of the chip, the types of comparison and / or verification required to determine the degree of autonomy and / or controllability of the chip are determined: in this embodiment, the types of comparison required are determined to be: comparison of the physical connection relationship between the chip and the packaging substrate and the corresponding design connection relationship (item 2.1), comparison of the physical information of the packaging substrate with the corresponding design information of the packaging substrate (item 2.2), and comparison of the physical information of the chip with the corresponding first design information of the chip (item 2.3); the types of verification required are determined to be: verification of the first design information of the chip with the corresponding second design information (item 2.4), verification of the second design information of the chip with the corresponding third design information, and / or verification of the second design information of the chip with the corresponding fourth design information (item 2.5), and verification of the third design information of the chip with the corresponding fourth design information (item 2.6);

[0427] For the required comparison types and / or verification types, scores are assigned to the required comparisons and / or verifications based on the difficulty and / or criticality of the links represented by the various types. In this embodiment, scores are assigned to the following comparisons and verifications: comparison of the physical connection relationship between the chip and the packaging substrate and the corresponding design connection relationship (item 2.1), comparison of the physical information of the packaging substrate and the corresponding design information of the packaging substrate (item 2.2), comparison of the physical information of the chip and the corresponding first design information of the chip (item 2.3), verification of the first design information of the chip and the corresponding second design information (item 2.4), verification of the second design information of the chip and the corresponding third design information, and / or verification of the second design information of the chip and the corresponding fourth design information (item 2.5), and verification of the third design information of the chip and the corresponding fourth design information (item 2.6).

[0428] For each of the required comparisons and / or verifications, when the comparisons and / or verifications are actually performed and passed, the chip obtains a score corresponding to the comparison and / or verification; when the comparisons and / or verifications are actually performed and failed or not actually performed, the chip does not obtain a score corresponding to the comparison and / or verification;

[0429] Based on the results of various comparisons and / or verifications actually carried out, invalid scores are sorted out from the scores corresponding to the various comparisons and / or verifications obtained by the chip;

[0430] Among the scores corresponding to various comparisons and verifications obtained by the chip, invalid scores are removed, and the remaining scores are valid scores, the valid scores are summed, and the summed result is used as the final score of the chip;

[0431] The autonomy and / or controllability of the chip is determined based on the final score of the chip.

[0432] Scenario Example 3:

[0433] For a certain model of a hybrid analog-digital chip that packages a bare die, an embodiment (two methods) is provided for determining the autonomy and / or controllability of the chip according to a process including but not limited to one or more of the following methods:

[0434] Method 1:

[0435] Consider a hybrid analog-digital chip as a chip composed of analog chip modules, digital chip modules, and other chip modules:

[0436] For the analog chip modules and digital chip modules in the chip, corresponding weights are assigned according to the difficulty and / or criticality of each chip module. The chip score is the weighted sum of the scores of each chip module. The chip's autonomy and / or controllability is determined based on the weighted sum.

[0437] The allocation of corresponding weights needs to ensure that when a chip with a given function is composed of one or more chip modules under different schemes, the scores corresponding to the same degree of autonomy and / or controllability are the same; the implementation method of ensuring that the scores corresponding to the same degree of autonomy and / or controllability are the same includes but is not limited to one or more of the following: weight allocation normalization, under different schemes, the sum of the weights of the chip modules of the given function is the same, when it is determined that the autonomy and / or controllability of each chip module is the highest, the scores of the chip modules are the same, and the full scores of the chip modules are the same: for example, in this embodiment, the sum of the weights of the analog chip module and the digital chip module is set to 1, and the full score of each chip module is set to 100;

[0438] For the analog chip module and the digital chip module in the analog-digital hybrid chip, the physical information and design information of the analog-digital hybrid chip are split into the analog chip module and the digital chip module according to the relationship between the module and the chip, so that the physical information of the analog chip module and the digital chip module does not overlap and / or repeat, and the sum of the physical information of each chip module is the physical information of the entire chip, so that the design information of the analog chip module and the digital chip module does not overlap and / or repeat, and the sum of the design information of each chip module is the design information of the entire chip, and the physical information and design information of each chip module maintain a corresponding relationship;

[0439] The score of the analog chip module is calculated with reference to Scenario Example 1 (the analog chip module is regarded as the chip in Scenario Example 1), and the score of the digital chip module is calculated with reference to Scenario Example 2 (the digital chip module is regarded as the chip in Scenario Example 2). The score of the chip is the weighted sum of the scores of each chip module, and the autonomy and / or controllability of the chip is determined based on the weighted sum. It should be noted that the connection relationship (including the physical connection relationship and the design connection relationship) in Scenario Example 1 and Scenario Example 2 only includes the physical connection relationship between the chip (chip module) and the packaging substrate. When this embodiment calculates the score of the analog chip module with reference to Scenario Example 1 (the analog chip module is regarded as the chip in Scenario Example 1) and calculates the score of the digital chip module with reference to Scenario Example 2 (the digital chip module is regarded as the chip in Scenario Example 2), the connection relationship should supplement the connection relationship between the analog chip module and the digital chip module, and reasonably split it into the analog chip module and the digital chip module, and then operate according to the methods in Scenario Example 1 and Scenario Example 2.

[0440] Method 2:

[0441] 1. Determine the physical and design information of the chip:

[0442] 1.1, Determine the physical connection relationship between the chip and the package substrate (a type of physical information):

[0443] Determine the physical connection relationship between the chip (including the internal bare die) and the package substrate. In this embodiment, it is determined to be the physical diagram describing the connection relationship - Figure A;

[0444] Here, it is assumed that all physical connections are concentrated in one layer, and the physical diagram of that layer represents the entire physical connection relationship. If the physical connection relationship has multiple layers, the connection relationship of all layers, some layers, or one layer can be recorded according to the actual situation to obtain a physical diagram describing the connection relationship.

[0445] 1.2, determine the physical information of the package substrate (a type of physical information):

[0446] Determine the physical information of the package substrate. In this embodiment, it is determined to be the physical package substrate and recorded as the physical package substrate images - images Bi and Bj (i and j are selected layer numbers);

[0447] Determine the physical object of the package substrate as the physical information of the package substrate. If the package substrate circuit has multiple layers, randomly select layer i and layer j (or other methods such as selection according to rules or settings), and record them as images using a combination of microscopy and photography to obtain images Bi and Bj.

[0448] This assumes that the package substrate circuitry has multiple layers, and that some layers (here, two layers, but three, four, or other numbers are also possible) are selected as physical information and recorded as images. For multi-layer package substrate circuitry, all layers can be selected as physical information and recorded as images, or a single layer can be selected as physical information and recorded as images. For package substrate circuitry with only one layer, the image of that layer can be directly recorded.

[0449] 1.3, Determine the physical information of the chip (a type of physical information):

[0450] Determine the physical information of the chip. In this embodiment, it is determined to be the physical layout of the chip, and recorded as the physical layout of the chip - Figure Cp, Figure Cq (p, q are selected layer numbers);

[0451] Determine the physical layout of the chip as the physical information of the chip. If the chip layout has multiple layers, set (or select randomly, according to a rule, or other methods) the p layer and the q layer as the physical information, and record them as images by combining microscopy and photography to obtain graphs Cp and Cq;

[0452] Here, we assume that the chip layout has multiple layers, and we select some layers (here, two layers, but it could be three, four, or any other number of layers) as physical information and record the image. If the chip layout has multiple layers, we can select all layers as physical information and record the image, or select one layer as physical information and record the image. If the chip layout has only one layer, we can directly record the image of that layer.

[0453] 1.4, Determine the design connection relationship between the chip and the package substrate (a type of design information):

[0454] Confirm the design connection relationship between the chip (including the internal bare die) and the package substrate. In this embodiment, it is determined to be the design diagram describing the connection relationship - Figure a;

[0455] The selection of layer numbers in the design drawing describing the connection relationship corresponds to the physical drawing describing the connection relationship.

[0456] 1.5, Determine the design information of the package substrate (a type of design information):

[0457] Determine the design information of the package substrate. In this embodiment, the design information is determined to be the package substrate design circuit diagrams - Figure bi and Figure bj (i and j are selected layer numbers);

[0458] The selection of layer numbers in the package substrate design circuit diagram corresponds to the actual diagram of the package substrate.

[0459] 1.6, determine the first design information of the chip (a type of design information):

[0460] Determine the first design information of the chip. In this embodiment, the first design information is determined to be the design layout of the chip - Figure c (the entire design layout of the chip), Figure cp, and Figure cq (where p and q are selected layer numbers);

[0461] Figure c is the entire design layout of the chip, that is, the layout of the entire area of ​​all layers, which is convenient for subsequent verification with the second design information. It is the first design information used for verification; Figure cp and Figure cq are the layouts of the p layer and q layer in the chip design layout, that is, the partial layout of Figure c. The selection of layer numbers corresponds to the physical layout of the chip, which is convenient for subsequent comparison with the physical layout of the chip. It is the first design information used for comparison.

[0462] 1.7, Determine the second design information of the chip (a type of design information):

[0463] Determine the second design information of the chip. In this embodiment, the second design information is determined to be the chip transistor-level netlist (such as the CDL netlist) and the gate-level netlist of the digital chip module in the chip to complete the final design (this embodiment uses this as an example, but it can also be other content such as the gate-level netlist corresponding to the first design information).

[0464] The chip transistor-level netlist (such as a CDL netlist) is used to verify with the first design information of the chip, and the gate-level netlist of the final design of the digital chip module is used to verify with the third design information and / or with the fourth design information;

[0465] Confirm the accuracy of the obtained design information before verification, including but not limited to: completing the final design gate-level netlist for the digital chip module, converting the format into the chip transistor-level netlist format, and comparing the content therein with the content of the digital chip module in the chip transistor-level netlist for similarity. The two should be identical and / or consistent and / or the similarity is greater than or equal to a preset threshold.

[0466] (Or: determining second design information of the chip, determining the second design information to be a chip transistor-level netlist, a gate-level netlist of a final design of a digital chip module in the chip, and a schematic diagram of an analog chip module in the chip;

[0467] At this time, the chip transistor-level netlist and the schematic diagram of the analog chip module in the chip are used to verify with the first design information of the chip (the two can be verified with the first design information separately, and the combined results of the two are used as the result of verification of the first design information and the second design information; when the schematic diagram of the analog chip module is verified, the layout side input can use Figure c as the LVS input, set the analog chip module as the top-level design and / or top-level unit and / or top-level logic and / or top-level module, or add the analog chip module layout to the first design information as the first design information, as the layout side input, and at this time, the first design information should be supplemented with the confirmation of the accuracy of this design information), and the gate-level netlist of the final design of the digital chip module is used for verification with the third design information and / or the fourth design information;

[0468] Confirm the accuracy of the acquired design information before verification, including but not limited to: for the digital chip module, complete the final design of the gate-level netlist, convert the format into the chip transistor-level netlist format, and compare the content therein with the content of the digital chip module in the chip transistor-level netlist for similarity. The two should be the same and / or remain consistent and / or have a similarity greater than or equal to a preset threshold; for the schematic diagram of the analog chip module, convert the format into the chip transistor-level netlist format, and compare the content therein with the content of the analog chip module in the chip transistor-level netlist for similarity. The two should be the same and / or remain consistent and / or have a similarity greater than or equal to a preset threshold;

[0469] Other modules can also be independently verified by referring to the analog chip module, and then the accuracy of the design information is confirmed and connected with other design information. This will not be repeated here.)

[0470] 1.8, Determine the third design information of the chip (a type of design information):

[0471] The third design information of the chip is determined. In this embodiment, the third design information is determined to be a gate-level netlist formed by synthesizing the RTL code of the digital chip module in the chip.

[0472] 1.9, determine the fourth design information of the chip (a type of design information):

[0473] The fourth design information of the chip is determined. In this embodiment, the fourth design information is determined to be the RTL code of the digital chip module in the chip.

[0474] 2. Compare the physical information with the design information and verify the design information:

[0475] 2.1. Compare the physical connection between the chip and the package substrate with the corresponding design connection to check whether they are consistent (a type of comparison):

[0476] Compare the connection relationship between the pins in Figure A with the connection relationship between the pins in Figure a to see if they are consistent.

[0477] 2.2. Compare the physical information of the package substrate with the design information of the corresponding package substrate to check whether the two are consistent (a type of comparison):

[0478] Compare Figure Bi with Figure bi, and Figure Bj with Figure bj, to check whether the geometric shapes, geometric shape features, etc. of the lines in the figures are consistent.

[0479] 2.3. Compare the physical information of the chip with the first design information of the corresponding chip to check whether the two are consistent (a type of comparison):

[0480] Compare Figure Cp with Figure cp, and compare Figure Cq with Figure cq, and check whether the geometric shapes, geometric shape features, etc. of the layouts in the figures are consistent.

[0481] 2.4. Verify the first design information of the chip and the corresponding second design information (a type of verification). The verification method includes but is not limited to LVS inspection or verification:

[0482] Perform LVS verification on the chip design layout (Figure C) and the chip transistor-level netlist (such as the CDL netlist).

[0483] 2.5. Verify the second chip design information with the corresponding third design information, and / or verify the second chip design information with the corresponding fourth design information (a type of verification). Verification methods include but are not limited to formal verification:

[0484] In this embodiment, the gate-level netlist of the final design of the digital chip module in the chip and the gate-level netlist formed by integrating the RTL code of the digital chip module in the chip are formally verified, and / or the gate-level netlist of the final design of the digital chip module in the chip and the RTL code of the digital chip module in the chip are formally verified.

[0485] 2.6. Verify the third design information of the chip with the corresponding fourth design information (a type of verification). The verification method includes but is not limited to formal verification:

[0486] In this embodiment, a gate-level netlist synthesized from the RTL code of the digital chip module in the chip is formally verified with the RTL code of the digital chip module in the chip.

[0487] 3. Based on the comparison and verification results, determine the chip's autonomy and / or controllability:

[0488] Based on the comparison and verification results, the chip's autonomy and / or controllability is determined, including but not limited to one or more of the following:

[0489] Based on the characteristics of the chip, the types of comparison and / or verification required to determine the degree of autonomy and / or controllability of the chip are determined: in this embodiment, the types of comparison required are determined to be: comparison of the physical connection relationship between the chip and the packaging substrate and the corresponding design connection relationship (item 2.1), comparison of the physical information of the packaging substrate with the corresponding design information of the packaging substrate (item 2.2), and comparison of the physical information of the chip with the corresponding first design information of the chip (item 2.3); the types of verification required are determined to be: verification of the first design information of the chip with the corresponding second design information (item 2.4), verification of the second design information of the chip with the corresponding third design information, and / or verification of the second design information of the chip with the corresponding fourth design information (item 2.5), and verification of the third design information of the chip with the corresponding fourth design information (item 2.6);

[0490] For the required comparison types and / or verification types, scores are assigned to the required comparisons and / or verifications based on the difficulty and / or criticality of the links represented by the various types. In this embodiment, scores are assigned to the following comparisons and verifications: comparison of the physical connection relationship between the chip and the packaging substrate and the corresponding design connection relationship (item 2.1), comparison of the physical information of the packaging substrate and the corresponding design information of the packaging substrate (item 2.2), comparison of the physical information of the chip and the corresponding first design information of the chip (item 2.3), verification of the first design information of the chip and the corresponding second design information (item 2.4), verification of the second design information of the chip and the corresponding third design information, and / or verification of the second design information of the chip and the corresponding fourth design information (item 2.5), and verification of the third design information of the chip and the corresponding fourth design information (item 2.6).

[0491] For each of the required comparisons and / or verifications, when the comparisons and / or verifications are actually performed and passed, the chip obtains a score corresponding to the comparison and / or verification; when the comparisons and / or verifications are actually performed and failed or not actually performed, the chip does not obtain a score corresponding to the comparison and / or verification;

[0492] Based on the results of various comparisons and / or verifications actually carried out, invalid scores are sorted out from the scores corresponding to the various comparisons and / or verifications obtained by the chip;

[0493] Among the scores corresponding to various comparisons and verifications obtained by the chip, invalid scores are removed, and the remaining scores are valid scores, the valid scores are summed, and the summed result is used as the final score of the chip;

[0494] The autonomy and / or controllability of the chip is determined based on the final score of the chip.

[0495] Scenario Example 4:

[0496] For a chip of a certain model that encapsulates n bare dies (respectively referred to as bare die 1, bare die 2... bare die n), each bare die is regarded as a chip module, and then the chip of this model can be regarded as consisting of n chip modules (respectively referred to as chip module 1, chip module 2... chip module n).

[0497] To determine the autonomy and / or controllability of a chip of this model, one or more chips of this model are randomly or regularly selected from one or more batches of chip products of this model (if a single chip can obtain all its physical information, then one chip is selected; if obtaining physical information requires destructive operations, rendering a single chip insufficient to obtain all physical information, then multiple chips are selected). The autonomy and / or controllability of chip module 1, chip module 2, ..., chip module n in each chip are determined separately according to the following process. The autonomy and / or controllability of the chip is determined based on this:

[0498] For a chip composed of one or more chip modules, the determination of the chip's degree of autonomy and / or controllability includes, but is not limited to, one or more of the following (in this embodiment, for a chip composed of chip module 1, chip module 2, ..., chip module n, the determination of the chip's degree of autonomy and / or controllability includes, but is not limited to, one or more of the following):

[0499] For each chip module in the chip (in this embodiment, chip module 1, chip module 2, ..., chip module n), a corresponding weight is assigned according to the difficulty and / or criticality of each chip module. The chip score is the weighted sum of the scores of each chip module. The chip's autonomy and / or controllability is determined based on the weighted sum.

[0500] Among them, the calculation of the score of each chip module can be carried out according to the category of the chip module with reference to scenario embodiment 1 (the chip module is regarded as the chip in scenario embodiment 1) and / or scenario embodiment 2 (the chip module is regarded as the chip in scenario embodiment 2) and / or scenario embodiment 3 (the chip module is regarded as the chip in scenario embodiment 3) and / or the present invention.

[0501] Among them, it needs to be supplemented that the connection relationship (including physical connection relationship and design connection relationship) of Scenario Example 1, Scenario Example 2, and Scenario Example 3 is only the physical connection relationship between the chip (equivalent to the chip module in this embodiment) and the packaging substrate. When this embodiment calculates the score of the chip module with reference to Scenario Example 1 and / or Scenario Example 2 and / or Scenario Example 3, the connection relationship needs to be supplemented as appropriate to the connection relationship between the chip modules (that is, the connection relationship between the chip module and other chip modules), and reasonably split into each chip module, and then operate according to the method in Scenario Example 1 and / or Scenario Example 2 and / or Scenario Example 3; the connection relationship needs to be supplemented as appropriate to the connection relationship between the chip modules, that is, when there is a connection between one or more chip modules and one or more other chip modules.

[0502] When assigning corresponding weights, it is necessary to ensure that when a chip with a given function is composed of one or more chip modules under different schemes, the scores corresponding to the same degree of autonomy and / or controllability are all the same; the implementation method of ensuring that the scores corresponding to the same degree of autonomy and / or controllability are all the same includes but is not limited to one or more of the following: weight allocation normalization (e.g., in this embodiment, the sum of the weights of chip module 1, chip module 2...chip module n is 1), the sum of the weights of the chip modules of the chip with the given function under different schemes is the same, when it is determined that the autonomy and / or controllability of each chip module is the highest, the scores of each chip module are the same, and the full score of each chip module is the same (e.g., in this embodiment, the full score of chip module 1, chip module 2...chip module n is 100);

[0503] For each chip module in the chip, when determining the physical information of each chip module, ensure that the physical information of each chip module does not overlap and / or repeat, and that the sum of the physical information of each chip module is the physical information of the entire chip; for each chip module in the chip, when determining the design information of each chip module, ensure that the design information of each chip module does not overlap and / or repeat, and that the sum of the design information of each chip module is the design information of the entire chip; the physical information and design information of each chip module maintain a corresponding relationship (for example, in this embodiment, when chip module 1, chip module 2...chip module n are placed on the same packaging substrate, the physical information and corresponding design information of the packaging substrate are divided according to their relationship with chip module 1, chip module 2...chip module n, ensuring that the physical information of the packaging substrate assigned to chip module 1, chip module 2...chip module n does not overlap, and that the sum of the physical information is exactly the total physical information of the packaging substrate, and ensuring that the design information of the packaging substrate assigned to chip module 1, chip module 2...chip module n does not overlap, and that the sum of the design information is exactly the total design information of the packaging substrate).

[0504] If some chip modules among chip module 1, chip module 2...chip module n are of the same model (e.g., chip module 1 and chip module 2 are of the same model), the chip modules of the same model may be uniformly regarded as a whole chip module for detection, and the scores and weights are uniformly calculated once and assigned (i.e., when assigning weights, chip module 1 and chip module 2 are no longer assigned weights separately, but are regarded as a whole and assigned a weight, and the weight and the weights of chip modules other than chip module 1 and chip module 2 continue to meet the normalization requirements when assigned); the processing method of uniformly treating the chip modules of the same model as a whole chip module for detection includes but is not limited to one or more of the following: determining the sum of the physical information of the chip modules of the same model as the physical information of the whole chip module for detection (e.g., the physical information of chip module 1 and chip module 2 is determined as the physical information of the whole chip module for detection); The sum of the design information of the chip modules of the same model is determined as the physical information of an entire chip module), the sum of the design information of the chip modules of the same model is determined as the design information of an entire chip module for detection (for example, the sum of the design information of chip module 1 and chip module 2 is determined as the design information of an entire chip module), and a score is calculated for an entire chip module for detection; from the chip modules of the same model, a chip module is randomly or according to a rule selected, and its score is used as the score of an entire chip module for detection (for example, the score of chip module 1 is used as the score of an entire chip module); for the chip modules of the same model, all or part of the chip modules are selected therefrom, the scores of the selected chip modules are calculated respectively, and the average value of the scores of the selected chip modules is used as the score of an entire chip module for detection.

[0505] Scenario Example 5:

[0506] Based on the results of the various comparisons and / or verifications carried out in the above comprehensive practice, invalid scores are sorted out from the scores corresponding to the various comparisons and / or verifications obtained by the chip or chip module, and the following examples are given to illustrate:

[0507] If, based on the characteristics of a chip or chip module, it is determined that in order to determine the degree of autonomy and / or controllability of the chip or chip module, the types of comparison and / or verification required are as follows: comparison of the physical connection relationship between the chip or chip module and the packaging substrate, and / or the physical connection relationship between the chip or chip module and other chips or chip modules, with the corresponding design connection relationship (comparison 1), comparison of the physical information of the packaging substrate with the design information of the corresponding packaging substrate (comparison 2), comparison of the physical information of the chip or chip module with the first design information of the corresponding chip or chip module (comparison 3), verification of the first design information of the chip or chip module with the corresponding second design information (verification 1), verification of the second design information of the chip or chip module with the corresponding third design information, and / or verification of the second design information of the chip or chip module with the corresponding fourth design information (verification 2), and verification of the third design information of the chip or chip module with the corresponding fourth design information (verification 3);

[0508] Invalid scores are sorted out, including but not limited to one or more of the following:

[0509] If comparison 3 fails, the chip module will obtain invalid scores for each required verification when it is actually carried out and passed. In this embodiment, the scores obtained for verification 1, verification 2, and verification 3 when they are actually carried out and passed will all be invalid scores.

[0510] When Verification 1 fails, the corresponding score obtained when the verification of the second design information of the chip or chip module and the corresponding third design information in Verification 2 is actually carried out and passed is an invalid score;

[0511] When Verification 1 fails, the corresponding scores obtained when the verification of the second design information of the chip or chip module and the corresponding fourth design information in Verification 2 is actually carried out and passed are invalid scores;

[0512] If Verification 1 fails, the corresponding score obtained when Verification 3 is actually carried out and passed will be invalid;

[0513] When the second design information of the chip or chip module and the corresponding third design information in Verification 2 fail to be verified, and the second design information of the chip or chip module and the corresponding fourth design information in Verification 2 fail to be verified, the corresponding scores obtained when Verification 3 is actually carried out and passed are invalid scores.

[0514] Scenario Example 6:

[0515] The following examples illustrate the method of obtaining the physical information (some methods of obtaining the physical information have been explained in the manual and will not be repeated here):

[0516] Some examples of obtaining the physical connection relationship between a chip or chip module and a packaging substrate, and / or the physical connection relationship between a chip or chip module and other chips or chip modules:

[0517] For the case where a chip or chip module is connected to a packaging substrate by wire bonding, and / or a chip or chip module is connected to other chips or chip modules, and the connection relationship established by the wire bonding is not blocked, the physical connection relationship can be obtained by combining a microscope (and / or a microscopic imaging instrument and / or CT and / or X-ray and / or X-ray and / or radiation and / or ultrasound and / or non-destructive testing, etc.) with photography; for the case where a chip or chip module is connected to a packaging substrate by flip-chip bonding, and / or a chip or chip module is connected to other chips or chip modules, and the connection relationship established by flip-chip bonding is blocked by the chip and / or chip module and / or packaging substrate, etc., the physical connection relationship can be obtained by combining a microscope (and / or a microscopic imaging instrument and / or CT and / or X-ray and / or X-ray and / or radiation and / or ultrasound and / or non-destructive testing, etc.) with photography; The physical connection relationship is obtained by flat grinding (and / or delamination and / or grinding and / or lapping and / or polishing and / or corrosion and / or etching and / or sectioning and / or dissection and / or staining, etc.), or the flip-chip interface (which represents the physical connection relationship) is exposed by flat grinding (and / or delamination and / or grinding and / or lapping and / or polishing and / or corrosion and / or etching and / or sectioning and / or dissection and / or staining, etc.), and then the physical connection relationship is obtained by microscopy and other methods combined with photography. Flat grinding and other methods can start from the chip and / or chip module side or from the packaging substrate side. In this way, the chip and / or chip module and / or packaging substrate will be damaged. If other physical information is required, one or more other chips and / or chip modules need to be selected for acquisition (this is also one of the situations in which one or more chips or chip modules to be tested are obtained and physical information is obtained);

[0518] Some examples of separating a chip or chip module from a packaging substrate, and / or separating a chip or chip module from other chips or chip modules: If multiple chip modules are on the same packaging substrate and other chip modules affect the acquisition of physical information of the chip module, the chip module may be separated from the packaging substrate first, including but not limited to one or more of the following: disconnecting or removing or removing connecting wires, corroding, etching, heating, delaminating, flat grinding, grinding, lapping, polishing, slicing, dissecting, or removing the chip;

[0519] Some examples of obtaining physical information of one or more layers: For the physical connection relationship and / or the physical information of the packaging substrate and / or the physical information of the chip or chip module, if the selected layer number corresponds to the surface layer and the information is not blocked, the physical information can be directly obtained, and / or recorded as an image by combining microscopy and photography; if the selected layer number corresponds to the middle layer, or the information is blocked, the layer can be exposed by delamination (and / or flat grinding and / or grinding and / or polishing and / or corrosion and / or etching and / or sectioning and / or dissection and / or staining and / or disconnection or removal or removal of connecting lines, etc.), and then the physical information can be directly obtained, and / or recorded as an image by combining microscopy and photography.

[0520] Scenario Example 7:

[0521] The comparison methods include, but are not limited to, one or more of the following: automatic comparison by a detection device, manual comparison, as illustrated below:

[0522] When the comparison method is automatic comparison by a detection device, it is necessary to determine whether the format of the physical information is a format that can be recognized and / or used by the detection device; when the format of the physical information is not a format that can be recognized and / or used by the detection device, it is necessary to adjust the format of the physical information to a format that can be recognized and / or used by the detection device; the method of adjusting the format of the physical information to a format that can be recognized and / or used by the detection device includes but is not limited to one or more of the following: recording the physical information as a physical image, converting the physical connection relationship into a table that describes the physical connection relationship;

[0523] When the comparison method is automatic comparison by a detection device, it is necessary to determine whether the format of the design information is a format that can be recognized and / or used by the detection device; when the format of the design information is not a format that can be recognized and / or used by the detection device, it is necessary to adjust the format of the design information to a format that can be recognized and / or used by the detection device; the method of adjusting the format of the design information to a format that can be recognized and / or used by the detection device includes but is not limited to one or more of the following: converting the design information into a design image, converting the design connection relationship into a table that describes the design connection relationship; the design image includes but is not limited to an image in which the design information is saved or / and converted or / and recorded as an image format;

[0524] Regarding the method of adjusting the format of the design information to a format that can be recognized and / or used by the detection device, the following examples are given: when the physical connection relationship and / or the physical information of the packaging substrate and / or the physical information of the chip or chip module are recorded as physical images, and the format of the design connection relationship and / or the design information of the packaging substrate and / or the first design information of the chip or chip module is a vector graphics format or other format that the detection device cannot use for image comparison, the format of the design information is converted from a vector graphics format or other format into an image format (the design information is converted into a design image), and the detection device compares the two images, the physical image and the design image; for the physical connection relationship and the design connection relationship, there is another way, which is to convert their respective connection relationships into tables, and then the detection device compares the two tables (the table describing the physical connection relationship and the table describing the design connection relationship).

[0525] The method of determining whether the format of the physical information and / or the design information is a format that can be recognized and / or used by the detection device includes but is not limited to one or more of the following: automatic determination by the detection device, manual determination;

[0526] The method of adjusting the format of the physical information and / or the design information to a format that can be recognized and / or used by the detection device includes but is not limited to one or more of the following: automatic adjustment by the detection device and manual adjustment.

[0527] Scenario Example 8:

[0528] For comparing the physical image of the chip or chip module with the design image (it may also be a comparison of image plates or a comparison of other physical information with the design information, which will not be described in detail in this embodiment), the comparison method adopts a combination of overall comparison and sampling comparison (it may also be a combination of these methods, which will not be described in detail in this embodiment), as illustrated below:

[0529] During the overall comparison, this embodiment performs a rough overall comparison, focusing on whether the area, outline, module structure, etc. of the chip or chip module are consistent in the two images;

[0530] During sampling comparison, for image comparison, an area available for comparison is calculated and / or set; based on the area available for comparison, a number of sampling blocks are selected from the image, and the sum of the areas of the sampling blocks must not exceed the area available for comparison; when selecting the sampling blocks, the sampling blocks in the two images maintain a corresponding relationship; the sampling block selection methods include but are not limited to one or more of the following: random sampling, sampling according to a rule, allocating the number of sampling blocks proportional to the density and / or complexity of the image, allocating the area of ​​the sampling blocks proportional to the density and / or complexity of the image, and setting; comparing the corresponding sampling blocks in the two images; and analyzing the results of the sampling comparison by comprehensively analyzing the comparison results of each sampling block;

[0531] One method for calculating the area available for comparison is: based on the time required to complete the comparison per unit area and the expected completion time of this comparison, the area available for comparison is calculated as follows: Area available for comparison = unit area * expected completion time of this comparison / time required to complete the comparison per unit area;

[0532] Analyze the results of this image comparison by combining the results of overall comparison and sampling comparison;

[0533] During the overall rough comparison and / or after selecting the sampling block, the resolution and / or pixel count of the physical image and / or design image to be compared may be adjusted, and the physical image and design image may be compared based on the adjustment results;

[0534] During the overall rough comparison and / or sampling comparison, the comparison implementation algorithm is adjusted according to one or more of the following situations, including but not limited to: different comparison purposes, different comparison contents, different comparison methods, different comparison modes, and different working stages in the comparison.

[0535] Scenario Example 9:

[0536] For comparing the physical object information or physical object image with the design information or design image (and / or comparing the physical object information plate or physical image plate with the design information plate or design image plate, which will not be described in detail in this embodiment), when the comparison method is automatic comparison by a detection device, the resolution and / or number of pixels of the physical object image and / or design image are adjusted according to the resolution of the physical object image and / or design image and / or the number of pixels of the physical object image and / or design image at the planned granularity of the comparison, as well as the comparison capability of the detection device. Based on the adjustment result, the physical image and the design image are compared, as illustrated below:

[0537] The comparison capability of the detection device includes but is not limited to: the minimum resolution required by the detection device for the physical image and / or the design image to complete the comparison at the granularity, and / or the minimum number of pixels required to be included in the granularity;

[0538] The adjustment method includes but is not limited to: with respect to the granularity of the planned comparison, reducing the resolution and / or the number of pixels of the physical image and / or the design image while ensuring the accuracy of the comparison, so that the resolution of the physical image and / or the design image is reduced, and / or the number of pixels included in the granularity in the physical image and / or the design image is reduced, and is greater than or equal to the comparison capability of the detection device;

[0539] For example, during a rough overall comparison, the granularity of this planned rough comparison is determined to be 0.1 mm (for example). In this embodiment, the resolutions of the physical image and the design image to be compared are expressed in units of pixels contained in an inch, both of which are 20 million per inch (for example). The comparison capability of the detection device is: at a granularity of 0.1 mm, the minimum resolution required for the physical image and the design image is 10,000 per inch (for example). Then, one adjustment method is to reduce the resolutions of the physical image and the design image so that the resolutions of the physical image and the design image are reduced (i.e., less than 20 million per inch) and greater than or equal to the comparison capability of the detection device (i.e., greater than or equal to 10,000 per inch). The adjusted physical image and the design image are then compared.

[0540] Scenario Example 10:

[0541] The following example illustrates the method for confirming the accuracy of the obtained design information:

[0542] One of the purposes of confirming the accuracy of the acquired design information is to confirm that the content and format of the acquired design information meet the requirements, confirm that the acquired design information is indeed the design information of the chip, and that the design information is connected. Some of the methods are given as examples:

[0543] For the second design information obtained for verification with the first design information, the second design information obtained for verification with the third design information, and the second design information obtained for verification with the fourth design information, for any and / or set one or more combinations of two of the three, and / or between the three, confirm that the design information of the overlapping parts and / or repeated parts is the same and / or remains consistent; the method for confirming that the design information of the overlapping parts and / or repeated parts is the same and / or remains consistent, includes but is not limited to one or more of the following: unifying the design information format; performing image comparison on the overlapping parts and / or repeated parts; performing graphic comparison on the overlapping parts and / or repeated parts; performing similarity comparison on the overlapping parts and / or repeated parts; determining that the similarity is greater than or equal to the thirtieth preset threshold; determining that the obtained Among the second design information used for verification with the first design information, the second design information obtained for verification with the third design information, and the second design information obtained for verification with the fourth design information, all or part of one or more of the information is obtained by extracting all or part of the information from another one or more of the information, and / or all or part of the information is obtained by extracting all or part of the information from another one or more of the information after format conversion. Application scenarios of the method for confirming that the design information of the overlapping and / or repeated parts is the same and / or consistent include, but are not limited to: for an analog-digital hybrid chip, confirming that the gate-level netlist of the digital chip module therein, after the format is converted into a transistor-level netlist, its content is the same as or consistent with the digital chip module part in the chip transistor-level netlist;

[0544] For example: if verification is used during verification, verification of the first design information and the second design information, verification of the second design information and the third design information, and verification of the second design information and the fourth design information are used, then any two of the second design information used for verification with the first design information (referred to as information 1 in this embodiment), the second design information used for verification with the third design information (referred to as information 2 in this embodiment), and the second design information used for verification with the fourth design information (referred to as information 3 in this embodiment) are the same or different design information, that is, information 1 and information 2 are the same or different design information, information 1 and information 3 are the same or different design information, and information 2 and information 3 are the same or different design information; any two of the second design information format used for verification with the first design information, the second design information format used for verification with the third design information, and the second design information format used for verification with the fourth design information are the same or different formats, that is, information 1 and information 2 are the same or different formats, information 1 and information 3 are the same or different formats, and information 2 and information 3 are the same or different formats.

[0545] Confirm the accuracy of the obtained design information. For the obtained information 1, information 2, and information 3, and for any and / or set one or more combinations of the three, confirm that the overlapping and / or repeated design information is the same and / or remains consistent (if the obtained information 1, information 2, and information 3 are indeed the design information of the chip, then information 1, information 2, and information 3 are all or part of the second design information, which should meet this requirement); that is, one or more of the following: the overlapping and / or repeated design information in the obtained information 1 and information 2 is the same and / or remains consistent; the overlapping and / or repeated design information in the obtained information 1 and information 3 is the same and / or remains consistent; the overlapping parts in the obtained information 2 and information 3 are the same and / or remain consistent. and / or the repeated part design information is the same and / or remains consistent; the overlapping part and / or repeated part design information in the obtained information 1, information 2, and information 3 is the same and / or remains consistent; explanation of the overlapping part: if the obtained information 1 is composed of three parts of information A and B, and the obtained information 2 is composed of information B, then the overlapping part and / or repeated part is the B information at this time, and it is confirmed that the overlapping part and / or repeated part design information in the obtained information 1 and information 2 are the same and / or remain consistent, that is: confirm that the B information in the obtained information 1 is the same as the B information in the obtained information 2 and / or remains consistent (that is, since the obtained information 1 and the obtained information 2 both belong to the second design information, the overlapping part and / or repeated part B information therein should be the same and / or remain consistent).

[0546] Methods for confirming that the design information of the overlapping parts and / or repeated parts are the same and / or remain consistent include, but are not limited to, one or more of the following: unifying the format of the design information; performing image comparison on the overlapping parts and / or repeated parts; performing graphic comparison on the overlapping parts and / or repeated parts; performing similarity comparison on the overlapping parts and / or repeated parts; determining that the similarity is greater than or equal to a thirtieth preset threshold; determining that all or part of one or more of the second design information obtained for verification with the first design information, the second design information obtained for verification with the third design information, and the second design information obtained for verification with the fourth design information is obtained by extracting all or part of the information from another one or more information, and / or all or part of the information of one or more of the information is obtained by converting the format of another one or more information and extracting all or part of the information therefrom; to confirm that the information 1, information Examples of the overlapping and / or repeated design information in 2 being the same and / or consistent include, but are not limited to, one or more of the following: if the formats of the obtained information 1 and the obtained information 2 are different (such as one is a transistor-level netlist and the other is a gate-level netlist), unifying the design information formats (such as unifying them into transistor-level netlists); performing image comparison on the overlapping and / or repeated parts; performing graphic comparison on the overlapping and / or repeated parts; performing similarity comparison on the overlapping and / or repeated parts (such as performing a similarity comparison on the information B in the obtained information 1 and the information B in the obtained information 2); determining that the similarity is greater than or equal to a preset threshold (referred to as threshold 1 in this embodiment, for example, threshold 1 is set to a value such as 95%, 100%, etc.); confirming that the information B in the obtained information 1 is obtained by converting the format of the obtained information 2 (such as converting it from a gate-level netlist to a transistor-level netlist) and extracting all information therefrom - that is, information B.

[0547] Similarly, for confirming that the design information of the overlapping parts and / or repeated parts in the obtained information 1 and information 3 is the same and / or remains consistent, the design information of the overlapping parts and / or repeated parts in the obtained information 2 and information 3 is the same and / or remains consistent, the method for confirming that the design information of the overlapping parts and / or repeated parts in the obtained information 1, information 2, and information 3 is the same and / or remains consistent is similar to the above-mentioned example method for confirming that the design information of the overlapping parts and / or repeated parts in the obtained information 1 and information 2 is the same and / or remains consistent, and the preset thresholds set for the similarity are assumed to be named threshold 2, threshold 3, and threshold 4 respectively, then any two of threshold 1, threshold 2, threshold 3, and threshold 4 can be the same or different.

[0548] It should be noted that the above scenario embodiments are only part of the protection scope of the present invention and are not used to limit the protection scope of the present invention. Other embodiments will not be described in detail.

[0549] It can be seen that this embodiment provides a simple and objective detection basis for the evaluation of chips or chip modules, improves the objectivity, practicality and comprehensiveness of the evaluation of the autonomy and / or controllability of chips or chip modules, and can serve as a supporting basis for the authenticity of the evidence materials collected for the evaluation of the autonomy and / or controllability of chips or chip modules, and can serve as a strong support for the evaluation of the autonomy and / or controllability of chips or chip modules.

[0550] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention.

Claims

1. A method for detecting a chip or a chip module, characterized in that: The method includes: Determining physical information of the chip or chip module and design information of the chip or chip module; The physical information includes but is not limited to one or more of the following: The physical connection relationship between the chip or chip module and the packaging substrate, and / or the physical connection relationship between the chip or chip module and other chips or chip modules; Physical information of the package substrate, including but not limited to one or more of the following: the physical package substrate, the physical circuit or circuit diagram of the package substrate, the physical layout or layout diagram of the package substrate, the physical wiring or wiring diagram of the package substrate, and the physical circuit or circuit diagram of the package substrate; Physical information of the chip or chip module, including but not limited to one or more of the following: the physical chip or chip module, the physical layout of the chip or chip module, the physical layout of the chip or chip module, the physical layout and wiring of the chip or chip module or the layout and wiring diagram, the physical circuit of the chip or chip module or the circuit diagram; The design information includes but is not limited to one or more of the following: The designed connection relationship between the chip or chip module and the packaging substrate, and / or the designed connection relationship between the chip or chip module and other chips or chip modules; Design information of the package substrate, including but not limited to one or more of the following: package substrate design circuits or circuit diagrams, package substrate design layouts or layout diagrams, package substrate design wiring or wiring diagrams, package substrate design circuits or circuit diagrams; First design information of the chip or chip module, the first design information including but not limited to one or more of the following: chip or chip module design layout, chip or chip module design layout, chip or chip module design layout and routing, or layout and routing diagram; Second design information of the chip or chip module, the second design information including but not limited to a schematic diagram and / or a netlist of the chip or chip module; Third design information of the chip or chip module, the third design information including but not limited to a gate-level netlist synthesized from register transfer level RTL code of the digital chip or digital chip module; Fourth design information of the chip or chip module, the fourth design information including but not limited to RTL code of the digital chip or digital chip module; Comparing the physical object information with the design information and verifying the design information; Based on the comparison and verification results, the design consistency of the chip or chip module is verified; The verification of the design information includes but is not limited to at least two of the following: Verifying the first design information of the chip or chip module with the corresponding second design information, wherein the verification method includes but is not limited to LVS inspection or verification; Verifying the second design information of the chip or chip module with the corresponding third design information, and / or verifying the second design information of the chip or chip module with the corresponding fourth design information, wherein the verification method includes but is not limited to formal verification; The third design information of the chip or chip module is verified with the corresponding fourth design information, and the verification method includes but is not limited to formal verification.

2. The method according to claim 1, characterized in that The chip includes but is not limited to one or more of the following: A chip that packages one or more dies; Unpackaged die.

3. The method according to claim 1, characterized in that The chip module includes but is not limited to one or more of the following: A die in a chip that packages one or more dies; Functional modules in a die.

4. The method according to claim 1, wherein The physical connection relationship includes but is not limited to one or more of the following expressions: physical connection relationship, physical diagram describing the connection relationship, table describing the physical connection relationship, physical pin names describing the physical connection relationship, and physical connection relationship expressed by name; and / or The physical information includes but is not limited to one or more of the following physical information: all layers, some layers, one layer, and the method for selecting the layer number includes but is not limited to one or more of the following: random selection, selection according to rules, and setting; for one of the layers, the physical information includes but is not limited to one or more of the following physical information: the entire area, multiple local areas, one local area, and the method for selecting the area includes but is not limited to one or more of the following: random selection, selection according to rules, and setting.

5. The method according to claim 1 or 4, characterized in that The methods for obtaining the physical object information include, but are not limited to, one or more of the following: Directly obtain one or more chips or chip modules to be tested and obtain physical information; Randomly or according to rules, select one or more chips or chip modules to be tested and obtain physical information; Directly obtain physical information through one or more of the following methods, including but not limited to: computerized tomography (CT), X-rays, radiography, ultrasound, and non-destructive testing; Uncap the packaged chip and obtain physical information; In the case where the physical connection relationship between the chip or chip module and the packaging substrate, and / or the physical connection relationship between the chip or chip module and other chips or chip modules is obscured, the physical connection relationship is obtained through one or more of the following methods, including but not limited to: CT, X-ray, X-ray, radiation, ultrasound, non-destructive testing, delamination, flat grinding, grinding, lapping, polishing, corrosion, etching, sectioning, dissection, and staining; the case where the physical connection relationship is obscured includes but is not limited to the physical connection relationship being obscured in a flip-chip chip; Separating the chip or chip module from the packaging substrate, and / or separating the chip or chip module from other chips or chip modules, wherein the separation method includes but is not limited to one or more of the following: disconnecting or removing or removing connecting wires, corroding, etching, heating, delaminating, flat grinding, grinding, lapping, polishing, slicing, dissecting, and removing the chip; Obtaining one or more layers of physical information by one or more of the following methods, including but not limited to: directly obtaining, obtaining through a microscope and / or microscopic imaging instrument and / or CT and / or X-ray and / or X-ray and / or radiology and / or ultrasound and / or non-destructive testing, delamination, flat grinding, grinding, lapping, polishing, corroding, etching, sectioning, dissecting, staining, disconnecting or removing or removing connecting lines; Obtain and record the physical image, video or video corresponding to the physical object information through a microscope and / or microscopic imaging instrument and / or CT and / or X-ray and / or X-ray and / or radiation and / or ultrasound and / or non-destructive testing, in combination with photography and / or image acquisition and / or video recording, or directly through photography and / or image acquisition and / or video recording; the physical image, video or video is a single file, or multiple files, or a single file composed of multiple files; Obtain physical object information and corresponding physical object images and videos through microscopes and / or microscopic imaging instruments and / or CT and / or X-rays and / or X-rays and / or radiation and / or ultrasound and / or non-destructive testing, combined with naked eye observation, or directly through naked eye observation.

6. The method according to claim 5, characterized in that Obtain or select multiple chips or chip modules to be tested and obtain physical information, including but not limited to one or more of the following: To obtain multiple samples, perform statistical analysis on physical information, or / and comparison of physical information with design information, or / and the degree of autonomy and / or controllability of the chip or chip module, obtain or select multiple chips or chip modules of the same model, and obtain the same physical information from each chip or chip module; In cases where destructive operations are required to obtain physical information or / and only partial physical information can be obtained from a chip or chip module, obtain or select multiple chips or chip modules of the same model and obtain different physical information from each chip or chip module, or obtain the same and different physical information simultaneously; In order to determine the autonomy and / or controllability of a chip composed of multiple chip modules, the physical information of each of the multiple chip modules in the chip is obtained respectively, and the autonomy and / or controllability is determined, and the autonomy and / or controllability of the chip is determined based on the results.

7. The method according to claim 1, characterized in that The design connection relationship includes but is not limited to one or more of the following expression forms: a design drawing describing the connection relationship, a table describing the design connection relationship, a pin design name describing the design connection relationship, and a design connection relationship expressed by the name; the design information includes but is not limited to one or more of the following design information: all layers, part of the layers, one layer, and the layer number selection method includes but is not limited to one or more of the following: random selection, selection according to rules, and setting; for one layer, the design information includes but is not limited to one or more of the following design information: the entire area, multiple local areas, one local area, and the area selection method includes but is not limited to one or more of the following: random selection, selection according to rules, and setting; the format of the design connection relationship includes but is not limited to one or more formats; and / or The design information includes but is not limited to one or more of the following: all layers, some layers, or one layer. The layer number selection method includes but is not limited to one or more of the following: random selection, selection according to a rule, or setting. For one layer, the design information includes but is not limited to one or more of the following: the entire area, multiple local areas, or one local area. The area selection method includes but is not limited to one or more of the following: random selection, selection according to a rule, or setting. The format of the design information of the package substrate includes but is not limited to one or more formats. and / or The first design information includes, but is not limited to, one or more of the following design information: all layers, some layers, or one layer. The layer number selection method includes, but is not limited to, one or more of the following: random selection, selection according to a rule, or setting. For one layer, the first design information includes, but is not limited to, one or more of the following design information: the entire area, multiple local areas, or one local area. The area selection method includes, but is not limited to, one or more of the following: random selection, selection according to a rule, or setting. The first design information used for comparison is all or part of the design information in the first design information. The first design information used for verification is all or part of the design information in the first design information. The first design information used for comparison and the first design information used for verification are the same or different design information. The format of the first design information includes but is not limited to one or more formats; the format of the first design information used for comparison and the format of the first design information used for verification are the same or different formats; and / or The second design information includes but is not limited to a schematic diagram and / or a netlist of the chip or chip module, and the schematic diagram and / or netlist includes but is not limited to one or more of the following: a schematic diagram, a netlist corresponding to the schematic diagram, a transistor-level netlist, a gate-level netlist of a final design of a digital chip or digital chip module, and a gate-level netlist corresponding to the first design information of the digital chip or digital chip module; the second design information includes but is not limited to all or part of the design information; The second design information used for verification with the first design information is all or part of the design information in the second design information; The second design information used for verification with the third design information is all or part of the design information in the second design information; The second design information used for verification with the fourth design information is all or part of the design information in the second design information; Any two of the second design information used for verification with the first design information, the second design information used for verification with the third design information, and the second design information used for verification with the fourth design information are the same or different design information; The format of the second design information includes but is not limited to one or more formats; Any two of the second design information format used for verification with the first design information, the second design information format used for verification with the third design information, and the second design information format used for verification with the fourth design information are the same or different formats; and / or The third design information includes but is not limited to all or part of the design information; The third design information used for verification with the second design information is all or part of the design information in the third design information; The third design information used for verification with the fourth design information is all or part of the third design information; The third design information used for verification with the second design information and the third design information used for verification with the fourth design information are the same as or different from each other; The format of the third design information includes but is not limited to one or more formats; The third design information format used for verification with the second design information and the third design information format used for verification with the fourth design information are the same as or different from each other; and / or The fourth design information includes but is not limited to all or part of the design information; The fourth design information used for verification with the second design information is all or part of the design information in the fourth design information; The fourth design information used for verification with the third design information is all or part of the design information in the fourth design information; The fourth design information used for verification with the second design information and the fourth design information used for verification with the third design information are the same as or different from each other; The format of the fourth design information includes but is not limited to one or more formats; The fourth design information format used for verification with the second design information and the fourth design information format used for verification with the third design information may be the same as or different from each other.

8. The method according to claim 1, 4 or 7, characterized in that: The comparison of the physical information with the design information includes, but is not limited to, one or more of the following: Comparing the physical connection relationship between the chip or chip module and the packaging substrate, and / or the physical connection relationship between the chip or chip module and other chips or chip modules, with the corresponding designed connection relationship to check whether the two are consistent; Compare the physical information of the package substrate with the design information of the corresponding package substrate to check whether the two are consistent; Comparing the physical information of the chip or chip module with the first design information of the corresponding chip or chip module to check whether the two are consistent; The comparison includes but is not limited to one or more of the following comparisons: all layers, part of the layers, one layer, and the layer number selection method includes but is not limited to one or more of the following: random selection, selection according to rules, and setting; for one of the layers, the comparison includes but is not limited to one or more of the following comparisons: the entire area, multiple local areas, one local area, and the area selection method includes but is not limited to one or more of the following: random selection, selection according to rules, and setting.

9. The method according to claim 1, characterized in that Before comparing the physical object information with the design information, the method further includes: Confirm the accuracy of the acquired design information.

10. The method according to claim 1, characterized in that The comparison method includes but is not limited to one or more of the following: automatic comparison by a detection device, manual comparison; When the comparison method is automatic comparison by a detection device, it is necessary to determine whether the format of the physical information is a format that can be recognized and / or used by the detection device; when the format of the physical information is not a format that can be recognized and / or used by the detection device, it is necessary to adjust the format of the physical information to a format that can be recognized and / or used by the detection device; the method of adjusting the format of the physical information to a format that can be recognized and / or used by the detection device includes but is not limited to one or more of the following: recording the physical information as a physical image, converting the physical connection relationship into a table that describes the physical connection relationship; When the comparison method is automatic comparison by a detection device, it is necessary to determine whether the format of the design information is a format that can be recognized and / or used by the detection device; When the format of the design information is not a format that can be recognized and / or used by the detection device, it is necessary to adjust the format of the design information to a format that can be recognized and / or used by the detection device; the method of adjusting the format of the design information to a format that can be recognized and / or used by the detection device includes but is not limited to one or more of the following: converting the design information into a design image, converting the design connection relationship into a table describing the design connection relationship; the design image includes but is not limited to an image obtained by saving or / and converting or / and recording the design information into an image format; The method of determining whether the format of the physical information and / or the design information is a format that can be recognized and / or used by the detection device includes but is not limited to one or more of the following: automatic determination by the detection device, manual determination; The method of adjusting the format of the physical information and / or the design information to a format that can be recognized and / or used by the detection device includes but is not limited to one or more of the following: automatic adjustment by the detection device and manual adjustment.

11. The method according to claim 1, wherein When comparing the physical object information with the design information, the corresponding relationship between the physical object information and the design information includes but is not limited to one or more of the following: Correspondence between the same layers; Correspondence between the same areas; The correspondence between the same positions; The corresponding relationship of the same position ratio includes, but is not limited to, one or more of the following: if the ratio of the position in the physical object information and / or physical object image to the distance between each point in the entire physical object information and / or physical object image is the same as the ratio of the position in the design information and / or design image to the distance between each point in the entire design information and / or design image, then the position of the physical object information and / or physical object image and the position of the design information and / or design image are in a corresponding relationship; If the position of the physical object information and / or the physical object image and the position of the design information and / or the design image coincide with each other after the entire physical object information and / or the entire physical image and / or the entire design information and / or the entire design image are scaled proportionally, then the position of the physical object information and / or the physical object image and the position of the design information and / or the design image are in a corresponding relationship. The corresponding relationship between the same pin names.

12. The method according to claim 1, characterized in that When comparing the physical object information or physical object image with the design information or design image, the method further includes: splitting the physical object information or physical object image and the corresponding design information or design image into one or more sections, maintaining a corresponding relationship between the sections of the physical object information or physical image and the sections of the design information or design image, performing a comparison on each section separately, and analyzing the comparison results of each section based on the comparison results of each section; The situations in which the splitting into one or more sections may be performed include but are not limited to one or more of the following: the physical information or physical image, and the comparison content with the design information or design image, are concentrated in one or more local areas, and the physical information or physical image, and the comparison content with the design information or design image, are split into one or more sections according to the concentrated areas; the physical information or physical image, and the comparison content with the design information or design image, have large differences in graphic sizes in different areas, and the physical information or physical image, and the comparison content with the design information or design image, are split into one or more sections according to different graphic sizes or different size ranges; Among them, after splitting into sections, if some sections do not have the required comparison content, the comparison of this section may be omitted or not omitted. When the comparison of this section is omitted, this section will not be included in the analysis of the comparison results of the comprehensive comparison results of each section.

13. The method according to claim 1, wherein Comparing the physical object information or physical object image with the design information or design image, and / or comparing the physical object information plate or physical image plate with the design information plate or design image plate, wherein the comparison method includes but is not limited to one or more of the following: overall comparison, detailed comparison, and sampling comparison; The comparison contents include but are not limited to one or more of the following: connection relationship, geometric shape, geometric shape features; The degree of comparison fineness of the comparison is expressed using granularity, which is related to the comparison mode, method, content and purpose. The granularity includes but is not limited to the degree of accuracy of the comparison content. The minimum limit of the granularity includes but is not limited to one or more of the following: the minimum graphic in the corresponding information and / or image, the minimum size in the corresponding information and / or image, the minimum area in the corresponding information and / or image, the graphic set according to the corresponding information and / or image, the size set according to the corresponding information and / or image, and the area set according to the corresponding information and / or image.

14. The method according to claim 1 or 10, characterized in that Comparing the physical object information or physical object image with the design information or design image, and / or comparing the physical object information plate or physical image plate with the design information plate or design image plate, the method further includes but is not limited to one or more of the following: Adjusting the resolution and / or number of pixels of the physical image and / or the design image and / or the physical image plate and / or the design image plate to be compared, and performing a comparison between the physical image and the design image, and / or the physical image plate and the design image plate based on the adjustment result; When the comparison method is automatic comparison by a detection device, with respect to the granularity of the planned comparison, the resolution and / or the number of pixels of the physical image and / or the design image and / or the physical image plate and / or the design image plate are adjusted according to the resolution of the physical image and / or the design image and / or the physical image plate and / or the design image plate, and / or the number of pixels of the granularity of the planned comparison contained in the physical image and / or the design image and / or the physical image plate and / or the design image plate, as well as the comparison capability of the detection device. Based on the adjustment result, the physical image and the design image, and / or the physical image plate and the design image plate are compared; The comparison capability of the detection device includes but is not limited to: the minimum resolution required by the detection device for completing the comparison at the granularity, for the physical image and / or the design image and / or the physical image plate and / or the design image plate, and / or the minimum number of pixels required to be included in the granularity; The adjustment method includes but is not limited to: with respect to the granularity of the planned comparison, on the premise of ensuring the accuracy of the comparison, reducing the resolution and / or number of pixels of the physical image and / or the design image and / or the physical image plate and / or the design image plate, so that the resolution of the physical image and / or the design image and / or the physical image plate and / or the design image plate is reduced, and / or the number of pixels contained in the granularity in the physical image and / or the design image and / or the physical image plate and / or the design image plate is reduced, and is greater than or equal to the comparison capability of the detection device.

15. The method according to claim 13, characterized in that The overall comparison method includes, but is not limited to, one or more of the following: Comparison of the entire object information or image with the design information or image, and / or comparison of the entire object information panel or image panel with the design information panel or image panel; The overall alignment includes but is not limited to one or more of the following: overall fine alignment, overall rough alignment; During the overall fine comparison, the granularity of the comparison has reached the minimum limit; During a rough overall comparison, the granularity of the comparison is greater than the minimum limit, and the comparison content includes but is not limited to one or more of the following: connection relationship, chip area, chip outline, package substrate area, package substrate outline, graphic overview, graphic distribution characteristics, and module structure; Applicable situations for the overall fine comparison of the entire physical object information or physical object image with the design information or design image include, but are not limited to, one or more of the following: the time required to complete the overall fine comparison is less than or equal to a first preset threshold; the number of pixels of the physical object image is less than or equal to a second preset threshold; the number of pixels of the design image is less than or equal to a third preset threshold; the resolution of the physical object image is less than or equal to a fourth preset threshold; the resolution of the design image is less than or equal to a fifth preset threshold; the area of ​​the physical object information and / or physical object image and / or design information and / or design image is less than or equal to a sixth preset threshold; The area of ​​the smallest graphic in the physical object information and / or physical object image and / or design information and / or design image is greater than or equal to a seventh preset threshold; The applicable conditions for the overall fine comparison of the entire physical information plate or physical image plate with the design information plate or design image plate include, but are not limited to, one or more of the following: the time required to complete the overall fine comparison of the plates is less than or equal to an eighth preset threshold; the number of pixels of the physical image plate is less than or equal to a ninth preset threshold; the number of pixels of the design image plate is less than or equal to a tenth preset threshold; The resolution of the physical image plate is less than or equal to an eleventh preset threshold; the resolution of the design image plate is less than or equal to a twelfth preset threshold; The area of ​​the physical object information panel and / or the physical object image panel and / or the design information panel and / or the design image panel is less than or equal to a thirteenth preset threshold; the area of ​​the smallest graphic in the physical object information panel and / or the physical object image panel and / or the design information panel and / or the design image panel is greater than or equal to a fourteenth preset threshold; The applicable conditions for the overall rough comparison of the entire physical object information or physical image with the design information or design image include, but are not limited to, one or more of the following: the time required to complete the overall fine comparison is greater than or equal to a fifteenth preset threshold; the number of pixels of the physical object image is greater than or equal to a sixteenth preset threshold; the number of pixels of the design image is greater than or equal to a seventeenth preset threshold; The resolution of the physical image is greater than or equal to an eighteenth preset threshold; the resolution of the design image is greater than or equal to a nineteenth preset threshold; The area of ​​the physical object information and / or physical object image and / or design information and / or design image is greater than or equal to the twentieth preset threshold; the area of ​​the smallest figure in the physical object information and / or physical object image and / or design information and / or design image is less than or equal to the twenty-first preset threshold; The overall rough alignment is combined with the other alignment methods described; The applicable conditions for the overall rough comparison of the entire physical information plate or physical image plate with the design information plate or design image plate include, but are not limited to, one or more of the following: the time required to complete the overall fine comparison of the plates is greater than or equal to a twenty-second preset threshold; the number of pixels in the physical image plate is greater than or equal to a twenty-third preset threshold; The number of pixels of the designed image plate is greater than or equal to a twenty-fourth preset threshold; The resolution of the physical image plate is greater than or equal to a twenty-fifth preset threshold; The resolution of the designed image plate is greater than or equal to a twenty-sixth preset threshold; The area of ​​the physical object information plate and / or the physical object image plate and / or the design information plate and / or the design image plate is greater than or equal to a twenty-seventh preset threshold; The area of ​​the smallest graphic in the physical object information plate and / or the physical object image plate and / or the design information plate and / or the design image plate is less than or equal to a twenty-eighth preset threshold; The overall rough comparison is combined with other comparison methods.

16. The method according to claim 13, characterized in that The detailed comparison method includes, but is not limited to, one or more of the following: For the comparison of the physical object information or physical object image with the design information or design image, and / or the comparison of the physical object information plate or physical image plate with the design information plate or design image plate, one or more comparisons are conducted by gradually narrowing the comparison area and / or reducing the granularity for one or more of the following areas, including but not limited to: areas that failed the overall comparison, areas of interest or considered critical after the overall comparison passed, areas with complex implementation, areas with critical functions, and the entire area; When performing one or more comparisons, the refinement limit is that the comparison area has been reduced to the minimum graphic and / or minimum size, and / or granularity in the corresponding information and / or image and / or information plate and / or image plate has reached the minimum limit, and the refined comparison needs to reach or not reach the refinement limit.

17. The method according to claim 13, wherein The sampling and comparison methods include, but are not limited to, one or more of the following: Calculating and / or setting an area available for comparison between the physical object information or physical object image and the design information or design image, and / or comparing the physical object information plate or physical object image plate and the design information plate or design image plate; Selecting a number of sampling blocks from the object information or the object image or the object information plate or the object image plate based on the area available for comparison, wherein the sum of the areas of the sampling blocks shall not exceed the area available for comparison; Selecting a number of sampling blocks from the design information or design image or design information plate or design image plate based on the area available for comparison, wherein the sum of the areas of the sampling blocks shall not exceed the area available for comparison; The sampling blocks selected from the physical object information or physical object image or physical object information plate or physical image plate maintain a corresponding relationship with the sampling blocks selected from the design information or design image or design information plate or design image plate; The sampling block selection method includes but is not limited to one or more of the following: random sampling, sampling according to a rule, allocating the number of sampling blocks proportional to the density and / or complexity of the graphics, allocating the area of ​​the sampling blocks proportional to the density and / or complexity of the graphics, setting; Comparing the sample blocks in the physical object information or physical object image or physical object information plate or physical image plate with the sample blocks in the corresponding design information or design image or design information plate or design image plate; Analyze the results of this sampling comparison by combining the comparison results of each sampling block; The fine limit of sampling comparison is that the granularity has reached the minimum limit, and the sampling comparison needs to reach or not reach the said fine limit.

18. The method according to claim 1 or 17, characterized in that Calculate the area that can be used for alignment, including but not limited to one or more of the following: For the physical object information or physical object image or physical object information plate or physical image plate, and the design information or design image or design information plate or design image plate, calculate the area available for comparison based on the time required to complete the comparison per unit area and the expected completion time of this comparison; The calculation method includes but is not limited to: area available for comparison = unit area * expected completion time of this comparison / time required to complete the comparison per unit area.

19. The method according to claim 13 or 16, characterized in that Methods for obtaining the minimum figure and / or minimum size and / or minimum area include, but are not limited to, one or more of the following: Obtaining a minimum size from corresponding design information and / or physical information and / or design information plate and / or physical information plate, wherein the obtaining method includes but is not limited to obtaining one or more of the following information: minimum line width, feature size, process technology, gate length, and channel length; Further analysis is performed based on the minimum size to obtain the minimum figure and / or minimum area; The minimum graphic and / or the minimum size and / or the minimum area are identified in the corresponding design image and / or the actual product image and / or the design image panel and / or the actual product image panel.

20. The method according to claim 10, or 12, or 13, or 15, or 16, or 17, characterized in that: In one or more of the following cases, but not limited to, the method further includes adjusting the corresponding resolution and / or number of pixels before comparing: Before image comparison begins and / or after splitting the panels and / or during overall comparison, adjust the resolution and / or pixel count of the physical image and / or design image and / or physical image panels and / or design image panels before comparison; After narrowing the comparison area and / or reducing the granularity, the resolution and / or number of pixels of the corresponding images are adjusted for the narrowed and / or granularity-reduced areas before re-comparison; After selecting the sampling blocks, the resolution and / or pixel count of the corresponding image are adjusted for each sampling block before comparison.

21. The method according to claim 1, or 10, or 12, or 13, or 15, or 16, or 17, characterized in that: The method further includes: Adjust the comparison implementation algorithm for one or more of the following situations, including but not limited to: different comparison purposes, different comparison contents, different comparison methods, different comparison modes, and different working stages of the comparison.

22. The method according to claim 1, wherein Before verifying the design information, the method further includes: Confirm the accuracy of the acquired design information.

23. The method according to claim 1, 7, 9 or 22, wherein: The method for confirming the accuracy of the obtained design information includes but is not limited to one or more of the following: For the first design information obtained for comparison and the first design information obtained for verification, confirming that the design information of the overlapping parts and / or repeated parts therein are identical and / or consistent; the method for confirming that the design information of the overlapping parts and / or repeated parts are identical and / or consistent includes, but is not limited to, one or more of the following: unifying the format of the first design information obtained for comparison and the format of the first design information obtained for verification, performing image comparison on the overlapping parts and / or repeated parts, performing graphic comparison on the overlapping parts and / or repeated parts, performing similarity comparison on the overlapping parts and / or repeated parts, determining that the similarity is greater than or equal to a twenty-ninth preset threshold, and determining that all or part of the information of one of the first design information obtained for comparison and the first design information obtained for verification is obtained by extracting all or part of the information from the other information, and / or all or part of the information of one of the information is obtained by converting the format of the other information into another information and extracting all or part of the information therefrom; unifying the format of the first design information obtained for comparison with the format of the first design information obtained for verification; the method of unifying the formats of the two includes but is not limited to one or more of the following: converting one of the two formats into the other format, converting both formats into a third format; the third format refers to a format other than the format of the first design information obtained for comparison and the format of the first design information obtained for verification; For the second design information obtained for verification with the first design information, the second design information obtained for verification with the third design information, and the second design information obtained for verification with the fourth design information, for any and / or set one or more pairwise combinations of the three, and / or among the three, confirming that the design information of the overlapping parts and / or repeated parts is the same and / or remains consistent; the method for confirming that the design information of the overlapping parts and / or repeated parts is the same and / or remains consistent includes but is not limited to one or more of the following: unifying the design information format; performing image comparison on the overlapping parts and / or repeated parts; performing graphic comparison on the overlapping parts and / or repeated parts; performing similarity comparison on the overlapping parts and / or repeated parts; and determining that the similarity is greater than or equal to a 30th preset threshold; Determining whether all or part of one or more of the second design information obtained for verification with the first design information, the second design information obtained for verification with the third design information, and the second design information obtained for verification with the fourth design information is obtained by extracting all or part of the information from another one or more of the information, and / or all or part of the information is obtained by extracting all or part of the information from another one or more of the information after format conversion. Application scenarios of the method for confirming that the design information of the overlapping and / or repeated parts is the same and / or consistent include, but are not limited to: for a hybrid analog-digital chip, confirming that the gate-level netlist of a digital chip module therein, after the format is converted into a transistor-level netlist, its content is the same as or consistent with the digital chip module part in the chip transistor-level netlist; For the second design information obtained for verification with the first design information, the second design information obtained for verification with the third design information, and the second design information obtained for verification with the fourth design information, for any and / or set one or more pairwise combinations of the three, and / or between the three, the design information formats are unified; the method for unifying the design information formats includes but is not limited to one or more of the following: for the pairwise combinations, converting one of the two formats into another format, for the pairwise combinations, converting both formats into a third format, for the pairwise combinations, the third format refers to a format other than the design information format in the combination, for the three, unifying the formats into one of the three formats, for the three, converting all the three formats into a fourth format, for the three, the fourth format refers to a format other than the design information format among the three; confirming that the design information of the overlapping and / or repeated parts of the third design information obtained for verification with the second design information and the third design information obtained for verification with the fourth design information are identical and / or consistent; methods for confirming that the design information of the overlapping and / or repeated parts are identical and / or consistent include, but are not limited to, one or more of the following: unifying the format of the third design information obtained for verification with the second design information and the format of the third design information obtained for verification with the fourth design information, performing image comparison on the overlapping and / or repeated parts, performing graphic comparison on the overlapping and / or repeated parts, and performing similarity comparison on the overlapping and / or repeated parts to determine that the similarity is greater than or equal to a thirty-first preset threshold, and determining that, between the third design information obtained for verification with the second design information and the third design information obtained for verification with the fourth design information, all or part of the information of one of the information is obtained by extracting all or part of the information from the other information, and / or all or part of the information of one of the information is obtained by converting the format of the other information into another information and extracting all or part of the information therefrom; unifying the format of the third design information obtained for verification with the second design information and the format of the third design information obtained for verification with the fourth design information; the method of unifying the formats of the two includes but is not limited to one or more of the following: converting one of the two formats into the other format, converting both formats into a third format; the third format refers to a format other than the format of the third design information obtained for verification with the second design information and the format of the third design information obtained for verification with the fourth design information; confirming that the design information of the overlapping and / or repeated parts of the fourth design information obtained for verification with the second design information and the fourth design information obtained for verification with the third design information are identical and / or consistent; methods for confirming that the design information of the overlapping and / or repeated parts are identical and / or consistent include, but are not limited to, one or more of the following: unifying the format of the fourth design information obtained for verification with the second design information and the format of the fourth design information obtained for verification with the third design information, performing image comparison on the overlapping and / or repeated parts, performing graphic comparison on the overlapping and / or repeated parts, and performing similarity comparison on the overlapping and / or repeated parts to determine that the similarity is greater than or equal to a thirty-second preset threshold, and determining that, between the fourth design information obtained for verification with the second design information and the fourth design information obtained for verification with the third design information, all or part of the information of one of the information is obtained by extracting all or part of the information from the other information, and / or all or part of the information of one of the information is obtained by converting the format of the other information into another information and extracting all or part of the information therefrom; unifying the obtained fourth design information format for verification with the second design information and the obtained fourth design information format for verification with the third design information; the method of unifying the formats of the two includes but is not limited to one or more of the following: converting one of the two formats into the other format, converting both formats into a third format; the third format refers to a format other than the obtained fourth design information format for verification with the second design information and the obtained fourth design information format for verification with the third design information; Confirming that the gate-level netlist in the acquired second design information is a back-end netlist and / or a non-front-end netlist; confirming that the gate-level netlist in the acquired third design information is a front-end netlist and / or a non-back-end netlist; The method for confirming that the gate-level netlist in the obtained second design information is a back-end netlist and / or a non-front-end netlist, and / or confirming that the gate-level netlist in the obtained third design information is a front-end netlist and / or a non-back-end netlist, includes but is not limited to one or more of the following: keyword search; performing a similarity comparison between the gate-level netlist in the obtained second design information and the gate-level netlist in the obtained third design information, and / or determining that the similarity is less than or equal to a thirty-third preset threshold; Confirming that the acquired RTL code is a register transfer level description and / or not a description at another level, wherein the description at another level includes but is not limited to a gate level description; The accuracy of the obtained design information is confirmed by the file suffix of the obtained design information.

24. The method according to claim 1 or 7, characterized in that When verifying the design information, the correspondence between the design information includes but is not limited to one or more of the following: correspondence of the same modules, correspondence of the same units, correspondence of the same functions, correspondence of the same logic, and correspondence of the same connections.

25. The method according to claim 1 or 7, characterized in that When conducting the verification, the verification settings and / or conditions are confirmed. The method of confirming the verification settings and / or conditions includes, but is not limited to, one or more of the following: When the verification is LVS verification, the settings and / or conditions of the LVS verification are confirmed by analyzing the design information targeted by the LVS verification, or / and checking the design specifications corresponding to the design information targeted by the LVS verification; the settings and / or conditions of the LVS verification include but are not limited to one or more of the following: top-level design, top-level unit, top-level logic, and top-level module; When the verification is formal verification, the settings and / or conditions of the formal verification are confirmed by analyzing the design information targeted by the formal verification and / or viewing the design specifications corresponding to the design information targeted by the formal verification; the settings and / or conditions of the formal verification include but are not limited to one or more of the following: top-level design, top-level unit, top-level logic, top-level module, and constant settings; The top-level design and / or top-level unit and / or top-level logic and / or top-level module in the verification settings and / or conditions are related to the design information targeted by the verification, and are all or part of the design information of the chip or chip module; the top-level design and / or top-level unit and / or top-level logic and / or top-level module in the verification settings are application scenarios of part of the design information of the chip, including but not limited to: for a mixed analog-digital chip, the top-level design and / or top-level unit and / or top-level logic and / or top-level module in the formal verification settings and / or conditions are digital chip modules in the mixed analog-digital chip.

26. The method according to claim 1 or 7, characterized in that When conducting the verification, a comprehensive analysis is performed on one or more verification results and / or reports to determine whether the verification has passed. When the verification is a formal verification, the verification results and / or reports include but are not limited to one or more of the following: comparison point matching check results, verification results, and verification reports.

27. The method according to claim 1, 4 or 7, wherein: The determination of the autonomy and / or controllability of the chip or chip module based on the comparison result and / or verification result includes, but is not limited to, one or more of the following: Determining, based on the characteristics of the chip or chip module, the type of comparison and / or verification required to determine the degree of autonomy and / or controllability of the chip or chip module; For the required comparison and / or verification types, assign scores corresponding to the required comparisons and / or verifications according to the difficulty and / or criticality of the steps represented by the types; For each of the required comparisons and / or verifications, when the comparisons and / or verifications are actually performed and passed, the chip or chip module obtains a score corresponding to the comparison and / or verification; For each of the required comparisons and / or verifications, if the comparisons and / or verifications are not actually performed or are not actually performed, the chip or chip module does not obtain a score corresponding to the comparison and / or verification; Based on the results of various comparisons and / or verifications actually carried out, invalid scores are sorted out from the scores corresponding to the various comparisons and / or verifications obtained for the chip or chip module; Among the scores corresponding to various comparisons and / or verifications obtained for the chip or chip module, invalid scores are removed, and the remaining scores are valid scores, the valid scores are summed, and the summed result is used as the final score of the chip or chip module; The degree of autonomy and / or controllability of the chip or chip module is determined based on the final score of the chip or chip module.

28. The method according to claim 27, characterized in that The results of the various comparisons and / or verifications actually carried out are summarized, and invalid scores are sorted out from the scores corresponding to the various comparisons and / or verifications obtained by the chip or chip module, including but not limited to one or more of the following: When the physical information of the chip or chip module fails to pass the comparison with the corresponding first design information, the corresponding scores obtained by the chip or chip module for each of the required verifications when actually carried out and passed are invalid scores; When the verification between the first design information of the chip or chip module and the corresponding second design information fails, the corresponding score obtained when the verification between the second design information of the chip or chip module and the corresponding third design information is actually carried out and passes is an invalid score; When the verification between the first design information of the chip or chip module and the corresponding second design information fails, the corresponding score obtained when the verification between the second design information of the chip or chip module and the corresponding fourth design information is actually carried out and passes is an invalid score; When the verification between the first design information of the chip or chip module and the corresponding second design information fails, the corresponding score obtained when the verification between the third design information of the chip or chip module and the corresponding fourth design information is actually carried out and passes is an invalid score; When the second design information of the chip or chip module and the corresponding third design information fail to be verified, and the second design information of the chip or chip module and the corresponding fourth design information fail to be verified, the corresponding score obtained when the verification of the third design information of the chip or chip module and the corresponding fourth design information is actually carried out and passed is an invalid score.

29. The method according to claim 1, 4 or 7, wherein: For a chip consisting of one or more chip modules, the determination of the chip's autonomy and / or controllability includes, but is not limited to, one or more of the following: For each chip module in the chip, a corresponding weight is assigned according to the difficulty and / or criticality of each chip module. The chip score is the weighted sum of the scores of each chip module. The chip's autonomy and / or controllability is determined based on the weighted sum. The allocation of corresponding weights needs to ensure that when a chip with a given function is composed of one or more chip modules under different solutions, the scores corresponding to the same degree of autonomy and / or controllability are the same; the implementation method of ensuring the same scores corresponding to the same degree of autonomy and / or controllability includes but is not limited to one or more of the following: weight allocation normalization, in which the sum of the weights of the chip modules of the chip with the given function is the same under different solutions, and when it is determined that the autonomy and / or controllability of each chip module is the highest, the scores of each chip module are the same, and the full scores of each chip module are the same; For each chip module in the chip, when determining the physical information of each chip module, ensure that the physical information of each chip module does not overlap and / or repeat, and that the sum of the physical information of each chip module is the physical information of the entire chip; For each chip module in the chip, when determining the design information of each chip module, ensure that the design information of each chip module does not overlap and / or repeat, and that the sum of the design information of each chip module is the design information of the entire chip; The physical information of each chip module corresponds to the design information.

30. The method according to claim 29, wherein When the chip modules constituting the chip have the same model, the chip modules of the same model are uniformly regarded as a whole chip module for detection, and a score is uniformly calculated and a weight is assigned. Methods for uniformly treating the chip modules of the same model as a whole chip module for detection include but are not limited to one or more of the following: Determining the sum of the physical information of the chip modules of the same model as the physical information of the entire chip module under test, determining the sum of the design information of the chip modules of the same model as the design information of the entire chip module under test, and calculating a score for the entire chip module under test; Randomly or according to a rule, select a chip module from the chip modules of the same model, and use the score of the chip module as the score of the entire chip module tested; For the chip modules of the same model, all or part of the chip modules are selected, scores of the selected chip modules are calculated respectively, and the average value of the scores of the selected chip modules is used as the score of the entire chip module detected.

31. The method according to claim 29, wherein The scope of application of the method for determining the autonomy and / or controllability of a chip composed of one or more chip modules includes, but is not limited to, one or more of the following: An analog-digital hybrid chip composed of a digital chip module and an analog chip module; A multi-chip module (MCM) is a package of multiple dies. RF front-end module.

32. A chip or chip module detection device, characterized in that: The device includes: An information determination module, used to determine physical information of the chip or chip module and design information of the chip or chip module; The physical information includes but is not limited to one or more of the following: The physical connection relationship between the chip or chip module and the packaging substrate, and / or the physical connection relationship between the chip or chip module and other chips or chip modules; Physical information of the package substrate, including but not limited to one or more of the following: the physical package substrate, the physical circuit or circuit diagram of the package substrate, the physical layout or layout diagram of the package substrate, the physical wiring or wiring diagram of the package substrate, and the physical circuit or circuit diagram of the package substrate; Physical information of the chip or chip module, including but not limited to one or more of the following: the physical chip or chip module, the physical layout of the chip or chip module, the physical layout of the chip or chip module, the physical layout and wiring of the chip or chip module or the layout and wiring diagram, the physical circuit of the chip or chip module or the circuit diagram; The design information includes but is not limited to one or more of the following: The designed connection relationship between the chip or chip module and the packaging substrate, and / or the designed connection relationship between the chip or chip module and other chips or chip modules; Design information of the package substrate, including but not limited to one or more of the following: package substrate design circuits or circuit diagrams, package substrate design layouts or layout diagrams, package substrate design wiring or wiring diagrams, package substrate design circuits or circuit diagrams; First design information of the chip or chip module, the first design information including but not limited to one or more of the following: chip or chip module design layout, chip or chip module design layout, chip or chip module design layout and routing, or layout and routing diagram; Second design information of the chip or chip module, the second design information including but not limited to a schematic diagram and / or a netlist of the chip or chip module; Third design information of the chip or chip module, the third design information including but not limited to a gate-level netlist synthesized from register transfer level RTL code of the digital chip or digital chip module; Fourth design information of the chip or chip module, the fourth design information including but not limited to RTL code of the digital chip or digital chip module; An information processing module, configured to compare the physical object information with the design information and verify the design information; A determination module, configured to verify the design consistency of the chip or chip module based on the comparison results and the verification results; The information processing module is used to verify the design information, including but not limited to at least two of the following: Verifying the first design information of the chip or chip module with the corresponding second design information, wherein the verification method includes but is not limited to LVS inspection or verification; Verifying the second design information of the chip or chip module with the corresponding third design information, and / or verifying the second design information of the chip or chip module with the corresponding fourth design information, wherein the verification method includes but is not limited to formal verification; The third design information of the chip or chip module is verified with the corresponding fourth design information, and the verification method includes but is not limited to formal verification.

33. A chip or chip module detection device, characterized in that: The apparatus comprises: a processor and a memory for storing a computer program capable of running on the processor, Wherein, when the processor is used to run the computer program, it executes the steps of the method described in any one of claims 1 to 31.

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