Semiconductor structure and method of forming the same, SRAM device

Abstract

A semiconductor structure and a method for forming the same, and an SRAM device, the method comprising: providing a substrate, the substrate comprising a substrate, a plurality of channel stacks separated on the substrate, and a dummy gate structure across the plurality of channel stacks, the dummy gate structure covering part of the top wall and part of the sidewall of the channel stacks, the channel stacks comprising a sacrificial layer and a channel layer on the sacrificial layer; forming an interlayer dielectric layer covering the sidewall of the dummy gate structure and exposing the top of the dummy gate structure; removing the dummy gate structure to form a gate opening in the interlayer dielectric layer; removing one or more channel layers on the top of the channel stacks; removing the sacrificial layer to form a channel; and forming a gate structure in the gate opening and the channel. The number of channel layers in the semiconductor structure is reduced by removing one or more channel layers on the top of the channel stacks, thereby reducing the overall on-current of the channel in the semiconductor structure when the semiconductor structure is in operation, so that the semiconductor structure can meet the process requirements.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same, and an SRAM device. Background Technology

[0002] In semiconductor manufacturing, with the development trend of very large-scale integrated circuits (VLSI), the feature size of integrated circuits continues to shrink. To adapt to the smaller feature size, the channel length of metal-oxide-semiconductor field-effect transistors (MOSFETs) is also continuously shortened. However, as the channel length of the device shortens, the distance between the source and drain of the device also shortens. Therefore, the gate structure's control over the channel becomes worse, and it becomes increasingly difficult to pinch off the channel with the gate voltage. This makes subthreshold leakage, also known as short-channel effects (SCE), more likely to occur.

[0003] Therefore, to better adapt to the requirements of proportionally shrinking device dimensions, semiconductor technology has gradually begun to transition from planar transistors to three-dimensional transistors with higher efficiency, such as gate-all-around (GAA) transistors. In a gate-all-around transistor, the gate surrounds the area where the channel is located from all sides. Compared with planar transistors, the gate of a gate-all-around transistor has stronger control over the channel and can better suppress short-channel effects.

[0004] The gate structure in a fully enclosed gate transistor is generally formed using a self-aligned double patterning process (SADP) or a self-aligned quadruple patterning process (SAQP). In the extension direction perpendicular to the gate structure, the lateral dimensions of each gate structure are the same, and the length of the channel below the corresponding gate structure is the same. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and its formation method, and an SRAM device, wherein the overall on-current of the channel of the semiconductor structure is reduced, so that the semiconductor structure can meet the process requirements.

[0006] To address the aforementioned problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a substrate, a plurality of channel stacks discretely disposed on the substrate, and a dummy gate structure spanning the plurality of channel stacks, the dummy gate structure covering a portion of the top wall and a portion of the sidewalls of the channel stacks, the channel stacks including a sacrificial layer and a channel layer located on the sacrificial layer; forming an interlayer dielectric layer covering the sidewalls of the dummy gate structure and exposing the top of the dummy gate structure; removing the dummy gate structure to form a gate opening in the interlayer dielectric layer; removing one or more of the channel layers at the top of the channel stacks; after removing one or more of the channel layers at the top of the channel stacks, removing the sacrificial layer between the remaining channel layers to form a channel; and forming a gate structure in the gate opening and the channel.

[0007] Accordingly, embodiments of the present invention also provide a semiconductor structure, comprising: a substrate, the substrate including a first region and a second region; a plurality of channel layers, spaced apart and suspended on the substrate in the normal direction of the substrate surface, wherein the number of channel layers in the second region is less than the number of channel layers in the first region; a gate structure surrounding the channel layers; a gate sidewall layer located on a sidewall above the channel layers near the top of the gate structure; and one or more end channel layers located between the gate sidewall layer in the second region and the topmost channel layer.

[0008] Accordingly, embodiments of the present invention also provide an SRAM device, including a semiconductor structure comprising: a substrate, the substrate including a first region and a second region; a plurality of channel layers, spaced apart and suspended on the substrate in the normal direction of the substrate surface, wherein the number of channel layers in the second region is less than the number of channel layers in the first region; a gate structure surrounding the channel layers; a gate sidewall layer located on the sidewall of the gate structure at the top of the channel layers; and one or more end channel layers located between the gate sidewall layer of the second region and the topmost channel layer; comprising: the first region including a pull-down transistor; and the second region including a transmission gate transistor or a pull-up transistor.

[0009] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0010] In the semiconductor structure formation method provided by this invention, the dummy gate structure is removed, a gate opening is formed in the interlayer dielectric layer, the gate opening exposes multiple channel stacks, and one or more channel layers on top of the channel stacks are removed, thereby reducing the number of channel layers in the semiconductor structure. This reduces the overall on-state current of the channels in the semiconductor structure during operation, enabling the semiconductor structure to meet process requirements. Furthermore, the sacrificial layer between the remaining channel layers is removed to form a channel, and a gate structure is formed in the gate opening and the channel. This provides a larger formation space for the gate structure, reducing the number of channel layers that need to be controlled by the gate structure. Consequently, during semiconductor structure operation, the gate structure's control over the remaining channel layers is strengthened, which helps reduce the probability of channel leakage current and improves the electrical performance of the semiconductor structure.

[0011] In the SRAM device provided in this embodiment of the invention, the first region includes a pull-down transistor; the second region includes a transmission gate transistor or a pull-up transistor. The number of channel layers of the pull-down transistor is greater than the number of channel layers of the transmission gate transistor or the pull-up transistor. Consequently, when the SRAM device is operating, the on-state current of the pull-down transistor is greater than the on-state current of the transmission gate transistor or the pull-up transistor, resulting in higher stability of the SRAM device and making it less susceptible to interference. Specifically, the greater on-state current of the pull-down transistor compared to the transmission gate transistor improves the stability of SRAM device read operations; the greater on-state current of the pull-down transistor compared to the pull-up transistor improves the write speed of the SRAM device. Attached Figure Description

[0012] Figures 1 to 3 This is a schematic diagram of a key step in a method for forming a semiconductor structure.

[0013] Figure 4 and Figure 5 This is a schematic diagram of a key step in another method for forming a semiconductor structure;

[0014] Figures 6 to 19 This is a schematic diagram of the structure corresponding to each step in the method for forming a semiconductor structure according to an embodiment of the present invention. Detailed Implementation

[0015] As the background technology shows, the devices currently being fabricated still suffer from poor performance. This paper analyzes the reasons for this poor performance by examining a semiconductor structure fabrication method.

[0016] refer to Figures 1 to 3 The diagram shows a schematic representation of a key step in a method for forming a semiconductor structure.

[0017] like Figure 1 As shown, a substrate is provided, the substrate including a first device region I and a second device region II, the substrate including a substrate 1 and a channel stack 2 located on the substrate 1, the channel stack 2 including a sacrificial layer 21 and a channel layer 22 located on the sacrificial layer 21; a dummy gate structure 4, spanning the channel stack 2, the dummy gate structure 4 covering part of the top wall and part of the sidewall of the channel stack 2, with the lateral direction being parallel to the surface of the substrate 1 and perpendicular to the extension direction of the dummy gate structure 4; source / drain doped layers 30, located in the channel stack 2 on both sides of the dummy gate structure 4; an inner sidewall layer 7, located between the sacrificial layer 21 and the source / drain doped layers 30; and an interlayer dielectric layer 6, located on the side of the dummy gate structure 4, with the top surface of the interlayer dielectric layer 6 flush with the top surface of the dummy gate structure 4.

[0018] like Figure 2 As shown, the pseudo-gate structure 4 is removed to form a gate opening 5; after forming the gate opening 5, the sacrificial layer 21 is removed to form a first channel 8 surrounded by the substrate 1, the channel layer 22 and the inner sidewall layer 7, and a second channel 9 surrounded by the channel layer 22 and the inner sidewall layer 7.

[0019] like Figure 3 As shown, a gate structure 10 is formed in the gate opening 5, the first channel 8, and the second channel 9.

[0020] Semiconductor technology is gradually transitioning from planar transistors to more efficient three-dimensional transistors, such as gate-all-around (GAA) transistors. GAA transistors offer stronger gate control over the channel and better suppress short-channel effects. Typically, the pseudo-gate structure 4 in the first device region I and the second device region II is formed using a self-aligned double patterning (SADP) process. Consequently, the lateral dimensions of the pseudo-gate structure 4 in the first device region I and the second device region II are the same. The lateral dimensions of the channel layer 22 in the first device region I and the second device region II are also the same. During semiconductor operation, the total conduction current in the channel of the first device region I is the same as the total conduction current in the channel of the second device region II. This cannot meet the requirement of inconsistent total conduction current in the channels of the first device region I and the second device region II, meaning it cannot satisfy the diverse electrical performance requirements of the semiconductor structure.

[0021] refer to Figure 4 and Figure 5 This is a schematic diagram of a key step in another method for forming a semiconductor structure.

[0022] The difference between the method for forming this semiconductor structure and the previous method for forming a semiconductor structure is that:

[0023] like Figure 4 As shown, the number of channel stacks 20 in the first region I is greater than the number of channel stacks 20 in the second region II.

[0024] like Figure 5 As shown, source / drain doped layers 30 are formed in the channel stack 20 on both sides of the pseudo-gate structure 40.

[0025] The number of channel stacks 20 in the first region I is greater than the number of channel stacks 20 in the second region II. Therefore, after the pseudo-gate structure 40 is replaced with a gate structure, the number of channel layers 22 in the first region I is greater than the number of channel layers in the second region II. When the semiconductor structure is working, the total current of the channel in the first region I is greater than the total current of the channel in the second region II.

[0026] The step of forming the source / drain doped layer 30 includes: forming trenches (not shown in the figure) in the channel stack 20 on both sides of the pseudo-gate structure 40. The depth of the trench in the first region I is greater than the depth of the trench in the second region II. Selective epitaxy growth (SEG) is typically used to form the source / drain doped layer 30 in the trench. The sidewalls and bottom surface of the trench provide the interface for selective epitaxy growth. Consequently, the thickness of the source / drain doped layer 30 in the pseudo-gate structure 40 of the first region I is greater than the thickness of the source / drain doped layer 30 formed on both sides of the pseudo-gate structure 40. The stress of the source / drain doped layer 30 on the channel in the first region I is greater than the stress of the source / drain doped layer 30 on the channel in the second region II, resulting in differences in the uniformity of the semiconductor structure.

[0027] To address the technical problems, the semiconductor structure formation method provided in this embodiment of the invention removes the dummy gate structure, forms a gate opening in the interlayer dielectric layer, exposes multiple channel stacks, and removes one or more channel layers on top of the channel stacks. This reduces the number of channel layers in the semiconductor structure, thereby reducing the overall on-state current of the channels during semiconductor structure operation, enabling the semiconductor structure to meet process requirements. Furthermore, the sacrificial layer between the remaining channel layers is removed to form a channel, and a gate structure is formed in the gate opening and the channel. This provides a larger formation space for the gate structure, reducing the number of channel layers that need to be controlled by the gate structure. Consequently, during semiconductor structure operation, the gate structure's control over the remaining channel layers is strengthened, which helps reduce the probability of channel leakage current and improves the electrical performance of the semiconductor structure.

[0028] In the SRAM device provided in this embodiment of the invention, the first region includes a pull-down transistor; the second region includes a transmission gate transistor or a pull-up transistor. The number of channel layers of the pull-down transistor is greater than the number of channel layers of the transmission gate transistor or the pull-up transistor. Consequently, when the SRAM device is operating, the on-state current of the pull-down transistor is greater than the on-state current of the transmission gate transistor or the pull-up transistor, resulting in higher stability of the SRAM device and making it less susceptible to interference. Specifically, the greater on-state current of the pull-down transistor compared to the transmission gate transistor improves the stability of SRAM device read operations; the greater on-state current of the pull-down transistor compared to the pull-up transistor improves the write speed of the SRAM device.

[0029] To make the above-mentioned objectives, features and advantages of the embodiments of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0030] Figures 6 to 19 This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming a semiconductor structure according to an embodiment of the present invention.

[0031] refer to Figure 6 and Figure 7 , Figure 7 for Figure 6 In a cross-sectional view along the AA direction, a substrate is provided, the substrate including a substrate 100, a plurality of channel stacks 300 disposed on the substrate 100, and a pseudo-gate structure 103 spanning the plurality of channel stacks 300, the pseudo-gate structure 103 covering a portion of the top wall and a portion of the sidewall of the channel stacks 300, the channel stacks 300 including a sacrificial layer 101 and a channel layer 102 located on the sacrificial layer 101.

[0032] Substrate 100 is used to provide a process platform for the subsequent formation of semiconductor structures.

[0033] In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate material may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide, or other materials. The substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates.

[0034] In this embodiment, the step of providing the substrate includes a first region I and a second region II.

[0035] It should be noted that in this embodiment, the first region I is used to form an NMOS (Negative Channel Metal Oxide Semiconductor), such as a pull-down transistor (PD), and the second region II is used to form a PMOS (Positive Channel Metal Oxide Semiconductor), such as a transmission gate transistor (PG) or a pull-up transistor (PU).

[0036] In this embodiment, the semiconductor structure formation method is used to form a semiconductor structure in which the total on-current of the transistor channel formed in the first region I is greater than the total on-current of the transistor formed in the second region II. That is, the number of channel layers 102 formed in the first region I is greater than the number of channel layers 102 formed in the second region II.

[0037] The channel stack 300 provides a process foundation for the subsequent formation of the suspended channel layer 102. The sacrificial layer 101 supports the channel layer 102, provides process conditions for the subsequent spacing and suspension of the channel layer 102, and also occupies space for the subsequently formed gate structure.

[0038] In this embodiment, the channel layer 102 is more difficult to etch than the sacrificial layer 101, so the channel layer 102 is less likely to be damaged when the sacrificial layer 101 is removed.

[0039] Specifically, the material of the channel layer 102 includes one or more of silicon, germanium, silicon germanide, silicon carbide, gallium arsenide, and indium gallium ionide. In this embodiment, the material of the channel layer 102 is silicon.

[0040] Specifically, the material of the sacrificial layer 101 includes one or both of silicon germanide and silicon. In this embodiment, the material of the sacrificial layer 101 is silicon germanide.

[0041] The pseudo-gate structure 103 occupies space for the gate structure to be formed in subsequent processes.

[0042] In this embodiment, the lateral dimension of the dummy gate structure 103 in the second region II is smaller than that of the dummy gate structure 103 in the first region I. Subsequently, source / drain doped layers are formed in the channel stack on both sides of the dummy gate structure 103. During semiconductor structure operation, the channel layer between the source / drain doped layers serves as the channel. Therefore, the lateral dimension of the dummy gate structure 103 defines the lateral dimension of the channel in the semiconductor structure. Later, the dummy gate structure 103 is replaced with a gate structure, and the lateral dimension of the gate structure in the second region II is smaller than that of the gate structure in the first region I. Correspondingly, the lateral dimension of the channel layer 102 below the gate structure in the second region II is smaller than that of the channel layer 102 below the gate structure in the first region I. During semiconductor structure operation, the on-current of the channel in the second region II is smaller than that of the channel in the first region I.

[0043] It should be noted that in the step of providing the substrate, the lateral direction, which is parallel to the surface of the substrate 100 and perpendicular to the extension direction of the pseudo-gate structure 103, should be defined as the lateral direction. The ratio of the lateral dimension of the pseudo-gate structure 103 in the second region II to the lateral dimension of the pseudo-gate structure 103 in the first region I should not be too large or too small. Typically, the semiconductor structure is used to form an SRAM device. Specifically, the first region I is used to form a pull-down transistor, and the second region II is used to form a transmission gate transistor or a pull-up transistor. If the ratio is too large, during semiconductor structure operation, the conduction current of the channel in the second region II will be approximately the same as the conduction current in the first region I, which cannot significantly improve the stability of SRAM device read and write speeds. If the ratio is too small, during semiconductor structure operation, the conduction current of the channel in the second region II will be too small compared to the conduction current in the first region I. In other words, the conduction current in the transmission gate transistor will be too small, which will limit the read and write speeds of the SRAM device. In this embodiment, during the step of providing the substrate, the lateral direction is parallel to the surface of the substrate 100 and perpendicular to the extension direction of the pseudo-gate structure 103. The lateral dimension of the pseudo-gate structure 103 in the second region II is 55% to 95% of the lateral dimension of the pseudo-gate structure 103 in the first region I.

[0044] In this embodiment, the pseudo gate structure 103 includes a pseudo gate oxide layer 1031 that conformally covers part of the top surface and part of the sidewalls of the channel stack, and a pseudo gate layer 1032 located on the pseudo gate oxide layer 1031.

[0045] In this embodiment, the dummy gate oxide layer 1031 is made of silicon oxide. In other embodiments, the dummy gate oxide layer may also be made of silicon oxynitride.

[0046] In this embodiment, the dummy gate layer 1032 is made of polycrystalline silicon. In other embodiments, the dummy gate layer may also be made of amorphous carbon.

[0047] The steps of forming the dummy gate structure 103 include: forming a dummy gate oxide layer (not shown) covering the channel stack and a dummy gate material layer (not shown) located on the dummy gate oxide layer; forming a gate mask layer 104 on the dummy gate material layer; etching the dummy gate material layer and the dummy gate oxide layer using the gate mask layer 104 as a mask, with the remaining dummy gate oxide layer serving as the dummy gate oxide layer 1031 and the remaining dummy gate material layer serving as the dummy gate layer 1032.

[0048] It should be noted that, taking the direction parallel to the surface of the substrate 100 and perpendicular to the extension direction of the pseudo-gate structure 103 as the lateral direction, in this embodiment, the pseudo-gate structures 103 in the first region I and the second region II are formed by a self-aligned double patterning process (SADP) or a self-aligned quadruple patterning process (SAQP). The lateral dimensions of the pseudo-gate structures 103 in the first region I and the second region II are the same, which simplifies the formation process of the pseudo-gate structure 103 and helps to improve the formation efficiency of the pseudo-gate structure 103.

[0049] It should be noted that, in the step of providing the substrate, a gate sidewall layer 105 is formed on the sidewall of the pseudo-gate structure 103.

[0050] The gate sidewall layer 105 is used to define the formation location of the subsequently formed source and drain doped layers, and also to protect the sidewalls of the dummy gate structure 103 from damage during the formation of the subsequent semiconductor structure.

[0051] The material of the gate sidewall layer 105 includes one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, boron nitride, silicon boron nitride, and silicon boron carbide.

[0052] It should also be noted that, in the step of providing the substrate, the substrate further includes: a fin 112, protruding from the substrate 100, and the fin 112 being located between the substrate 100 and the channel stack; and an isolation layer 113, located on the substrate 100 exposed by the fin 112. The dummy gate structure 103 is located on the isolation layer 113.

[0053] The fin 112 protrudes from the substrate 100, and the side of the fin 112 provides process space for the isolation layer 113.

[0054] In this embodiment, the material of the fin 112 is the same as the material of the substrate 100. In other embodiments, the material of the fin may be different from the material of the substrate.

[0055] The isolation layer 113 enables the gate structure formed by the subsequent replacement of the pseudo-gate structure 113 to be electrically isolated from the substrate 100, and the isolation layer 113 also enables electrical isolation between the various fins 112.

[0056] In this embodiment, the material of the isolation layer 113 is a dielectric material. Specifically, the material of the isolation layer 113 includes silicon oxide. Silicon oxide is a commonly used and low-cost dielectric material with high process compatibility, which helps to reduce the process difficulty and cost of forming the isolation layer 113.

[0057] Correspondingly, the pseudo-gate structure 103 is located on the isolation layer 113, the pseudo-gate structure 103 spans the fin 112, and covers part of the top wall and part of the side wall of the fin 112.

[0058] refer to Figure 8 and Figure 9 This forms a sidewall covering the pseudo-gate structure 103, and exposes the interlayer dielectric layer 115 (e.g., ...) on top of the pseudo-gate structure 103. Figure 9 (As shown).

[0059] The interlayer dielectric layer 115 is used for electrical isolation of adjacent devices. Furthermore, the interlayer dielectric layer 115 provides process space for subsequent formation of gate openings.

[0060] In this embodiment, the material of the interlayer dielectric layer 115 is an insulating material. Specifically, the material of the interlayer dielectric layer 115 includes silicon oxide.

[0061] It should be noted that the gate mask layer 104 is removed during the formation of the interlayer dielectric layer 115.

[0062] like Figure 8 As shown, the method for forming the semiconductor structure further includes: after providing the substrate and before forming the interlayer dielectric layer 115, etching the channel stack 300 on both sides of the dummy gate structure 103, and forming a trench 106 in the channel stack 300.

[0063] The trench 106 provides process space for the subsequent formation of source and drain doped layers.

[0064] In this embodiment, using the gate mask layer 104 as a mask, a dry etching process is employed to etch the channel stack 300 on both sides of the dummy gate structure 103, forming a trench 106. The dry etching process exhibits anisotropic etching characteristics and offers good control over the etching profile, which helps ensure the morphology of the trench 106 meets process requirements. During the formation of the trench 106 using the dry etching process, the top of the fin 112 can be used as the etching stop position, reducing damage to other film structures. Furthermore, by changing the etching gas, the sacrificial layer 101 and the channel layer 102 can be etched in the same etching equipment, which helps to increase the formation rate of the trench 106.

[0065] In other embodiments, wet etching or a combination of dry and wet etching can be used to etch the trench stacks on both sides of the pseudo-gate structure to form trenches.

[0066] It should be noted that the lateral dimensions of the pseudo-gate structure 103 in the first region I and the second region II are the same. Correspondingly, after the trench is formed, the lateral dimensions of the channel layer at the bottom of the gate structure in the first region I and the second region II are the same.

[0067] It should be noted that in this embodiment, the first region I and the second region II share the same source / drain doped layer, and the dopant ion types of the corresponding source / drain doped layers are the same. In other embodiments, the source / drain doped layers of the first region and the second region are independent, and the dopant ion types of the source / drain doped layers may also be different.

[0068] It should be noted that source and drain doped layers are subsequently formed in the trench 106. When the semiconductor structure is working, the channel layer between the source and drain doped layers serves as the channel. Therefore, the lateral dimension of the pseudo-gate structure 103 defines the lateral dimension of the channel in the semiconductor structure. Thus, the lateral dimension of the channel layer 102 in the second region II is 55% to 95% of the lateral dimension of the channel layer 102 in the first region I.

[0069] Subsequently, the pseudo-gate structure 103 is replaced with a gate structure. The lateral dimension of the channel layer 102 in the second region II is smaller than the lateral dimension of the channel layer 102 below the gate structure in the first region I. When the semiconductor structure is working, the conduction current of the channel in the second region II is smaller than the conduction current of the channel in the first region I.

[0070] The method for forming the semiconductor structure further includes: after forming the trench 106 and before forming the source / drain doped layer, laterally etching the exposed sacrificial layer 101 of the trench 106 to form a sidewall groove (not shown in the figure); and forming an inner sidewall layer 110 in the sidewall groove.

[0071] The sidewall grooves in the first region I provide process space for forming the inner sidewall layer 110.

[0072] In this embodiment, a wet etching process is used to laterally etch the sacrificial layer 101 exposed in the trench 106 to form the sidewall groove. Wet etching is an isotropic etching process, which has a high etching rate, is simple to operate, and has low processing cost. In other embodiments, an isotropic dry etching process can also be used to laterally etch the sacrificial layer exposed in the trench to form the sidewall groove.

[0073] In this embodiment, the material of the sacrificial layer 101 is silicon germanide. Correspondingly, in the process of laterally etching the sacrificial layer 101 exposed by the trench 106 using a wet etching process, the wet etching solution used includes an HCl solution.

[0074] The inner wall layer 110 is used to reduce the capacitive coupling effect between the subsequently formed source / drain doped layers and the gate structure, thereby reducing parasitic capacitance and improving the electrical performance of the transistor structure.

[0075] In this embodiment, the inner wall layer 110 is made of a low-k dielectric material. Low-k dielectric materials (referring to dielectric materials with a relative permittivity greater than or equal to 2.6 and less than or equal to 3.9) have excellent insulating properties, reducing the electrical coupling effect between the gate structure and the source / drain doped layers subsequently formed on both sides of the inner wall layer 110, thereby reducing parasitic capacitance and improving the electrical performance of the transistor structure.

[0076] Specifically, the material of the inner wall layer 110 includes: SiON, SiBCN, SiCN, carbon-doped SiN, or oxygen-doped SiN. In this embodiment, the material of the inner wall layer 110 includes carbon-doped SiN or oxygen-doped SiN.

[0077] The method for forming the inner sidewall layer 110 includes: forming a sidewall material film (not shown in the figure) that conformally covers the pseudo-grid structure 103, the groove 106 and the sidewall groove; removing the sidewall material film from the bottom of the groove 106 and the sidewall of the pseudo-grid structure 103, and the remaining sidewall material layer located in the sidewall groove as the inner sidewall layer 110.

[0078] In this embodiment, the sidewall material film is formed using atomic layer deposition (ALD). ALD is a deposition process in which a vapor precursor is alternately pulsed into a reaction chamber, causing chemical adsorption and surface reaction on the substrate. Through ALD, the sidewall material film is formed in atomic layers on the surfaces of the pseudo-gate structure 103, trench 106, and sidewall recesses. This improves the uniformity of the deposition rate, the thickness uniformity of the sidewall material film, and the structural uniformity within the sidewall material film, while also providing good coverage. Furthermore, the process temperature of ALD is typically low, which helps reduce the thermal budget and lowers the probability of semiconductor structural performance deviation.

[0079] like Figure 9 As shown, a source / drain doped layer 114 is formed in the trench 106.

[0080] When the semiconductor structure is in operation, the source and drain doped layers 114 are used to provide stress to the channel, thereby increasing the migration rate of carriers in the channel.

[0081] In this embodiment, the first region I is used to form an NMOS, and the source / drain doped layer 114 serves as the source and drain of the NMOS. During semiconductor structure operation, the source / drain doped layer 114 applies tensile stress to the channel beneath the gate structure, which can increase the electron migration rate. The material of the source / drain doped layer 114 in the first region I includes silicon carbide or silicon phosphide doped with N-type ions. N-type ions include one or more of P, As, and Sb.

[0082] The second region II is used to form the PMOS, and the source / drain doped layer 114 of the second region II serves as the source and drain of the PMOS. During semiconductor structure operation, the source / drain doped layer applies compressive stress to the channel beneath the gate structure, which improves hole mobility. The material of the source / drain doped layer 114 of the second region II includes silicon germanide doped with P-type ions. The P-type ions include one or more of B, Ga, and In.

[0083] refer to Figures 10 to 12 , Figure 11 for Figure 10 Cross-sectional view at BB. Figure 12 for Figure 10 In the cross-sectional view at CC, the pseudo-gate structure 103 is removed, and a gate opening 116 is formed in the interlayer dielectric layer 115.

[0084] The gate opening 116 provides process space for the subsequent formation of the gate structure.

[0085] In this embodiment, a wet etching process is used to remove the dummy gate structure 103. The wet etching process has a high etching rate, is simple to operate, and has low processing costs.

[0086] In this embodiment, the dummy gate structure 103 includes a dummy gate oxide layer 1031 and a dummy gate layer 1032. The material of the dummy gate oxide layer 1031 is silicon oxide, and the material of the dummy gate layer 1032 is polysilicon. Specifically, in the step of removing the dummy gate structure 103, the etching solution used includes ammonia and tetramethylammonium hydroxide solution.

[0087] It should be noted that the lateral dimension of the gate opening 116 in the second region II is smaller than the lateral dimension of the gate opening 116 in the first region I. Accordingly, the lateral dimension of the gate structure subsequently formed in the gate opening 116 of the second region II is smaller than the lateral dimension of the gate structure in the gate opening 116 of the first region I.

[0088] refer to Figures 13 to 15 , Figure 15 for Figure 14 A cross-sectional view at CC, showing the removal of one or more of the channel layers 102 at the top of the channel stack 300.

[0089] In this embodiment of the invention, one or more channel layers 102 at the top of the channel stack 300 are removed, thereby reducing the number of channel layers 102 in the semiconductor structure. Consequently, when the semiconductor structure is operating, the overall on-state current of the channels in the semiconductor structure is reduced, enabling the semiconductor structure to meet process requirements. Subsequently, the sacrificial layer 101 between the remaining channel layers 102 is removed to form a channel. A gate structure is then formed in the gate opening and the channel. The formation space of the gate structure is larger, reducing the number of channel layers 102 that need to be controlled by the gate structure. When the semiconductor structure is operating, the gate structure has stronger control over the remaining channel layers 102, which helps to reduce the probability of channel leakage current and improve the electrical performance of the semiconductor structure.

[0090] In the step of removing one or more of the channel layers 102 at the top of the channel stack 300, one or more of the channel layers 102 in the second region II are removed. As a result, the number of remaining channel layers 102 in the second region II is less than the number of channel layers 102 in the first region I, such that the overall on-state current of the channels in the second region II is less than the overall on-state current of the channels in the first region I.

[0091] It should be noted that after removing one or more of the channel layers 102 at the top of the channel stack 300, the remaining channel layers 102 located at the bottom of the gate sidewall layer 105 serve as the end channel layer 119.

[0092] In this embodiment, the step of removing one or more of the channel layers 102 in the second region II includes: forming a mask layer 109 that covers the first region I and exposes the second region II; and removing one or more of the channel layers 102 in the second region II using the mask layer 109 as a mask.

[0093] The mask layer 109 is made of a material that is easy to remove, which can reduce damage to the formed film layer when the mask layer 109 is removed in the future.

[0094] In this embodiment, the material of the mask layer 109 includes: an organic material layer (not shown in the figure), an anti-reflective coating (not shown in the figure) located on the organic material layer, and a photoresist layer (not shown in the figure) located on the anti-reflective coating.

[0095] The organic material layer includes one or more of the following: SOC (spin on carbon) material, ODL (organic dielectric layer) material, DUO material, or APF (Advanced Patterning Film) material.

[0096] Anti-reflective coatings include BARC (bottom anti-reflective coating) materials or DARC (dielectric anti-reflective coating) materials.

[0097] In this embodiment, using the mask layer 109 as a mask, a wet etching process is employed to remove one of the channel layers 102 at the top of the channel stack 300. The wet etching process is isotropic etching, which has a high etching rate, is simple to operate, and has low process cost.

[0098] In this embodiment, the material of the channel layer 101 is silicon. Correspondingly, in the process of removing the exposed portion of the width of the channel layer 101 from the sidewall of the trench 106 by a wet etching process, the wet etching solution used includes tetramethylammonium hydroxide solution.

[0099] It should be noted that during the process of removing one of the channel layers 102 at the top of the channel stack 300 in the second region II using a wet etching process, the top surface and sidewalls of the top channel layer 102 are exposed in the gate opening 116, and the sidewalls of the remaining channel layer 102 are exposed in the gate opening 116. After removing the top one of the channel layers 102, the sidewalls of the remaining channel layers 102 in the second region II are slightly damaged.

[0100] In other embodiments, the mask layer can also be used as a mask, and a dry etching process can be employed to remove one or more of the channel layers at the top of the channel stack. During the dry etching process, by changing the etching gas during the etching of multiple channel layers, the channel layers and sacrificial layers can be etched in the same etching equipment, simplifying the process steps. The dry etching process has anisotropic etching characteristics, and during the removal of one or more channel layers at the top of the channel stack in the second region, it is less likely to damage the sidewalls of the remaining channel layers, which is beneficial to improving the morphology quality of the remaining channel layers in the second region. When the semiconductor structure is operating, the carrier migration rate in the channels of the second region is higher.

[0101] Specifically, in the process of removing one or more of the channel layers at the top of the channel stack using a dry etching process, the etching gases used include CF4, CHF3, or C2F6, etc.

[0102] In other embodiments, the method of forming the semiconductor structure further includes: after forming the mask layer, and before removing one or more channel layers on top of the channel stack in the second region, forming a masking layer in the second region that exposes one or more of the channel layers.

[0103] The shielding layer covers the channel layers that need to be retained in the second region, exposing the channel layers that need to be removed. During the removal of one or more channel layers at the top of the channel stack in the second region, the channel layers that need to be retained are less likely to be damaged, which helps to improve the morphology quality of the remaining channel layers in the second region. When the semiconductor structure is in operation, the carrier migration rate in the channels of the second region is higher.

[0104] The shielding layer includes an organic material layer.

[0105] In other embodiments, the shielding layer is removed after removing one or more of the channel layers on top of the channel stack.

[0106] The method for forming the semiconductor structure further includes removing one or more of the channel layers 101 on the top of the channel stack 300, and then removing the mask layer 109.

[0107] In this embodiment, an ashing process is used to remove the mask layer 109. After removing one or more of the channel layers 101 at the top of the channel stack 300, it is possible to avoid contamination of the machine by organic materials in the mask layer 109, and it also prepares for the subsequent removal of the sacrificial layer 102.

[0108] refer to Figure 16After removing one or more of the channel layers 102 at the top of the channel stack 300, the sacrificial layers 101 between the remaining channel layers 102 are removed to form a channel 117.

[0109] The channel 117 and the gate opening 116 together provide process space for the subsequent formation of the gate structure.

[0110] In this embodiment, a wet etching process is used to remove the sacrificial layer 101. The wet etching process has a high etching rate, is simple to operate, and has low processing costs.

[0111] Specifically, the sacrificial layer 101 is made of silicon germanide. Correspondingly, the etching solution used in the wet etching process to remove the sacrificial layer 101 is an HCl solution.

[0112] It should be noted that in the step of removing the sacrificial layer 101 between the remaining channel layers 102 to form the channel 117, the sacrificial layer 101 on top of the remaining channel layers 102.

[0113] refer to Figures 17 to 19 , Figure 18 for Figure 17 Cross-sectional view at DD Figure 19 for Figure 17 In the cross-sectional view at EE, a gate structure 118 is formed in the gate opening 116 and the channel 117.

[0114] When the semiconductor structure is in operation, the gate structure 118 is used to control the opening and closing of the channel.

[0115] The number of channel layers 102 in the second region II is less than the number of channel layers 102 in the first region I. As a result, when the semiconductor structure is working, the overall on-current of the channel in the second region II is less than the overall on-current of the channel in the first region I, enabling the semiconductor structure to meet process requirements. In addition, the number of channel layers 102 that need to be controlled by the gate structure 118 in the second region II is reduced. When the semiconductor structure is working, the gate structure 118 has a stronger control over the remaining channel layers 102, which helps to reduce the probability of channel leakage and improve the electrical performance of the semiconductor structure.

[0116] The gate structure 118 includes a work function layer and a gate layer located on the work function layer.

[0117] Specifically, the materials used in the work function layer of an NMOS include one or more of titanium aluminide, tantalum carbide, and titanium carbide. The materials used in the work function layer of a PMOS include one or more of titanium nitride, tantalum nitride, titanium carbide, silicon tantalum nitride, titanium silicon nitride, and tantalum carbide.

[0118] Specifically, the gate layer is made of one or more of magnesium-tungsten alloy, tungsten, copper, nickel, and titanium. In this embodiment, the gate layer is made of magnesium-tungsten alloy.

[0119] In this embodiment, the lateral dimension of the pseudo-gate structure 103 in the second region II is smaller than the lateral dimension of the pseudo-gate structure 103 in the first region I. Correspondingly, the lateral dimension of the gate structure 118 in the second region II is smaller than the lateral dimension of the gate structure 118 in the first region I. Since the lateral dimension of the channel layer 102 below the gate structure 118 in the second region II is smaller than the lateral dimension of the channel layer 102 below the gate structure 118 in the first region I, when the semiconductor structure is working, the conduction current of the channel in the second region II is smaller than the conduction current of the channel in the first region I.

[0120] In this embodiment, the lateral direction is defined as parallel to the surface of the substrate 100 and perpendicular to the extension direction of the gate structure 118. The lateral dimension of the gate structure 118 in the second region II is 55% to 95% of the lateral dimension of the gate structure 118 in the first region I.

[0121] The method for forming the semiconductor structure further includes: before forming the gate structure 118, forming a gate dielectric layer (not shown in the figure) in the channel 117 and the gate opening 116.

[0122] The gate dielectric layer is used to achieve electrical isolation between the gate structure 118 and the fin 112. It should be noted that the material of the gate dielectric layer is a high-k dielectric material. Here, a high-k dielectric material refers to a dielectric material with a relative permittivity greater than that of silicon oxide.

[0123] In this embodiment, the material of the gate dielectric layer is HfO2. In other embodiments, the material of the gate dielectric layer may also be selected from one or more of ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3.

[0124] Accordingly, embodiments of the present invention also provide a semiconductor structure. (See reference...) Figures 17 to 19 , Figure 18 for Figure 17 Cross-sectional view at DD Figure 19 for Figure 17 The cross-sectional view at EE shows a schematic diagram of an embodiment of the semiconductor structure of the present invention.

[0125] The semiconductor structure includes: a substrate 100, the substrate 100 including a first region I and a second region II; a plurality of channel layers 102, spaced apart and suspended on the substrate 100 in the normal direction of the surface of the substrate 100, wherein the number of channel layers 102 in the second region II is less than the number of channel layers 102 in the first region I; a gate structure 118 surrounding the channel layers 102; a gate sidewall layer 105 located on a sidewall above the channel layers 102 near the top of the gate structure 118; and one or more end channel layers 119 located between the gate sidewall layer 105 in the second region II and the topmost channel layer 102.

[0126] In the semiconductor structure provided by this embodiment of the invention, the number of channel layers 102 in the second region II is less than the number of channel layers 102 in the first region I. As a result, when the semiconductor structure is working, the overall on-current of the channel in the second region II is less than the overall on-current of the channel in the first region I, enabling the semiconductor structure to meet process requirements. In addition, the number of channel layers 102 in the second region II that need to be controlled by the gate structure 118 is reduced. When the semiconductor structure is working, the gate structure 118 has a stronger control capability over the channel layers 102 in the second region II than it has over the channel layers 102 in the first region I. This helps to reduce the probability of channel leakage in the second region II and improve the electrical performance of the semiconductor structure.

[0127] Substrate 100 is used to provide a process platform for forming semiconductor structures.

[0128] In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate material may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide, or other materials. The substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates.

[0129] It should be noted that in this embodiment, the first region I is used to form an NMOS (Negative Channel Metal Oxide Semiconductor), such as a pull-down transistor (PD), and the second region II is used to form a PMOS (Positive Channel Metal Oxide Semiconductor), such as a transmission gate transistor (PG) or a pull-up transistor (PU).

[0130] Specifically, the material of the channel layer 102 includes one or more of silicon, germanium, silicon germanide, silicon carbide, gallium arsenide, and indium gallium ionide. In this embodiment, the material of the channel layer 102 is silicon.

[0131] In this embodiment, the lateral dimension of the channel layer 102 in the second region II is smaller than the lateral dimension of the channel layer 102 below the gate structure 118 in the first region I. Accordingly, when the semiconductor structure is in operation, the on-current of the channel in the second region II is smaller than the on-current of the channel in the first region I.

[0132] It should be noted that, in the step of providing the substrate, with the lateral direction parallel to the surface of the substrate 100 and perpendicular to the extension direction of the gate structure 118 as the lateral direction, the ratio of the lateral dimension of the channel layer 102 of the second region II to the lateral dimension of the channel layer 102 of the first region I should not be too large or too small. Typically, the semiconductor structure is used to form an SRAM device. Specifically, the first region I is used to form a pull-down transistor, and the second region II is used to form a transmission gate transistor or a pull-up transistor. If the ratio is too large, during semiconductor structure operation, the conduction current of the channel in the second region II will be approximately the same as the conduction current in the first region I, which cannot significantly improve the stability of the SRAM device's read and write speeds. If the ratio is too small, during semiconductor structure operation, the conduction current of the channel in the second region II will be too small compared to the conduction current in the first region I, meaning the conduction current in the transmission gate transistor will be too small, limiting the read and write speeds of the SRAM device. In this embodiment, during the step of providing the substrate, the lateral dimension of the channel layer 102 in the second region II is 55% to 95% of the lateral dimension of the channel layer 102 in the first region I, with the lateral dimension being parallel to the surface of the substrate 100 and perpendicular to the extension direction of the gate structure 118.

[0133] It should also be noted that the semiconductor structure further includes: a fin 112 protruding from the substrate 100 and located between the substrate 100 and the channel stack; an isolation layer 113 located on the substrate 100 exposed by the fin 112; and a gate structure 118 located on the isolation layer 113, the gate structure 118 spanning the fin 112 and covering part of the top wall and part of the side wall of the fin 112.

[0134] The fin 112 protrudes from the substrate 100, and the side of the fin 112 provides process space for the isolation layer 113.

[0135] In this embodiment, the material of the fin 112 is the same as the material of the substrate 100. In other embodiments, the material of the fin may be different from the material of the substrate.

[0136] The isolation layer 113 provides electrical isolation between the gate structure 118 and the substrate 100, and also provides electrical isolation between the various fins 112.

[0137] In this embodiment, the material of the isolation layer 113 is a dielectric material. Specifically, the material of the isolation layer 113 includes silicon oxide. Silicon oxide is a commonly used and low-cost dielectric material with high process compatibility, which helps to reduce the process difficulty and cost of forming the isolation layer 113.

[0138] When the semiconductor structure is in operation, the gate structure 118 is used to control the opening and closing of the channel.

[0139] The gate structure 118 includes a work function layer and a gate layer located on the work function layer.

[0140] Specifically, the materials used in the work function layer of an NMOS include one or more of titanium aluminide, tantalum carbide, and titanium carbide. The materials used in the work function layer of a PMOS include one or more of titanium nitride, tantalum nitride, titanium carbide, silicon tantalum nitride, titanium silicon nitride, and tantalum carbide.

[0141] Specifically, the gate layer is made of one or more of magnesium-tungsten alloy, tungsten, copper, nickel, and titanium. In this embodiment, the gate layer is made of magnesium-tungsten alloy.

[0142] In this embodiment, the gate structure 118 completely surrounds the channel layer 102. The lateral dimension of the channel layer 102 in the second region II is smaller than that in the first region I, and correspondingly, the lateral dimension of the gate structure 118 in the second region II is smaller than that in the first region I. When the semiconductor structure is working, the on-current of the channel in the second region II is smaller than that in the first region I.

[0143] In this embodiment, the lateral direction is defined as parallel to the surface of the substrate 100 and perpendicular to the extension direction of the gate structure 118. The lateral dimension of the gate structure 118 in the second region II is 55% to 95% of the lateral dimension of the gate structure 118 in the first region I.

[0144] During the formation of the semiconductor structure, the gate sidewall layer 105 is used to protect the sidewalls of the gate structure 118 from damage.

[0145] The material of the gate sidewall layer 105 includes one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, boron nitride, silicon boron nitride, and silicon boron carbide.

[0146] The semiconductor structure further includes: source and drain doped layers 114, which are discretely disposed on the substrate 100 and are lateral, parallel to the surface of the substrate 100 and perpendicular to the extension direction of the gate structure 118, and the source and drain doped layers 114 are located at both ends of the lateral direction of the channel layer 102.

[0147] When the semiconductor structure is in operation, the source and drain doped layers 114 are used to provide stress to the channel in the channel layer 102, thereby increasing the migration rate of charge carriers in the channel.

[0148] In this embodiment, the first region I is used to form an NMOS, and the source / drain doped layer 114 serves as the source and drain of the NMOS. During semiconductor structure operation, the source / drain doped layer 114 applies tensile stress to the channel beneath the gate structure, which can increase the electron migration rate. The material of the source / drain doped layer 114 in the first region I includes silicon carbide or silicon phosphide doped with N-type ions. N-type ions include one or more of P, As, and Sb.

[0149] The second region II is used to form the PMOS, and the source / drain doped layer 114 of the second region II serves as the source and drain of the PMOS. During semiconductor structure operation, the source / drain doped layer applies compressive stress to the channel beneath the gate structure, which improves hole mobility. The material of the source / drain doped layer 114 of the second region II includes silicon germanide doped with P-type ions. The P-type ions include one or more of B, Ga, and In.

[0150] In this embodiment, the source / drain doped layers 114 in the first region I and the second region II are formed simultaneously, and the formation conditions of the source / drain doped layers 114 in the first region I and the second region II are the same. Accordingly, the thickness of the source / drain doped layer 114 in the first region I is equal to the thickness of the source / drain doped layer 114 in the second region II.

[0151] The semiconductor structure further includes an interlayer dielectric layer 115, which covers the sidewalls of the gate structure 118 and exposes the top of the gate structure.

[0152] The interlayer dielectric layer 115 is used for electrical isolation of adjacent devices. The material of the interlayer dielectric layer 115 is an insulating material. Specifically, the material of the interlayer dielectric layer 115 includes silicon oxide. Silicon oxide is a commonly used and low-cost dielectric material with high process compatibility, which helps to reduce the process difficulty and cost of forming the interlayer dielectric layer 115.

[0153] One or more end channel layers 119 are located between the gate sidewall layer 105 and the topmost channel layer 102 in the second region II. In this embodiment, only one end channel layer 119 is illustrated.

[0154] During the formation of the semiconductor structure, the first region I and the second region II have the same number of channel layers 102. One or more of the channel layers 102 exposed by etching the gate sidewall layer 105 of the second region II are formed. One or more end channel layers 119 are formed directly below the gate sidewall layer 105. The number of channel layers 102 in the second region II is less than the number of channel layers 102 in the first region I. When the semiconductor structure is working, the conduction current in the second region is less than the conduction current in the first region.

[0155] The semiconductor structure further includes an inner sidewall layer 110 located between the source / drain doped layer 114 and the gate structure 118.

[0156] The inner wall layer 110 is used to reduce the capacitive coupling effect between the source / drain doped layer 114 and the gate structure 118, thereby reducing parasitic capacitance and improving the electrical performance of the transistor structure.

[0157] Correspondingly, the inner wall layer 110 is also located between the end channel layers 119, or between the end channel layers 119 and the channel layers 102, or between the channel layers 102.

[0158] In this embodiment, the inner wall layer 110 is made of a low-k dielectric material. Low-k dielectric materials (referring to dielectric materials with a relative permittivity greater than or equal to 2.6 and less than or equal to 3.9) have excellent insulating properties. This reduces the capacitive coupling effect between the source / drain doped layers 114 and the gate structure 118, thereby reducing parasitic capacitance and improving the electrical performance of the transistor structure.

[0159] Specifically, the material of the inner wall layer 110 includes: SiON, SiBCN, SiCN, carbon-doped SiN, or oxygen-doped SiN. In this embodiment, the material of the inner wall layer 110 includes carbon-doped SiN or oxygen-doped SiN.

[0160] Accordingly, embodiments of the present invention also provide an SRAM device. A schematic diagram of an embodiment of the SRAM device of the present invention is shown.

[0161] The SRAM device includes the semiconductor structure described above, the semiconductor structure comprising: a substrate including a first region and a second region; a plurality of channel layers spaced apart on the substrate in the normal direction of the substrate surface, wherein the number of channel layers in the second region is less than the number of channel layers in the first region; a gate structure surrounding the channel layers; a gate sidewall layer located on the sidewall of the gate structure at the top of the channel layers; and one or more end channel layers located between the gate sidewall layer in the second region and the topmost channel layer.

[0162] The first region I includes a pull-down transistor (PD); the second region II includes a pass-gate transistor (PG) or a pull-up transistor (PD).

[0163] The number of channel layers 102 of the pull-down transistor is greater than the number of channel layers 102 of the transmission gate transistor or the pull-up transistor. Consequently, when the SRAM device is working, the on-current of the pull-down transistor is greater than the on-current of the transmission gate transistor or the pull-up transistor. This results in higher stability of the SRAM device and makes it less susceptible to interference. Specifically, the on-current of the pull-down transistor being greater than the on-current of the transmission gate transistor is beneficial to improving the stability of SRAM device read operations; the on-current of the pull-down transistor being greater than the on-current of the pull-up transistor is beneficial to improving the write speed of the SRAM device.

[0164] In this embodiment, the SRAM device is a six-transistor SRAM (6T-SRAM).

[0165] Specifically, in this embodiment, the number of channel layers 102 of the pull-down transistor is three; the number of channel layers of the transmission gate transistor is two; and the number of channel layers 102 of the pull-up transistor is one, or the number of channel layers 102 of the transmission gate transistor is one; and the number of channel layers 102 of the pull-up transistor is two.

[0166] In this embodiment, the lateral dimension of the channel layer 102 in the second region II is smaller than the lateral dimension of the channel layer 102 in the first region I. Accordingly, when the semiconductor structure is operating, the on-state current of the channel in the second region II is smaller than the on-state current of the channel in the first region I.

[0167] It should be noted that, in the step of providing the substrate, with the lateral direction parallel to the surface of the substrate 100 and perpendicular to the extension direction of the gate structure 118 as the lateral direction, the ratio of the lateral dimension of the channel layer 102 of the second region II to the lateral dimension of the channel layer 102 of the first region I should not be too large or too small. Typically, the semiconductor structure is used to form an SRAM device. Specifically, the first region I is used to form a pull-down transistor, and the second region II is used to form a transmission gate transistor or a pull-up transistor. If the ratio is too large, during semiconductor structure operation, the conduction current of the channel in the second region II will be approximately the same as the conduction current in the first region I, which cannot significantly improve the stability of the SRAM device's read and write speeds. If the ratio is too small, during semiconductor structure operation, the conduction current of the channel in the second region II will be too small compared to the conduction current in the first region I, meaning the conduction current in the transmission gate transistor will be too small, limiting the read and write speeds of the SRAM device. In this embodiment, during the step of providing the substrate, the lateral dimension of the channel layer 102 in the second region II is 55% to 95% of the lateral dimension of the channel layer 102 in the first region I, with the lateral dimension being parallel to the surface of the substrate 100 and perpendicular to the extension direction of the gate structure 118.

[0168] In this embodiment, the lateral direction is defined as parallel to the surface of the substrate 100 and perpendicular to the extending direction of the gate structure 118. The lateral dimension of the gate structure 118 in the second region II is 55% to 95% of the lateral dimension of the gate structure 118 in the first region I. Specific advantages are described in the semiconductor structure section and will not be repeated here.

[0169] The semiconductor structure can be formed using the formation method of the foregoing embodiments, or it can be formed using other formation methods. For a detailed description of the semiconductor structure of this embodiment, please refer to the corresponding descriptions in the foregoing embodiments; these descriptions will not be repeated here.

[0170] While the embodiments of the present invention have been disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the embodiments of the present invention. Therefore, the scope of protection of the embodiments of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a substrate, a plurality of channel stacks discrete on the substrate, and a pseudo-gate structure spanning the plurality of channel stacks, the pseudo-gate structure covering a portion of the top wall and a portion of the sidewall of the channel stacks, the channel stacks including a sacrificial layer and a channel layer located on the sacrificial layer; In the step of providing a substrate, the substrate includes a first region and a second region; A sidewall is formed to cover the pseudo-gate structure, exposing the interlayer dielectric layer at the top of the pseudo-gate structure; Remove the dummy gate structure and form a gate opening in the interlayer dielectric layer; Remove one or more of the channel layers at the top of the channel stack; In the step of removing one or more of the channel layers at the top of the channel stack, one or more of the channel layers in the second region are removed, wherein the number of channel layers in the second region is less than the number of channel layers in the first region; After removing one or more of the channel layers at the top of the channel stack, the sacrificial layers between the remaining channel layers are removed to form a channel; A gate structure is formed in the gate opening and channel.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of providing the substrate, the lateral direction is parallel to the substrate surface and perpendicular to the extension direction of the pseudo-gate structure, and the lateral dimension of the pseudo-gate structure in the second region is 55% to 95% of the lateral dimension of the pseudo-gate structure in the first region.

3. The method for forming a semiconductor structure as described in claim 1, characterized in that, The step of removing one or more of the channel layers in the second region includes: forming a mask layer that covers the first region and exposes the second region; and removing one or more of the channel layers in the second region using the mask layer as a mask. The method for forming the semiconductor structure further includes: removing one or more of the channel layers on top of the channel stack, and then removing the mask layer.

4. The method for forming a semiconductor structure as described in claim 3, characterized in that, The mask layer includes: an organic material layer, an anti-reflective coating on the organic material layer, and a photoresist layer on the anti-reflective coating.

5. The method for forming a semiconductor structure as described in claim 3, characterized in that, The method of forming the semiconductor structure includes: after forming the mask layer, and before removing one or more trench layers on top of the trench stack in the second region, forming a masking layer in the second region that exposes one or more of the trench layers; The method for forming the semiconductor structure further includes: removing one or more of the channel layers on top of the channel stack, and then removing the shielding layer.

6. The method for forming a semiconductor structure as described in claim 5, characterized in that, The shielding layer includes an organic material layer.

7. The method for forming a semiconductor structure as described in claim 1, characterized in that, One of the trench layers at the top of the trench stack is removed using a wet etching process.

8. The method for forming a semiconductor structure as described in claim 7, characterized in that, The wet etching solution includes a tetramethylammonium hydroxide solution.

9. The method for forming a semiconductor structure as described in claim 1, characterized in that, One or more of the channel layers at the top of the channel stack are removed using a dry etching process.

10. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method for forming the semiconductor structure further includes: after providing the substrate and before forming the interlayer dielectric layer, etching the channel stack on both sides of the dummy gate structure to form a trench in the channel stack; Source and drain doped layers are formed in the trench.

11. The method for forming a semiconductor structure as described in claim 10, characterized in that, The lateral direction is parallel to the substrate surface and perpendicular to the extension direction of the pseudo-gate structure; The method for forming the semiconductor structure further includes: after forming the trench and before forming the source / drain doped layer, laterally etching the sacrificial layer exposed by the trench to form a sidewall groove; and forming an inner sidewall layer in the sidewall groove.

12. The method for forming a semiconductor structure as described in claim 10, characterized in that, In the step of forming the trench, the lateral direction is parallel to the substrate surface and perpendicular to the extension direction of the pseudo-gate structure, and the lateral dimension of the trench layer in the second region is 55% to 95% of the lateral dimension of the trench layer in the first region.

13. The method for forming a semiconductor structure as described in claim 10, characterized in that, In the step of providing the substrate, the substrate further includes: a fin located between the substrate and the channel stack; An isolation layer is located on the substrate exposed by the fin, and the isolation layer covers a portion of the sidewall of the fin; The pseudo-gate structure is located on the isolation layer, spans the fin, and covers part of the top wall and part of the side wall of the fin.

14. A semiconductor structure, characterized in that, include: A substrate, the substrate comprising a first region and a second region; Multiple channel layers are spaced apart and suspended on the substrate in the direction normal to the substrate surface, and the number of channel layers in the second region is less than the number of channel layers in the first region; A gate structure surrounds the channel layer; A gate sidewall layer is located on a sidewall above the channel layer near the top of the gate structure; One or more end channel layers are located between the gate sidewall layer and the topmost channel layer in the second region, and the one or more end channel layers are located directly below the gate sidewall layer.

15. The semiconductor structure as described in claim 14, characterized in that, The semiconductor structure further includes: source and drain doped layers, which are discretely disposed on the substrate and are arranged laterally parallel to the surface of the substrate and perpendicular to the extension direction of the gate structure, and the source and drain doped layers are located at both ends of the channel layer laterally.

16. The semiconductor structure as claimed in claim 15, characterized in that, The semiconductor structure further includes: an inner sidewall layer located between the source / drain doped layers and the gate structure, and located between the end channel layers, or between the end channel layers and the channel layers, or between the channel layers.

17. The semiconductor structure as claimed in claim 15, characterized in that, The thickness of the source / drain doped layer in the first region is equal to the thickness of the source / drain doped layer in the second region.

18. The semiconductor structure as claimed in claim 15, characterized in that, The first region is an NMOS, and the material of the source and drain doped layer of the first region includes: silicon carbide or silicon phosphide doped with N-type ions, wherein the N-type ions include one or more of P, As and Sb. The second region is a PMOS, and the material of the source and drain doped layer of the second region includes silicon germanide doped with P-type ions, wherein the P-type ions include one or more of B, Ga and In.

19. The semiconductor structure as claimed in claim 14, characterized in that, The semiconductor structure further includes: fins located between the substrate and the plurality of channel layers; An isolation layer is located on the substrate on the side of the fin, and the isolation layer covers a portion of the sidewall of the fin; The gate structure is located on the isolation layer, and the gate structure spans the fin and covers part of the top wall and part of the side wall of the fin.

20. The semiconductor structure as claimed in claim 14, characterized in that, The material of the channel layer includes one or more of silicon, germanium, silicon germanide, silicon carbide, gallium arsenide, and indium gallium.

21. The semiconductor structure as described in claim 14, characterized in that, The gate structure includes a work function layer and a gate layer located on the work function layer; The first region is an NMOS, and the material of the work function layer in the NMOS includes one or more of titanium aluminide, tantalum carbide, and titanium carbide; the second region is a PMOS, and the material of the work function layer in the PMOS includes one or more of titanium nitride, tantalum nitride, titanium carbide, silicon tantalum nitride, silicon titanium nitride, and tantalum carbide. The gate layer is made of one or more of magnesium-tungsten alloy, tungsten, copper, nickel, and titanium.

22. The semiconductor structure as described in claim 14, characterized in that, The lateral direction is defined as the direction parallel to the substrate surface and perpendicular to the extension direction of the gate structure. The lateral dimension of the channel layer in the second region is 55% to 95% of the lateral dimension of the channel layer in the first region.

23. The semiconductor structure as described in claim 14, characterized in that, The lateral direction is defined as the direction parallel to the substrate surface and perpendicular to the extension direction of the gate structure. The lateral dimension of the gate structure in the second region is 55% to 95% of the lateral dimension of the gate structure in the first region.

24. An SRAM device comprising a semiconductor structure, said semiconductor structure comprising: A substrate, the substrate comprising a first region and a second region; Multiple channel layers are spaced apart and suspended on the substrate in the direction normal to the substrate surface, and the number of channel layers in the second region is less than the number of channel layers in the first region; A gate structure surrounds the channel layer; A gate sidewall layer is located on the sidewall of the gate structure at the top of the channel layer; One or more end channel layers are located between the gate sidewall layer and the topmost channel layer in the second region, and the one or more end channel layers are located directly below the gate sidewall layer; Its features include: The first region includes a pull-down transistor; The second region includes a transmission gate transistor or a pull-up transistor.

25. The SRAM device as claimed in claim 24, characterized in that, The pull-down transistor has three channel layers, the transmission gate transistor has two channel layers, and the pull-up transistor has one channel layer. or, The pull-down transistor has three channel layers, the transmission gate transistor has one channel layer, and the pull-up transistor has two channel layers.

26. The SRAM device as claimed in claim 24, characterized in that, The lateral direction is defined as the direction parallel to the substrate surface and perpendicular to the extension direction of the gate structure. The lateral dimension of the channel layer in the second region is 55% to 95% of the dimension of the first region.

27. The SRAM device as claimed in claim 24, characterized in that, The lateral direction is defined as the direction parallel to the substrate surface and perpendicular to the extension direction of the gate structure. The lateral dimension of the gate structure in the second region is 55% to 95% of the lateral dimension of the gate structure in the first region.

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