NPN triode type anti-static protection device and implementation method thereof

Abstract

The application discloses an NPN triode type anti-static protection device and an implementation method thereof. The method increases high-concentration N type doping (24) in a P well (30) to strengthen the isolation of an N well (20), connects and leads out electrodes to form a cathode of the device by connecting and leading out electrodes of high-concentration P type doping (26) and high-concentration N type doping (24) of the P well (30), and leads out electrodes to form an anode of the device by leading out electrodes of high-concentration N type doping (22) of the N well (20), so that the NPN triode type anti-static protection device is obtained.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor integrated circuits, in particular to an NPN triode type anti-static protection device and a method for implementing the same. BACKGROUND

[0002] Currently, an 8V IO port needs to be used in a certain high-voltage process platform, and the gate oxide layer thickness of the 8V IO device is 215A, so the anti-static protection design window thereof is 9V~43V. However, the hysteresis effect curve of the 8V GGNMOS device in the actual high-voltage process platform is as follows Figure 1 From the hysteresis effect curve, it can be concluded that the trigger voltage Vt1 thereof is about 11.8V (the right lower corner point of the right curve), and the holding voltage Vh thereof is only about 7.9V (the left lower corner point of the right curve), which is lower than 9V. Therefore, the 8V GGNMOS device cannot be directly applied to the anti-static protection design of the 8V IO port.

[0003] Under the same process condition, the GGNMOS (Gate Grounded N-Channel Metal Oxide Semiconductor) type ESD device with a larger gate length has a smaller current gain due to a larger base width of the parasitic NPN triode, so the holding voltage Vh of the hysteresis effect of the GGNMOS type ESD device with a larger gate length is also larger, Figure 2 The relationship curve between the holding voltage and the gate length of the actual 8V GGNMOS type ESD device obtained in the certain high-voltage process platform is as follows Figure 2 Fitting formula The calculation can conclude that when x=2.0825, y=9, that is, when the gate length is at least increased to 1.8~2µm, the holding voltage Vh can be greater than 9V. However, when the gate length is too long, the current driving capability of the 8V GGNMOS type ESD device will be too low, so the industry generally does not use the way of increasing the gate length to increase the holding voltage Vh of the hysteresis effect. Therefore, it is necessary to find a new ESD device which is suitable for the anti-static protection design of the 8V IO port. SUMMARY

[0004] In order to overcome the deficiencies of the prior art, the purpose of the present application is to provide an NPN triode type anti-static protection device and a method for implementing the same, so as to realize an ESD device which is completely suitable for the anti-static protection design of the 8V IO port of a certain high-voltage process platform.

[0005] In order to achieve the above and other purposes, the present application provides an NPN triode type anti-static protection device, which comprises:

[0006] a semiconductor substrate (80);

[0007] N-well (20) and P-well (30) are formed on the semiconductor substrate (80);

[0008] A shallow trench isolation layer (10) is formed on the interface of the N-well (20) and the P-well (30), a high-concentration N-type doping (22) is formed on the N-well (20) near the shallow trench isolation layer (10), a high-concentration N-type doping (24) is formed on the P-well (30) near the shallow trench isolation layer (10), and a high-concentration P-type doping (26) is formed on the P-well (30) at a distance from the high-concentration N-type doping (24);

[0009] Metal silicide (40) is formed on the high-concentration N-type doping (22), on the high-concentration N-type doping (24), and on the high-concentration P-type doping (26), respectively;

[0010] The metal silicide (40) on the high-concentration N-type doping (22) forms an anode of the NPN transistor type anti-static protection device, and the metal silicide (40) on the high-concentration N-type doping (24) and the metal silicide (40) on the high-concentration P-type doping (26) are connected and form a cathode of the NPN transistor type anti-static protection device.

[0011] Preferably, the width of the shallow trench isolation layer (10) in the N-well (20) is a, and the width of the shallow trench isolation layer (10) in the P-well (30) is b.

[0012] Preferably, the width a of the shallow trench isolation layer (10) in the N-well (20) and the width b of the shallow trench isolation layer (10) in the P-well (30) determine the trigger voltage of the NPN transistor type anti-static protection device.

[0013] Preferably, the width b of the shallow trench isolation layer (10) in the P-well (30) determines the holding voltage of the NPN transistor type anti-static protection device.

[0014] Preferably, the width of the high-concentration N-type doping (22) is W1.

[0015] Preferably, the width of the high-concentration N-type doping (24) is W2.

[0016] Preferably, the width of the high-concentration P-type doping (26) is W3.

[0017] Preferably, the semiconductor substrate (80) is a P-type substrate.

[0018] To achieve the above object, the application further provides an implementation method of the NPN triode type anti-static protection device, which comprises the following steps: adding high-concentration N-type doping (24) in a P well (30) to strengthen the isolation of an N well (20), connecting and leading out electrodes of high-concentration P-type doping (26) and high-concentration N-type doping (24) of the P well (30) to form a cathode of the device, and leading out electrodes of high-concentration N-type doping (22) of the N well (20) to form an anode of the device, so as to obtain the NPN triode type anti-static protection device.

[0019] Preferably, the method comprises:

[0020] Step S1, providing a semiconductor substrate (80);

[0021] Step S2, generating an N well (20) and a P well (30) on the semiconductor substrate (80);

[0022] Step S3, generating a shallow trench isolation layer (10) on an upper portion of an interface between the N well (20) and the P well (30), generating high-concentration N-type doping (22) on an upper portion of the N well (20) close to the shallow trench isolation layer (10), generating high-concentration N-type doping (24) on an upper portion of the P well (30) close to the shallow trench isolation layer (10), and generating high-concentration P-type doping (26) on an upper portion of the P well (30) at a distance from the high-concentration N-type doping (24);

[0023] Step S4, generating metal silicide (40) above the high-concentration N-type doping (22), above the high-concentration N-type doping (24) and above the high-concentration P-type doping (26), respectively;

[0024] Step S5, leading out electrodes of the metal silicide (40) above the high-concentration N-type doping (22) to form an anode of the NPN triode type anti-static protection device, and connecting and leading out electrodes of the metal silicide (40) above the high-concentration N-type doping (24) and the metal silicide (40) above the high-concentration P-type doping (26) to form a cathode of the NPN triode type anti-static protection device.

[0025] Compared with the prior art, the NPN triode type anti-static protection device and the implementation method thereof can strengthen the isolation of the N well (N-Well) 20 by adding high-concentration N-type doping (N+) 24 in the P well (P-Well) 30, and connect the outpoint P-type doping (P+) 26 of the P-Well 30 and the N-type doping (N+) 24 and lead out the electrode to form the cathode of the ESD device, and the outpoint N-type doping (N+) 22 of the N-Well 20 is led out to form the anode of the ESD device, so that the ESD device suitable for the anti-static protection design of the 8V IO port of a high-voltage process platform is realized. BRIEF DESCRIPTION OF DRAWINGS

[0026] Figure 1 It is a 1.2V GGNMOS hysteresis effect characteristic curve of a 55LP process platform of a company;

[0027] Figure 2 It is a structure diagram of a prior art gate-grounded NMOS type ESD device;

[0028] Figure 3 It is a device structure diagram of a preferred embodiment of the NPN triode type anti-static protection device of the application;

[0029] Figure 4 It is a relationship diagram of the hysteresis effect trigger voltage and the a / b of the NPN triode type anti-static protection device of the application

[0030] Figure 5 It is a step flow chart of the implementation method of the NPN triode type anti-static protection device of the application;

[0031] Figure 6 It is a schematic diagram of the application scenario of the application. DETAILED DESCRIPTION

[0032] The embodiments of the application are described below by specific concrete examples and in conjunction with the drawings, and other advantages and effects of the application can be easily understood by those skilled in the art from the content disclosed in the specification. The application can also be implemented or applied by other different specific examples, and each detail in the specification can be modified and changed in various ways based on different views and applications without departing from the spirit of the application.

[0033] Figure 3 It is a device structure diagram of a preferred embodiment of the NPN triode type anti-static protection device of the application. As Figure 3As shown, the NPN transistor type anti-static protection device of the present application comprises: a shallow trench isolation layer (STI) 10, a high concentration N-type doping (N+) 22, a high concentration N-type doping (N+) 24, a high concentration P-type doping (P+) 26, an N well (N-Well) 20, a P well (P-Well) 30, a P-type substrate (P-Sub) 80, and a plurality of metal silicides (Silicide) 40 connecting the doping regions and electrodes.

[0034] The entire NPN transistor type anti-static protection (ESD) device is placed on the P-type substrate (P-Sub) 80, an N well (N-Well) 20 is generated on one side of the P-type substrate (P-Sub) 80, a P well (P-Well) 30 is generated on the other side of the P-type substrate (P-Sub) 80, and a shallow trench isolation layer (STI) 10 is generated on the upper part of the interface between the N well (N-Well) 20 and the P well (P-Well) 30. The width of the shallow trench isolation layer (STI) 10 in the N well (N-Well) 20 is a, the width of the shallow trench isolation layer (STI) 10 in the P well (P-Well) 30 is b, and the parameters a and b determine the trigger voltage (Vt1) of the NPN transistor type anti-static protection device of the present application, while b determines the holding voltage (Vh) of the NPN transistor type anti-static protection device of the present application. In the specific embodiment of the present application, the parameter a and b have a value range of 0.2-2µm. The high concentration N-type doping (N+) 22 is placed on the upper part of the N well (N-Well) 20 close to the shallow trench isolation layer (STI) 10, and the width of the high concentration N-type doping (N+) 22 is W1. The high concentration N-type doping (N+) 24 is placed on the upper part of the P well (P-Well) 30 close to the shallow trench isolation layer (STI) 10, and the width of the high concentration N-type doping (N+) 24 is W2. The high concentration P-type doping (P+) 26 is placed on the upper part of the P well (P-Well) 30, and the distance between the high concentration P-type doping (P+) 26 and the high concentration N-type doping (N+) 24 is c. The width of the high concentration P-type doping (P+) 26 is W3.

[0035] Specifically, one side of the high-concentration N-type doped (N+) 22 is connected to one side of the shallow trench isolation layer (STI) 10, and one side of the high-concentration N-type doped (N+) 24 is connected to the other side of the shallow trench isolation layer (STI) 10. The other side of the high-concentration N-type doped (N+) 24 is part of the P-well 30, and the distance from this side to the side closer to the high-concentration P-type doped (P+) 26 is c, that is, the width of the P-well 30 between the high-concentration N-type doped (N+) 24 and the high-concentration P-type doped (P+) 26 is c; the other side of the high-concentration N-type doped (N+) 22 is part of the N-well 20, and the other side of the high-concentration P-type doped (P+) 26 is part of the P-well 30.

[0036] Metal silicides 40 are generated above high-concentration N-type dopant (N+) 22, high-concentration N-type dopant (N+) 24, and high-concentration P-type dopant (P+) 26, respectively.

[0037] The metal silicide 40 above the high-concentration N-type doped (N+) 22 leads out an electrode to form the anode of the NPN transistor-type ESD device of the present invention. The metal silicide 40 above the high-concentration N-type doped (N+) 24 is connected to the metal silicide 40 above the high-concentration P-type doped (P+) 26 and leads out an electrode to form the cathode of the NPN transistor-type anti-static protection device of the present invention.

[0038] Based on existing isolation structures, this invention proposes the following... Figure 3 The NPN transistor-type ESD device shown is composed of Figure 3 As can be seen, the NPN transistor-type ESD device of the present invention adds a high concentration of N-type dopant (N+) 24 to the P-well 30 to enhance the isolation of the N-well 20, and connects the P-type dopant (P+) 26 and the N-type dopant (N+) 24 at the junction of the P-well 30 and leads out an electrode to form the cathode of the ESD device, while leading out the N-type dopant (N+) 22 at the junction of the N-well 20 to form the anode of the ESD device. According to the hysteresis effect curve of the NPN transistor-type anti-static protection device according to the embodiment of the present invention, the NPN transistor-type ESD device of the present invention is fully applicable to the anti-static protection design of the 8V IO port of a high-voltage process platform.

[0039] Figure 4The a / b relationship graph of the NPN triode type anti-static protection device of the present application is shown in the figure, the lower square line is the holding voltage Vh, the upper diamond line is the trigger voltage Vt1, with the increase of a / b, the holding voltage Vh of the esd device of the present application rises, and when a / b=0.4, it reaches saturation, the peak value of the holding voltage is 17.6V, which fully meets the anti-static design of 8V IO port.

[0040] Figure 5 The step flow chart of the implementation method of the NPN triode type anti-static protection device of the present application is shown in the figure. Figure 5 The implementation method of the NPN triode type anti-static protection device of the present application comprises the following steps:

[0041] Step S1, a semiconductor substrate is provided, in the specific embodiment of the present application, a P-type substrate (P-Sub) 80 is provided.

[0042] Step S2, an N well (N-Well) 20 and a P well (P-Well) 30 are generated on the P-type substrate (P-Sub) 80. Specifically, an N well (N-Well) 20 is generated on one side of the P-type substrate (P-Sub) 80, and a P well (P-Well) 30 is generated on the other side of the P-type substrate (P-Sub) 80.

[0043] Step S3, a shallow trench isolation layer (STI, Shallow Trench Isolation) 10 is generated at the interface of the N well (N-Well) 20 and the P well (P-Well) 30, a high-concentration N-type doping (N+) 22 is generated on the upper part of the N well (N-Well) 20 close to the shallow trench isolation layer (STI, Shallow Trench Isolation) 10, a high-concentration N-type doping (N+) 24 is generated on the upper part of the P well (P-Well) 30 close to the shallow trench isolation layer (STI, Shallow Trench Isolation) 10, and a high-concentration P-type doping (P+) 26 is generated on the upper part of the P well (P-Well) 30 at a distance c from the high-concentration N-type doping (N+) 24.

[0044] Specifically, the shallow trench isolation (STI) 10 has a width of a in the N-well 20 and a width of b in the P-well 30, where the parameters a and b determine the trigger voltage (Vt1) of the NPN transistor type electrostatic discharge protection device, and the parameter b determines the holding voltage (Vh) of the NPN transistor type electrostatic discharge protection device. The high-concentration N-type doping (N+) 22 is arranged on the upper portion of the N-well 20 close to the shallow trench isolation (STI) 10, and has a width of W1; the high-concentration N-type doping (N+) 24 is arranged on the upper portion of the P-well 30 close to the shallow trench isolation (STI) 10, and has a width of W2; the high-concentration P-type doping (P+) 26 is arranged on the upper portion of the P-well 30 at a distance of c from the high-concentration N-type doping (N+) 24, and has a width of W3.

[0045] In step S4, metal silicides 40 are formed above the high-concentration N-type doping (N+) 22, above the high-concentration N-type doping (N+) 24, and above the high-concentration P-type doping (P+) 26.

[0046] In step S5, the metal silicide 40 above the high-concentration N-type doping (N+) 22 is used as an anode Anode of the NPN transistor type ESD device, and the metal silicide 40 above the high-concentration N-type doping (N+) 24 is connected to the metal silicide 40 above the high-concentration P-type doping (P+) 26 and used as a cathode Cathode of the NPN transistor type electrostatic discharge protection device.

[0047] In application, the NPN transistor type ESD device can be connected between an IO terminal and ground for IO protection, where the positive electrode Anode is connected to the IO terminal, and the negative electrode Cathode is connected to ground (Vss). The NPN transistor type ESD device can also be connected between a power supply and ground for power clamp, where the positive electrode Anode is connected to the positive terminal of the power supply (Vdd), and the negative electrode Cathode is connected to ground (Vss), as shown in FIG. 3. Figure 6

[0048] ​In summary, the NPN triode type anti-static protection device and the implementation method thereof add high concentration N type doping (N+) 24 in the P well (P-Well) 30 to strengthen the isolation of the N well (N-Well) 20, connect the P type doping (P+) 26 and the N type doping (N+) 24 of the P well 30 and lead out the electrode to form the cathode of the ESD device, and lead out the N type doping (N+) 22 of the N well 20 to form the anode of the ESD device, thereby realizing an ESD device completely suitable for the anti-static protection design of the 8V IO port of a high voltage process platform.

[0049] The above embodiments only exemplarily illustrate the principles and effects of the present application, and are not used to limit the present application. Any person skilled in the art can modify and change the above embodiments without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application should be subject to the claims.

Claims

1. An NPN transistor-type anti-static protection device, characterized in that, The NPN transistor-type anti-static protection device includes: Semiconductor substrate (80); N-well (20) and P-well (30) formed on the semiconductor substrate (80); A shallow trench isolation layer (10) is formed at the upper part of the interface between the N-well (20) and the P-well (30). A high-concentration N-type dopant (22) is placed on the upper part of the N-well (20) near the shallow trench isolation layer (10). A high-concentration N-type dopant (24) is placed on the upper part of the P-well (30) near the shallow trench isolation layer (10). A high-concentration P-type dopant (26) is placed on the upper part of the P-well (30) at a set distance from the high-concentration N-type dopant (24). Metal silicides (40) are generated above the high-concentration N-type dopant (22), the high-concentration N-type dopant (24), and the high-concentration P-type dopant (26), respectively. The metal silicide (40) above the high-concentration N-type dopant (22) leads out an electrode to form the anode of the NPN transistor-type antistatic protection device. The metal silicide (40) above the high-concentration N-type dopant (24) is connected to the metal silicide (40) above the high-concentration P-type dopant (26) and leads out an electrode to form the cathode of the NPN transistor-type antistatic protection device.

2. The NPN transistor-type anti-static protection device as described in claim 1, characterized in that, The shallow trench isolation layer (10) has a width of a in the N-well (20) and a width of b in the P-well (30).

3. The NPN transistor-type anti-static protection device as described in claim 2, characterized in that: The width a of the shallow trench isolation layer (10) in the N-well (20) and the width b of the shallow trench isolation layer (10) in the P-well (30) determine the trigger voltage of the NPN transistor-type anti-static protection device.

4. The NPN transistor-type anti-static protection device as described in claim 3, characterized in that: The width b of the shallow trench isolation layer (10) within the P-well (30) determines the sustaining voltage of the NPN transistor-type anti-static protection device.

5. The NPN transistor-type anti-static protection device as described in claim 4, characterized in that: The width of the high-concentration N-type dopant (22) is W1.

6. The NPN transistor-type anti-static protection device as described in claim 4, characterized in that: The width of the high-concentration N-type dopant (24) is W2.

7. The NPN transistor-type anti-static protection device as described in claim 4, characterized in that: The width of the high-concentration P-type dopant (26) is W3.

8. The NPN transistor-type anti-static protection device as described in claim 1, characterized in that: The semiconductor substrate (80) is a P-type substrate.

9. A method for implementing an NPN transistor-type anti-static protection device as described in any one of claims 1 to 8, characterized in that: The method involves adding a high concentration of N-type dopant (24) to the P-well (30) to enhance the isolation of the N-well (20), and connecting the high concentration of P-type dopant (26) and the high concentration of N-type dopant (24) at the junction of the P-well (30) and leading out an electrode to form the cathode of the device, while leading out an electrode of the high concentration of N-type dopant (22) at the junction of the N-well (20) to form the anode of the device, thereby obtaining the NPN transistor-type anti-static protection device.

10. The method for implementing an NPN transistor-type anti-static protection device as described in claim 9, characterized in that, The method includes: Step S1, provide a semiconductor substrate (80); Step S2, an N-well (20) and a P-well (30) are formed on the semiconductor substrate (80); Step S3: A shallow trench isolation layer (10) is formed at the upper part of the interface between the N well (20) and the P well (30). A high concentration of N-type dopant (22) is formed on the upper part of the N well (20) near the shallow trench isolation layer (10). A high concentration of N-type dopant (24) is formed on the upper part of the P well (30) near the shallow trench isolation layer (10). A high concentration of P-type dopant (26) is formed on the upper part of the P well (30) at a set distance from the high concentration of N-type dopant (24). Step S4: Metal silicides (40) are generated above the high-concentration N-type dopant (22), the high-concentration N-type dopant (24), and the high-concentration P-type dopant (26), respectively. Step S5: The metal silicide (40) above the high-concentration N-type dopant (22) leads out an electrode to form the anode of the NPN transistor-type antistatic protection device. The metal silicide (40) above the high-concentration N-type dopant (24) is connected to the metal silicide (40) above the high-concentration P-type dopant (26) and leads out an electrode to form the cathode of the NPN transistor-type antistatic protection device.

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