High-voltage NPN triode type anti-static protection device and implementation method thereof

Abstract

The application discloses a high-voltage NPN triode type anti-static protection device and an implementation method thereof. The method increases high-concentration N-type doping (24) in a P-well (30), and moves high-concentration P-type doping (26) of an outgoing point of the P-well (30) to an interface between an N-well (20) and the P-well (30), so that the high-concentration P-type doping (26) is located between the high-concentration N-type doping (24) and the interface between the N-well (20) and the P-well (30), the probability of injection of electrons from the high-concentration N-type doping (24) into the P-well (30) and migration to the interface between the N-well (20) and the P-well (30) is reduced, and thus the high-voltage NPN triode type anti-static protection device is obtained.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit technology, and in particular to a high-voltage NPN transistor-type anti-static protection device suitable for high-voltage integrated circuits and its implementation method. Background Technology

[0002] The design of electrostatic discharge (ESD) protection for high-voltage circuits has always been a technical challenge. This is because the core components of high-voltage circuits—high-voltage devices (such as LDMOS)—are not as suitable for ESD protection design as ordinary low-voltage devices, due to the poor characteristics exhibited by their hysteresis curves. Figure 1 As shown, from Figure 1 It can be concluded that: 1) The sustaining voltage Vh (the lower right inflection point of the TLPcurrent curve, the initial failure point) is too low, often much lower than the operating voltage of the high voltage circuit, which can easily lead to latch-up when the high voltage circuit is working normally; 2) The secondary breakdown current (thermal breakdown current, It2) is too low, which is caused by the localized current crowding when the LDMOS discharges ESD current due to the device structure characteristics.

[0003] Therefore, when solving the design of electrostatic discharge (ESD) protection for high-voltage circuits, the industry often adopts two approaches: 1) Adjusting the structure of the high-voltage devices used in the ESD protection module and optimizing their hysteresis curves to make them suitable for ESD protection design. However, this is often difficult to implement due to the structural characteristics of the high-voltage devices themselves; 2) Connecting a certain number of low-voltage ESD protection devices in series to form an ESD protection circuit that can withstand high voltage. Because the characteristics of low-voltage ESD protection devices are relatively easy to adjust and control, the industry, especially integrated circuit design companies, often prefers to use the method of connecting a certain number of low-voltage ESD protection devices in series.

[0004] The electrostatic discharge (ESD) protection design window for a 32V high-voltage I / O port in a certain high-voltage process requires that the sustaining voltage of the multi-stage ESD protection device connected in series must be greater than 35.2V (1.1HVVdd). Existing ESD devices only sustain a voltage of 17.6V. Therefore, existing NPN transistor-type ESD protection devices need at least three stages connected in series to meet the ESD protection design requirements of the 32V high-voltage I / O port in this high-voltage process. Therefore, it is desirable to find a device with a sustaining voltage Vh above 17.6V, in which only two stages connected in series can meet the ESD protection design requirements of the 32V high-voltage I / O port in the high-voltage process, thus saving layout area. Summary of the Invention

[0005] To overcome the above-mentioned deficiencies of the prior art, the purpose of the present application is to provide a high-voltage NPN transistor type anti-static protection device and its implementation method, so as to realize a high-voltage NPN transistor type anti-static protection device suitable for high-voltage integrated circuits.

[0006] To achieve the above and other purposes, the present application proposes a high-voltage NPN transistor type anti-static protection device, characterized in that the high-voltage NPN transistor type anti-static protection device comprises:

[0007] a semiconductor substrate (80);

[0008] an N-well (20) and a P-well (30) generated on the semiconductor substrate (80);

[0009] a shallow trench isolation layer (10) generated on the upper part of the interface between the N-well (20) and the P-well (30), a high-concentration N-type doping (22) placed on the upper part of the N-well (20) close to the shallow trench isolation layer (10), a high-concentration P-type doping (26) placed on the upper part of the P-well (30) close to the shallow trench isolation layer (10), and a high-concentration N-type doping (24) placed on the upper part of the P-well (30) at a set distance from the high-concentration P-type doping (26);

[0010] a metal silicide (40) generated above the high-concentration N-type doping (22), above the high-concentration P-type doping (26), and above the high-concentration N-type doping (24), respectively;

[0011] the metal silicide (40) above the high-concentration N-type doping (22) forms an anode electrode of the high-voltage NPN transistor type anti-static protection device, and the metal silicide (40) above the high-concentration N-type doping (24) is connected to the metal silicide (40) above the high-concentration P-type doping (26) and forms a cathode electrode of the high-voltage NPN transistor type anti-static protection device.

[0012] Preferably, the width of the shallow trench isolation layer (10) in the N-well (20) is a, and the width of the shallow trench isolation layer (10) in the P-well (30) is b.

[0013] Preferably, the trigger voltage of the high-voltage NPN transistor type anti-static protection device is influenced by the width a of the shallow trench isolation layer (10) in the N-well (20) and the width b of the shallow trench isolation layer (10) in the P-well (30) within a certain range.

[0014] Preferably, the width a of the shallow trench isolation layer (10) in the N-well (20) and the width b of the shallow trench isolation layer (10) in the P-well (30) are 0.2-2 µm.

[0015] Preferably, the high-concentration P-type doping (26) has a width W2.

[0016] Preferably, the holding voltage of the high-voltage NPN triode type anti-static protection device is affected by the width W2 of the high-concentration P-type doping (26) within a certain range.

[0017] Preferably, the width W2 of the high-concentration P-type doping (26) ranges from 0.2 to 2 µm.

[0018] Preferably, the semiconductor substrate (80) is a P-type substrate.

[0019] To achieve the above-mentioned purpose, the application further provides an implementation method of a high-voltage NPN triode type anti-static protection device, which comprises the following steps:

[0020] Preferably, the method comprises:

[0021] Step S1, providing a semiconductor substrate (80);

[0022] Step S2, generating an N-well (20) and a P-well (30) on the semiconductor substrate (80);

[0023] Step S3, generating a shallow trench isolation layer (10) on the interface between the N-well (20) and the P-well (30), generating a high-concentration N-type doping (22) on the upper portion of the N-well (20) close to the shallow trench isolation layer (10), generating a high-concentration P-type doping (26) on the upper portion of the P-well (30) close to the shallow trench isolation layer (10), and generating a high-concentration N-type doping (24) on the upper portion of the P-well (30) at a distance from the high-concentration P-type doping (26);

[0024] Step S4, generating a metal silicide (40) above the high-concentration N-type doping (22), above the high-concentration P-type doping (26), and above the high-concentration N-type doping (24), respectively;

[0025] Step S5, the metal silicide (40) above the high concentration N-type doping (22) forms an anode of the high-voltage NPN transistor type anti-static protection device, and the metal silicide (40) above the high concentration N-type doping (24) is connected with the metal silicide (40) above the high concentration P-type doping (26) and forms a cathode of the high-voltage NPN transistor type anti-static protection device.

[0026] Compared with the prior art, the high-voltage NPN transistor type anti-static protection device and the implementation method thereof increase N-type doping (N+) 24 in the P-Well 30, and move the P-type doping (P+) 26 of the P-Well 30 to the N-Well 20 / P-Well 30 interface, so that the P-type doping (P+) 26 is located between the N-type doping (N+) 24 and the N-Well 20 / P-Well 30 interface, thereby reducing the probability of injection of electrons from the N-type doping (N+) 24 into the P-Well 30 and migration to the N-Well 20 / P-Well 30 interface, i.e., reducing the current gain of the NPN transistor type anti-static protection device, thereby increasing the holding voltage Vh of the new NPN transistor type anti-static protection device, so that the new NPN transistor type anti-static protection structure saves the required series number when applied to high-voltage port anti-static protection design, and the application is very suitable for anti-static protection design of high-voltage integrated circuits. BRIEF DESCRIPTION OF DRAWINGS

[0027] Figure 1 It is a 1.2V GGNMOS hysteresis characteristic curve of a 55LP process platform of a company;

[0028] Figure 2 It is a device structure diagram of a preferred embodiment of the high-voltage NPN transistor type anti-static protection device of the application;

[0029] Figure 3 It is a step flow chart of the implementation method of the high-voltage NPN transistor type anti-static protection device of the application;

[0030] Figure 4 It is an application scenario diagram of the application. DETAILED DESCRIPTION

[0031] The embodiments of the application are described below by specific examples and in conjunction with the drawings, and other advantages and effects of the application can be easily understood by those skilled in the art from the content disclosed in the specification. The application can also be implemented or applied by other different specific examples, and each detail in the specification can be modified and changed in various ways based on different views and applications without departing from the spirit of the application.

[0032] Figure 2 Figure 1 is a device structure diagram of a preferred embodiment of a high-voltage NPN transistor type electrostatic discharge protection device of the present application. As shown, the high-voltage NPN transistor type electrostatic discharge protection device of the present application comprises a shallow trench isolation layer (STI) 10, a high-concentration N-type doping (N+) 22, a high-concentration P-type doping (P+) 26, a high-concentration N-type doping (N+) 24, an N well (N-Well) 20, a P well (P-Well) 30, a P-type substrate (P-Sub) 80, and a plurality of metal silicides (Silicide) 40 connecting the doping regions and electrodes. Figure 2

[0033] The entire high-voltage NPN transistor type electrostatic discharge protection (ESD) device is placed on the P-type substrate (P-Sub) 80, an N well (N-Well) 20 is generated on one side of the P-type substrate (P-Sub) 80, a P well (P-Well) 30 is generated on the other side of the P-type substrate (P-Sub) 80, and a shallow trench isolation layer (STI) 10 is generated on the upper part of the interface between the N well (N-Well) 20 and the P well (P-Well) 30. The width of the shallow trench isolation layer (STI) 10 in the N well (N-Well) 20 is a, the width of the shallow trench isolation layer (STI) 10 in the P well (P-Well) 30 is b, the trigger voltage (Vt1) of the high-voltage NPN transistor type electrostatic discharge protection device of the present application is affected by the parameter a / b within a certain range, and the value range of a / b is 0.2-2 µm. The high-concentration N-type doping (N+) 22 is placed on the upper part of the N well (N-Well) 20 close to the shallow trench isolation layer (STI) 10, and the width of the high-concentration N-type doping (N+) 22 is W1. The high-concentration P-type doping (P+) 26 is placed on the upper part of the P well (P-Well) 30 close to the shallow trench isolation layer (STI) 10, and the width of the high-concentration P-type doping (P+) 26 is W2. The holding voltage Vh of the high-voltage NPN transistor type electrostatic discharge protection device of the present application is affected by W2 within a certain range, and the value range of W2 is 0.2-2 µm. The high-concentration N-type doping (N+) 24 is placed on the upper part of the P well (P-Well) 30, and the distance between the high-concentration N-type doping (N+) 24 and the high-concentration P-type doping (P+) 26 is c. The width of the high-concentration N-type doping (N+) 24 is W3.

[0034] ​Specifically, one side of the high-concentration N-type doping (N+) 22 is connected with one side of the shallow trench isolation (STI) 10, one side of the high-concentration P-type doping (P+) 26 is connected with the other side of the shallow trench isolation (STI) 10, the other side of the high-concentration P-type doping (P+) 26 is part of the P-well (P-Well) 30, the distance from the side of the high-concentration N-type doping (N+) 24 to the side of the high-concentration P-type doping (P+) 26 is c, that is, the width of the P-well (P-Well) 30 between the high-concentration N-type doping (N+) 24 and the high-concentration P-type doping (P+) 26 is c; the other side of the high-concentration N-type doping (N+) 22 is part of the N-well (N-Well) 20, and the other side of the high-concentration N-type doping (N+) 24 is part of the P-well (P-Well) 30.

[0035] The metal silicide 40 is generated above the high-concentration N-type doping (N+) 22, above the high-concentration P-type doping (P+) 26 and above the high-concentration N-type doping (N+) 24.

[0036] The metal silicide 40 above the high-concentration N-type doping (N+) 22 is the anode of the NPN transistor type ESD device of the application, the metal silicide 40 above the high-concentration N-type doping (N+) 24 is connected with the metal silicide 40 above the high-concentration P-type doping (P+) 26 and is the cathode of the NPN transistor type ESD device of the application.

[0037] The application is based on the existing isolation structure, and proposes an NPN transistor type ESD device as shown in Figure 2 Figure 3 ​It can be known that the high-voltage NPN triode type ESD device of the application increases N-type doping (N+) 24 in P-Well 30, and moves P-type doping (P+) 26 of the outpoint of P-Well 30 to the N-Well 20 / P-Well 30 interface, so that P-type doping (P+) 26 is located between N-type doping (N+) 24 and the N-Well 20 / P-Well 30 interface, reduces the probability of electron injection from N-type doping (N+) 24 to P-Well 30 and migration to the N-Well 20 / P-Well 30 interface, i.e. reduces the current gain of the NPN triode type anti-static protection device, thereby increasing the holding voltage Vh of the new NPN triode type anti-static protection device, Vh can reach more than 18V, so that the new NPN triode type anti-static protection structure is applied to high-voltage port anti-static protection design to save the required series number of multiple series connection, so the new anti-static protection structure without hysteresis effect proposed in the application is very suitable for anti-static protection design of high-voltage integrated circuit.

[0038] In the application, the trigger voltage Vt1 of the high-voltage NPN triode type ESD device is affected by parameters a / b within a certain range, and the value range of a / b is 0.2-2µm; and the holding voltage Vh of the high-voltage NPN triode type ESD device is affected by W2 within a certain range, and the value range of W2 is 0.2-2µm.

[0039] Figure 3 The figure is a step flow chart of the implementation method of the high-voltage NPN triode type anti-static protection device of the application. Figure 3 As shown in the figure, the implementation method of the high-voltage NPN triode type anti-static protection device of the application comprises the following steps:

[0040] Step S1, providing a semiconductor substrate, in the specific embodiment of the application, providing a P-type substrate (P-Sub) 80.

[0041] Step S2, generating N well (N-Well) 20 and P well (P-Well) 30 on the P-type substrate (P-Sub) 80. Specifically, generating an N well (N-Well) 20 on one side of the P-type substrate (P-Sub) 80, and generating a P well (P-Well) 30 on the other side of the P-type substrate (P-Sub) 80.

[0042] Step S3, generating a shallow trench isolation (STI) 10 on the interface of the N-well (N-Well) 20 and the P-well (P-Well) 30, generating a high-concentration N-type doping (N+) 22 on the upper portion of the N-well (N-Well) 20 close to the shallow trench isolation (STI) 10, generating a high-concentration P-type doping (P+) 26 on the upper portion of the P-well (P-Well) 30 close to the shallow trench isolation (STI) 10, and generating a high-concentration N-type doping (N+) 24 on the upper portion of the P-well (P-Well) 30 at a distance c from the high-concentration N-type doping (N+) 24.

[0043] Specifically, the shallow trench isolation (STI) 10 has a width of a in the N-well (N-Well) 20 and a width of b in the P-well (P-Well) 30. The trigger voltage (Vt1) of the high-voltage NPN transistor type anti-static protection device is affected by the parameter a / b within a certain range. The value range of a / b is 0.2-2 µm. The high-concentration N-type doping (N+) 22 is placed on the upper portion of the N-well (N-Well) 20 close to the shallow trench isolation (STI) 10, and the width of the high-concentration N-type doping (N+) 22 is W1. The high-concentration N-type doping (N+) 24 is placed on the upper portion of the P-well (P-Well) 30 close to the shallow trench isolation (STI) 10, and the width of the high-concentration N-type doping (N+) 24 is W2. The holding voltage Vh of the high-voltage NPN transistor type anti-static protection device is affected by W2 within a certain range. The value range of W2 is 0.2-2 µm. The high-concentration P-type doping (P+) 26 is placed on the upper portion of the P-well (P-Well) 30 at a distance c from the high-concentration N-type doping (N+) 24, and the width of the high-concentration P-type doping (P+) 26 is W3.

[0044] Step S4, generating a metal silicide 40 above the high-concentration N-type doping (N+) 22, above the high-concentration P-type doping (P+) 26, and above the high-concentration N-type doping (N+) 24.

[0045] Step S5, the metal silicide 40 above the high concentration N-type doping (N+) 22 forms the anode Anode of the high voltage NPN transistor type ESD device of the present application, the metal silicide 40 above the high concentration N-type doping (N+) 24 is connected with the metal silicide 40 above the high concentration P-type doping (P+) 26 and forms the cathode Cathode of the high voltage NPN transistor type ESD device of the present application.

[0046] In application, the high voltage NPN transistor type ESD device of the present application can be connected between IO port and ground for IO protection, the anode Anode of the present application is connected with the IO port, and the cathode Cathode of the present application is connected with the ground (Vss). The high voltage NPN transistor type ESD device of the present application can also be connected between power supply and ground for power clamp, the anode Anode of the present application is connected with the positive terminal of the power supply (Vdd), and the cathode Cathode of the present application is connected with the ground (Vss), as shown in the following figure. Figure 4

[0047] In summary, the high voltage NPN transistor type ESD device of the present application and the implementation method thereof increase the N-type doping (N+) 24 in the P-Well 30, and move the out point P-type doping (P+) 26 of the P-Well 30 to the N-Well 20 / P-Well 30 interface, so that the P-type doping (P+) 26 is located between the N-type doping (N+) 24 and the N-Well 20 / P-Well 30 interface, which reduces the probability of the electrons injected from the N-type doping (N+) 24 to the P-Well 30 and migrated to the N-Well 20 / P-Well 30 interface, i.e. reduces the current gain of the NPN transistor type ESD device, thereby increases the holding voltage Vh of the new NPN transistor type ESD device, so that the new NPN transistor type ESD device is applied to the high voltage port ESD protection design to save the series number of the series connection, and the present application is very suitable for the ESD protection design of high voltage integrated circuit.

[0048] The above embodiments only exemplarily illustrate the principles and effects of the present application, and are not used to limit the present application. Any person skilled in the art can modify and change the above embodiments without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application should be as listed in the claims.​

Claims

1. A high-voltage NPN transistor-type anti-static protection device, characterized in that, The high-voltage NPN transistor-type anti-static protection device includes: Semiconductor substrate (80); N-well (20) and P-well (30) formed on the semiconductor substrate (80); A shallow channel isolation layer (10) is formed at the upper part of the interface between the N-well (20) and the P-well (30). A high-concentration N-type dopant (22) is placed on the upper part of the N-well (20) near the shallow channel isolation layer (10), and a high-concentration P-type dopant (26) is placed on the upper part of the P-well (30) near the shallow channel isolation layer (10). A high-concentration N-type dopant (24) and a high-concentration P-type dopant (26) are placed on the upper part of the P-well (30) at a set distance. Metal silicides (40) are generated above the high-concentration N-type dopant (22), the high-concentration P-type dopant (26), and the high-concentration N-type dopant (24), respectively. The metal silicide (40) above the high-concentration N-type dopant (22) leads out an electrode to form the anode of the high-voltage NPN transistor-type antistatic protection device. The metal silicide (40) above the high-concentration N-type dopant (24) is connected to the metal silicide (40) above the high-concentration P-type dopant (26) and leads out an electrode to form the cathode of the high-voltage NPN transistor-type antistatic protection device.

2. The high-voltage NPN transistor-type anti-static protection device as described in claim 1, characterized in that, The shallow trench isolation layer (10) has a width of a in the N-well (20) and a width of b in the P-well (30).

3. The high-voltage NPN transistor-type anti-static protection device as described in claim 2, characterized in that: The trigger voltage of the high-voltage NPN transistor-type anti-static protection device is affected by the width a of the shallow trench isolation layer (10) in the N-well (20) and the width b of the shallow trench isolation layer (10) in the P-well (30).

4. The high-voltage NPN transistor-type anti-static protection device as described in claim 3, characterized in that: The width a of the shallow trench isolation layer (10) in the N-well (20) and the width b of the shallow trench isolation layer (10) in the P-well (30) are both 0.2~2µm.

5. The high-voltage NPN transistor-type anti-static protection device as described in claim 4, characterized in that: The width of the high-concentration P-type dopant (26) is W2.

6. The high-voltage NPN transistor-type anti-static protection device as described in claim 5, characterized in that: The sustaining voltage of the high-voltage NPN transistor-type anti-static protection device is affected by the width W2 of the high-concentration P-type dopant (26) within a certain range.

7. A high-voltage NPN transistor-type anti-static protection device as described in claim 6, characterized in that: The width W2 of the high-concentration P-type dopant (26) ranges from 0.2 to 2 µm.

8. The high-voltage NPN transistor-type anti-static protection device as described in claim 1, characterized in that: The semiconductor substrate (80) is a P-type substrate.

9. A method for implementing a high-voltage NPN transistor-type anti-static protection device as described in any one of claims 1 to 8, characterized in that: The method adds a high concentration of N-type dopant (24) to the P-well (30) and moves the high concentration of P-type dopant (26) at the junction of the P-well (30) to the interface between the N-well (20) and the P-well (30), so that the high concentration of P-type dopant (26) is located between the high concentration of N-type dopant (24) and the interface between the N-well (20) and the P-well (30), thereby reducing the probability of electrons being injected from the high concentration of N-type dopant (24) into the P-well (30) and migrating to the interface between the N-well (20) and the P-well (30).

10. The method for implementing a high-voltage NPN transistor-type anti-static protection device as described in claim 9, characterized in that, The method includes: Step S1, provide a semiconductor substrate (80); Step S2, an N-well (20) and a P-well (30) are formed on the semiconductor substrate (80); Step S3: A shallow trench isolation layer (10) is formed at the upper part of the interface between the N well (20) and the P well (30). A high concentration of N-type dopant (22) is formed on the upper part of the N well (20) near the shallow trench isolation layer (10). A high concentration of P-type dopant (26) is formed on the upper part of the P well (30) near the shallow trench isolation layer (10). A high concentration of N-type dopant (24) is formed on the upper part of the P well (30) at a set distance from the high concentration of P-type dopant (26). Step S4: Metal silicides (40) are generated above the high-concentration N-type dopant (22), the high-concentration P-type dopant (26), and the high-concentration N-type dopant (24), respectively. Step S5: The metal silicide (40) above the high-concentration N-type dopant (22) leads out an electrode to form the anode of the high-voltage NPN transistor-type anti-static protection device. The metal silicide (40) above the high-concentration N-type dopant (24) is connected to the metal silicide (40) above the high-concentration P-type dopant (26) and leads out an electrode to form the cathode of the high-voltage NPN transistor-type anti-static protection device.

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