Semiconductor device manufacturing method, semiconductor device and memory system

Abstract

The present application provides a method for manufacturing a semiconductor device, a semiconductor device and a memory system, the manufacturing method comprising: forming a dielectric layer and a plurality of first shallow isolation grooves arranged at intervals on a substrate, the substrate comprising a first region and a second region, the dielectric layer filling the first shallow isolation grooves, the first shallow isolation grooves being located in the first region, and a fin portion being formed on the substrate between two adjacent first shallow isolation grooves; forming a first opening and at least two second openings, the first opening exposing the top of the fin portion, and the second opening penetrating the dielectric layer on the second region; forming a first gate structure and a second gate structure, the first gate structure wrapping the top, and the second gate structure being located on the dielectric layer between two adjacent second openings; forming a source and a drain in the second region through the second opening, thereby simplifying the manufacturing process of the semiconductor device and reducing the process cost.

Description

[Technical field]

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a semiconductor device, a semiconductor device and a memory system. [Background technology]

[0002] In 3D NAND three-dimensional memory, the peripheral circuit is one of the core components, which is mainly used for logical operations, as well as controlling and detecting the switching state of each storage unit in the three-dimensional memory through metal connections to achieve data storage and reading.

[0003] The electronic components in the peripheral circuit mainly include MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), and according to the different working voltages of MOSFET, it can be divided into high-voltage MOS tube and low-voltage MOS tube. However, in the existing peripheral circuit manufacturing process, the overall manufacturing process of MOS tube is relatively complicated, which is not conducive to reducing the process cost. [Summary of the invention]

[0004] The object of the present invention is to provide a method for manufacturing a semiconductor device, a semiconductor device and a memory system, which can simplify the manufacturing process of electronic components and reduce the manufacturing cost.

[0005] In order to solve the above problems, an embodiment of the present application provides a method for manufacturing a semiconductor device, comprising:

[0006] providing a substrate, the substrate comprising a first region and a second region;

[0007] forming a dielectric layer and a plurality of first shallow isolation trenches spaced apart on the substrate, wherein the dielectric layer fills the first shallow isolation trenches, the first shallow isolation trenches are located in the first region, and the substrate between two adjacent first shallow isolation trenches forms a fin;

[0008] forming a first opening and at least two second openings in the dielectric layer, wherein the first opening extends into the first shallow isolation trench and exposes the top of the fin, and the second opening is located on the second region and penetrates the dielectric layer;

[0009] forming a first gate structure and a second gate structure, wherein the first gate structure wraps the top end, and the second gate structure is located on the dielectric layer between two adjacent second openings;

[0010] A source and a drain are formed in the second region through the second opening.

[0011] Wherein, the step of forming a first opening and at least two second openings in the dielectric layer comprises:

[0012] forming a second mask layer on the dielectric layer;

[0013] Using the same mask, forming a patterned second photoresist layer on the second mask layer, wherein a first preliminary opening and at least two second preliminary openings penetrating the second photoresist layer are formed in the second photoresist layer, wherein the positions of the second preliminary openings correspond to the second region, and the positions of the first preliminary openings correspond to the first region;

[0014] A first opening is formed in the dielectric layer through the first preliminary opening, and simultaneously, a second opening is formed in the dielectric layer through the second preliminary opening.

[0015] The dielectric layer includes a gate dielectric layer, a first mask layer and a filling layer, and the step of forming the dielectric layer and a plurality of first shallow isolation trenches spaced apart on the substrate includes:

[0016] forming the gate dielectric layer on the substrate;

[0017] forming the first mask layer on the gate dielectric layer;

[0018] forming a plurality of first shallow isolation trenches spaced apart from each other, wherein the first shallow isolation trenches penetrate the first mask layer and extend into the substrate in the first region;

[0019] A filling layer is formed on the first mask layer, and the filling layer fills the first shallow isolation trench.

[0020] The step of forming the first opening in the dielectric layer through the first preliminary opening and forming the second opening in the dielectric layer through the second preliminary opening comprises:

[0021] A first etching opening is formed through the first preliminary opening, penetrating the second mask layer and extending into the first shallow isolation trench, wherein the first etching opening exposes a side wall of a top end of the fin portion;

[0022] forming a second etching opening penetrating through the second mask layer and extending to the upper surface of the substrate in the second region through the second preliminary opening;

[0023] The second photoresist layer, the second mask layer, the filling layer outside the first shallow isolation groove and the first mask layer are removed to expose the top and obtain a first opening corresponding to the first etching opening and a second opening corresponding to the second etching opening.

[0024] The step of forming a plurality of first shallow isolation trenches arranged at intervals includes:

[0025] forming a patterned first photoresist layer on the first mask layer;

[0026] Sequentially etching the first mask layer, the gate dielectric layer, and the substrate to form a plurality of first shallow isolation trenches penetrating the first mask layer and extending into the substrate in the first region;

[0027] The first photoresist layer is removed.

[0028] Wherein, when forming a plurality of first shallow isolation trenches arranged at intervals, the step further includes:

[0029] forming a plurality of second shallow isolation trenches spaced apart from each other, wherein the second shallow isolation trenches penetrate the first mask layer and extend into the substrate in the second region;

[0030] Wherein, the filling layer fills the second shallow isolation trench.

[0031] Wherein, the step of forming the first gate structure and the second gate structure includes:

[0032] forming a gate insulating layer wrapping the top end;

[0033] forming a first gate located on the gate insulating layer and a second gate located on the dielectric layer between two adjacent second openings;

[0034] Sidewall spacers are formed on both sides of the first gate and both sides of the second gate respectively.

[0035] After forming the source and the drain, the method further comprises:

[0036] forming a planarization layer on the dielectric layer, wherein the planarization layer covers the first gate structure, the second gate structure, the source electrode, and the drain electrode;

[0037] Leads are formed in the planarization layer to contact the first gate structure, the second gate structure, the source electrode, and the drain electrode, respectively.

[0038] In order to solve the above problems, an embodiment of the present application further provides a semiconductor device, which is manufactured using any of the manufacturing methods described above.

[0039] In order to solve the above problems, an embodiment of the present application further provides a memory system, comprising any of the above semiconductor devices, and a controller coupled to the semiconductor device, wherein the controller is used to control the semiconductor device to perform data writing and reading operations.

[0040] The semiconductor device manufacturing method, semiconductor device and memory system provided by the embodiments of the present application are achieved by manufacturing a first opening and a second opening before forming a first gate structure and a second gate structure, wherein the first opening is used to expose the top of the fin in the substrate so as to subsequently manufacture the first gate structure, and the second opening is used to expose the source region and the drain region on the substrate so as to subsequently manufacture the second gate structure, the source and the drain, thereby simplifying the manufacturing process of the semiconductor device, saving the number of masks, reducing process costs, and shortening the production cycle.

Brief Description of the Drawings

[0041] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0042] Figure 1 It is a schematic flow chart of a method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0043] Figure 2a is a schematic diagram of a cross-sectional structure of a semiconductor device in different process steps provided in an embodiment of the present application;

[0044] Figure 2b is a schematic diagram of a cross-sectional structure of a semiconductor device in different process steps provided in an embodiment of the present application;

[0045] Figure 2c is a schematic diagram of a cross-sectional structure of a semiconductor device in different process steps provided in an embodiment of the present application;

[0046] Figure 2d is a schematic diagram of a cross-sectional structure of a semiconductor device in different process steps provided in an embodiment of the present application;

[0047] Figure 2e is a schematic diagram of a cross-sectional structure of a semiconductor device in different process steps provided in an embodiment of the present application;

[0048] Figure 2f is a schematic diagram of a cross-sectional structure of a semiconductor device in different process steps provided in an embodiment of the present application;

[0049] Figure 2g is a schematic diagram of a cross-sectional structure of a semiconductor device in different process steps provided in an embodiment of the present application;

[0050] Figure 2h is a schematic diagram of a cross-sectional structure of a semiconductor device in different process steps provided in an embodiment of the present application;

[0051] Figure 2i is a schematic diagram of a cross-sectional structure of a semiconductor device in different process steps provided in an embodiment of the present application;

[0052] Figure 2j is a schematic diagram of a cross-sectional structure of a semiconductor device in different process steps provided in an embodiment of the present application;

[0053] Figure 2k is a schematic diagram of a cross-sectional structure of a semiconductor device in different process steps provided in an embodiment of the present application;

[0054] Figure 3a is a schematic cross-sectional structural diagram of a semiconductor device in different process steps provided by another embodiment of the present application;

[0055] Figure 3b is a schematic cross-sectional structural diagram of a semiconductor device in different process steps provided by another embodiment of the present application;

[0056] Figure 3c is a schematic cross-sectional structural diagram of a semiconductor device in different process steps provided by another embodiment of the present application;

[0057] Figure 3d is a schematic cross-sectional structural diagram of a semiconductor device in different process steps provided by another embodiment of the present application;

[0058] Figure 4 It is a schematic diagram of the structure of the memory system provided in an embodiment of the present application. [Specific implementation method]

[0059] The present invention is further described in detail below in conjunction with the accompanying drawings and examples. It is particularly pointed out that the following examples are only used to illustrate the present invention, but do not limit the scope of the present invention. Similarly, the following examples are only some embodiments of the present invention rather than all embodiments, and all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0060] In the description herein, it should be understood that the terms "center", "lateral", "up", "down", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features.

[0061] In the description of this article, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0062] The terms used herein are only for describing specific embodiments and are not intended to limit exemplary embodiments. Unless the context clearly indicates otherwise, the singular forms "one", "one" and "item" used herein are also intended to include plural numbers. The meaning of "multiple" is two or more. It should also be understood that the terms "include" and / or "comprise" used herein specify the existence of stated features, integers, steps, operations, units and / or components, without excluding the existence or addition of one or more other features, integers, steps, operations, units, components and / or combinations thereof.

[0063] Embodiments of the present application provide a method for manufacturing a semiconductor device, a semiconductor device, and a memory system.

[0064] See also Figure 1 , Figure 1 The present invention provides a method for manufacturing a semiconductor device, wherein the semiconductor device may include one or more high-voltage electronic devices and low-voltage electronic devices, wherein the electronic device mainly refers to a MOS tube, and the manufacturing method includes the following steps:

[0065] S101, providing a substrate, the substrate comprising a first region and a second region;

[0066] S102, forming a dielectric layer and a plurality of first shallow isolation trenches spaced apart on the substrate, wherein the dielectric layer fills the first shallow isolation trenches, the first shallow isolation trenches are located in the first region, and the substrate between two adjacent first shallow isolation trenches forms a fin;

[0067] S103, forming a first opening and at least two second openings in the dielectric layer, wherein the first opening extends into the first shallow isolation trench and exposes the top of the fin, and the second opening is located on the second region and penetrates the dielectric layer;

[0068] S104, forming a first gate structure and a second gate structure, wherein the first gate structure wraps the top, and the second gate structure is located on the dielectric layer between two adjacent second openings;

[0069] S105 , forming a source and a drain in the second region through the second opening.

[0070] It should be understood that the steps shown in the above production method are not exclusive, and other steps may be performed before, after or between any of the steps shown.

[0071] See also Figure 2a to Figure 2k , Figure 2a to Figure 2k is a schematic diagram of the cross-sectional structure of the semiconductor device 10 at different process steps in the above-mentioned manufacturing method. Figure 2a to Figure 2k , further describing the above steps S101-S105, wherein:

[0072] Step S101 : providing a substrate 11 , wherein the substrate 11 includes a first region LV and a second region HV.

[0073] The substrate 11 may include at least one of single crystal silicon (Si), single crystal germanium (Ge), III-V compound semiconductor materials, II-VI compound semiconductor materials, or other semiconductor materials known in the art. The first region LV mainly refers to a low voltage device region, and the second region HV mainly refers to a high voltage device region, where the operating voltage of the electronic devices in the high voltage device region is greater than the operating voltage of the electronic devices in the low voltage device region.

[0074] Step S102 , forming a dielectric layer 12 and a plurality of first shallow isolation trenches Q1 spaced apart on the substrate 11 , wherein the dielectric layer 12 fills the first shallow isolation trenches Q1 , the first shallow isolation trenches Q1 are located in the first region LV, and the substrate 11 between two adjacent first shallow isolation trenches Q1 forms a fin 111 .

[0075] Among them, Figure 2dIn the embodiment, the first shallow isolation trench Q1 and the dielectric layer 12 filled therein constitute a first shallow trench isolation structure, which is mainly used to isolate the electronic devices subsequently formed on the first region LV to prevent electrical coupling between adjacent electronic devices. The material of the dielectric layer 12 mainly includes insulating materials, such as oxides, nitrides, etc., which may include multiple film layers.

[0076] It should be noted that since the fin field-effect transistor (Fin Field-Effect Transistor, FinFET) can better suppress the short channel effect and is more conducive to the miniaturization of semiconductor devices compared to the planar transistor structure, the fin field-effect transistor can be manufactured as its electronic device at least in the first area LV (low-voltage device area), and adjacent fin field-effect transistors are isolated by a first shallow trench isolation structure.

[0077] In some embodiments, see Figure 2a-2d , the dielectric layer 12 includes a gate dielectric layer 121, a first mask layer 122 and a filling layer 123. At this time, the above step S102 may specifically include:

[0078] forming the gate dielectric layer 121 on the substrate 11;

[0079] forming the first mask layer 122 on the gate dielectric layer 121;

[0080] forming a plurality of first shallow isolation trenches Q1 spaced apart from each other, wherein the first shallow isolation trenches Q1 penetrate the first mask layer 122 and extend into the substrate 11 in the first region LV;

[0081] A filling layer 123 is formed on the first mask layer 122 , and the filling layer 123 fills the first shallow isolation trench Q1 .

[0082] The materials of the gate dielectric layer 121 and the filling layer 123 may be the same, such as both including silicon oxide, or different. The first mask layer 122 is a hard mask layer, and its material may include nitride, such as silicon nitride or titanium nitride, which is mainly used to form an active area on the substrate 11. The first mask layer 122 and the filling layer 123 may be formed by processes such as CVD, PVD or plasma assisted deposition. After the filling layer 123 is formed, a planarization process, such as chemical mechanical polishing (CMP), may be used to process it.

[0083] It should be pointed out that since the devices on the first region LV and the devices on the second region HV have different operating voltages, and the electric fields formed between the substrate 11 and the gate (equivalent to the electric field borne by the gate dielectric layer 121) at different operating voltages have different electric field strengths, and the thicker the gate dielectric layer 121 is, the stronger the electric field strength it can withstand is, and the more conducive it is to improving the electrical parameters of the device such as the saturation current and the leakage current, the gate dielectric layer 121 corresponding to the first region LV and the second region HV can be set to have different thicknesses, and the thickness h1 of the gate dielectric layer 121 corresponding to the first region LV is smaller than the thickness h2 of the gate dielectric layer 121 corresponding to the second region HV (see Figure 2a ). In order to achieve the corresponding thickness relationship, the gate dielectric layer 121 can be formed by an oxidation process, such as a thermal oxidation process (Thermal Oxidation), a soft plasma oxidation process (Soft Plasma Oxidation) or an ultraviolet assisted oxidation process (UV Photo Assistant Oxidation), for example, the substrate 11 is doped in advance so that the first region LV and the second region HV have different oxidation rates, and then oxidized by an oxidation process to form gate dielectric layers 121 of different thicknesses. In other embodiments, the gate dielectric layer 121 can also be formed by multiple depositions, such as chemical vapor deposition (Chemical Vapor Deposition, CVD), physical vapor deposition (PVD) or plasma assisted deposition process.

[0084] In some embodiments, see Figure 2b-Figure 2c The above step of “forming a plurality of first shallow isolation trenches Q1 spaced apart from each other” may specifically include:

[0085] forming a patterned first photoresist layer 13 on the first mask layer 122;

[0086] The first mask layer 122 , the gate dielectric layer 121 , and the substrate 11 are sequentially etched to form a plurality of first shallow isolation trenches Q1 penetrating the first mask layer 122 and extending into the substrate 11 in the first region LV;

[0087] The first photoresist layer 13 is removed.

[0088] The material of the first photoresist layer 13 includes photoresist, such as positive photoresist or negative photoresist. Specifically, a layer of photoresist can be coated on the surface of the first mask layer 122, and then patterned by photolithography processes such as exposure and development to obtain a patterned first photoresist layer 13, and then the first mask layer 122 and the gate dielectric layer 121 are etched by processes such as reactive ion etching or plasma etching with the first photoresist layer 13 as a mask to expose the surface of the first region LV of the substrate 11, and then the substrate 11 is further etched by an inert gas, such as a fluorine-containing gas, to form a first shallow isolation trench Q1 through the exposed surface of the first region LV, at which point the substrate 11 between two adjacent first shallow isolation trenches Q1 will serve as a fin 111 for subsequent fabrication of a fin field effect transistor.

[0089] It should be noted that the number of electronic devices in the first area LV and the second area HV can be determined according to the requirements. Figure 2a to Figure 2k These are just simple schematic diagrams and do not represent the actual number of electronic devices. Usually, multiple electronic devices are made in the first area LV and the second area HV, and adjacent electronic devices need to be isolated from each other. Therefore, when making the first shallow trench isolation structure in the first area LV, it is also necessary to make the second shallow trench isolation structure in the second area HV. That is, please continue to refer to Figure 2b-2d In the step of forming a plurality of first shallow isolation trenches Q1 spaced apart from each other, the method for manufacturing the semiconductor device 10 further includes:

[0090] A plurality of second shallow isolation trenches Q2 are formed at intervals. The second shallow isolation trenches Q2 penetrate the first mask layer 122 and extend into the substrate 11 in the second region HV.

[0091] At this time, the filling layer 123 fills the second shallow isolation trench Q2 to form a second shallow trench isolation structure.

[0092] The number of the first shallow isolation groove Q1 and the second shallow isolation groove Q2 is determined according to the number of electronic devices, and the cross-sectional shape thereof is, for example, a trapezoid. The first shallow isolation groove Q1 and the second shallow isolation groove Q2 usually have the same depth and width, and can be formed in the same etching process. For example, a mask is designed according to the positions of the first shallow isolation groove Q1 and the second shallow isolation groove Q2 to pattern the first photoresist layer 13, and then the first shallow isolation groove Q1 and the second shallow isolation groove Q2 are formed synchronously by etching. In other embodiments, the first shallow isolation groove Q1 and the second shallow isolation groove Q2 may also have different depths and / or widths, and can be formed in different etching processes, which is not limited here.

[0093] It should be pointed out that when a fin field effect transistor is formed on the first region LV and a planar transistor is formed on the second region HV, since the width of the planar transistor is usually larger than the width of the fin field effect transistor, the spacing distance between two adjacent second shallow isolation trenches Q2 is usually larger than the spacing distance between two adjacent first shallow isolation trenches Q1.

[0094] Step S103 , forming a first opening K1 and at least two second openings K2 in the dielectric layer 12 , wherein the first opening K1 extends into the first shallow isolation trench Q1 and exposes the top of the fin 111 , and the second opening K2 is located on the second region HV and penetrates the dielectric layer 12 .

[0095] Among them, see Figure 2i The first opening K1 is used to expose the top of the fin 111, and the second opening K2 is used to expose the source region s and the drain region d of the second region HV. The first opening K1 and the second opening K2 are completed in the same etching process, that is, the first opening K1 and the second opening K2 are formed by a single mask.

[0096] In some implementations, the above step S103 may specifically include:

[0097] A second mask layer 14 is formed on the dielectric layer 12 (see Figure 2e );

[0098] A patterned second photoresist layer 15 is formed on the second mask layer 14 through the same mask plate. A first preliminary opening 151 and at least two second preliminary openings 152 are formed in the second photoresist layer 15, which penetrates the second photoresist layer 15. The second preliminary opening 152 is located above the second region HV, and the first preliminary opening 151 is located above the first region LV (see Figure 2f );

[0099] The first opening K1 is formed in the dielectric layer 12 through the first preliminary opening 151; meanwhile, the second opening K2 is formed in the dielectric layer 12 through the second preliminary opening 152 (see Figure 2g-Figure 2i ).

[0100] The second mask layer 14 is a hard mask layer, and its material may include nitride, such as silicon nitride or titanium nitride, or may include polysilicon. The second mask layer 14 may be formed by a process such as CVD, PVD or plasma assisted deposition. The material of the second photoresist layer 15 includes photoresist, which may be a positive photoresist or a negative photoresist. The second photoresist layer 15 may be formed on the second mask layer 14 by a photolithography process such as exposure and development.

[0101] In some embodiments, see Figure 2f-Figure 2iThe above step of “forming a first opening K1 in the dielectric layer 12 through the first preliminary opening 151 and forming a second opening K2 in the dielectric layer 12 through the second preliminary opening 152” may specifically include:

[0102] A first etching opening M1 is formed through the first preliminary opening 151 , penetrating the second mask layer 14 and extending into the first shallow isolation trench Q1 , wherein the first etching opening M1 exposes the sidewall of the top of the fin 111 ;

[0103] A second etching opening M2 is formed through the second preliminary opening 152 , penetrating the second mask layer 14 and extending to the upper surface of the substrate 11 in the second region HV;

[0104] The second photoresist layer 15 , the second mask layer 14 , the filling layer 123 and the first mask layer 122 outside the first shallow isolation trench Q1 are removed to expose the top and obtain a first opening K1 corresponding to the first etching opening M1 and a second opening K2 corresponding to the second etching opening M2.

[0105] The first etching opening M1 and the second etching opening M2 are simultaneously made in the same etching process. The etching process can be completed in multiple etching steps. For example, in the above Figure 2g to Figure 2h The etching is completed in two steps. The first etching is performed with the second photoresist layer 15 as a mask and the upper surface of the gate dielectric layer 121 in the second region HV as the etching stop position. The first etching is performed by controlling the etching time (the structure after etching can be seen in FIG. Figure 2g ), at this time, the first mask layer 122 and the second mask layer 14 are both opened. Then, the second photoresist layer 15 and the first mask layer 122 are used as masks, and the second etching is performed by controlling the material ratio and etching time (the structure after etching can be seen in Figure 2h ), ensuring that the gate dielectric layer 121 on the second region HV in the substrate 11 can be opened without damaging the substrate 11, exposing the source region s and the drain region d, and at the same time etching away part of the filling layer 123 in the first shallow isolation trench Q1, so that the surface of the filling layer 123 around the fin 111 is recessed, exposing the two side walls of the top of the fin 111. In other embodiments, the number of etchings to form the first etching opening M1 and the second etching opening M2 can be other cases, which are not limited here.

[0106] In some embodiments, when the first mask layer 122 and the second mask layer 14 are both made of silicon nitride material, hot phosphoric acid can be used to remove the second mask layer 14 and the first mask layer 122 by wet etching. When the second mask layer 14 is made of polysilicon material and the first mask layer 122 is made of silicon nitride material, a tetramethylammonium hydroxide (TMAH) solution can be used to remove the second mask layer 14 first, and then the first mask layer 122 can be removed by hot phosphoric acid. Since TMAH has a strong corrosive effect on both polysilicon and single crystal silicon, in order to avoid damaging the fin 111 when removing the second mask layer 14 by a wet etching process, in some embodiments, before removing the second mask layer 14, carbon or germanium doping can be performed on both sides of the top of the exposed fin 111, so as to greatly slow down the etching speed of the etching solution on both sides of the top of the fin 111, thereby protecting the top of the fin 111.

[0107] Step S104 , forming a first gate structure 161 and a second gate structure 162 , wherein the first gate structure 161 wraps the top, and the second gate structure 162 is located on the dielectric layer 12 between two adjacent second openings K2 .

[0108] Among them, see Figure 2j The second gate structure 162 is planar and has only a single surface for controlling the channel, while the first gate structure 161 surrounds the top of the fin 111 from three sides and has three surfaces for controlling the channel, which greatly enhances the gate control capability and can effectively suppress the short channel effect.

[0109] In some embodiments, for example, please continue to refer to the above Figure 2i and Figure 2j Before forming the first gate structure 161, it is necessary to cover the surface of the fin 111 with a gate insulating layer (not shown in the figure) to prevent the subsequent first gate structure 161 from contacting the fin 111. At this time, the above step S104 may specifically include:

[0110] forming a gate insulating layer wrapping the top end;

[0111] Forming a first gate (not shown in the figure) located on the gate insulating layer and a second gate (not shown in the figure) located on the dielectric layer (mainly referring to the gate dielectric layer 121) between two adjacent second openings K2;

[0112] Sidewall spacers (not shown in the figure) are formed on both sides of the first gate and on both sides of the second gate respectively.

[0113] The material of the gate insulating layer includes oxide, such as silicon oxide, and the material thereof may be the same as or different from the material of the gate dielectric layer 121. Each gate structure includes a gate and sidewalls on both sides of the gate, and the gate insulating layer and the gate may be formed by processes such as CVD, PVD or plasma assisted deposition. The material of the gate may include polysilicon, and the material of the sidewall may include at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, boron nitride and boron carbonitride, which are mainly used to protect the gate.

[0114] Step S105 , forming a source S and a drain D in the second region HV through the second opening K2 .

[0115] Among them, see Figure 2k The source S and the drain D of the semiconductor device 10 in the second region HV may be formed by ion implantation. For example, boron ions may be implanted for a P-type semiconductor device, and arsenic ions may be implanted for an N-type semiconductor device.

[0116] It should be emphasized that the second opening K2 and the first opening K1 in the embodiment of the present application are made synchronously, that is, the first opening K1 and the second opening K2 are formed synchronously by the same mask before the first gate structure 161 and the second gate structure 162 are formed. In other embodiments, the second opening K2 and the first opening K1 are made separately, for example, the first opening K1 is formed first, then the first gate structure 161 and the second gate structure 162 are made, and then the second opening K2 is formed. For details, please refer to Figures 3a to 3d , wherein the structure of the semiconductor device 10 before forming the first opening K1 can be referred to above Figures 2a to 2e . See Figure 3a-3b , a first opening K1 may be formed through a mask to expose the top of the fin 111, and then a first gate structure 161 and a second gate structure 162 may be formed (for details, see Figure 3c ), and then a second opening K2 is formed through another mask to expose the source region s and the drain region d (for the specific structure, see Figure 3d ).

[0117] It is easy to see that, compared with the above-mentioned implementation of forming the first opening K1 and the second opening K2 in steps, the implementation of forming the first opening K1 and the second opening K2 simultaneously not only saves the number of masks, but also greatly simplifies the process flow and reduces the process cost.

[0118] In some embodiments, after forming the source S and the drain D, the method for manufacturing the semiconductor device 10 further includes the following steps:

[0119] A planarization layer (not shown in the figure) is formed on the dielectric layer (mainly the gate dielectric layer 121 ), and the planarization layer covers the first gate structure 161 , the second gate structure 162 , the source electrode S and the drain electrode D;

[0120] Leads (not shown in the figure) respectively contacting the first gate structure 161 , the second gate structure 162 , the source S and the drain D are formed in the planarization layer.

[0121] The material of the planarization layer (not shown in the figure) includes phosphorus silicon glass PSG, and the material of the lead (not shown in the figure) includes a metal material, such as aluminum. The planarization layer can be first formed by a process such as CVD, PVD or plasma assisted deposition, and then a plurality of contact holes are formed that penetrate the planarization layer and extend to the first gate structure 161, the second gate structure 162, the source S and the drain D respectively, and then a layer of metal material is deposited to fill the contact holes, and the metal material is etched to obtain the lead.

[0122] In summary, the manufacturing method of the semiconductor device 10 provided in the embodiment of the present application is through forming a dielectric layer 12 and a plurality of first shallow isolation trenches Q1 arranged at intervals on a substrate 11, the substrate 11 includes a first region LV and a second region HV, the dielectric layer 12 fills the first shallow isolation trench Q1, the first shallow isolation trench Q1 is located in the first region LV, the substrate 11 between two adjacent first shallow isolation trenches Q1 forms a fin 111, then, a first opening K1 and at least two second openings K2 are formed, the first opening K1 exposes the top of the fin 111, the second opening K2 penetrates the dielectric layer 12 on the second region HV, then, a first gate structure 161 and a second gate structure 162 are formed, the first gate structure 161 wraps the top, and the second gate structure 162 is located on the dielectric layer 12 between two adjacent second openings K2, and then, through the second opening K2, a source S and a drain D are formed in the second region HV, thereby simplifying the manufacturing process of the semiconductor device 10, saving the number of mask plates, reducing process costs, and shortening the production cycle.

[0123] Based on the above-mentioned method for manufacturing a semiconductor device, an embodiment of the present application further provides a semiconductor device, which is manufactured using any of the above-mentioned methods for manufacturing a semiconductor device. Its structure and manufacturing process can be referred to in the above-mentioned embodiment and will not be described in detail here. It should be pointed out that the semiconductor device can be any circuit involving a high-voltage device and a low-voltage device, or a peripheral circuit in a memory.

[0124] In addition, the present application also provides a memory system, see Figure 4The memory system 100 includes any semiconductor device 10 provided in the embodiments of the present application, and a controller 20 coupled to the semiconductor device 10, and the controller 20 is used to control the semiconductor device 10 to perform data writing and reading operations. The semiconductor device 10 may include an array storage structure 101 and a peripheral circuit 102, and the electronic components in the peripheral circuit 102 may be prepared by any of the above-mentioned semiconductor device manufacturing methods. It should be noted that the array storage structure 101 and the peripheral circuit 102 are Figure 4 The positions shown in the figure do not represent the actual positions of the two in the semiconductor device 10. Figure 4 It is only used to describe the communication connection relationship between the components in the memory system. In the actual semiconductor device structure, the array storage structure 101 and the peripheral circuit 102 are stacked and arranged, and the two are not staggered.

[0125] The peripheral circuit 102 is configured to perform operations such as reading, writing, erasing and verifying on the array storage structure 101, and the peripheral circuit 102 may include a word line driver, a bit line driver, a column decoder, a sensing circuit, a data buffer, a program verification logic and an erase verification circuit, etc., which can perform the above operations according to the acquired computer program instructions.

[0126] In the example of the present application, the semiconductor device 10 may be a three-dimensional NAND memory, and the array storage structure 101 may be a three-dimensional NAND array storage structure. However, the semiconductor device 10 is not limited to a three-dimensional NAND memory, and the array storage structure 101 is not limited to a three-dimensional NAND array storage structure. Without violating the disclosure or teaching of the present application, the semiconductor device 10 and the array storage structure 101 may be implemented as other types of non-volatile memories and non-volatile array storage structures that can retain stored data when the power is turned off.

[0127] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, It is characterized in that include: providing a substrate, the substrate comprising a first region and a second region; forming a dielectric layer and a plurality of first shallow isolation trenches spaced apart on the substrate, wherein the dielectric layer fills the first shallow isolation trenches, the first shallow isolation trenches are located in the first region, and the substrate between two adjacent first shallow isolation trenches forms a fin; forming a first opening and at least two second openings in the dielectric layer in the same process step, wherein the first opening extends into the first shallow isolation trench and exposes the top of the fin, and the second opening is located on the second region and penetrates the dielectric layer; forming a first gate structure and a second gate structure, wherein the first gate structure wraps the top end, and the second gate structure is located on the dielectric layer between two adjacent second openings; A source and a drain are formed in the second region through the second opening.

2. The method for manufacturing a semiconductor device according to claim 1, It is characterized in that The step of forming a first opening and at least two second openings in the dielectric layer comprises: forming a second mask layer on the dielectric layer; Using the same mask, forming a patterned second photoresist layer on the second mask layer, wherein a first preliminary opening and at least two second preliminary openings penetrating the second photoresist layer are formed in the second photoresist layer, wherein the positions of the second preliminary openings correspond to the second region, and the positions of the first preliminary openings correspond to the first region; A first opening is formed in the dielectric layer through the first preliminary opening, and simultaneously, a second opening is formed in the dielectric layer through the second preliminary opening.

3. The method for manufacturing a semiconductor device according to claim 2, It is characterized in that The dielectric layer includes a gate dielectric layer, a first mask layer and a filling layer. The step of forming the dielectric layer and a plurality of first shallow isolation trenches spaced apart on the substrate includes: forming the gate dielectric layer on the substrate; forming the first mask layer on the gate dielectric layer; forming a plurality of first shallow isolation trenches spaced apart from each other, wherein the first shallow isolation trenches penetrate the first mask layer and extend into the substrate in the first region; A filling layer is formed on the first mask layer, and the filling layer fills the first shallow isolation trench.

4. The method for manufacturing a semiconductor device according to claim 3, It is characterized in that The step of forming the first opening in the dielectric layer through the first preliminary opening and forming the second opening in the dielectric layer through the second preliminary opening comprises: A first etching opening is formed through the first preliminary opening, penetrating the second mask layer and extending into the first shallow isolation trench, wherein the first etching opening exposes a side wall of a top end of the fin portion; forming a second etching opening penetrating through the second mask layer and extending to the upper surface of the substrate in the second region through the second preliminary opening; The second photoresist layer, the second mask layer, the filling layer outside the first shallow isolation groove and the first mask layer are removed to expose the top and obtain a first opening corresponding to the first etching opening and a second opening corresponding to the second etching opening.

5. The method for manufacturing a semiconductor device according to claim 3, It is characterized in that The step of forming a plurality of first shallow isolation trenches arranged at intervals comprises: forming a patterned first photoresist layer on the first mask layer; Sequentially etching the first mask layer, the gate dielectric layer, and the substrate to form a plurality of first shallow isolation trenches penetrating the first mask layer and extending into the substrate in the first region; The first photoresist layer is removed.

6. The method for manufacturing a semiconductor device according to claim 5, It is characterized in that The step of forming a plurality of first shallow isolation trenches spaced apart from each other further includes: forming a plurality of second shallow isolation trenches spaced apart from each other, wherein the second shallow isolation trenches penetrate the first mask layer and extend into the substrate in the second region; Wherein, the filling layer fills the second shallow isolation trench.

7. The method for manufacturing a semiconductor device according to claim 1, It is characterized in that The step of forming the first gate structure and the second gate structure includes: forming a gate insulating layer wrapping the top end; forming a first gate located on the gate insulating layer and a second gate located on the dielectric layer between two adjacent second openings; Sidewall spacers are formed on both sides of the first gate and both sides of the second gate respectively.

8. The method for manufacturing a semiconductor device according to claim 1, It is characterized in that After forming the source and the drain, the method further comprises: forming a planarization layer on the dielectric layer, wherein the planarization layer covers the first gate structure, the second gate structure, the source electrode, and the drain electrode; Leads are formed in the planarization layer to contact the first gate structure, the second gate structure, the source electrode, and the drain electrode, respectively.

9. A semiconductor device, It is characterized in that The semiconductor device is manufactured by the manufacturing method according to any one of claims 1 to 8.

10. A memory system, It is characterized in that The method comprises at least one semiconductor device as claimed in claim 9 and a controller coupled to the semiconductor device, wherein the controller is used to control the semiconductor device to perform data writing and reading operations.

Images