Semiconductor device and method for manufacturing the same

Abstract

The present disclosure relates to a semiconductor device and a method for manufacturing the same. The semiconductor device includes: a cell stack structure comprising a first cell stack layer and a stacked conductive layer; a cell plug penetrating the cell stack structure; and a cell chip protector surrounding the cell stack structure and the cell plug. The cell chip protector includes a protector semiconductor layer and a protector insulating layer covering sidewalls of the protector semiconductor layer.

Description

Technical Field

[0001] The present disclosure generally relates to a semiconductor device and a method for manufacturing the semiconductor device, and more particularly, to a three-dimensional semiconductor device and a method for manufacturing the three-dimensional semiconductor device. Background Art

[0002] A semiconductor device includes memory cells capable of storing data. A three-dimensional semiconductor device includes memory cells arranged three-dimensionally, thereby reducing the area of a substrate occupied by the memory cells.

[0003] In order to improve the integration density of a three-dimensional semiconductor device, the number of stacked memory cells may be increased. As the number of stacked memory cells increases, the operational reliability of the three-dimensional semiconductor device may decrease. Summary of the Invention

[0004] According to one aspect of the present disclosure, a semiconductor device can be provided, which includes: a unit stacking structure, the unit stacking structure including an overlapping first unit stacking layer and a stacked conductive layer; a unit plug, the unit plug penetrating the unit stacking structure; and a unit chip protection member, the unit chip protection member surrounding the unit stacking structure and the unit plug, wherein the unit chip protection member includes a protection member semiconductor layer and a protection member insulating layer covering the sidewalls of the protection member semiconductor layer.

[0005] According to another aspect of the present disclosure, a semiconductor device may be provided, comprising: a unit stack structure comprising alternately stacked conductive layers and a first unit stack layer; a unit plug penetrating the unit stack structure; and a protection member plug surrounding the unit stack structure and the unit plug, wherein the protection member plug comprises a plug semiconductor layer and a plug insulating layer surrounding the plug semiconductor layer.

[0006] According to another aspect of the present disclosure, a semiconductor device may be provided, comprising: a cell stack structure comprising alternatingly stacked conductive layers and a first cell stack layer; a cell plug penetrating the cell stack structure; a first cell chip protection member surrounding the cell stack structure and the cell plug; a cell source structure connected to the cell plug; and a first dummy source structure connected to the first cell chip protection member, wherein the first dummy source structure surrounds the cell source structure.

[0007] According to another aspect of the present disclosure, a method for manufacturing a semiconductor device may be provided, the method comprising the following steps: forming alternately stacked first unit layer stacks and second unit layer stacks, and alternately stacked first dummy layer stacks and second dummy layer stacks; forming unit holes penetrating the first unit layer stacks and the second unit layer stacks, and protective member grooves penetrating the first dummy layer stacks and the second dummy layer stacks, wherein the protective member grooves surround the unit holes; forming a first material layer covering the surface of the unit holes and the protective member grooves; and forming a second material layer covering the surface of the first material layer.

[0008] According to another aspect of the present disclosure, a method for manufacturing a semiconductor device may be provided, the method comprising the following steps: forming alternately stacked first unit layer stacks and second unit layer stacks, and alternately stacked first dummy layer stacks and second dummy layer stacks; forming unit holes penetrating the first unit layer stacks and the second unit layer stacks, and protective member holes penetrating the first dummy layer stacks and the second dummy layer stacks, wherein the protective member holes surround the unit holes; forming a first material layer covering the surfaces of the unit holes and the protective member holes; and forming a second material layer covering the surface of the first material layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Examples of implementations will be described more fully hereinafter with reference to the accompanying drawings; however, they may be embodied in different forms and should not be construed as limited to only the implementations set forth herein.

[0010] In the accompanying drawings, dimensions may be exaggerated for clarity of illustration. It should be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements, or one or more intermediate elements may also be present. Throughout the text, the same reference numerals refer to the same elements.

[0011] Hereinafter, the terms "first" and "second" are used to distinguish one component from another component. The terms can be used to describe various components, but the components are not limited by the terms.

[0012] Figure 1A is a plan view of a semiconductor device according to an embodiment of the present disclosure.

[0013] Figure 1B It is along Figure 1A A cross-sectional view taken along line A1-A1' shown in FIG.

[0014] Figure 1C It is along Figure 1A sectional view taken along line B1 - B1 ′ shown in FIG.

[0015] Figure 1D It is along Figure 1A A cross-sectional view taken along line C1-C1' shown in FIG.

[0016] Figure 1E It shows that according to Figures 1A to 1D A perspective view of a unit chip protection member and an upper chip protection member of a semiconductor device according to the embodiment shown.

[0017] Figure 1F It shows that according to Figures 1A to 1D A perspective view of a lower chip protection member of a semiconductor device according to the embodiment shown.

[0018] Figure 2A 、 Figure 2B 、 Figure 3A 、 Figure 3B 、 Figure 4A and Figure 4B is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0019] Figure 5A is a plan view of a semiconductor device according to an embodiment of the present disclosure.

[0020] Figure 5B It is along Figure 5A A cross-sectional view taken along line A2-A2' shown in FIG.

[0021] Figure 5C It is along Figure 5A A cross-sectional view taken along line B2-B2' shown in FIG.

[0022] Figure 5D It shows that according to Figures 5A to 5C A perspective view of a protection plug and an upper chip protection member of a semiconductor device according to the embodiment shown.

[0023] Figure 6 、 Figure 7 and Figure 8 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0024] Figure 9 is a block diagram illustrating a configuration of a memory system according to an embodiment of the present disclosure.

[0025] Figure 10 is a block diagram illustrating a configuration of a computing system according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0026] The specific structural or functional descriptions disclosed herein are merely illustrative and are intended to describe embodiments of the present disclosure. Embodiments of the present disclosure can be implemented in various forms and should not be construed as being limited to the embodiments described herein.

[0027] Embodiments may provide a semiconductor device having improved operational reliability and a method of manufacturing the semiconductor device.

[0028] Figure 1A 1 is a plan view of a semiconductor device according to an embodiment of the present disclosure. For ease of description, the bit line BL, the bit line contact portion BCT, the second insulating layer 120, and the first and second upper chip protection members UG1 and UG2 are not shown. Figure 1A . Figure 1B It is along Figure 1A A cross-sectional view taken along line A1-A1' is shown. Figure 1C It is along Figure 1A A cross-sectional view taken along line B1-B1' is shown. Figure 1D It is along Figure 1A A cross-sectional view taken along line C1-C1' is shown. Figure 1E It shows that according to Figures 1A to 1D A perspective view of a unit chip protection member and an upper chip protection member of a semiconductor device according to the embodiment shown. Figure 1F It shows that according to Figures 1A to 1D A perspective view of a lower chip protection member of a semiconductor device according to the embodiment shown.

[0029] Reference Figures 1A to 1D The semiconductor device may include a substrate 100. The substrate 100 may have a plate shape extending along a plane defined by a first direction D1 and a second direction D2. The first direction D1 and the second direction D2 may intersect each other. In one example, the first direction D1 and the second direction D2 may be orthogonal to each other. The substrate 100 may be a semiconductor substrate. In one example, the substrate 100 may be a silicon substrate.

[0030] The substrate 100 may include a cell region CER and a chip protector region CGR. The cell region CER and the chip protector region CGR may be regions distinguished from each other on a plane. The chip protector region CGR may surround the cell region CER.

[0031] The chip protection region CGR may include a first region RG1 and a second region RG2. The first region RG1 may extend in a first direction D1. The second region RG2 may extend in a second direction D2. The first regions RG1 may be spaced apart from each other in the second direction D2. The cell regions CER may be disposed between the first regions RG1. The second regions RG2 may be spaced apart from each other in the first direction D1. The cell regions CER may be disposed between the second regions RG2.

[0032] A first insulating layer 110 may be provided covering the substrate 100. The first insulating layer 110 may include an insulating material. In one example, the first insulating layer 110 may include oxide or nitride. The first insulating layer 110 may be a multilayer including a plurality of insulating layers.

[0033] The peripheral transistor TR may be provided between the substrate 100 and the first insulating layer 110. The peripheral transistor TR may be provided on the cell region CER of the substrate 100. The peripheral transistor TR may constitute a peripheral circuit of the semiconductor device or may be a transistor connected to the peripheral circuit of the semiconductor device.

[0034] Each peripheral transistor TR may include an impurity region IR, a gate insulating layer GI, and a gate GM. The impurity regions IR of the peripheral transistors TR may be spaced apart from each other, with the gate insulating layer GI interposed therebetween. The channel of the peripheral transistor TR may be disposed between the impurity regions IR. The gate GM may be spaced apart from the channel of the peripheral transistor TR by the gate insulating layer GI. The impurity regions IR may be formed by doping impurities into the substrate 100. The gate insulating layer GI may include an insulating material. In one example, the gate insulating layer GI may include an oxide. The gate GM may include a conductive material. In one example, the gate GM may include tungsten.

[0035] An isolation layer IS may be provided in the substrate 100. The isolation layer IS may electrically isolate regions of the substrate 100 from each other. The isolation layer IS may include an insulating material. In one example, the isolation layer IS may include an oxide.

[0036] The first contact portion CT1 and the first line ML1 may be provided in the first insulating layer 110. The first contact portion CT1 and the first line ML1 may be provided on the cell region CER of the substrate 100. Each first contact portion CT1 may connect the peripheral transistor TR and the first line ML1 to each other, and may connect the first lines ML1 to each other. The first line ML1 may be connected to the first contact portion CT1. The first contact portion CT1 and the first line ML1 may include a conductive material. In one example, the first contact portion CT1 and the first line ML1 may include tungsten.

[0037] The cell source structure CSS, the first dummy source structure DSS1, and the second dummy source structure DSS2 may be disposed on the first insulating layer 110. The cell source structure CSS may be disposed on the cell region CER of the substrate 100. The first dummy source structure DSS1 and the second dummy source structure DSS2 may be disposed on the chip protection region CGR of the substrate 100. The first dummy source structure DSS1 may surround the cell source structure CSS. The second dummy source structure DSS2 may surround the cell source structure CSS and the first dummy source structure DSS1.

[0038] The cell source structure CSS may include a first cell source layer CSL1, a second cell source layer CSL2, and a third cell source layer CSL3 stacked sequentially in a third direction D3. The third direction D3 may be a direction intersecting the first direction D1 and the second direction D2. In one example, the third direction D3 may be a direction orthogonal to the first direction D1 and the second direction D2. The second cell source layer CSL2 may be disposed on the first cell source layer CSL1, and the third cell source layer CSL3 may be disposed on the second cell source layer CSL2. The first to third cell source layers CSL1, CSL2, and CSL3 may include a conductive material. In one example, the first to third cell source layers CSL1, CSL2, and CSL3 may include doped polysilicon.

[0039] Each of the first dummy source structure DSS1 and the second dummy source structure DSS2 may include a first dummy source layer DSL1, a first etch-stop layer ESL1, a second dummy source layer DSL2, a second etch-stop layer ESL2, and a third dummy source layer DSL3, which are sequentially stacked in a third direction D3. The first etch-stop layer ESL1 may be disposed on the first dummy source layer DSL1. The second dummy source layer DSL2 may be disposed on the first etch-stop layer ESL1, and the second etch-stop layer ESL2 may be disposed on the second dummy source layer DSL2. The third dummy source layer DSL3 may be disposed on the second etch-stop layer ESL2.

[0040] The first dummy source layer DSL1 may be disposed at the same height as the first cell source layer CSL1. The third dummy source layer DSL3 may be disposed at the same height as the third cell source layer CSL3. The first to third dummy source layers DSL1, DSL2, and DSL3 may include a semiconductor material. In one example, the first to third dummy source layers DSL1, DSL2, and DSL3 may include polysilicon. The first etch stop layer ESL1 and the second etch stop layer ESL2 may include a material having an etch selectivity relative to the material included in the first to third dummy source layers DSL1, DSL2, and DSL3. In one example, the first etch stop layer ESL1 and the second etch stop layer ESL2 may include an oxide.

[0041] Although the case where the number of dummy source structures DSS1 and DSS2 is two has been illustrated and described, the number of dummy source structures DSS1 and DSS2 may not be limited thereto. In one example, the number of dummy source structures DSS1 and DSS2 may be one, or may be three or more.

[0042] The insulating structure IST may be disposed between the first dummy source structure DSS1 and the second dummy source structure DSS2. The insulating structure IST may be disposed on the chip protection region CGR of the substrate 100. The first dummy source structure DSS1 and the second dummy source structure DSS2 may be separated from each other by the insulating structure IST. The insulating structure IST may include an insulating material. In one example, the insulating structure IST may include an oxide.

[0043] The first lower chip protection member LG1 may be disposed in the first insulating layer 110 and the first dummy source structure DSS1. The second lower chip protection member LG2 may be disposed in the first insulating layer 110 and the second dummy source structure DSS2. The first lower chip protection member LG1 and the second lower chip protection member LG2 may be disposed on the chip protection member region CGR of the substrate 100. Although the case where the number of the lower chip protection members LG1 and LG2 is two has been shown and described, the number of the lower chip protection members LG1 and LG2 may not be limited thereto. In one example, the number of the lower chip protection members LG1 and LG2 may be one, or may be three or more. The first lower chip protection member LG1 and the second lower chip protection member LG2 will be described later.

[0044] The cell stack structure CST may be disposed on the cell source structure CSS. The cell stack structure CST may be disposed on the cell region CER of the substrate 100. The cell stack structure CST may include stacked conductive layers SCL and a first cell stack layer CIL1 alternately stacked in a third direction D3. The stacked conductive layer SCL may serve as a word line or a select line of the semiconductor device. The stacked conductive layer SCL may include a conductive material. In one example, the stacked conductive layer SCL may include tungsten. The first cell stack layer CIL1 may include an insulating material. In one example, the first cell stack layer CIL1 may include an oxide.

[0045] A cell plug CPL may be provided that penetrates the cell stack structure CST. The cell plug CPL may be provided on the cell region CER of the substrate 100. The cell plug CPL may extend in a third direction D3. The cell plug CPL may include a cell fill layer CFI, a cell channel layer CCL surrounding the cell fill layer CFI, and a cell memory layer CML surrounding the cell channel layer CCL. The cell fill layer CFI, the cell channel layer CCL, and the cell memory layer CML may penetrate the cell stack structure CST while extending along the third direction D3.

[0046] The cell fill layer CFI may include an insulating material. In one example, the cell fill layer CFI may include an oxide. The cell channel layer CCL may include a semiconductor material. In one example, the cell channel layer CCL may include polysilicon. The cell memory layer CML may include a tunnel insulating layer surrounding the cell channel layer CCL, a data storage layer surrounding the tunnel insulating layer, and a blocking layer surrounding the data storage layer. The tunnel insulating layer may include a material through which charges can tunnel. In one example, the tunnel insulating layer may include an oxide. In one embodiment, the data storage layer may include a material that can capture charges. In one example, the data storage layer may include a nitride. In another embodiment, the data storage layer may include various materials depending on the data storage method. In one example, the data storage layer may include silicon, a phase change material, or nanodots. The blocking layer may include a material that can block the movement of charges. In one example, the blocking layer may include an oxide.

[0047] The cell plug CPL may penetrate the second cell source layer CSL2 and the third cell source layer CSL3 of the cell source structure CSS. The cell plug CPL may be connected to the second cell source layer CSL2. The cell channel layer CCL of the cell plug CPL may contact the second cell source layer CSL2. The cell channel layer CCL of the cell plug CPL may be electrically connected to the second cell source layer CSL2.

[0048] The cell plug CPL may include an upper portion CPL_U and a lower portion CPL_L. The upper portion CPL_U of the cell plug CPL may penetrate the upper portion of the cell stack structure CST. The lower portion CPL_L of the cell plug CPL may penetrate the lower portion of the cell stack structure CST. The width of the upper portion CPL_U of the cell plug CPL may become smaller as the width becomes closer to the substrate 100. The width of the lower portion CPL_L of the cell plug CPL may become smaller as the width becomes closer to the substrate 100.

[0049] The dummy stack structure DST may be disposed on the first dummy source structure DSS1, the second dummy source structure DSS2, and the insulation structure IST. The dummy stack structure DST may be disposed on the chip protection region CGR of the substrate 100. The dummy stack structure DST may surround the cell stack structure CST. The dummy stack structure DST may include a first dummy stack layer DIL1 and a second dummy stack layer DIL2 alternately stacked in a third direction D3. The first dummy stack layer DIL1 may include an insulating material. In one example, the first dummy stack layer DIL1 may include an oxide. The second dummy stack layer DIL2 may include an insulating material different from the insulating material of the first dummy stack layer DIL1. In one example, the second dummy stack layer DIL2 may include a nitride. The first dummy stack layer DIL1 may be seamlessly connected to the first cell stack layer CIL1. In other words, the first dummy stack layer DIL1 and the first cell stack layer CIL1 may be integrally formed.

[0050] A first unit chip protection member CG1 and a second unit chip protection member CG2 may be provided that penetrate the dummy stack structure DST. The first unit chip protection member CG1 and the second unit chip protection member CG2 may be provided on the chip protection member region CGR of the substrate 100. Although a case where the number of unit chip protection members CG1 and CG2 is two has been shown and described, the number of unit chip protection members CG1 and CG2 may not be limited thereto. In one example, the number of unit chip protection members CG1 and CG2 may be one, or may be three or more. The first unit chip protection member CG1 and the second unit chip protection member CG2 will be described later.

[0051] A second insulating layer 120 covering the cell stack structure CST and the dummy stack structure DST may be provided. The second insulating layer 120 may include an insulating material. In one example, the second insulating layer 120 may include oxide or nitride. The second insulating layer 120 may be a multilayer including a plurality of insulating layers.

[0052] The bit line contact portion BCT and the bit line BL may be disposed in the second insulating layer 120. The bit line contact portion BCT and the bit line BL may be disposed on the cell region CER of the substrate 100. The bit line contact portion BCT may connect the cell channel layer CCL of the cell plug CPL to the bit line BL. The bit line BL may extend in the second direction D2. The bit lines BL may be spaced apart from each other in the first direction D1. The bit line contact portion BCT and the bit line BL may include a conductive material. In one example, the bit line contact portion BCT and the bit line BL may include tungsten.

[0053] A first upper chip protection member UG1 and a second upper chip protection member UG2 may be provided in the second insulating layer 120. The first upper chip protection member UG1 and the second upper chip protection member UG2 may be provided on the chip protection member region CGR of the substrate 100. Although the case where two upper chip protection members UG1 and UG2 are provided has been illustrated and described, the number of upper chip protection members UG1 and UG2 is not limited thereto. In one example, the number of upper chip protection members UG1 and UG2 may be one, or may be three or more. The first upper chip protection member UG1 and the second upper chip protection member UG2 will be described later.

[0054] Reference Figures 1A to 1F The first lower chip protection member LG1 may surround the first contact portion CT1, the first line ML1, and the cell source structure CSS. The second lower chip protection member LG2 may surround the first contact portion CT1, the first line ML1, the cell source structure CSS, and the first lower chip protection member LG1.

[0055] The first lower chip protection member LG1 may include a first portion extending in a first direction D1 and a second portion extending in a second direction D2. The first portions of the first lower chip protection member LG1 may be spaced apart from each other in the second direction D2. The second portions of the first lower chip protection member LG1 may be spaced apart from each other in the first direction D1. The first portion of the first lower chip protection member LG1 may be disposed on the first region RG1 of the substrate 100. The second portion of the first lower chip protection member LG1 may be disposed on the second region RG2 of the substrate 100. The first contact portion CT1, the first line ML1, and the cell source structure CSS may be disposed between the first portion of the first lower chip protection member LG1. The first contact portion CT1, the first line ML1, and the cell source structure CSS may be disposed between the second portion of the first lower chip protection member LG1. The first and second portions of the first lower chip protection member LG1 may be connected to each other. The first contact portion CT1, the first line ML1, and the cell source structure CSS may be surrounded by the first and second portions of the first lower chip protection member LG1.

[0056] The first lower chip protection member LG1 may include a first lower protection member part LP1 and a first penetration protection member part PP1. The first lower protection member part LP1 and the first penetration protection member part PP1 may be sequentially arranged along the third direction D3. The first lower protection member part LP1 and the first penetration protection member part PP1 may be connected to each other.

[0057] The first through protector part PP1 may penetrate the first dummy source structure DSS1. The top surface height of the first through protector part PP1 may be equal to the top surface height of the first dummy source structure DSS1. The first through protector part PP1 may surround the cell source structure CSS. The first lower protector part LP1 may be disposed in the first insulating layer 110. The first lower protector part LP1 may surround the first contact portion CT1 and the first line ML1.

[0058] Each of the first lower protector component LP1 and the first penetration protector component PP1 may include a first component extending in the first direction D1 and a second component extending in the second direction D2. The first component of each of the first lower protector component LP1 and the first penetration protector component PP1 may be disposed on the first region RG1 of the substrate 100. The second component of each of the first lower protector component LP1 and the first penetration protector component PP1 may be disposed on the second region RG2 of the substrate 100. The first component of each of the first lower protector component LP1 and the first penetration protector component PP1 may be spaced apart from each other in the second direction D2. The second component of each of the first lower protector component LP1 and the first penetration protector component PP1 may be spaced apart from each other in the first direction D1. The first component and the second component of each of the first lower protector component LP1 and the first penetration protector component PP1 may be connected to each other.

[0059] The first lower protector component LP1 and the first penetration protector component PP1 may include a conductive material. In one example, the first lower protector component LP1 and the first penetration protector component PP1 may include tungsten.

[0060] The second lower chip protection member LG2 may include a first portion extending in a first direction D1 and a second portion extending in a second direction D2. The first portions of the second lower chip protection member LG2 may be spaced apart from each other in the second direction D2. The second portions of the second lower chip protection member LG2 may be spaced apart from each other in the first direction D1. The first portion of the second lower chip protection member LG2 may be disposed on the first region RG1 of the substrate 100. The second portion of the second lower chip protection member LG2 may be disposed on the second region RG2 of the substrate 100. The first contact portion CT1, the first line ML1, the cell source structure CSS, and the first lower chip protection member LG1 may be disposed between the first portion of the second lower chip protection member LG2. The first contact portion CT1, the first line ML1, the cell source structure CSS, and the first lower chip protection member LG1 may be disposed between the second portion of the second lower chip protection member LG2. The first contact portion CT1, the first line ML1, the cell source structure CSS, and the first lower chip protection member LG1 may be surrounded by the first and second portions of the second lower chip protection member LG2.

[0061] The second lower chip protection member LG2 may include a second lower protection member part LP2 and a second penetration protection member part PP2. The second lower protection member part LP2 and the second penetration protection member part PP2 may be sequentially arranged along the third direction D3. The second lower protection member part LP2 and the second penetration protection member part PP2 may be connected to each other.

[0062] The second through-protector part PP2 may penetrate the second dummy source structure DSS2. The height of the top surface of the second through-protector part PP2 may be equal to the height of the top surface of the second dummy source structure DSS2. The second through-protector part PP2 may surround the cell source structure CSS and the first through-protector part PP1. The second lower protector part LP2 may be disposed in the first insulating layer 110. The second lower protector part LP2 may surround the first contact part CT1, the first line ML1, and the first lower protector part LP1.

[0063] Each of the second lower protector component LP2 and the second penetration protector component PP2 may include a first component extending in the first direction D1 and a second component extending in the second direction D2. The first component of each of the second lower protector component LP2 and the second penetration protector component PP2 may be disposed on the first region RG1 of the substrate 100. The second component of each of the second lower protector component LP2 and the second penetration protector component PP2 may be disposed on the second region RG2 of the substrate 100. The first component of each of the second lower protector component LP2 and the second penetration protector component PP2 may be spaced apart from each other in the second direction D2. The second component of each of the second lower protector component LP2 and the second penetration protector component PP2 may be spaced apart from each other in the first direction D1. The first component and the second component of each of the second lower protector component LP2 and the second penetration protector component PP2 may be connected to each other.

[0064] The second lower protector component LP2 and the second penetration protector component PP2 may include a conductive material. In one example, the second lower protector component LP2 and the second penetration protector component PP2 may include tungsten.

[0065] The first cell chip protection member CG1 may surround the cell stack structure CST and the cell plug CPL. The second cell chip protection member CG2 may surround the cell stack structure CST, the cell plug CPL, and the first cell chip protection member CG1.

[0066] The first cell chip protection member CG1 may include a first cell extension part CE1 and a second cell extension part CE2. The first cell extension part CE1 may extend in a first direction D1. The second cell extension part CE2 may extend in a second direction D2. The first cell extension parts CE1 may be spaced apart from each other in the second direction D2. The second cell extension parts CE2 may be spaced apart from each other in the first direction D1. The cell stack structure CST and the cell plugs CPL may be disposed between the first cell extension parts CE1. The cell stack structure CST and the cell plugs CPL may be disposed between the second cell extension parts CE2. Two first cell extension parts CE1 may be connected to one second cell extension part CE2. Two second cell extension parts CE2 may be connected to one first cell extension part CE1. Each first cell extension part CE1 may be disposed on each first region RG1 of the substrate 100. Each second cell extension part CE2 may be disposed on each second region RG2 of the substrate 100. The cell stack structure CST and the cell plugs CPL may be surrounded by the first cell extension part CE1 and the second cell extension part CE2.

[0067] The first unit chip protection element CG1 may include a first protection element semiconductor layer GSE1, a first protection element insulating layer GIL1, and a first protection element filling layer GFI1. The first protection element semiconductor layer GSE1 may be disposed in the first protection element insulating layer GIL1. The first protection element filling layer GFI1 may be disposed in the first protection element semiconductor layer GSE1. The first protection element semiconductor layer GSE1 may cover the sidewalls, bottom surface, and top surface of the first protection element filling layer GFI1. The first protection element insulating layer GIL1 may cover the sidewalls and bottom surface of the first protection element semiconductor layer GSE1.

[0068] The first cell chip protection member CG1 may extend along the third direction D3 while penetrating the dummy stack structure DST. Each of the first protector semiconductor layer GSE1, the first protector insulating layer GIL1, and the first protector filling layer GFI1 may extend along the third direction D3 while penetrating the dummy stack structure DST. Each of the first protector semiconductor layer GSE1, the first protector insulating layer GIL1, and the first protector filling layer GFI1 may surround the cell stack structure CST and the cell plug CPL. A portion of the first cell chip protection member CG1 may be disposed at the same height as a portion of the first lower chip protection member LG1.

[0069] Each of the first protector semiconductor layer GSE1, the first protector insulating layer GIL1, and the first protector filling layer GFI1 may include a first portion extending along a first direction D1 and a second portion extending along a second direction D2. The first portion of each of the first protector semiconductor layer GSE1, the first protector insulating layer GIL1, and the first protector filling layer GFI1 may be disposed on the first region RG1 of the substrate 100. The second portion of each of the first protector semiconductor layer GSE1, the first protector insulating layer GIL1, and the first protector filling layer GFI1 may be disposed on the second region RG2 of the substrate 100. The first portion of each of the first protector semiconductor layer GSE1, the first protector insulating layer GIL1, and the first protector filling layer GFI1 may be spaced apart from each other in the second direction D2. The second portion of each of the first protector semiconductor layer GSE1, the first protector insulating layer GIL1, and the first protector filling layer GFI1 may be spaced apart from each other in the first direction D1. The first and second parts of each of the first protector semiconductor layer GSE1 , the first protector insulating layer GIL1 , and the first protector filling layer GFI1 may be connected to each other.

[0070] The second cell chip protection member CG2 may include a third cell extension member CE3 and a fourth cell extension member CE4. The third cell extension member CE3 may extend in the first direction D1. The fourth cell extension member CE4 may extend in the second direction D2. The third cell extension members CE3 may be spaced apart from each other in the second direction D2. The fourth cell extension members CE4 may be spaced apart from each other in the first direction D1. The cell stack structure CST, the cell plug CPL, and the first cell chip protection member CG1 may be disposed between the third cell extension member CE3. The cell stack structure CST, the cell plug CPL, and the first cell chip protection member CG1 may be disposed between the fourth cell extension member CE4. Two third cell extension members CE3 may be connected to one fourth cell extension member CE4. Two fourth cell extension members CE4 may be connected to one third cell extension member CE3. Each third cell extension member CE3 may be disposed on each first region RG1 of the substrate 100. Each fourth cell extension member CE4 may be disposed on each second region RG2 of the substrate 100. The cell stack structure CST, the cell plug CPL, and the first cell chip protection member CG1 may be surrounded by the third and fourth cell extension parts CE3 and CE4 .

[0071] The second unit chip protection element CG2 may include a second protection element semiconductor layer GSE2, a second protection element insulating layer GIL2, and a second protection element filling layer GFI2. The second protection element semiconductor layer GSE2 may be disposed in the second protection element insulating layer GIL2. The second protection element filling layer GFI2 may be disposed in the second protection element semiconductor layer GSE2. The second protection element semiconductor layer GSE2 may cover the sidewalls, bottom surface, and top surface of the second protection element filling layer GFI2. The second protection element insulating layer GIL2 may cover the sidewalls and bottom surface of the second protection element semiconductor layer GSE2.

[0072] The second chip protection member CG2 may extend along the third direction D3 while penetrating the dummy stack structure DST. Each of the second protector semiconductor layer GSE2, the second protector insulating layer GIL2, and the second protector filling layer GFI2 may extend along the third direction D3 while penetrating the dummy stack structure DST. Each of the second protector semiconductor layer GSE2, the second protector insulating layer GIL2, and the second protector filling layer GFI2 may surround the cell stack structure CST, the cell plug CPL, and the first chip protection member CG1. A portion of the second chip protection member CG2 may be disposed at the same height as a portion of the second lower chip protection member LG2.

[0073] Each of the second protector semiconductor layer GSE2, the second protector insulating layer GIL2, and the second protector filling layer GFI2 may include a first portion extending along the first direction D1 and a second portion extending along the second direction D2. The first portion of each of the second protector semiconductor layer GSE2, the second protector insulating layer GIL2, and the second protector filling layer GFI2 may be disposed on the first region RG1 of the substrate 100. The second portion of each of the second protector semiconductor layer GSE2, the second protector insulating layer GIL2, and the second protector filling layer GFI2 may be disposed on the second region RG2 of the substrate 100. The first portion of each of the second protector semiconductor layer GSE2, the second protector insulating layer GIL2, and the second protector filling layer GFI2 may be spaced apart from each other in the second direction D2. The second portion of each of the second protector semiconductor layer GSE2, the second protector insulating layer GIL2, and the second protector filling layer GFI2 may be spaced apart from each other in the first direction D1. The first portion and the second portion of each of the second protector semiconductor layer GSE2, the second protector insulating layer GIL2, and the second protector filling layer GFI2 may be connected to each other.

[0074] The cell channel layer CCL, the first protective semiconductor layer GSE1, and the second protective semiconductor layer GSE2 may include the same material. In one example, the cell channel layer CCL, the first protective semiconductor layer GSE1, and the second protective semiconductor layer GSE2 may include polysilicon. The cell memory layer CML, the first protective insulating layer GIL1, and the second protective insulating layer GIL2 may include the same material. The first protective insulating layer GIL1 and the second protective insulating layer GIL2 may include a first protective layer including the same material as the tunnel insulating layer of the cell memory layer CML, a second protective layer including the same material as the data storage layer of the cell memory layer CML, and a third protective layer including the same material as the barrier layer of the cell memory layer CML. The cell fill layer CFI, the first protective fill layer GFI1, and the second protective fill layer GFI2 may include the same material. In one example, the cell fill layer CFI, the first protective fill layer GFI1, and the second protective fill layer GFI2 may include oxide.

[0075] The first and second cell chip protectors CG1 and CG2 may be disposed at the same height as the cell plugs CPL. A portion of the first and second cell chip protectors CG1, CG2, an upper portion of the first and second penetration protector parts PP1, and PP2 may be disposed at the same height.

[0076] A portion of the first unit chip protection member CG1 may be disposed in the first dummy source structure DSS1 and may penetrate the first and second etch stop layers ESL1 and ESL2 and the second and third dummy source layers DSL2 and DSL3 of the first dummy source structure DSS1.

[0077] A portion of the second unit chip protection member CG2 may be disposed in the second dummy source structure DSS2 and may penetrate the first and second etch stop layers ESL1 and ESL2 and the second and third dummy source layers DSL2 and DSL3 of the second dummy source structure DSS2.

[0078] The first unit chip protection member CG1 may include an upper portion CG1_U and a lower portion CG1_L. The upper portion CG1_U of the first unit chip protection member CG1 may penetrate the upper portion of the dummy stack structure DST. The lower portion CG1_L of the first unit chip protection member CG1 may penetrate the lower portion of the dummy stack structure DST. The width of the upper portion CG1_U of the first unit chip protection member CG1 may become smaller as the width becomes closer to the substrate 100. The width of the lower portion CG1_L of the first unit chip protection member CG1 may become smaller as the width becomes closer to the substrate 100. The minimum width of the upper portion CG1_U of the first unit chip protection member CG1 may be smaller than the maximum width of the lower portion CG1_L of the first unit chip protection member CG1. In one embodiment, the width of the upper portion CG1_U of the first unit chip protection member CG1 becomes smaller as the width becomes closer to the lower portion CG1_L of the first unit chip protection member CG1. In one embodiment, the width of the lower portion CG1_L of the first unit chip protection member CG1 becomes larger as the width becomes closer to the upper portion CG1_U of the first unit chip protection member CG1 .

[0079] The second unit chip protection member CG2 may include an upper portion CG2_U and a lower portion CG2_L. The upper portion CG2_U of the second unit chip protection member CG2 may penetrate the upper portion of the dummy stack structure DST. The lower portion CG2_L of the second unit chip protection member CG2 may penetrate the lower portion of the dummy stack structure DST. The width of the upper portion CG2_U of the second unit chip protection member CG2 may become smaller as the width becomes closer to the substrate 100. The width of the lower portion CG2_L of the second unit chip protection member CG2 may become smaller as the width becomes closer to the substrate 100. The minimum width of the upper portion CG2_U of the second unit chip protection member CG2 may be smaller than the maximum width of the lower portion CG2_L of the second unit chip protection member CG2.

[0080] The first upper chip protection member UG1 may surround the bit line contact portion BCT and the bit line BL. The second upper chip protection member UG2 may surround the bit line contact portion BCT, the bit line BL, and the first upper chip protection member UG1. The first upper chip protection member UG1 may be connected to the first unit chip protection member CG1. The second upper chip protection member UG2 may be connected to the second unit chip protection member CG2.

[0081] The first upper chip protection member UG1 may include a first portion extending in a first direction D1 and a second portion extending in a second direction D2. The first portions of the first upper chip protection member UG1 may be spaced apart from each other in the second direction D2. The second portions of the first upper chip protection member UG1 may be spaced apart from each other in the first direction D1. The first portion of the first upper chip protection member UG1 may be disposed on the first region RG1 of the substrate 100. The second portion of the first upper chip protection member UG1 may be disposed on the second region RG2 of the substrate 100. A bit line contact BCT and a bit line BL may be disposed between the first portion of the first upper chip protection member UG1. The bit line contact BCT and the bit line BL may be disposed between the second portion of the first upper chip protection member UG1. The first portion and the second portion of the first upper chip protection member UG1 may be connected to each other.

[0082] The first upper chip protection member UG1 may include a first upper protection member part UP1. The first upper protection member parts UP1 may be sequentially arranged along the third direction D3. The first upper protection member parts UP1 may be connected to each other.

[0083] The first upper protector part UP1 may be disposed in the second insulating layer 120. The first upper protector part UP1 may surround the bit line contact part BCT and the bit line BL.

[0084] Each first upper protector part UP1 may include a first part extending in a first direction D1 and a second part extending in a second direction D2. The first part of each first upper protector part UP1 may be disposed on the first region RG1 of the substrate 100. The second part of each first upper protector part UP1 may be disposed on the second region RG2 of the substrate 100. The first part of each first upper protector part UP1 may be spaced apart from each other in the second direction D2. The second part of each first upper protector part UP1 may be spaced apart from each other in the first direction D1. The first part and the second part of each first upper protector part UP1 may be connected to each other.

[0085] The first upper protector part UP1 may include a conductive material. In one example, the first upper protector part UP1 may include tungsten.

[0086] The second upper chip protection member UG2 may include a first portion extending in the first direction D1 and a second portion extending in the second direction D2. The first portions of the second upper chip protection member UG2 may be spaced apart from each other in the second direction D2. The second portions of the second upper chip protection member UG2 may be spaced apart from each other in the first direction D1. The first portion of the second upper chip protection member UG2 may be disposed on the first region RG1 of the substrate 100. The second portion of the second upper chip protection member UG2 may be disposed on the second region RG2 of the substrate 100. The bit line contact BCT, the bit line BL, and the first upper chip protection member UG1 may be disposed between the first portion of the second upper chip protection member UG2. The bit line contact BCT, the bit line BL, and the first upper chip protection member UG1 may be disposed between the second portion of the second upper chip protection member UG2. The first portion and the second portion of the second upper chip protection member UG2 may be connected to each other.

[0087] The second upper chip protection member UG2 may include a second upper protection member part UP2. The second upper protection member parts UP2 may be sequentially arranged along the third direction D3. The second upper protection member parts UP2 may be connected to each other.

[0088] The second upper protector part UP2 may be disposed in the second insulating layer 120. The second upper protector part UP2 may surround the bit line contact part BCT, the bit line BL, and the first upper chip protector UG1.

[0089] Each second upper protector part UP2 may include a first part extending in the first direction D1 and a second part extending in the second direction D2. The first part of each second upper protector part UP2 may be disposed on the first region RG1 of the substrate 100. The second part of each second upper protector part UP2 may be disposed on the second region RG2 of the substrate 100. The first part of each second upper protector part UP2 may be spaced apart from each other in the second direction D2. The second part of each second upper protector part UP2 may be spaced apart from each other in the first direction D1. The first part and the second part of each second upper protector part UP2 may be connected to each other.

[0090] The second upper protector part UP2 may include a conductive material. In one example, the second upper protector part UP2 may include tungsten.

[0091] In the chip protection members CG1 and CG2 of the semiconductor device according to the embodiment of the present disclosure, the protection member filling layers GFI1 and GFI2 can substantially fill or completely fill the spaces between the protection member semiconductor layers GSE1 and GSE2. Therefore, the formation of voids or cracks in the chip protection members CG1 and CG2 can be prevented or reduced.

[0092] The unit chip protection members CG1 and CG2 of the semiconductor device according to the embodiment of the present disclosure are formed to be divided into upper portions CG1_U and CG2_U and lower portions CG1_L and CG2_L. Therefore, in contrast to the unit chip protection members that are not divided into upper and lower portions, the widths of the unit chip protection members CG1 and CG2 can be relatively small, and the formation of voids or cracks in the unit chip protection members CG1 and CG2 having relatively small widths can be prevented.

[0093] Figure 2A 、 Figure 2B 、 Figure 3A 、 Figure 3B 、 Figure 4A and Figure 4B 2 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. Hereinafter, descriptions of portions overlapping with the above contents will be omitted.

[0094] Reference Figure 2A and 2B , a substrate 100 may be formed. Subsequently, an isolation layer IS and a peripheral transistor TR may be formed on the substrate 100.

[0095] A first insulating layer 110 covering the substrate 100 and the peripheral transistor TR may be formed. While forming the first insulating layer 110, a first contact portion CT1, a first line ML1, a first lower chip protection member LG1, and a second lower chip protection member LG2 may be formed.

[0096] The preliminary cell source structure pCSS may be formed on the first insulating layer 110. The preliminary cell source structure pCSS may include a first cell source layer CSL1, a third etch stop layer ESL3, a preliminary source layer pCSL, a fourth etch stop layer ESL4, and a third cell source layer CSL3 sequentially stacked in the third direction D3. The preliminary cell source structure pCSS may be formed on the cell region CER of the substrate 100.

[0097] The first and second dummy source structures DST1 and DST2 may be formed on the first insulating layer 110. The insulating structure IST may be formed on the first insulating layer 110.

[0098] The first cell stack CIL1 and the second cell stack CIL2 may be alternately formed on the preliminary cell source structure pCSS. The second cell stack CIL2 may include an insulating material different from that of the first cell stack CIL1. In one example, the second cell stack CIL2 may include a nitride. The first cell stack CIL1 and the second cell stack CIL2 may be formed on the cell region CER of the substrate 100.

[0099] First and second dummy stacks DIL1 and DIL2 may be alternately formed on the first and second dummy source structures DST1 and DST2 . The first and second dummy stacks DIL1 and DIL2 may be formed on the chip protector region CGR of the substrate 100 .

[0100] The first unit layer stack CIL1 and the first dummy layer stack DIL1 may be formed simultaneously. The first unit layer stack CIL1 and the first dummy layer stack DIL1 may be formed continuously without any boundary. The second unit layer stack CIL2 and the second dummy layer stack DIL2 may be formed simultaneously. The second unit layer stack CIL2 and the second dummy layer stack DIL2 may be formed continuously without any boundary.

[0101] A cell sacrificial structure CFS may be formed to penetrate the first cell stack CIL1 and the second cell stack CIL2. The step of forming the cell sacrificial structure CFS may include forming a first cell hole CHO1 that penetrates the first cell stack CIL1 and the second cell stack CIL2, and forming the cell sacrificial structure CFS in the first cell hole CHO1. The cell sacrificial structure CFS may be formed on the cell region CER of the substrate 100. The cell sacrificial structure CFS may have a cylindrical shape. The cell sacrificial structure CFS may include a material having an etching selectivity relative to the material included in the first cell stack CIL1 and the second cell stack CIL2. In one example, the cell sacrificial structure CFS may include tungsten.

[0102] A protective member sacrificial structure GFS may be formed that penetrates the first dummy layer stack DIL1 and the second dummy layer stack DIL2. The step of forming the protective member sacrificial structure GFS may include forming a first protective member trench GT1 that penetrates the first dummy layer stack DIL1 and the second dummy layer stack DIL2 and forming the protective member sacrificial structure GFS in the first protective member trench GT1. The first protective member trench GT1 may surround the first cell hole CHO1. The protective member sacrificial structure GFS may be formed on the chip protective member region CGR of the substrate 100. The protective member sacrificial structure GFS may be formed simultaneously with the cell sacrificial structure CFS. The protective member sacrificial structure GFS may surround the cell sacrificial structure CFS. The protective member sacrificial structure GFS may include the same material as the cell sacrificial structure CFS. In one example, the protective member sacrificial structure GFS may include tungsten.

[0103] Reference Figure 3A and Figure 3B , the first cell stack layers CIL1 and the second cell stack layers CIL2 may be alternately formed on the cell sacrificial structure CFS.

[0104] Subsequently, a second cell hole CHO2 penetrating the first and second cell stack layers CIL1 and CIL2 on the cell sacrificial structure CFS may be formed When the second cell hole CHO2 is formed, a top surface of the cell sacrificial structure CFS may be exposed.

[0105] The first dummy layer stack DIL1 and the second dummy layer stack DIL2 may be alternately formed on the protection member sacrificial structure GFS.

[0106] Subsequently, a second protector trench GT2 may be formed that penetrates the first and second dummy stacks DIL1 and DIL2 on the protector sacrificial structure GFS. When the second protector trench GT2 is formed, the top surface of the protector sacrificial structure GFS may be exposed. The second protector trench GT2 may surround the second unit hole CHO2.

[0107] Reference Figure 4A and Figure 4B , a cell plug CPL may be formed. The step of forming the cell plug CPL may include removing the cell sacrificial structure CFS through the second cell hole CHO2 and forming the cell plug CPL in the first cell hole CHO1 and the second cell hole CHO2.

[0108] A first unit chip protection member CG1 and a second unit chip protection member CG2 may be formed. The steps of forming the first unit chip protection member CG1 and the second unit chip protection member CG2 may include removing the protection member sacrificial structure GFS through the second protection member trench CT2 and forming the first unit chip protection member CG1 and the second unit chip protection member CG2 in the first protection member trench GT1 and the second protection member trench GT2.

[0109] The cell plug CPL, the first cell chip protection member CG1, and the second cell chip protection member CG2 can be formed simultaneously. The steps of forming the cell plug CPL, the first cell chip protection member CG1, and the second cell chip protection member CG2 may include: forming a first material layer covering the surfaces of the first cell hole CHO1 and the second cell hole CHO2 and the first protection member trench GT1 and the second protection member trench GT2, forming a second material layer covering the surface of the first material layer, and forming a third material layer covering the surface of the second material layer. The first material layer may be multilayer. In one example, the first material layer may include multiple insulating layers. The second material layer may include a semiconductor material. Through subsequent processes, the first material layer may be isolated into a cell memory layer CML, a first protection member insulating layer GIL1, and a second protection member insulating layer GIL2, the second material layer may be isolated into a cell channel layer CCL, a first protection member semiconductor layer GSE1, and a second protection member semiconductor layer GSE2, and the third material layer may be isolated into a cell fill layer CFI, a first protection member fill layer GFI1, and a second protection member fill layer GFI2.

[0110] A cell source structure CSS and a stacked conductive layer SCL may be formed. The steps of forming the cell source structure CSS and the stacked conductive layer SCL may include: forming a slit penetrating the cell stack structure CST, removing the preliminary source layer pCSL, the third etch-stop layer ESL3, and the fourth etch-stop layer ESL4 through the slit, forming a second cell source layer CSL2 in the empty space where the preliminary source layer pCSL, the third etch-stop layer ESL3, and the fourth etch-stop layer ESL4 are removed, removing the second cell stack layer CIL2 through the slit, and forming the stacked conductive layer SCL in the empty space where the second cell stack layer CIL2 is removed. When the second cell source layer CSL2 is formed, the preliminary cell source structure pCSS may be defined as a cell source structure CSS.

[0111] A second insulating layer 120 (see FIG. 1 ) covering the cell plug CPL, the cell stack structure CST, the first and second cell chip protection members CG1 and CG2, and the dummy stack structure DST may be formed. Figures 1B to 1D The bit line contact portion BCT, the bit line BL, the first upper chip protection member UG1 and the second upper chip protection member UG2 may be formed in the second insulating layer 120 (see Figures 1B to 1D ).

[0112] In the method for manufacturing a semiconductor device according to an embodiment of the present disclosure, the unit chip protection members CG1 and CG2 are formed by using the first protection member trench GT1 and the second protection member trench GT2. Therefore, the widths of the first protection member trench GT1 and the second protection member trench GT2 can be relatively small, and the formation of voids or cracks in the unit chip protection members CG1 and CG2 can be reduced or prevented.

[0113] In the method for manufacturing a semiconductor device according to an embodiment of the present disclosure, the cell chip protection members CG1 and CG2 are formed simultaneously with the cell plugs CPL, thereby minimizing the manufacturing cost and time of the semiconductor device.

[0114] Figure 5A 1 is a plan view of a semiconductor device according to an embodiment of the present disclosure. For ease of description, the bit line BL, the bit line contact portion BCT, the second insulating layer 120, and the first and second upper chip protection members UG1 and UG2 are not shown. Figure 5A . Figure 5B It is along Figure 5A A cross-sectional view taken along line A2-A2' is shown. Figure 5C It is along Figure 5A A cross-sectional view taken along line B2-B2' is shown. Figure 5D It shows that according to Figures 5A to 5C A perspective view of a protection member plug and an upper chip protection member of a semiconductor device according to an embodiment of the present invention is shown. Hereinafter, descriptions of parts overlapping with the above contents will be omitted.

[0115] Reference 5A to 5D A dummy source structure DSS may be provided on the first insulating layer 110. The dummy source structure DSS may be provided on the chip protection region CGR. The dummy source structure DSS may surround the cell source structure CSS.

[0116] The dummy source structure DSS may include a first dummy source layer DSL1 , a first etch stop layer ESL1 , a second dummy source layer DSL2 , a second etch stop layer ESL2 , and a third dummy source layer DSL3 sequentially stacked in the third direction D3 .

[0117] A first lower chip protection member LG1 may be disposed in the first insulating layer 110 and the dummy source structure DSS. A second lower chip protection member LG2 may be disposed in the first insulating layer 110 and the dummy source structure DSS.

[0118] A protection plug GPL may be provided that penetrates the dummy stack structure DST. The protection plug GPL may extend in the third direction D3. The protection plug GPL may have a cylindrical shape. The protection plug GPL may be provided on the chip protection region CGR of the substrate 100. The protection plug GPL may be provided on the first region RG1 and the second region RG2 of the substrate 100. The protection plug GPL may surround the cell plug CPL and the cell stack structure CST. Figure 5A From the perspective of the illustrated plane, the cell stack structure CST and the cell plugs CPL may be disposed in a space surrounded by the protective member plugs GPL. The protective member plugs GPL may serve as a chip protection member of the semiconductor device.

[0119] Each protection plug GPL may include a plug filling layer PFI, a plug semiconductor layer PSE surrounding the plug filling layer PFI, and a plug insulating layer PIL surrounding the plug semiconductor layer PSE. The plug filling layer PFI, the plug semiconductor layer PSE, and the plug insulating layer PIL may penetrate the dummy stack structure DST while extending along the third direction D3.

[0120] The plug filling layer PFI may include the same material as the cell filling layer CFI. In one example, the plug filling layer PFI may include oxide. The plug semiconductor layer PSE may include the same material as the cell channel layer CCL. In one example, the plug semiconductor layer PSE may include polysilicon. The plug insulating layer PIL may include the same material as the cell memory layer CML. The plug insulating layer PIL may include a first plug layer including the same material as the tunnel insulating layer of the cell memory layer CML, a second plug layer including the same material as the data storage layer of the cell memory layer CML, and a third plug layer including the same material as the barrier layer of the cell memory layer CML.

[0121] The protective member plug GPL may include an upper portion GPL_U and a lower portion GPL_L. The upper portion GPL_U of the protective member plug GPL may penetrate the upper portion of the dummy stack structure DST. The lower portion GPL_L of the protective member plug GPL may penetrate the lower portion of the dummy stack structure DST. The width of the upper portion GPL_U of the protective member plug GPL may become smaller as the width becomes closer to the substrate 100. The width of the lower portion GPL_L of the protective member plug GPL may become smaller as the width becomes closer to the substrate 100. The minimum width of the upper portion GPL_U of the protective member plug GPL may be smaller than the maximum width of the lower portion GPL_L of the protective member plug GPL.

[0122] The distance between the protection member plugs GPL may be equal to or greater than the distance between the cell plugs CPL. In one example, the distance between the protection member plugs GPL in the first direction D1 may be equal to or greater than the distance between the cell plugs CPL in the first direction D1.

[0123] The first upper chip protection member UG1 and the second upper chip protection member UG2 may be disposed on the protection member plug GPL. Each of the first upper chip protection member UG1 and the second upper chip protection member UG2 may overlap with a plurality of protection member plugs GPL. In one example, each of the first upper chip protection member UG1 and the second upper chip protection member UG2 may overlap with a plurality of protection member plugs GPL in a third direction D3.

[0124] Figure 6 、 Figure 7 and Figure 8 2 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. Hereinafter, descriptions of portions overlapping with the above contents will be omitted.

[0125] Reference Figure 6 , a dummy source structure DSS may be formed on the first insulating layer 110. The dummy source structure DSS may be formed on the chip protection member region CGR of the substrate 100.

[0126] The first dummy layer stack DIL1 and the second dummy layer stack DIL2 may be alternately formed on the dummy source structure DSS. The first dummy layer stack DIL1 and the second dummy layer stack DIL2 may be formed on the chip protection member region CGR.

[0127] A plug sacrificial structure PFS may be formed penetrating the first and second dummy layer stacks DIL1 and DIL2. The plug sacrificial structure PFS may have a cylindrical shape. The step of forming the plug sacrificial structure PFS may include forming a first protector hole GHO1 penetrating the first and second dummy layer stacks DIL1 and DIL2, and forming the plug sacrificial structure PFS in the first protector hole GHO1. The first protector hole GHO1 may surround the first unit hole.

[0128] Reference Figure 7 , a first dummy layer stack DIL1 and a second dummy layer stack DIL2 may be formed on the plug sacrificial structure PFS.

[0129] Subsequently, a second protector hole GHO2 may be formed through the first and second dummy layer stacks DIL1 and DIL2 on the plug sacrificial structure PFS. When the second protector hole GHO2 is formed, the top surface of the plug sacrificial structure PFS may be exposed. The second protector hole GHO2 may surround the second unit hole.

[0130] Reference Figure 8 , a protection plug GPL may be formed. The step of forming the protection plug GPL may include removing the plug sacrificial structure PFS through the second protection hole GHO2 and forming the protection plug GPL in the first protection hole GHO1 and the second protection hole GHO2.

[0131] The steps of forming the cell plugs and the protection plugs GPL may include forming a first material layer covering the surfaces of the first and second cell holes and the first and second protection holes GHO1 and GHO2, forming a second material layer covering the surface of the first material layer, and forming a third material layer covering the surface of the second material layer. Through subsequent processes, the first material layer may be isolated into a cell memory layer and a plug insulating layer PIL, the second material layer may be isolated into a cell channel layer and a plug semiconductor layer PSE, and the third material layer may be isolated into a cell filling layer and a plug filling layer PFI.

[0132] Figure 9 is a block diagram illustrating a configuration of a memory system according to an embodiment of the present disclosure.

[0133] Reference Figure 9 , a memory system 1100 according to an embodiment of the present disclosure includes a memory device 1120 and a memory controller 1110 .

[0134] The memory device 1120 may include a semiconductor device according to an embodiment of the present disclosure. The memory device 1120 may be a multi-chip package configured with a plurality of flash memory chips.

[0135] The memory controller 1110 is configured to control the memory device 1120 and may include a static random access memory (SRAM) 1111, a central processing unit (CPU) 1112, a host interface 1113, an error correction block 1114, and a memory interface 1115. The SRAM 1111 serves as an operating memory for the CPU 1112, which performs overall control operations for data exchange with the memory controller 1110, and the host interface 1113 includes a data exchange protocol for a host connected to the memory system 1100. The error correction block 1114 detects and corrects errors included in data read from the memory device 1120, and the memory interface 1115 interfaces with the memory device 1120. In addition, the memory controller 1110 may further include a ROM or the like for storing code data for interfacing with the host.

[0136] The memory system 1100 configured as described above may be a memory card or a solid state disk (SSD) in which the memory device 1120 is combined with the memory controller 1110. For example, when the memory system 1100 is an SSD, the memory controller 1110 may communicate with the outside (e.g., a host) through one of various interface protocols such as a universal serial bus (USB) protocol, a multimedia card (MMC) protocol, a peripheral component interconnect (PCI) protocol, a PCI-Express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA (SATA) protocol, a parallel ATA (PATA) protocol, a small computer system interface (SCSI) protocol, an enhanced minidisk interface (ESDI) protocol, and an integrated drive electronics (IDE) protocol.

[0137] Figure 10 is a block diagram illustrating a configuration of a computing system according to an embodiment of the present disclosure.

[0138] Reference Figure 10 The computing system 1200 according to an embodiment of the present disclosure may include a CPU 1220 electrically connected to a system bus 1260, a random access memory (RAM) 1230, a user interface 1240, a modem 1250, and a memory system 1210. When the computing system 1200 is a mobile device, it may further include a battery for supplying an operating voltage to the computing system 1200, and may also include an application chipset, a camera image processor (CIS), a mobile D-RAM, and the like.

[0139] The memory system 1210 may be configured with reference to Figure 9 The memory device 1212 and memory controller 1211 are similar to those described.

[0140] In the semiconductor device according to the present disclosure, the unit chip protection member is formed to be divided into an upper portion and a lower portion, so that formation of voids or cracks in the unit chip protection member can be reduced or prevented, thereby improving operational reliability of the semiconductor device.

[0141] Examples of embodiments of the present disclosure have been described in the drawings and the specification. Although specific terms are used herein, they are only used to explain the embodiments of the present disclosure. Therefore, the present disclosure is not limited to the above-described embodiments and many variations are possible within the spirit and scope of the present disclosure. In addition to the embodiments disclosed herein, various modifications can be made based on the technical scope of the present disclosure.

[0142] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the meanings commonly understood by those skilled in the art to which this disclosure belongs. Terms with dictionary definitions should be understood to have meanings consistent with the context of the relevant art. Unless otherwise defined in this application, terms should not be understood in an idealistic or overly formal manner.

[0143] CROSS-REFERENCE TO RELATED APPLICATIONS

[0144] This application claims the benefit of Korean Patent Application No. 10-2020-0158815 filed on November 24, 2020, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device, comprising: a unit stacking structure comprising a first unit stacking layer and a stacked conductive layer that are alternately stacked; a unit plug, the unit plug penetrating the unit stacking structure; a unit chip protection member surrounding the unit stack structure and the unit plug; a dummy source structure connected to the unit chip protection element; as well as a penetrating protection member component, wherein the penetrating protection member component penetrates the dummy source structure, The unit chip protection member includes a protection member semiconductor layer and a protection member insulating layer covering the sidewall of the protection member semiconductor layer. wherein the top surface of the penetration protection member and the top surface of the dummy source structure are arranged at the same height, and Part of the unit chip protection member is disposed in the dummy source structure and is spaced apart from the penetration protection member component.

2. The semiconductor device according to claim 1, wherein The unit chip protection member further includes a protection member filling layer in the protection member semiconductor layer.

3. The semiconductor device according to claim 1, wherein The stacked conductive layers and the first unit stacked layers are alternately stacked in a first direction, and The unit chip protection member includes a first unit extension part extending in a second direction intersecting the first direction and a second unit extension part extending in a third direction intersecting the first direction and the second direction.

4. The semiconductor device according to claim 3, wherein The cell stack structure and the cell plug are disposed between the first cell extension parts and between the second cell extension parts.

5. The semiconductor device according to claim 1, further comprising a dummy stack structure surrounding the unit stack structure. in, The dummy stack structure includes first dummy stack layers and second dummy stack layers that are alternately stacked. The semiconductor device according to claim 5 , wherein: The unit chip protection member penetrates the dummy stacked structure.

7. The semiconductor device according to claim 6, wherein The unit chip protection member includes an upper portion and a lower portion, the upper portion penetrating the upper portion of the dummy stack structure and the lower portion penetrating the lower portion of the dummy stack structure.

8. The semiconductor device according to claim 7, wherein The width of the upper portion of the unit chip protection member becomes smaller as the width becomes closer to the lower portion of the unit chip protection member.

9. The semiconductor device according to claim 7, wherein The width of the lower portion of the unit chip protection member becomes larger as the width becomes closer to the upper portion of the unit chip protection member.

10. The semiconductor device according to claim 1, wherein The dummy source structure includes a first dummy source layer, a first etch stop layer, a second dummy source layer, a second etch stop layer and a third dummy source layer stacked in sequence.

11. A semiconductor device comprising: a unit stacking structure comprising alternately stacked conductive layers and a first unit stacking layer; a unit plug, the unit plug penetrating the unit stacking structure; a protector plug surrounding the unit stack and the unit plug; a dummy source structure connected to the protection member plug; as well as a penetrating protection member component, wherein the penetrating protection member component penetrates the dummy source structure, The protective plug includes a plug semiconductor layer and a plug insulating layer surrounding the plug semiconductor layer. wherein the top surface of the penetration protection member and the top surface of the dummy source structure are arranged at the same height, and A portion of each of the protector plugs is disposed in the dummy source structure and is spaced apart from the through protector component.

12. The semiconductor device according to claim 11, further comprising a substrate including a cell region and a chip protection member region surrounding the cell region, in, The cell stack structure and the cell plug are provided on the cell region, and The protector plug is disposed on the chip protector region.

13. The semiconductor device according to claim 12, wherein The chip protection member region includes a first region extending in a first direction and a second region extending in a second direction intersecting the first direction, and The unit region is arranged between the first regions and between the second regions.

14. The semiconductor device according to claim 13, wherein The protector plugs are provided on the first area and the second area.

15. The semiconductor device according to claim 11, further comprising a cell source structure connected to the cell plug, in, The dummy source structure surrounds the cell source structure.

16. The semiconductor device according to claim 15, wherein The unit source structure includes a first unit source layer, a second unit source layer and a third unit source layer stacked in sequence, and The dummy source structure includes a first dummy source layer, a first etch stop layer, a second dummy source layer, a second etch stop layer and a third dummy source layer stacked in sequence.

17. The semiconductor device according to claim 16, wherein The first cell source layer is disposed at the same height as the first dummy source layer, and The third cell source layer is disposed at the same height as the third dummy source layer.

18. A semiconductor device comprising: a unit stacking structure comprising alternately stacked conductive layers and a first unit stacking layer; a unit plug, the unit plug penetrating the unit stacking structure; a first unit chip protection member surrounding the unit stack structure and the unit plug; a cell source structure connected to the cell plug; a first dummy source structure connected to the first unit chip protection element; as well as a penetrating protection member, wherein the penetrating protection member penetrates the first dummy source structure, wherein the first dummy source structure surrounds the unit source structure, wherein a top surface of the penetration guard component and a top surface of the first dummy source structure are arranged at the same height, and Part of the first unit chip protection member is disposed in the first dummy source structure and is spaced apart from the penetration protection member component. 19 . The semiconductor device according to claim 18 , further comprising a second unit chip protection member surrounding the first unit chip protection member.

20. The semiconductor device according to claim 19, further comprising a second dummy source structure surrounding the first dummy source structure, in, The second dummy source structure is connected to the second unit chip protection member.

21. The semiconductor device according to claim 18, wherein A portion of the penetration protector member is disposed at the same height as the portion of the first cell chip protector.

22. A method for manufacturing a semiconductor device, the method comprising the steps of: forming alternately stacked first unit layer stacking layers and second unit layer stacking layers, and alternately stacked first dummy layer stacking layers and second dummy layer stacking layers; forming a cell hole penetrating the first cell stack and the second cell stack, and a protection member groove penetrating the first dummy stack and the second dummy stack, wherein the protection member groove surrounds the cell hole; forming a first material layer covering surfaces of the unit hole and the protection member groove; and forming a second material layer covering the surface of the first material layer, The semiconductor device includes: a dummy source structure connected to a unit chip protection member, the unit chip protection member including the first material layer and the second material layer inside a groove of the protection member; and a penetrating protection member component penetrating the dummy source structure. wherein the top surface of the penetration protection member and the top surface of the dummy source structure are arranged at the same height, and Part of the unit chip protection member is disposed in the dummy source structure and is spaced apart from the penetration protection member component.

23. The method according to claim 22, wherein The first material layer includes a plurality of insulating layers.

24. The method according to claim 22, wherein The second material layer includes semiconductor material.

25. The method according to claim 22, further comprising the steps of: The first material layer is isolated into a unit memory layer in the unit hole and a protection member insulating layer in the protection member trench.

26. The method according to claim 22, further comprising the steps of: The second material layer is separated into a cell channel layer in the cell hole and a protection member semiconductor layer in the protection member trench.

27. A method for manufacturing a semiconductor device, the method comprising the steps of: forming alternately stacked first unit layer stacking layers and second unit layer stacking layers, and alternately stacked first dummy layer stacking layers and second dummy layer stacking layers; forming a unit hole penetrating the first unit layer stack and the second unit layer stack and a plurality of protection member holes penetrating the first dummy layer stack and the second dummy layer stack, wherein the plurality of protection member holes surround the unit hole; forming a first material layer covering surfaces of the unit holes and the protection member holes; and forming a second material layer covering the surface of the first material layer, The semiconductor device includes: a dummy source structure connected to a unit chip protection member, the unit chip protection member including the first material layer and the second material layer inside the protection member hole; and a penetrating protection member component, the penetrating protection member component penetrating the dummy source structure, wherein the top surface of the penetration protection member and the top surface of the dummy source structure are arranged at the same height, and Part of the unit chip protection member is disposed in the dummy source structure and is spaced apart from the penetration protection member component.

28. The method according to claim 27, wherein The first material layer includes a plurality of insulating layers.

29. The method according to claim 27, wherein The second material layer includes semiconductor material.

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