Display device and method of manufacturing the same

Abstract

Disclosed is a display device with improved reliability and a method for manufacturing the display device. In the display device, at least one of a plurality of dielectric films provided between an oxide semiconductor layer and a light-emitting element includes a lower region provided on the oxide semiconductor layer and an upper region provided on the lower region, the upper region including a trapping element configured to trap hydrogen, whereby the reliability of a thin film transistor including the oxide semiconductor layer is improved.

Description

Technical Field

[0001] The present invention relates to a display device and a method for manufacturing the display device, and more specifically, to a display device with improved reliability and a method for manufacturing the display device. Background Technology

[0002] In display devices, thin-film transistors (TFTs) are used as switching devices and / or driving devices. Based on the material used as the active layer, TFTs are classified into TFTs using amorphous silicon, TFTs using polycrystalline silicon, or TFTs using oxide semiconductors. Among these, TFTs using oxide semiconductors have higher mobility and lower leakage current compared to TFTs using amorphous silicon.

[0003] However, the excess hydrogen introduced into the oxide semiconductor layer increases the carrier concentration in the channel region. As a result, the electrical characteristics of the thin-film transistor (e.g., threshold voltage) change, thereby degrading the reliability of the thin-film transistor. Summary of the Invention

[0004] Therefore, the present invention relates to a display device and a method of manufacturing the display device, which substantially eliminates one or more problems caused by the limitations and disadvantages of the prior art.

[0005] The object of this invention is to provide a display device with improved reliability.

[0006] Other advantages, objects, and features of the invention will be set forth in part in the description which follows, and in part will become apparent to one of ordinary skill in the art upon reading the following, or may be learned by practice of the invention. The objects and other advantages of the invention can be realized and obtained by means of the structures particularly pointed out in the written description and its claims, as well as the accompanying drawings.

[0007] To achieve these and other advantages, and according to the purposes of the invention, as embodied and broadly described herein, a display device includes a thin-film transistor disposed on a substrate, the thin-film transistor including an oxide semiconductor layer, a light-emitting device electrically connected to the thin-film transistor, and a plurality of dielectric films disposed between the oxide semiconductor layer and the light-emitting device, wherein at least one of the plurality of dielectric films includes a lower region disposed on the oxide semiconductor layer and an upper region disposed on the lower region, the upper region including a capturing element configured to capture hydrogen.

[0008] The capturing element may be at least one of nitrogen, fluorine, and boron.

[0009] The content of the captured element in the lower region may be lower than the content of the captured element in the upper region.

[0010] The content of the captured element in the lower region can be 0%.

[0011] The capturing element can be configured such that the content of the capturing element gradually decreases from the upper part of the upper region to the lower part of the upper region.

[0012] The lower region is formed of SiOx.

[0013] The thin-film transistor may include: a gate electrode disposed on the oxide semiconductor layer; a source electrode configured to contact the oxide semiconductor layer; and a drain electrode opposite to the source electrode, the drain electrode being configured to contact the oxide semiconductor layer, and the plurality of dielectric films may include an interlayer dielectric film disposed between each of the source electrode and the drain electrode and the gate electrode, and a gate dielectric film disposed between the oxide semiconductor layer and the gate electrode.

[0014] At least one of the interlayer dielectric film and the gate dielectric film may include a lower interlayer region as the lower region and an upper interlayer region as the upper region.

[0015] The gate electrode may include an upper gate region and a lower gate region, the upper gate region including the trapping element, and the lower gate region disposed between the oxide semiconductor layer and the upper gate region.

[0016] The trapping element, including in the upper interlayer region of the gate dielectric film, can be disposed in the remaining region other than the region configured to overlap with the gate electrode.

[0017] The trapping elements included in the upper interlayer region of the gate dielectric film can be disposed in the remaining regions other than those configured to overlap with the channel regions of the oxide semiconductor layer.

[0018] The display device may further include a first upper buffer layer, a second upper buffer layer, and a storage capacitor, wherein the first upper buffer layer, the second upper buffer layer, and the storage capacitor are disposed below the oxide semiconductor layer. At least a portion of at least one of the first upper buffer layer and the lower storage capacitor electrode of the storage capacitor may include the trapping element.

[0019] The upper storage capacitor electrode of the storage capacitor can be electrically connected to the drain electrode of the thin-film transistor.

[0020] The display device may further include an encapsulation unit disposed on the light-emitting device. The encapsulation unit may include a plurality of inorganic encapsulation layers and an organic encapsulation layer disposed between the plurality of inorganic encapsulation layers.

[0021] A method of manufacturing a display device may include the following steps: forming an oxide semiconductor layer of a thin-film transistor on a substrate; forming a gate dielectric film on the oxide semiconductor layer and forming a gate electrode of the thin-film transistor on the gate dielectric film; performing a preliminary plasma treatment on the surface of each of the gate electrode and the gate dielectric film using a source gas including a trapping element, such that at least one of the gate electrode and the gate dielectric film includes an upper region containing a trapping element and a lower region not containing a trapping element; forming an interlayer dielectric film on the gate electrode and the gate dielectric film; performing a secondary plasma treatment on the surface of the interlayer dielectric film using a gas including a trapping element, such that the interlayer dielectric film includes an upper region containing a trapping element and a lower region not containing a trapping element; and sequentially forming a source electrode and a drain electrode of the thin-film transistor, a pixel connection electrode, a light-emitting device, and a packaging unit on the substrate.

[0022] It should be understood that the above summary and the following detailed description of the invention are exemplary and explanatory, and are intended to provide further explanation of the claimed invention. Attached Figure Description

[0023] The accompanying drawings, included to provide a further understanding of the invention, are incorporated in and constitute a part of this application, illustrate one or more embodiments of the invention, and, together with the description, serve to explain the principles of the invention. In the drawings:

[0024] Figure 1 This is a block diagram of a display device according to an embodiment of the present invention;

[0025] Figure 2 yes Figure 1 The diagram shown is a cross-sectional view of a display device according to an embodiment of the present invention;

[0026] Figure 3 This illustrates hydrogen from an embodiment of the present invention. Figure 2 A view showing the process of the inorganic encapsulation layer moving;

[0027] Figure 4 yes Figure 1 A cross-sectional view of another embodiment of the display device according to an embodiment of the present invention is shown;

[0028] Figure 5 It shows that hydrogen comes from Figure 4 A view showing the process of the inorganic encapsulation layer moving;

[0029] Figure 6 It is shown Figure 4 A view showing the process by which the trapped element and hydrogen combine;

[0030] Figures 7A to 7G This illustrates the manufacturing process according to an embodiment of the present invention. Figure 4 A cross-sectional view of the method of the display device shown; and

[0031] Figure 8 This is a view illustrating the fluctuation of the threshold voltage of a thin-film transistor according to an embodiment of the present invention, the fluctuation depending on the flow rate of the source gas including the trapping element. Detailed Implementation

[0032] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0033] Figure 1 This is a block diagram of an organic light-emitting display device according to an embodiment of the present invention.

[0034] Figure 1 The illustrated organic light-emitting display device includes an organic light-emitting display panel 10 and a panel driving unit configured to drive the display panel 10. The panel driving unit includes a data driving unit 20, gating driving units 40A and 40B, and a timing controller 30.

[0035] The timing controller 30 generates data control signals and gating control signals for controlling the timing of the data driving unit 20 and the gating driving units 40A and 40B, and provides them to the data driving unit 20 and the gating driving units 40A and 40B. The timing controller 30 performs image processing on the image data and provides it to the data driving unit 20.

[0036] The data drive unit 20 is controlled by a data control signal provided by the timing controller 30, and converts the image data provided by the timing controller 30 into an analog data signal and provides it to the data line DL of the display panel 10.

[0037] Each of the gating drive units 40A and 40B is implemented by an in-panel gating (GIP) circuit formed directly in the non-display area NA on the display panel 10 in the form of a thin-film transistor. The gating drive units 40A and 40B are disposed in the non-display area NA on at least one of the left and right sides of the display panel 10.

[0038] Each of the gating drive units 40A and 40B outputs a gating signal in response to a gating control signal provided from the timing controller 30, while simultaneously shifting the level of the gating voltage. Each of the gating drive units 40A and 40B outputs the gating signal via the gating line GL.

[0039] The display panel 10 includes a display area AA and a non-display area NA. The display area AA is configured to display an input image on a screen, and the non-display area NA is disposed on at least one side of the display area AA.

[0040] The non-display area NA is the area where the input image is not displayed. No sub-pixels SP are set in the non-display area NA, and signal lines and gating drive units 40A and 40B are set in the non-display area NA.

[0041] Within the display area AA, sub-pixels SP are set in a matrix form, connecting to the intersecting data lines DL and GL. For example... Figure 2 As shown, each sub-pixel SP includes a light-emitting device 130 and at least one driving transistor 150 and at least one switching transistor 100 electrically connected to the light-emitting device 130. Here, one of the switching transistor 100 and the driving transistor 150 includes one of an oxide semiconductor layer and a polycrystalline semiconductor layer, and the other of the switching transistor 100 and the driving transistor 150 includes the other of an oxide semiconductor layer and a polycrystalline semiconductor layer. The structure in which the switching transistor 100 includes an oxide semiconductor layer and the driving transistor 150 includes a polycrystalline semiconductor layer will be described below by way of example.

[0042] Switching transistor 100 switches the data voltage written to each sub-pixel SP located in the display area AA. For example... Figure 2 As shown, the switching transistor 100 includes an oxide semiconductor layer 104, a first gate electrode 102, a first source electrode 106, and a first drain electrode 108.

[0043] The first gate electrode 102 is formed on the second gate dielectric film 124, so as to overlap with the oxide semiconductor layer 104 via the second gate dielectric film 124. The first gate electrode 102 is electrically connected to the gate line GL.

[0044] An oxide semiconductor layer 104 is formed on the second upper buffer layer 122 to overlap with the first gate electrode 102, thereby forming a channel between the first source electrode 106 and the first drain electrode 108. The oxide semiconductor layer 104 is formed of an oxide comprising at least one metal selected from Zn, Cd, Ga, In, Sn, Hf, and Zr. Compared to a driving transistor 150 comprising a polycrystalline semiconductor layer 154, a switching transistor 100 comprising an oxide semiconductor layer 104 has higher charge mobility and lower leakage current. Therefore, it is preferable to apply the switching transistor comprising an oxide semiconductor layer 104 to switching and sensing thin-film transistors with short on-time and long off-time.

[0045] Each of the second gate dielectric film 124 and the second upper buffer layer 122, which are adjacent to the upper and lower portions of the oxide semiconductor layer 104, is formed of an inorganic film having a smaller number of hydrogen particles than the first upper buffer layer 118 and the third interlayer dielectric film 148. For example, each of the second gate dielectric film 124 and the second upper buffer layer 122 is formed of silicon oxide (SiOx), and each of the first upper buffer layer 118 and the third interlayer dielectric film 148 is formed of silicon nitride (SiNx). Therefore, when the oxide semiconductor layer 104 is heat-treated, hydrogen in the first upper buffer layer 118 and the third interlayer dielectric film 148, as well as hydrogen in the polycrystalline semiconductor layer 154, can be prevented from diffusing into the oxide semiconductor layer 104.

[0046] Each of the first source electrode 106 and the first drain electrode 108 may be formed on the third interlayer dielectric film 148 to have a single-layer or multi-layer structure formed of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof. However, the invention is not limited thereto.

[0047] The first source electrode 106 is connected to the source region of the oxide semiconductor layer 104 through a first source contact hole 110S formed through the second gate dielectric film 124, the second interlayer dielectric film 146, and the third interlayer dielectric film 148. Additionally, the first source electrode 106 is electrically connected to the data line DL.

[0048] The first drain electrode 108 is connected to the drain region of the oxide semiconductor layer 104 through a first drain contact hole 110D formed through the second gate dielectric film 124, the second interlayer dielectric film 146 and the third interlayer dielectric film 148.

[0049] The first source electrode 106 and the first drain electrode 108 are formed opposite each other via a channel region of the oxide semiconductor layer 104.

[0050] The drive transistor 150 is operated such that a drive current flows between a high-voltage power line and a low-voltage power line according to the data voltage stored in the storage capacitor 180. For example... Figure 2 As shown, the driving transistor 150 includes a second gate electrode 152 electrically connected to the first drain electrode 108 of the switching transistor 100, a second source electrode 156 connected to a high-voltage power supply line, a second drain electrode 158 connected to the light-emitting device 130, and a polycrystalline semiconductor layer 154 configured to form a channel between the second source electrode 156 and the second drain electrode 158.

[0051] A polycrystalline semiconductor layer 154 is formed on the lower buffer layer 112 to overlap with the second gate electrode 152, thereby forming a channel between the second source electrode 156 and the second drain electrode 158. The polycrystalline semiconductor layer 154 has high mobility, resulting in low power consumption and high reliability. Therefore, preferably, the polycrystalline semiconductor layer 154 is applied to each driving transistor 150 of each pixel, each gate driving unit 40A and 40B driving the gate line GL, and / or a multiplexer (MUX). A multi-buffer layer 140 and the lower buffer layer 112 are disposed between the polycrystalline semiconductor layer 154 and the substrate 101. The multi-buffer layer 140 prevents the diffusion of moisture and / or oxygen that has permeated the substrate 101. The multi-buffer layer 140 is formed as a result of alternating stacking of silicon nitride (SiNx) and silicon oxide (SiOx) at least once. The lower buffer layer 112 blocks various defects introduced from the substrate 101, thereby preventing damage to the polycrystalline semiconductor layer 154. The lower buffer layer 112 may be formed of a-Si, silicon nitride (SiNx), or silicon oxide (SiOx).

[0052] The second gate electrode 152 is formed on the first gate dielectric film 114 to overlap with the channel region of the polycrystalline semiconductor layer 154 via the first gate dielectric film 114. The second gate electrode 152 may have a single-layer or multi-layer structure formed of the same material as the lower storage capacitor electrode 182, such as one or an alloy of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). However, the invention is not limited thereto.

[0053] The second source electrode 156 is connected to the source region of the polycrystalline semiconductor layer 154 through a second source contact hole 160S formed through the first gate dielectric film 114, the first interlayer dielectric film 116, the first upper buffer layer 118, the second upper buffer layer 122, the second gate dielectric film 124, the second interlayer dielectric film 146 and the third interlayer dielectric film 148.

[0054] The second drain electrode 158 is connected to the drain region of the polycrystalline semiconductor layer 154 through a second drain contact hole 160D formed through the first gate dielectric film 114, the first interlayer dielectric film 116, the first upper buffer layer 118, the second upper buffer layer 122, the second gate dielectric film 124, the second interlayer dielectric film 146, and the third interlayer dielectric film 148. The second source electrode 156 and the second drain electrode 158 are formed to face each other through the channel region of the polycrystalline semiconductor layer 154.

[0055] As a result of the lower storage capacitor electrode 182 and the upper storage capacitor electrode 184 overlapping each other via the first interlayer dielectric film 116, a storage capacitor 180 is formed.

[0056] The lower storage capacitor electrode 182 is formed on the first gate dielectric film 114 and is formed on the same layer as the second gate electrode 152 using the same material. The lower storage capacitor electrode 182 is exposed through a storage contact hole 186 formed through the first interlayer dielectric film 116, the first upper buffer layer 118, the second upper buffer layer 122, the second gate dielectric film 124, the second interlayer dielectric film 146, and the third interlayer dielectric film 148, so as to be electrically connected to the first drain electrode 108 of the switching transistor 100.

[0057] The upper storage capacitor electrode 184 is disposed on the first interlayer dielectric film 116. The upper storage capacitor electrode 184 is electrically connected to the second drain electrode 158 of the driving transistor 150.

[0058] A first interlayer dielectric film 116 disposed between the lower storage capacitor electrode 182 and the upper storage capacitor electrode 184 is formed of an inorganic dielectric material such as SiOx or SiNx. Preferably, the first interlayer dielectric film 116 is formed of SiNx, which has a higher dielectric constant than SiOx. Therefore, the lower storage capacitor electrode 182 and the upper storage capacitor electrode 184 overlap each other via the first interlayer dielectric film 116 formed of SiNx with a high dielectric constant, thereby increasing the capacitance of the storage capacitor proportional to the dielectric constant.

[0059] The light-emitting device 130 includes an anode 132, a cathode 136, and a light-emitting stack 134 formed between the anode 132 and the cathode 136.

[0060] The anode 132 is disposed on the second planarization layer 128, thus being independent for each sub-pixel. The anode 132 is connected to the pixel connection electrode 142 exposed through the second pixel contact hole 144 formed through the second planarization layer 128. Here, the pixel connection electrode 142 is connected to the second drain electrode 158 exposed through the first pixel contact hole 120 formed through the first planarization layer 126.

[0061] The anode 132 is disposed on the second planarization layer 128 to overlap with at least one of the driving transistor 150 and the switching transistor 100 and the light-emitting area provided by the dam 138, thereby increasing the light-emitting area.

[0062] A dam 138 is formed to expose the anode 132, thereby providing a light-emitting area. Alternatively, the dam 138 may be formed in the non-light-emitting area of ​​the display area AA, and simultaneously formed of an opaque material (e.g., black) to prevent light interference between adjacent sub-pixels. Or, the dam 138 may be formed in both the non-display area NA and the non-light-emitting area of ​​the display area AA, overlapping with the gate drive units 40A and 40B. In this case, the dam 138 comprises a light-shielding material composed of at least one of colored pigments, organic black, and carbon.

[0063] As a result of stacking the hole correlation layer, organic light-emitting layer, and electron correlation layer on the anode 132 in this order or the reverse order, a light-emitting stack 134 is formed. The light-emitting stack 134 is formed using a fine metal mask (FMM) manufacturing process. At this time, to prevent damage to the light-emitting stack 134 and / or the dam 138 due to the fine metal mask (FMM), spacers 178 are provided on the dam 138. The spacers 178 are formed of an organic dielectric material in the same manner as the dam 138 and the first planarization layer 126 and the second planarization layer 128.

[0064] A cathode 136 is formed on the upper and side surfaces of the light-emitting stack 134, thereby facing the anode 132 via the light-emitting stack 134. The cathode 136 is formed to be shared by all sub-pixels disposed in the display area AA. An encapsulation unit 170 is disposed on a substrate 101 on which the cathode 136 is formed.

[0065] The encapsulation unit 170 prevents external moisture or oxygen from penetrating into the light-emitting device 130, which has low resistance to external moisture or oxygen. For this purpose, the encapsulation unit 170 includes a plurality of inorganic encapsulation layers 172 and 176 and an organic encapsulation layer 174 disposed between the plurality of inorganic encapsulation layers 172 and 176. The inorganic encapsulation layer 176 is positioned as the uppermost layer. In this case, the encapsulation unit 170 includes at least two inorganic encapsulation layers 172 and 176 and at least one organic encapsulation layer 174. Hereinafter, the encapsulation unit 170 having a structure with the organic encapsulation layer 174 disposed between the first inorganic encapsulation layer 172 and the second inorganic encapsulation layer 176 will be described by way of example.

[0066] An organic encapsulation layer 174 is disposed between inorganic encapsulation layers 172 and 176 to reduce stress between the corresponding layers caused by bending of the substrate 101 of the flexible display device. That is, the organic encapsulation layer 174 acts as a shock absorber. Additionally, the organic encapsulation layer 174 enhances planarization performance. The organic encapsulation layer 174 is formed of an organic dielectric material such as acrylic resin, epoxy resin, polyimide, polyethylene, or silicon carbide (SiOC).

[0067] A first inorganic encapsulation layer 172 is formed on a substrate 101 on which a cathode 136 is formed, and is located closest to the light-emitting device 130. The first inorganic encapsulation layer 172 is formed of an inorganic dielectric material that can be deposited at low temperatures, such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3). Therefore, by depositing the first inorganic encapsulation layer 172 in a low-temperature atmosphere, damage to the light-emitting stack 134, which has low resistance to high-temperature atmospheres, can be prevented during the process of depositing the first inorganic encapsulation layer 172.

[0068] A second inorganic encapsulation layer 176 is formed on a substrate 101 on which an organic encapsulation layer 174 is formed, to cover the upper and side surfaces of each of the organic encapsulation layer 174 and the first inorganic encapsulation layer 172. Therefore, the second inorganic encapsulation layer 176 reduces or minimizes or prevents external moisture or oxygen from penetrating into the first inorganic encapsulation layer 172 and the organic encapsulation layer 174. The second inorganic encapsulation layer 176 is formed of an inorganic dielectric material such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3).

[0069] To prevent the channel region 104C of the oxide semiconductor layer 104 from becoming conductive due to hydrogen (H) diffusion from the first inorganic encapsulation layer 172 and the second inorganic encapsulation layer 176 to the substrate 101, the second interlayer dielectric film 146 is formed to include a trapping element Te, such as... Figure 3 As shown.

[0070] like Figure 2 and Figure 3 As shown, the second interlayer dielectric film 146 adjacent to the oxide semiconductor layer 104 includes a lower interlayer region 146a and an upper interlayer region 146b sequentially disposed on the second gate dielectric film 124.

[0071] The lower interlayer region 146a is disposed on the second gate dielectric film 124. The lower interlayer region 146a is formed of SiOx such that the content of the trapping element Te, which is capable of trapping hydrogen atoms (H), is 0%, or it is formed of SiOx having a lower content of the trapping element Te than the upper interlayer region 146b.

[0072] An upper interlayer region 146b is formed on a lower interlayer region 146a to include a trapping element Te capable of trapping hydrogen atoms (H). The trapping element Te is composed of at least one of nitrogen (N), fluorine (F), and boron (B). The trapping element Te is formed in the upper interlayer region 146b to have a predetermined content, or is formed such that the content of the trapping element Te gradually decreases from the upper part of the upper interlayer region 146b to the lower interlayer region 146a.

[0073] The second interlayer dielectric film 146, comprising a lower interlayer region 146a and an upper interlayer region 146b, is formed by the following steps: SiOx is completely deposited on a substrate 101 on which an oxide semiconductor layer 104 has a source region 104S and a drain region 104D formed by a doping process, and the trapping element Te is implanted into at least a portion of the SiOx by a surface plasmon bonding process or a doping process. Therefore, the second interlayer dielectric film 146 is divided into an upper interlayer region 146b including the trapping element Te and a lower interlayer region 146a excluding the trapping element Te.

[0074] At this point, the trapping element Te, implanted into the second interlayer dielectric film 146 via a plasma treatment process, traps unbound hydrogen (H+), i.e., separated hydrogen (H+), thereby suppressing the introduction of hydrogen (H) into the oxide semiconductor layer 104. Specifically, when the trapping element Te is nitrogen (N), the hydrogen (H)-nitrogen (N) bond dissociation energy is lower than the hydrogen (H)-oxygen (O) bond dissociation energy. Therefore, the separated hydrogen (H+) irreversibly binds to nitrogen (N) in the upper interlayer region 146b, but not irreversibly binds to oxygen (O) in the oxide semiconductor layer 104, and is trapped in the upper interlayer region 146b.

[0075] In this invention, as described above, hydrogen (H) diffusing from the packaging unit 170 is captured by nitrogen (N) included in the third interlayer dielectric film 148 formed of SiNx and by the trapping element Te included in the second interlayer dielectric film 146. Therefore, it is possible to prevent hydrogen (H) diffusing from the packaging unit 170 from being introduced into the oxide semiconductor layer 104, thereby preventing fluctuations in the threshold voltage of the switching transistor 100 including the oxide semiconductor layer 104.

[0076] Figure 4 This is a cross-sectional view of an organic light-emitting display device according to a second embodiment of the present invention.

[0077] Figure 4 The organic light-emitting display device shown is structurally similar to... Figure 2 The organic light-emitting display device shown is the same, except that not only the second interlayer dielectric film 146, but also the second gate dielectric film 124 and the first gate electrode 102 include trapping elements. Therefore, a detailed description of the same components will be omitted.

[0078] like Figure 4 and Figure 5 As shown, the second gate dielectric film 124 includes a lower dielectric region 124a and an upper dielectric region 124b sequentially disposed on the second upper buffer layer 122.

[0079] The lower dielectric region 124a is disposed on the second upper buffer layer 122. The lower dielectric region 124a is formed of SiOx such that it does not contain the trapping element Te, which is capable of trapping hydrogen atoms (H), or it is formed of SiOx having a lower content of the trapping element Te than the upper dielectric region 124b.

[0080] An upper dielectric region 124b is formed on a lower dielectric region 124a to include a trapping element Te capable of trapping hydrogen atoms (H). The trapping element Te is composed of at least one of nitrogen (N), fluorine (F), and boron (B). The trapping element Te is formed in the upper dielectric region 124b to have a predetermined content, or is formed such that the content of the trapping element Te gradually decreases from the upper part of the upper dielectric region 124b to the lower dielectric region 124a.

[0081] After the first gate electrode 102 is formed, the trapping element Te is implanted into the second gate dielectric film 124 via a plasma processing process. In this case, the upper dielectric region 124b is formed to include the trapping element Te in the remaining region except for the region where it overlaps with the lower gate region 102a of the first gate electrode 102. Therefore, the trapping element can be implanted into both the second gate dielectric film 124, including the upper dielectric region 124b, and the first gate electrode 102 simultaneously, thereby simplifying the process.

[0082] The first gate electrode 102 includes a lower gate region 102a and an upper gate region 102b disposed on the second gate dielectric film 124.

[0083] The lower gate region 102a is formed of a gate metal layer (e.g., Mo) such that the trapping element Te is not included on the second gate dielectric film 124, or it is formed of a gate metal layer having a lower content of the trapping element Te than the upper gate region 102b.

[0084] An upper gate region 102b is formed on the upper surface and side surface of the lower gate region 102a to include a trapping element Te capable of trapping hydrogen atoms (H). The trapping element Te is composed of at least one of nitrogen (N), fluorine (F), and boron (B). The trapping element Te is formed in the upper gate region 102b to have a predetermined content, or is formed such that the content of the trapping element Te gradually decreases from the upper part of the upper gate region 102b to the lower gate region 102a.

[0085] The trapping element Te, comprising at least one of the upper gate region 102b, the upper dielectric region 124b, and the upper interlayer region 146b, traps unbound hydrogen (H+), i.e., separated hydrogen (H+), thereby suppressing the introduction of hydrogen (H) into the oxide semiconductor layer 104. Specifically, when the trapping element Te is nitrogen (N), the hydrogen (H)-nitrogen (N) bond dissociation energy is lower than the hydrogen (H)-oxygen (O) bond dissociation energy, such as... Figure 6 As shown in the diagram, the separated hydrogen (H+) irreversibly binds to nitrogen (N) in each of the upper gate region 102b, upper dielectric region 124b, and upper interlayer region 146b, but not irreversibly binds to oxygen (O) in the oxide semiconductor layer 104, and is trapped in each of the upper gate region 102b, upper dielectric region 124b, and upper interlayer region 146b.

[0086] In this invention, as described above, hydrogen diffused from the package unit 170 is trapped in the upper gate region 102b, upper dielectric region 124b, and upper interlayer region 146b by a trapping element Te (e.g., nitrogen (N)). In this case, hydrogen diffused from the package unit 170 can be prevented from being introduced into the oxide semiconductor layer 104. Therefore, in this invention, it is possible to prevent the channel region 104C of the oxide semiconductor layer 104 from becoming conductive due to hydrogen diffused from the package unit 170, thereby preventing fluctuations in the threshold voltage of the switching transistor 100.

[0087] Figures 7A to 7G This illustrates the manufacturing process according to an embodiment of the present invention. Figure 4 A cross-sectional view of the method for the organic light-emitting display device shown.

[0088] Reference Figure 7A An oxide semiconductor layer 104 is formed on a substrate 101, which has a polycrystalline semiconductor layer 154, a second gate electrode 152 for driving transistors, and a storage capacitor 180 formed thereon.

[0089] Specifically, an inorganic dielectric material, such as SiOx or SiNx, is completely deposited on a substrate 101, which has a polycrystalline semiconductor layer 154, a second gate electrode 152 for driving transistors, and a storage capacitor 180 formed thereon, thereby sequentially forming a first upper buffer layer 118 and a second upper buffer layer 122. Subsequently, an oxide comprising at least one metal selected from Zn, Cd, Ga, In, Sn, Hf, and Zr is completely deposited and patterned on the second upper buffer layer 122 to form an oxide semiconductor layer 104.

[0090] Reference Figure 7B A second gate dielectric film 124 is formed on a substrate 101 on which an oxide semiconductor layer 104 is formed, and a first gate electrode 102 is formed on the second gate dielectric film 124.

[0091] Specifically, SiOx is completely deposited on a substrate 101 on which an oxide semiconductor layer 104 is formed, thereby forming a second gate dielectric film 124. Subsequently, a gate metal layer is completely deposited and patterned on the second gate dielectric film 124, thereby forming a first gate electrode 102 with a monolayer structure. The oxide semiconductor layer 104 is doped with a dopant using a doping process that uses the first gate electrode 102 as a mask. As a result, a source region 104S and a drain region 104D configured not to overlap with the first gate electrode 102, and a channel region 104C configured to overlap with the first gate electrode 102 are formed.

[0092] Reference Figure 7C Each of the second gate dielectric film 124 and the first gate electrode 102 formed on the substrate 101 is formed to have a multilayer structure.

[0093] Specifically, after the doping process using the first gate electrode 102 as a mask, the surfaces of each of the first gate electrode 102 and the second gate dielectric film 124 are subjected to preliminary plasma treatment using a source gas (e.g., NH3) containing the trapping element Te (e.g., nitrogen (N)). As a result, the first gate electrode 102 is formed with a multilayer structure, which includes an upper gate region 102b containing the trapping element and a lower gate region 102a not containing the trapping element. Similarly, the second gate dielectric film 124 is formed with a multilayer structure, which includes an upper dielectric region 124b containing the trapping element and a lower dielectric region 124a not containing the trapping element.

[0094] Reference Figure 7D A second interlayer dielectric film 146 with a multilayer structure is formed on a substrate 101 on which multiple layers of second gate dielectric film 124 and multiple layers of first gate electrode 102 are formed.

[0095] Specifically, SiOx is completely deposited on a substrate 101 on which multiple layers of second gate dielectric films 124 and multiple layers of first gate electrodes 102 are formed, thereby forming a second interlayer dielectric film 146. Subsequently, the surface of the second interlayer dielectric film 146 is subjected to a secondary plasma treatment using a gas (e.g., NH3) containing the trapping element Te (e.g., nitrogen (N)). As a result, the second interlayer dielectric film 146 is formed to have a multilayer structure, which includes an upper interlayer region 146b containing the trapping element and a lower interlayer region 146a not containing the trapping element.

[0096] Reference Figure 7E Source contact holes 110S and 160S, drain contact holes 110D and 160D, and storage contact hole 186 are formed on a substrate 101 on which a second interlayer dielectric film 146 is formed.

[0097] Specifically, SiOx is completely deposited on the substrate 101 on which the second interlayer dielectric film 146 is formed, thereby forming the third interlayer dielectric film 148. Subsequently, the first gate dielectric film 114, the first interlayer dielectric film 116, the first upper buffer layer 118, the second upper buffer layer 122, the second gate dielectric film 124, the second interlayer dielectric film 146, and the third interlayer dielectric film 148 are selectively patterned to form source contact holes 110S and 160S, drain contact holes 110D and 160D, and storage contact hole 186. Here, the first source contact hole 110S and the first drain contact hole 110D are formed to pass through the second gate dielectric film 124, the second interlayer dielectric film 146, and the third interlayer dielectric film 148 to expose the oxide semiconductor layer 104. The second source contact 160S and the second drain contact 160D are formed to pass through the first gate dielectric film 114, the first interlayer dielectric film 116, the first upper buffer layer 118, the second upper buffer layer 122, the second gate dielectric film 124, the second interlayer dielectric film 146, and the third interlayer dielectric film 148, so as to expose the polycrystalline semiconductor layer 154. The storage contact 186 is formed to pass through the first interlayer dielectric film 116, the first upper buffer layer 118, the second upper buffer layer 122, the second gate dielectric film 124, the second interlayer dielectric film 146, and the third interlayer dielectric film 148, so as to expose the lower storage capacitor electrode 182.

[0098] Reference Figure 7F Source electrodes 106 and 156 and drain electrodes 108 and 158 are formed on a substrate 101 on which source contact holes 110S and 160S, drain contact holes 110D and 160D and storage contact hole 186 are formed.

[0099] The source / drain metal layers are completely deposited on a substrate 101 on which source contact holes 110S and 160S, drain contact holes 110D and 160D, and storage contact hole 186 are formed. Subsequently, the source / drain metal layers are patterned to form a first source electrode 106 and a second source electrode 156, as well as a first drain electrode 108 and a second drain electrode 158.

[0100] Reference Figure 7G The pixel connection electrode 142, the light-emitting device 130 and the packaging unit 170 are sequentially formed on the substrate 101 on which active electrodes 106, 156 and drain electrodes 108, 158 are formed.

[0101] In this invention, as described above, hydrogen diffusing from the package unit 170 is trapped by a trapping element Te (e.g., nitrogen (N)) in the upper gate region 102b, the upper dielectric region 124b, and the upper interlayer region 146b, where the trapping element Te is included. As a result, hydrogen diffusing from the package unit 170 can be prevented from being introduced into the oxide semiconductor layer 104. Therefore, in this invention, it is possible to prevent the channel region 104C of the oxide semiconductor layer 104 from becoming conductive due to hydrogen diffusing from the package unit 170, thereby preventing fluctuations in the threshold voltage of the switching transistor 100.

[0102] Specifically, such as Figure 8 As shown, it can be seen that when the flow rate of the source gas (NH3) including the trapping element (N) is increased under conditions where the flow rate of the silane gas (SiH4) is uniform, the threshold voltage Vth of the transistor shifts in the positive (+) direction. That is, even if the carrier concentration in the channel of the oxide semiconductor layer 104 increases due to hydrogen and therefore the threshold voltage Vth of the switching transistor 100 shifts in the negative (-) direction, the threshold voltage Vth of the switching transistor 100 also shifts in the positive (+) direction by using a plasma processing process that includes the source gas (NH3) including the trapping element (N). Therefore, in this invention, fluctuations in the threshold voltage of the switching transistor 100 can be prevented.

[0103] Furthermore, in this invention, the first gate electrode 102 can be formed as a single-layer structure without a Ti conductive layer by means of a trapping element Te included in one of the second interlayer dielectric film 146, the second gate dielectric film 124, and the first gate electrode 102. Therefore, the first gate electrode 102 according to the invention has a lower load resistance than the first gate electrode according to the comparative example which has a multilayer structure including a Ti conductive layer, thereby ensuring brightness uniformity in the display area AA and reducing costs. For example, in this invention, when the first gate electrode 102 is formed as a single-layer structure formed of Mo, the Ti layer, whose resistivity is eight times that of Mo, can be removed, thereby reducing resistance.

[0104] Furthermore, in this invention, problems arising from differences in etching properties between the Mo and Ti layers included in the first gate electrode according to the comparative example, such as Ti layer tailing, high taper angle, and linewidth (CD) deviation between the Mo and Ti layers, can be prevented.

[0105] Meanwhile, although the present invention has described by way of example a structure in which at least one of the first gate electrode 102, the second gate dielectric film 124, and the second interlayer dielectric film 146 disposed on the oxide semiconductor layer 104 includes the trapping element Te, the trapping element may also be included in a portion of a thin film layer disposed below the oxide semiconductor layer 104. For example, the trapping element Te may be included in a portion of at least one of the first upper buffer layer 118, the second upper buffer layer 122, and the upper storage capacitor electrode 184 disposed below the oxide semiconductor layer 104.

[0106] Furthermore, in this invention, the nitrogen (N) content included in at least one of the third interlayer dielectric film 148 and the first upper buffer layer 118 formed of SiNx can be higher than the nitrogen (N) content of the SiNx film included in the multi-buffer layer 140. In this case, the nitrogen (N) included in the third interlayer dielectric film 148 and the first upper buffer layer 118 traps hydrogen diffusing into the oxide semiconductor layer 104, thereby preventing fluctuations in the threshold voltage of the switching transistor 100.

[0107] Furthermore, although a structure in which at least one of the first gate electrode 102, the second gate dielectric film 124, and the second interlayer dielectric film 146 is included in the present invention by way of example through a plasma processing process, the trapping element Te may also be included in at least one of the first gate electrode 102, the second gate dielectric film 124, and the second interlayer dielectric film 146 through a doping process. A source gas including the trapping element Te may be injected during the SiOx deposition of the second gate dielectric film 124 and the second interlayer dielectric film 146, or a source gas including the trapping element Te may be injected during the Mo deposition of the first gate electrode 102.

[0108] Furthermore, although organic light-emitting display devices have been described by way of example in this invention, the invention can also be applied to electronic devices including transistors.

[0109] As is evident from the above description, the trapping element is injected into a portion of a nitrogen-free thin film layer disposed above or below the oxide semiconductor layer, thereby preventing hydrogen diffusion into the oxide semiconductor layer. Therefore, in this invention, the carrier concentration in the channel of the switching transistor can be prevented from increasing due to hydrogen. As a result, fluctuations in the threshold voltage of the switching transistor can be prevented, thereby improving the reliability of the switching transistor.

[0110] Furthermore, in this invention, the first gate electrode disposed on the oxide semiconductor layer is formed with a single-layer structure, thereby reducing the load resistance of the gate electrode and reducing processing and material costs.

[0111] Furthermore, in this invention, tailing, high taper angle, and linewidth deviation that occur in the first gate electrode having a multilayer structure can be prevented.

[0112] Various modifications and variations can be made to this invention without departing from its spirit or scope, as will be apparent to those skilled in the art. Therefore, this invention is intended to cover any modifications and variations that fall within the scope of the appended claims and their equivalents.

[0113] Cross-references to related applications

[0114] This patent application claims the benefit of Korean Patent Application No. 10-2020-0161715, filed on November 26, 2020, which is incorporated herein by reference as if fully set forth herein.

Claims

1. A display device, the display device comprising: A thin-film transistor disposed on a substrate, the thin-film transistor comprising an oxide semiconductor layer and a gate electrode disposed on the oxide semiconductor layer; A light-emitting device, wherein the light-emitting device is electrically connected to the thin-film transistor; as well as Multiple dielectric films are disposed between the oxide semiconductor layer and the light-emitting device. Wherein, at least one of the plurality of dielectric films is an interlayer dielectric film disposed on the gate electrode, and The interlayer dielectric film includes: The lower region disposed on the gate electrode; and An upper region is disposed on the lower region, the upper region including a trapping element configured to prevent hydrogen diffusion into the oxide semiconductor layer. Among them, another of the plurality of dielectric films is a gate dielectric film disposed between the oxide semiconductor layer and the gate electrode, and The trapping element included in the gate dielectric film is disposed in the remaining region except for the region configured to overlap with the channel region of the oxide semiconductor layer.

2. The display device according to claim 1, wherein, The captured element includes at least one of nitrogen, fluorine, and boron.

3. The display device according to claim 1, wherein, The content of the captured element in the lower region is lower than that in the upper region.

4. The display device according to claim 1, wherein, The content of the captured element in the lower region is 0%.

5. The display device according to claim 1, wherein, The capturing element is configured such that its content gradually decreases from the upper part of the upper region to the lower part of the upper region.

6. The display device according to claim 1, wherein, The lower region is formed of SiOx.

7. The display device according to claim 1, wherein, The thin-film transistor further includes: The source electrode is configured to contact the oxide semiconductor layer; and The drain electrode, opposite the source electrode, is configured to contact the oxide semiconductor layer, and The interlayer dielectric film is disposed between the source electrode and the gate electrode in each of the source electrode and the drain electrode.

8. The display device according to claim 7, wherein, The interlayer dielectric film includes: The lower interlayer region, which is the lower region; and The upper interlayer region, which is the upper region.

9. The display device according to claim 8, wherein, The gate electrode includes: Upper gate region, the upper gate region including the trapping element; and The lower gate region is disposed between the oxide semiconductor layer and the upper gate region.

10. The display device according to claim 8, wherein, The gate dielectric film includes a lower dielectric region and an upper dielectric region, which is another upper region. The trapping element, which is included in the upper dielectric region of the gate dielectric film, is disposed in the remaining region except for the region configured to overlap with the gate electrode.

11. The display device according to claim 8, wherein, The gate dielectric film includes a lower dielectric region and an upper dielectric region, which is another upper region. The trapping element is included in the upper dielectric region of the gate dielectric film.

12. The display device according to claim 1, further comprising: A first upper buffer layer, a second upper buffer layer, and a storage capacitor are disposed beneath the oxide semiconductor layer. The capture element is included in at least a portion of at least one of the first upper buffer layer and the second upper buffer layer, as well as the upper storage capacitor electrode of the storage capacitor.

13. The display device according to claim 12, wherein, The upper storage capacitor electrode of the storage capacitor is electrically connected to the drain electrode of the thin-film transistor.

14. The display device according to claim 1, further comprising: The encapsulation unit disposed on the light-emitting device includes a plurality of inorganic encapsulation layers and an organic encapsulation layer disposed between the plurality of inorganic encapsulation layers.

15. A method for manufacturing a display device, the method comprising the following steps: An oxide semiconductor layer for forming thin-film transistors is formed on a substrate; A gate dielectric film is formed in the oxide semiconductor layer, and the gate electrode of the thin-film transistor is formed on the gate dielectric film; The surfaces of each of the gate electrode and the gate dielectric film are plasma-treated using a source gas containing a trapping element, such that at least one of the gate electrode and the gate dielectric film includes an upper region containing the trapping element and a lower region not containing the trapping element. An interlayer dielectric film is formed on the gate electrode and the gate dielectric film; The surface of the interlayer dielectric film is subjected to plasma treatment using a gas containing the trapping element, such that the interlayer dielectric film includes an upper interlayer region containing the trapping element and a lower interlayer region not containing the trapping element; and The source and drain electrodes of the thin-film transistor, pixel connection electrodes, light-emitting devices, and packaging units are sequentially formed on the substrate. The trapping element included in the gate dielectric film is disposed in the remaining region except for the region configured to overlap with the channel region of the oxide semiconductor layer.

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