DC-DC Power Supply Architecture Capable of Rapid Output Power Switching and Its Control Method

Abstract

The present invention relates to a DC-DC power supply architecture capable of realizing rapid switching of output power and a control method thereof. The power supply architecture includes a driving module Driver, a switching module, an LC module, a sampling module, and a feedback control module that are connected in sequence to form a loop. When the output voltage changes from high to low, the current flowing through the feedback resistor will increase instantaneously, causing the node voltage of the feedback voltage to be instantaneously lifted. When the feedback voltage > the second threshold voltage > the first threshold voltage, the output of the third comparator becomes high, controlling the first NMOS transistor to pull down and pulling the feedback voltage of the Vfb2 node to the reference voltage Vref. By setting the priority of the control signal Vctrl becoming high to be higher than the low-power mode enable signal, the present invention can accelerate the jump adjustment of the output power, thereby solving the technical problem of long establishment time during the switching of the output voltage in the existing DC-DC power supply architecture, shortening the stabilization time after the output voltage jumps, and realizing the rapid switching of the output power.

Description

Technical Field

[0001] The present invention relates to a DC-DC power supply architecture and a control method thereof, and particularly to a DC-DC power supply architecture capable of realizing rapid switching of output power and a control method thereof. Background Art

[0002] For the most basic implementation of a DC-DC power supply architecture with variable output power and its control method, refer to Figure 1 , taking a buck converter circuit (Buck circuit) as an example. For the first variable output power DC-DC power supply architecture, its working principle is that, based on a conventional DC-DC power supply architecture, a digital-to-analog conversion unit (DAC) is added, that is, Figure 1 the first digital-to-analog conversion unit DAC1 in , so that when the system detects that in a certain mode, it is necessary to adjust the output voltage Vout to change the power supply of the power system to the load, the central control unit can issue an instruction through a digital interface to modify the DAC code word stored in the register, thereby modifying the first reference voltage Vref1 at the output end of the first digital-to-analog conversion unit DAC1. Then, under the action of negative feedback adjustment of the loop, the purpose of changing the power supply output voltage is achieved.

[0003] Figure 1 The peripheral auxiliary circuit is omitted; its logic control unit Logic is a control circuit such as PWM / PFM / COT, and EA is an error amplifier for increasing the loop gain; the first comparator comp1 is the main loop comparator to complete the negative feedback loop adjustment function; when in light load, the efficiency of the Buck circuit decreases, the ripple of the output voltage Vout increases, and the fluctuation of the feedback voltage Vfb also increases.

[0004] In order to improve the efficiency, a second comparator comp2 can be added on the basis of the first variable output power DC-DC power supply architecture, and then its input reference voltage is set to the second reference voltage Vref2, where the second reference voltage Vref2 > the first reference voltage Vref1. When the feedback voltage Vfb > the second reference voltage Vref2, the logic control unit Logic is controlled through the comparison result to turn off the circuits of other power-consuming parts in the loop except the second comparator comp2. When the output voltage decreases, resulting in the feedback voltage Vfb dropping below the second reference voltage Vref2, the system loop is established again. Through this dynamic adjustment, the purpose of improving the system efficiency under light load conditions is achieved, and this mode is called the low-power mode (Low-Iq mode). At this time, the driver unit Driver outputs to maintain the MOS power tube output in a floating state.

[0005] It should be noted that if a low power consumption mode is added, in order to improve efficiency under light load conditions with different output voltages, the second reference voltage Vref2 must be able to change in the same direction as the first reference voltage Vref1, which requires an additional second digital-to-analog conversion unit DAC2, resulting in a waste of circuit board or integrated chip area. This disadvantage becomes more serious when the DAC has a large number of bits.

[0006] In addition, this DC-DC power supply architecture has a shortcoming that needs to be overcome: due to the relatively complex Buck loop, when the DC-DC power supply architecture performs dynamic output switching, the output voltage Vout will vary within a relatively wide range, which requires the digital-to-analog conversion unit to control the corresponding reference voltage to vary within a relatively wide range. This will increase the design complexity of the comparator to a certain extent, such as the requirement for the input common-mode voltage range to be more stringent; there is also the drift of the static operating point, which may also affect the loop stability of the power supply system under different output conditions; it will also bring a series of negative effects in design simulation.

[0007] The module structure of the second variable output power DC-DC power supply architecture is different from that of the first architecture in that the second architecture places the digital-to-analog conversion unit DAC for adjusting the output voltage Vout at the output feedback resistor, see Figure 2 .

[0008] Compared with the first architecture, this architecture has the following two advantages:

[0009] 1) This architecture only requires one digital-to-analog conversion unit DAC to achieve both the dynamic change of output voltage and the low-power mode tracking and discrimination.

[0010] 2) The input reference voltages of the comparators used are all fixed values, making comparator design and loop stability verification relatively easy.

[0011] However, this architecture has a shortcoming: when the DAC codeword changes the resistance value of the feedback resistor Rf from large to small, due to the slow change rate of the output voltage Vout1, at the moment when the DAC state of the digital-to-analog conversion unit switches, a transient current will flow through the gain resistor Rg across the feedback resistor Rf, causing a large overshoot in the node voltage of the feedback voltage Vfb1. This node is a high-resistance node, which will cause the node voltage recovery process of the feedback voltage Vfb1 to be too long, resulting in a longer stabilization time when the output voltage Vout1 switches from high to low. What's worse is that this overshoot of the feedback voltage Vfb1 is often greater than the second reference voltage Vref2, which will trigger the low-power mode mentioned earlier, that is, actively disconnecting the loop adjustment, causing the loop to lose the pull-down adjustment capability of the NMOS power tube, making the establishment time of the output voltage Vout1 during the switching process deteriorate to an unacceptable level.

[0012] When the output voltage Vout1 switches to a high voltage, fundamentally speaking, the system will not enter the low-power mode. At this time, although the feedback voltage Vfb1 is still a high-impedance node, under the action of loop negative feedback, the system has a relatively short settling time. Therefore, only the process of the digital-to-analog conversion unit controlling the output voltage to drop needs to be considered. In this process, how to eliminate or reduce the impact brought by this deficiency, without preventing the normal entry into the low-power mode under light load, and enabling the settling time during the system power down to meet the performance requirements, becomes a problem that this architecture must solve. Summary of the Invention

[0013] The object of the present invention is to provide a DC-DC power supply architecture capable of realizing rapid switching of output power and its control method, which solves the technical problem of long settling time during the switching of the output voltage Vout1 in the existing DC-DC power supply architecture, can shorten the settling time after the jump of the output voltage Vout1, and realize the rapid switching of output power.

[0014] The technical solution of the present invention is as follows:

[0015] A DC-DC power supply architecture capable of realizing rapid switching of output power. The special feature is that it includes a driving module Driver, a switching module, an LC module, a sampling module, and a feedback control module that are connected in sequence and form a loop; the switching module includes a PMOS power transistor and an NMOS power transistor connected in sequence; the sampling module includes a digital-to-analog conversion unit DAC, and a feedback resistor Rf and a gain resistor Rg connected in series; the feedback resistor Rf is a digitally adjustable resistor, and its resistance value control terminal is connected to the output terminal of the digital-to-analog conversion unit DAC; the feedback control module includes a first comparison unit, a second comparison unit, a first logic control unit Logic, and a pull-down unit; the output terminal of the first logic control unit Logic is connected to the input terminal of the driving module Driver to control the operation of the driving module Driver; the first comparison unit includes an error amplifier EA and a first comparator comp1; the positive input terminal of the error amplifier EA is connected to a first reference voltage Vref1, and its negative input terminal is connected to the connection point of the feedback resistor Rf and the gain resistor Rg; the positive input terminal of the first comparator comp1 is connected to the connection point of the feedback resistor Rf and the gain resistor Rg, its negative input terminal is connected to the output terminal of the error amplifier EA, and its output terminal is connected to one of the input terminals of the first logic control unit; the second comparison unit includes a second comparator comp2, an inverter, and a NOR gate; the positive input terminal of the second comparator comp2 is connected to the connection point of the feedback resistor Rf and the gain resistor Rg, its negative input terminal is connected to a first threshold voltage Vth_1, and its output terminal is connected to one of the input terminals of the NOR gate through the inverter; the other input terminal of the NOR gate is connected to a control signal Vctrl, and its output terminal is connected to the other input terminal of the first logic control unit; the pull-down unit includes a third comparator comp3, a delay unit Delay, and a pull-down NMOS transistor NMOS1; the positive input terminal of the third comparator comp3 is connected to the connection point of the feedback resistor Rf and the gain resistor Rg, its negative input terminal is connected to a second threshold voltage Vth_2, and its output terminal outputs a control signal Vctrl after being delayed by the delay unit; the control signal Vctrl is connected to the gate of the pull-down NMOS transistor NMOS1; the drain of the pull-down NMOS transistor NMOS1 is connected to the connection point of the feedback resistor Rf and the gain resistor Rg, and its source is connected to a reference voltage Vref; the first reference voltage Vref1 is a fixed value; the first threshold voltage Vth_1 is a fixed value; the second threshold voltage Vth_2 is a fixed value, and the second threshold voltage Vth_2 > the first threshold voltage Vth_1 > the reference voltage Vref > the first reference voltage Vref1.

[0016] The above reference voltage Vref = Vref1 + B, where B ranges from 5 to 20 mV, preferably 10 mV.

[0017] The present invention also provides a control method for the above variable output power DC-DC power supply architecture, including the following steps:

[0018] The driving module controls the on / off of the switching module;

[0019] The switching module controls the power supply to provide the output voltage Vout2 to the load RL within half a cycle, and within the other half cycle, the capacitor Cs in the LC module provides the output voltage Vout2 to the load RL; when it is necessary to adjust the output voltage Vout2 to change the power supply to the load RL, the central control unit adjusts the resistance value of the feedback resistor Rf in the sampling module through the digital-to-analog conversion unit DAC, and correspondingly adjusts the magnitude of the feedback voltage Vfb2; in the feedback control module, the first comparator comp1 compares the feedback voltage Vfb2 with the first reference voltage Vref1, the second comparator comp2 compares the feedback voltage Vfb2 with the first threshold voltage Vth_1, and the third comparator comp3 compares the feedback voltage Vfb2 with the second threshold voltage Vth_2;

[0020] When the feedback voltage Vfb2 is greater than the first reference voltage Vref1, the first comparator comp1 outputs a corresponding negative feedback control signal, and under the action of the negative feedback control signal, the driving module drives the loop to adjust the magnitude of the output voltage Vout2;

[0021] When the feedback voltage Vfb2 is greater than the first threshold voltage Vth_1, the second comparator comp2 outputs a corresponding negative feedback control signal, and under the action of the negative feedback control signal, the driving module turns off other power-consuming circuits in the power supply architecture loop except the second comparison unit and the third comparison unit;

[0022] When the feedback voltage Vfb2 is greater than the second threshold voltage Vth_2, the control signal Vctrl output by the third comparator comp3 after being delayed by the delay unit controls the pull-down NMOS transistor NMOS1 to pull down, pulling down the feedback voltage Vfb2 to the reference voltage Vref, enabling the power supply architecture loop to quickly recover, and relying on the loop negative feedback to accelerate the output power jump adjustment; the reference voltage Vref is greater than the first reference voltage Vref1 and less than the first threshold voltage Vth_1.

[0023] Advantages of the present invention:

[0024] The present invention only needs to add a conventional comparator, a delay unit Td, and a pull-down NMOS transistor NMOS1 for pull-down on the basis of a conventional DC-DC power supply architecture, and at the same time set the priority of the control signal Vctrl becoming high to be higher than the low-power mode enable signal to accelerate the output power jump adjustment. The implementation method is simple, and the chip structure is simpler. The present invention is suitable for various DC-DC power supply architectures.

[0025] The present invention solves the technical problem of long establishment time during the switching of the output voltage Vout1 in the existing DC-DC power supply architecture, can shorten the stabilization time after the jump of the output voltage Vout1, and realizes the rapid switching of the output power. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 FIG. 6 is a schematic diagram of the existing first variable-output-power DC-DC power supply architecture;

[0027] Figure 2 FIG. 7 is a schematic diagram of the existing second variable-output-power DC-DC power supply architecture;

[0028] Figure 3 FIG. 8 is a schematic diagram of the DC-DC power supply architecture of the present invention capable of rapidly switching the output power;

[0029] Figure 4 FIG. 9 is a schematic diagram of the action stages of each comparator of the present invention and the relationship of the reference voltages;

[0030] Figure 5 FIG. 10 is a schematic diagram of the comparison of the waveform effects of the key nodes between the existing power supply architecture and the DC-DC power supply architecture of the present invention capable of rapidly switching the output power. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0031] A DC-DC power supply architecture capable of realizing rapid switching of the output power according to the present invention is shown in Figure 3, and its special feature is that it includes a driving module Driver, a switching module, an LC module, a sampling module, and a feedback control module that are connected in sequence to form a loop; the switching module includes a PMOS power transistor and an NMOS power transistor connected in sequence; the sampling module includes a digital-to-analog conversion unit DAC, as well as a feedback resistor Rf and a gain resistor Rg connected in series; the feedback resistor Rf is a digitally adjustable resistor, and its resistance value control terminal is connected to the output terminal of the digital-to-analog conversion unit DAC; the feedback control module includes a first comparison unit, a second comparison unit, a first logic control unit Logic, and a pull-down unit; the output terminal of the first logic control unit Logic is connected to the input terminal of the driving module Driver to control the operation of the driving module Driver; the first comparison unit includes an error amplifier EA and a first comparator comp1; the positive input terminal of the error amplifier EA is connected to a first reference voltage Vref1, and its negative input terminal is connected to the connection point of the feedback resistor Rf and the gain resistor Rg; the positive input terminal of the first comparator comp1 is connected to the connection point of the feedback resistor Rf and the gain resistor Rg, its negative input terminal is connected to the output terminal of the error amplifier EA, and its output terminal is connected to one of the input terminals of the first logic control unit; the second comparison unit includes a second comparator comp2, an inverter, and a NOR gate; the positive input terminal of the second comparator comp2 is connected to the connection point of the feedback resistor Rf and the gain resistor Rg, its negative input terminal is connected to a first threshold voltage Vth_1, and its output terminal is connected to one of the input terminals of the NOR gate after passing through the inverter; the other input terminal of the NOR gate is connected to a control signal Vctrl, and its output terminal is connected to the other input terminal of the first logic control unit; the pull-down unit includes a third comparator comp3, a delay unit Delay, and a pull-down NMOS transistor NMOS1; the positive input terminal of the third comparator comp3 is connected to the connection point of the feedback resistor Rf and the gain resistor Rg, its negative input terminal is connected to a second threshold voltage Vth_2, and its output terminal outputs a control signal Vctrl after being delayed by the delay unit; the control signal Vctrl is connected to the gate of the pull-down NMOS transistor NMOS1; the drain of the pull-down NMOS transistor NMOS1 is connected to the connection point of the feedback resistor Rf and the gain resistor Rg, and its source is connected to a reference voltage Vref; the first reference voltage Vref1 is a fixed value; the first threshold voltage Vth_1 is a fixed value; the second threshold voltage Vth_2 is a fixed value, and the second threshold voltage Vth_2 > the first threshold voltage Vth_1 > the reference voltage Vref > the first reference voltage Vref1.

[0032] Preferably, the above reference voltage Vref = Vref1 + B, where B ranges from 5 to 20 mV, preferably 10 mV.

[0033] When the output voltage Vout2 changes from high to low, the current flowing through the feedback resistor Rf will instantaneously increase, causing the node voltage of the feedback voltage Vfb2 to be instantaneously lifted. When the feedback voltage Vfb2 > the second threshold voltage Vth_2 > the first threshold voltage Vth_1, the output of the third comparator comp3 becomes high, controlling Figure 3 the first NMOS transistor NMOS1 in Figure 3 to pull down, pulling the feedback voltage of the Vfb2 node (the connection point of the feedback resistor Rf and the gain resistor Rg) to the reference voltage Vref (the first reference voltage Vref1 < the reference voltage Vref < the first threshold voltage Vth_1, usually taking Vref = Vref1 + B, where B ranges from 5 - 20 mV, preferably 10 mV). Because in the normal light load state, when the feedback voltage Vfb2 > the first threshold voltage Vth_1, the system will temporarily turn off both the PMOS power transistor and the NMOS power transistor in the switching circuit simultaneously to improve the system efficiency. During this period, the loop is disconnected and only powered by the output capacitor Cs. The feedback voltage Vfb2 is pulled back to the reference voltage Vref by the output of the third comparator comp3 (the reference voltage Vref < the first threshold voltage Vth_1, and the reference voltage Vref should have the ability to absorb the excess charge instantaneously accumulated by the feedback voltage Vfb2), which can directly skip the function of the second comparator comp2, forcefully get rid of the false low-power mode, and quickly restore the loop, relying on the loop negative feedback to accelerate the output power jump adjustment. Figure 3 In Figure 3 , only a conventional comparator, a delay unit Td, a pull-down NMOS transistor NMOS1 for pulling down need to be added, and at the same time, set the priority of the control signal Vctrl becoming high to be higher than the low-power mode enable signal, and the implementation method is relatively simple.

[0034] The present invention also provides a control method for the above variable output power DC-DC power supply architecture, including the following steps:

[0035] The driving module controls the on and off of the switching module;

[0036] The switching module controls the power supply to provide the output voltage Vout2 to the load RL within half a cycle, and within the other half cycle, the capacitor Cs in the LC module provides the output voltage Vout2 to the load RL; when it is necessary to adjust the output voltage Vout2 to change the power supply to the load RL, the central control unit adjusts the resistance value of the feedback resistor Rf in the sampling module through the digital-to-analog conversion unit DAC, and correspondingly adjusts the magnitude of the feedback voltage Vfb2; in the feedback control module, the first comparator comp1 compares the feedback voltage Vfb2 with the first reference voltage Vref1, the second comparator comp2 compares the feedback voltage Vfb2 with the first threshold voltage Vth_1, and the third comparator comp3 compares the feedback voltage Vfb2 with the second threshold voltage Vth_2;

[0037] When the feedback voltage Vfb2 is greater than the first reference voltage Vref1, the first comparator comp1 outputs a corresponding negative feedback control signal. Under the action of the negative feedback control signal, the driving module drives the loop to adjust the magnitude of the output voltage Vout2.

[0038] When the feedback voltage Vfb2 is greater than the first threshold voltage Vth_1, the second comparator comp2 outputs a corresponding negative feedback control signal. Under the action of the negative feedback control signal, the driving module turns off other power-consuming circuits in the power supply architecture loop except the second comparison unit and the third comparison unit.

[0039] When the feedback voltage Vfb2 is greater than the second threshold voltage Vth_2, the control signal Vctrl output by the third comparator comp3 after being delayed by the delay unit controls the pull-down NMOS transistor NMOS1 to pull down, pulling down the feedback voltage Vfb2 to the reference voltage Vref, enabling the power supply architecture loop to quickly recover, and relying on the loop negative feedback to accelerate the output power jump adjustment; the reference voltage Vref is greater than the first reference voltage Vref1 and less than the first threshold voltage Vth_1.

[0040] Figure 4 It is an explanatory diagram of the action stages of the three comparators. Figure 5 It is the actual circuit simulation test result. As can be seen from the figure, after adding the control logic, the stabilization time after the output voltage Vout2 jumps has been reduced from the original 380 us to about 37 us; obviously, the present invention only needs to add a conventional comparator, a delay unit Td, a pull-down NMOS transistor NMOS1 for pull-down on the basis of the conventional DC-DC power supply architecture, and at the same time set the priority of the control signal Vctrl becoming high to be higher than the low-power mode enable signal to accelerate the output power jump adjustment, which can effectively solve the technical problem of the long setup time during the switching of the output voltage Vout1 in the existing DC-DC power supply architecture, can shorten the stabilization time after the output voltage Vout1 jumps, realize the fast switching of the output power, the implementation method is simple, and the chip structure is simpler.

Claims

1. A DC-DC power supply architecture capable of achieving rapid switching of output power, characterized in that: It includes a driving module Driver, a switching module, an LC module, a sampling module, and a feedback control module that are connected in sequence and form a loop. The switching module includes a PMOS power transistor and an NMOS power transistor connected in sequence. The sampling module includes a digital-to-analog conversion unit DAC, and a feedback resistor Rf and a gain resistor Rg connected in series; the feedback resistor Rf is a digitally adjustable resistor, and its resistance value control terminal is connected to the output terminal of the digital-to-analog conversion unit DAC. The feedback control module includes a first comparison unit, a second comparison unit, a first logic control unit Logic, and a pull-down unit. The output terminal of the first logic control unit Logic is connected to the input terminal of the driving module Driver to control the operation of the driving module Driver. The first comparison unit includes an error amplifier EA and a first comparator comp1; the positive input terminal of the error amplifier EA is connected to a first reference voltage Vref1, and its negative input terminal is connected to the connection point of the feedback resistor Rf and the gain resistor Rg; the positive input terminal of the first comparator comp1 is connected to the connection point of the feedback resistor Rf and the gain resistor Rg, its negative input terminal is connected to the output terminal of the error amplifier EA, and its output terminal is connected to one of the input terminals of the first logic control unit; the second comparison unit includes a second comparator comp2, an inverter, and a NOR gate; the positive input terminal of the second comparator comp2 is connected to the connection point of the feedback resistor Rf and the gain resistor Rg, its negative input terminal is connected to a first threshold voltage Vth_1, and its output terminal is connected to one of the input terminals of the NOR gate through the inverter; the other input terminal of the NOR gate is connected to a control signal Vctrl, and its output terminal is connected to the other input terminal of the first logic control unit. The pull-down unit includes a third comparator comp3, a delay unit Delay, and a pull-down NMOS transistor NMOS1; the positive input terminal of the third comparator comp3 is connected to the connection point of the feedback resistor Rf and the gain resistor Rg, its negative input terminal is connected to a second threshold voltage Vth_2, and its output terminal outputs a control signal Vctrl after being delayed by the delay unit; the control signal Vctrl is connected to the gate of the pull-down NMOS transistor NMOS1; the drain of the pull-down NMOS transistor NMOS1 is connected to the connection point of the feedback resistor Rf and the gain resistor Rg, and its source is connected to a reference voltage Vref. The first reference voltage Vref1 is a fixed value; the first threshold voltage Vth_1 is a fixed value; the second threshold voltage Vth_2 is a fixed value, and the second threshold voltage Vth_2 > the first threshold voltage Vth_1 > the reference voltage Vref > the first reference voltage Vref1.

2. The DC-DC power supply architecture capable of achieving rapid switching of output power according to claim 1, characterized in that: The reference voltage Vref = Vref1 + B, where B ranges from 5 to 20 mV.

3. The DC-DC power supply architecture capable of achieving rapid switching of output power according to claim 2, characterized in that: The value of B is 10 mV.

4. A control method for a DC-DC power supply architecture capable of achieving rapid switching of output power, characterized in that, It includes the following steps: The driving module controls the on / off of the switching module. The voltage output by the switching module passes through the LC module and then provides an output voltage Vout2 to the load RL. When it is necessary to adjust the output voltage Vout2 to change the power supply to the load RL, the central control unit adjusts the resistance value of the feedback resistor Rf in the sampling module through the digital-to-analog conversion unit DAC, and correspondingly adjusts the magnitude of the feedback voltage Vfb2; in the feedback control module, the first comparator comp1 compares the feedback voltage Vfb2 with the first reference voltage Vref1, the second comparator comp2 compares the feedback voltage Vfb2 with the first threshold voltage Vth_1, and the third comparator comp3 compares the feedback voltage Vfb2 with the second threshold voltage Vth_2; When the feedback voltage Vfb2 is greater than the first reference voltage Vref1 and less than the first threshold voltage Vth_1, the first comparator comp1 outputs a corresponding negative feedback control signal. Under the action of the negative feedback control signal, the driving module drives the loop to adjust the magnitude of the output voltage Vout2; When the feedback voltage Vfb2 is greater than the first threshold voltage Vth_1 and less than the second threshold voltage Vth_2, the first comparator comp1 outputs a low level; the second comparator comp2 outputs a low-power mode enabling signal. Under the action of the low-power mode enabling signal, the driving module turns off other power-consuming circuits in the power supply architecture loop except the second comparison unit and the third comparison unit; When the feedback voltage Vfb2 is greater than the second threshold voltage Vth_2, both the first comparator comp1 and the second comparator comp2 output a low level; the control signal Vctrl output by the third comparator comp3 becomes high. After being delayed by the delay unit, it controls the pull-down NMOS transistor NMOS1 to pull down, pulling down the feedback voltage Vfb2 to the reference voltage Vref, enabling the power supply architecture loop to quickly recover and relying on the loop negative feedback to accelerate the output power jump adjustment; the reference voltage Vref is greater than the first reference voltage Vref1 and less than the first threshold voltage Vth_1.

5. The control method for a DC-DC power supply architecture capable of achieving rapid switching of output power according to claim 4, characterized in that: The priority of the control signal Vctrl output by the third comparator comp3 becoming high is higher than that of the low-power mode enabling signal.

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