Analog-to-digital conversion device for providing digital values to a driver and camera module comprising the same

Abstract

The present disclosure relates to an analog-digital conversion apparatus and a camera module, the analog-digital conversion apparatus including: an analog-digital converter (ADC) included in an integrated circuit (IC) and configured to operate based on a sampling clock constituting a part of a plurality of clocks; and a driver included in the IC and configured to operate based on another part of the plurality of clocks, and to generate a driving signal based on a digital value output from the ADC. The ADC and the driver are synchronized with each other based on an interrupt request (Irq) of the IC.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of priority to Korean Patent Application No. 10-2020-0158699, filed with the Korean Intellectual Property Office on November 24, 2020, the entire disclosure of which is incorporated herein by reference for all purposes. Technical Field

[0003] The following description relates to an analog-to-digital converter for providing digital values ​​to a driver. Background Technology

[0004] Typically, electronic devices may include components such as a camera module, the position of which should be controlled, and a driver can control the position of the component by driving it. The driver may receive position and / or acceleration information of the component, and calculate, based on this information, a value for precisely driving the component according to control logic (e.g., optical image stabilization and / or autofocus control), and drive the component based on that value. Since the position and / or acceleration information of the component is collected as analog values, an analog-to-digital converter can convert the analog values ​​into digital values ​​and provide the digital values ​​to the driver.

[0005] As the optical magnification of the lenses in the camera module increases and the lens barrel of the lens module becomes longer, the detection range of the position and / or acceleration of the lens module may increase, and the number of sensors used for detecting position and / or acceleration may also increase. Therefore, the timing control of the analog-to-digital converter may become more complex, and the number of clocks used in the analog-to-digital converter may increase. Summary of the Invention

[0006] The summary portion of this invention is intended to provide a brief overview of the chosen inventive concepts, which will be further described in the detailed description portion below. This summary portion is not intended to identify key or essential features of the claimed subject matter, nor is it intended to help determine the scope of the claimed subject matter.

[0007] In a general sense, an analog-to-digital conversion device includes: an analog-to-digital converter (ADC) included in an integrated circuit (IC) and configured to operate based on a sampling clock that constitutes part of a plurality of clocks; and a driver included in the IC and configured to operate based on another part of the plurality of clocks, and generating a drive signal based on the digital value output from the ADC. The ADC and the driver are synchronized with each other based on interrupt requests (Irq) from the IC.

[0008] Irq can be the timer Irq of the IC.

[0009] The ADC can include an ADC modulator configured to convert the analog value into a digital value based on a sampling clock, and an ADC controller configured to determine whether the ADC is in an enabled state based on the Irq, and control the ADC modulator based on a time point at which the enabled state changes.

[0010] The ADC controller is further configured to control conversion timing of the ADC modulator based on a conversion start time signal having a unit analog-digital conversion period. A conversion start time of the conversion start time signal can be synchronized at the time point at which the enabled state changes.

[0011] The ADC can include an ADC modulator configured to convert the analog value into a digital value based on a sampling clock, and an ADC controller configured to control conversion timing of the ADC modulator based on a conversion start time signal having a unit analog-digital conversion period. A reference time point of the conversion start time signal can be determined according to a time point at which the ADC controller receives the Irq.

[0012] The ADC can include an ADC modulator configured to sequentially convert at least one analog value input from at least one channel into a digital value, and an ADC controller configured to generate a reset signal corresponding to conversion timing of the at least one analog value of the ADC modulator based on a conversion start time signal having a period in which the at least one analog value is converted into a digital value, and provide the reset signal to the ADC modulator.

[0013] The at least one channel can correspond to at least one Hall sensor.

[0014] The driver can be further configured to perform a PID control action based on the digital value, and generate the driving signal based on the PID control action. A period of the PID control action can be determined based on the other portion of the plurality of clocks, and the other portion of the clock can be associated with the Irq.

[0015] The driver can be further configured to generate a driving current corresponding to the driving signal based on the PID control action, and output the driving current to the voice coil motor.

[0016] The ADC can include a first ADC configured to convert a first analog value into a first digital value based on a first sampling clock of a sampling clock, and a second ADC configured to convert a second analog value into a second digital value based on a second sampling clock of the sampling clock. The first ADC and the second ADC can be synchronized with each other based on the Irq.

[0017] In another general aspect, an analog-to-digital conversion apparatus includes a first analog-to-digital converter (ADC) included in an integrated circuit (IC) and configured to convert a first analog value into a first digital value based on a first sampling clock that constitutes a portion of a plurality of clocks, and a second ADC included in the integrated circuit (IC) and configured to convert a second analog value into a second digital value based on a second sampling clock that constitutes another portion of the plurality of clocks. The first ADC and the second ADC are configured to be synchronized with each other based on an interrupt request (Irq) of the IC.

[0018] The Irq can be a timer Irq of the IC.

[0019] The first ADC can include a first ADC modulator configured to convert the first analog value into the first digital value based on the first sampling clock, and a first ADC controller configured to determine whether the first ADC controller is in a first enabled state based on the Irq, and configured to control the first ADC modulator based on a time point at which the first enabled state changes. The second ADC can include a second ADC modulator configured to convert the second analog value into the second digital value based on the second sampling clock, and a second ADC controller configured to determine whether the second ADC controller is in a second enabled state based on the Irq, and configured to control the second ADC modulator based on a time point at which the second enabled state changes.

[0020] The first ADC controller can be further configured to control a conversion timing of the first ADC modulator based on a first conversion start time signal having a first unit analog-to-digital conversion period. A conversion start time of the first conversion start time signal can be synchronized at the time point at which the first enabled state changes. The second ADC controller can be further configured to control a conversion timing of the second ADC modulator based on a second conversion start time signal having a second unit analog-to-digital conversion period. A conversion start time of the second conversion start time signal can be synchronized at the time point at which the second enabled state changes.

[0021] The first ADC can include a first ADC modulator configured to convert the first analog value into the first digital value based on the first sampling clock, and a first ADC controller configured to control a conversion timing of the first ADC modulator based on a first conversion start time signal having a first unit analog-to-digital conversion period. The second ADC can include a second ADC modulator configured to convert the second analog value into the second digital value based on the second sampling clock, and a second ADC controller configured to control a conversion timing of the second ADC modulator based on a second conversion start time signal having a second unit analog-to-digital conversion period. A reference time point of the first conversion start time signal can be determined according to a time point at which the first ADC controller receives the Irq. A reference time point of the second conversion start time signal can be determined according to a time point at which the second ADC controller receives the Irq.

[0022] The first ADC can include a first ADC modulator configured to sequentially convert at least one first analog value input from at least one first channel into a first digital value, and a first ADC controller configured to generate a first reset signal corresponding to a conversion timing of the at least one first analog value of the first ADC modulator based on a first conversion start time signal having a period in which the at least one first analog value is converted into the first digital value, and provide the first reset signal to the first ADC modulator. The second ADC can include a second ADC modulator configured to sequentially convert at least one second analog value input from at least one second channel into a second digital value, and a second ADC controller configured to generate a second reset signal corresponding to a conversion timing of the at least one second analog value of the second ADC modulator based on a second conversion start time signal having a period in which the at least one second analog value is converted into the second digital value, and provide the second reset signal to the second ADC modulator.

[0023] In another general aspect, a camera module includes a lens module, a sensor configured to detect a position of the lens module and generate an analog value based on the detected position of the lens module, and an integrated circuit (IC). The IC includes an analog-to-digital converter (ADC) configured to convert the analog value into a digital value based on a sampling clock that constitutes a part of a plurality of clocks, and a driver configured to operate based on another part of the plurality of clocks and generate a driving signal to move the lens module based on the digital value output from the ADC. The ADC and the driver are synchronized with each other based on an interrupt request (Irq) of the IC.

[0024] The Irq can be a timer Irq of the IC.

[0025] The ADC can be further configured to determine whether the ADC is in an enabled state based on the Irq. The ADC can be configured to control conversion of the analog value into the digital value based on a point in time at which the enabled state changes.

[0026] The driver can be further configured to perform a PID control action based on the digital value and generate the driving signal based on the PID control action. A period of the PID control action can be determined based on the other part of the plurality of clocks, and the other part of the clock can be associated with the Irq.

[0027] Other features and aspects will become apparent from the following specific description, drawings and appended claims. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figures 1A-1C FIG. 1 is a diagram illustrating various synchronization methods based on an interrupt request (Irq) of an analog-to-digital conversion device according to an embodiment.

[0029] Figure 1Dis a block diagram illustrating an optical image stabilization structure that can be included in an analog-digital conversion device according to an embodiment.

[0030] Figure 2A and Figure 2B is a timing diagram illustrating an optical image stabilization structure that can be included in an analog-digital conversion device according to an embodiment.

[0031] Figure 3 is a timing diagram illustrating synchronization of an enable state signal (ADC_EN) and a conversion start time signal (ADC_SOC) of an analog-digital conversion device according to an embodiment.

[0032] Figure 4 and Figure 5 is a timing diagram illustrating a point in time at which an enable state signal (ADC_EN) of an analog-digital conversion device is determined to change based on an Irq according to an embodiment.

[0033] Figure 6 is a timing diagram illustrating a point in time at which an Irq itself serves as a conversion start time signal (ADC_SOC) of an analog-digital conversion device according to an embodiment.

[0034] Figure 7A and Figure 7B is a block diagram illustrating synchronization between at least one first channel and at least one second channel of a first analog-digital conversion device and a second analog-digital conversion device according to an embodiment.

[0035] In all of the drawings and specific embodiments, like reference numerals refer to like elements. The drawings can not be to scale and the relative dimensions, proportions, and depiction of elements in the drawings can be exaggerated for clarity, illustration, and convenience. DETAILED DESCRIPTION

[0036] The following detailed description is provided to help the reader obtain a thorough understanding of the methods, devices, and / or systems described herein. However, various changes, modifications, and equivalents thereof will become readily apparent to those skilled in the art after reviewing the present disclosure. For example, the order in which operations are described is merely exemplary and is not intended to be limiting, unless otherwise specified. Such changes, modifications, and equivalents can be made in the apparatuses, compositions, and / or methods described herein, without departing from the scope of the present disclosure. In addition, it is possible to omit certain features from the device described herein, based on the particular implementation, in order to make the device more cost-effective and / or to achieve other goals.

[0037] The features described herein can be implemented in different forms and should not be construed as limited to the examples described herein. Rather, these examples are provided as illustrative of a number of possible implementations of the methods, devices, and / or systems described herein, in one form or another. In the following description, numerous specific details are set forth to provide examples of implementing the disclosed technology. One skilled in the relevant art, however, will recognize that the technology can be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. In other instances, well-known structures, materials, or operations are not shown or described in detail in order to avoid obscuring aspects of the technology.

[0038] Throughout the specification, where an element such as a layer, region, or substrate is described as being "on" or "connected to" or "coupled to" another element, it can be directly on, connected, or coupled to the other element, or one or more other elements can be interposed therebetween. Conversely, where an element such as a layer, region, or substrate is described as being "directly on," "directly connected to," or "directly coupled to" another element, then there are no intervening elements interposed therebetween. As used herein, a "portion" of an element can include the entire element or less than the entire element.

[0039] As used herein, the term "and / or" includes any one of the associated listed items, as well as any combination of any two or more of the associated listed items; likewise, "at least one of' includes any one of the associated listed items, as well as any combination of any two or more of the associated listed items.

[0040] Although terminology can be used in this document, such as "first," "second," and "third," such terminology is only used to distinguish one component, assembly, region, layer, or portion from another component, assembly, region, layer, or portion. More specifically, such terminology is not intended to denote a particular order of implementation or order of execution. Thus, examples mentioned herein with a first component, assembly, region, layer, or portion can also be referred to as a second component, assembly, region, layer, or portion, without departing from the teachings of the examples described herein.

[0041] Spatially relative terms, such as "on", "upper", "lower", "below", "above", and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. Such spatially relative terms can encompass different orientations of the device in use or operation, depending on the context in which it is used. For example, if the device in the figures is turned over, elements described as "on" or "upper" relative to other elements or features would then be oriented "below" or "lower" relative to the other elements or features. Accordingly, the spatially relative terminology herein is intended to encompass such relative terms as "above" and "below" when the device is in use or operation. The terms "above" and "below" are used to indicate the relative orientation of elements or features when the device is in an orientation in which the upper side is up and the lower side is down. The terms "above" and "below" are used to indicate the relative orientation of elements or features when the device is in an orientation in which the upper side is up and the lower side is down. The device can be oriented in other ways (rotated 90 degrees or at other orientations) and the spatially relative terms used herein are to be interpreted accordingly.

[0042] The terminology used herein is for the purpose of describing various examples only and is not intended to be limiting of the disclosure. As used herein, the articles "a", "an" and "the" are intended to include one or more items, unless the context clearly indicates otherwise. The terms "comprises", "comprising", "includes", "including" and "has" are intended to be inclusive and allow for

[0043] The features of the examples described herein can be combined in various ways without departing from the disclosure. Furthermore, although examples are described herein with reference to particular configurations, those skilled in the art will appreciate that other configurations are possible without departing from the scope of the disclosure.

[0044] In this document, the use of the term "may" with respect to examples using the term "may" means, for example, that at least one example includes the feature, but that not all examples have to include the feature. In other words, the use of the term "may" indicates that the feature is "optional".

[0045] Figures 1A-1C FIG. 1 is a diagram illustrating various synchronization methods based on an interrupt request (Irq) of an analog-digital conversion device according to an embodiment.

[0046] Referring to Figure 1A The analog-digital conversion device can include an analog-digital converter (ADC) 100a, and can further include a driver 220a.

[0047] The ADC 100a is included in an integrated circuit (IC), and can operate based on a sampling clock that constitutes a part of a plurality of clocks.

[0048] The driver 220a is included in the IC, and can generate a driving signal based on another portion of the plurality of clocks and based on a digital value output from the ADC 100a.

[0049] Since different clock groups are provided to the ADC 100a and the driver 220a, respectively, the sampling clock of the ADC 100a and the clock of the driver 220a can be reduced in influence on each other. Accordingly, the driver 220a and the ADC 100a can have reduced noise, while the ADC 100a can have high resolution in accordance with the reduced noise. Further, the timing configuration of the ADC 100a can be independent of the timing configuration of the driver 220a, and the ADC 100a can be more fine or accurate.

[0050] The ADC 100a and the driver 220a can be synchronized with each other based on an interrupt request (Irq) of the IC. In this regard, even when the ADC 100a and the driver 220a operate based on different clock groups, the timing control for the ADC 100a and the driver 220a can be more fine or accurate. Accordingly, the performance (e.g., signal-to-noise ratio, conversion speed, resolution, power consumption, reliability, etc.) of the ADC 100a can be further improved.

[0051] The ADC 100a can include a first ADC (upper half of 100a) and a second ADC (lower half of 100a).

[0052] The first ADC (upper half of 100a) is included in the IC, and can convert a first analog value into a first digital value (upper digital n-bit) provided to the driver 220a based on a first sampling clock (upper sampling clock) as a portion of the plurality of clocks, while the second ADC (lower half of 100a) is included in the IC, and can convert a second analog value into a second digital value (lower digital n-bit) provided to the driver 220a based on a second sampling clock (lower sampling clock) as a portion of the plurality of clocks.

[0053] That is, the first ADC and the second ADC (upper half / lower half of 100a) can be configured in parallel with each other. In other examples, the ADC 100a can further include at least one additional ADC configured in parallel with the first ADC and the second ADC (upper half / lower half of 100a).

[0054] Since the different first and second sampling clocks (up-sampling clock / down-sampling clock) are configured to correspond to the first and second ADCs (upper half / lower half of 100a) respectively, the first and second sampling clocks (up-sampling clock / down-sampling clock) can reduce the influence on each other. Accordingly, the first and second ADCs (upper half / lower half of 100a) can have reduced noise and can have high resolution depending on the reduced noise. In addition, the timing configuration of the first and second ADCs (upper half / lower half of 100a) can be more refined and / or accurate.

[0055] The first and second ADCs (upper half / lower half of 100a) can be synchronized with each other based on an interrupt request (Irq) of the IC. Accordingly, even when the first and second ADCs (upper half / lower half of 100a) operate based on the first and second sampling clocks (up-sampling clock / down-sampling clock) different from each other, the timing control of the first and second ADCs (upper half / lower half of 100a) can be more complex or accurate. In this regard, the performance (e.g., signal-to-noise ratio, conversion speed, resolution, power consumption, reliability, etc.) of the ADC 100a can be further improved.

[0056] For example, the Irq can be an Irq of a timer 130 of the IC. The timer 130 can be provided in the process of designing and implementing the IC, and the Irq configuration of the timer 130 can be appropriately handled by a user.

[0057] For example, the first and second ADCs (upper half / lower half of 100a) can include first and second ADC modulators (upper side / lower side 110) respectively, and can include first and second ADC controllers (upper half / lower half of 120) respectively.

[0058] The first and second ADC modulators (upper side / lower side 110) can convert first and second analog values into first and second digital values (upper digital n-bit / lower digital n-bit) based on the first and second sampling clocks (up-sampling clock / down-sampling clock) respectively. The analog-to-digital conversion method of the first and second ADC modulators (upper side / lower side 110) is not limited to a sigma-delta method, and can be, for example, a successive approximation method or a method in which each bit is arranged in parallel. These methods can also operate based on a sampling clock.

[0059] For example, the first and second ADCs (upper half / lower half of 100a) can further include first and second decimation controllers (upper side / lower side 115), and can perform decimation filtering on values according to a sigma-delta modulation.

[0060] The enable state of the first and second ADC controllers (upper / lower half of 120) is determined based on the Irq of the timer 130, and the first and second ADC modulators (upper / lower side 110) can control based on the time point at which the enable state changes.

[0061] For example, the first and second ADC controllers (upper / lower half of 120) can include first and second CDCs (upper / lower side 121), respectively, and / or can include first and second mean and amplitude stop filters (upper / lower side 122), respectively. The first and second CDCs (upper / lower side 121) can control the timing and / or delay of the first and second ADC modulators (upper / lower side 110), respectively, and the first and second mean and amplitude stop filters (upper / lower side 122) can control the order or combination of digital values of the respective channels (CH1, CHN, CH1', and CHN').

[0062] For example, the first and second ADCs (upper / lower half of 100a) can further include first and second registers (upper / lower side 125), respectively. The first and second registers (upper / lower side 125) can sequentially store the digital values, and the driver 220a can sequentially retrieve the stored digital values.

[0063] For example, the driver 220a can perform a proportional-integral-derivative (PID) control action based on the first and second digital values (high digital n-bit / low digital n-bit) and generate a driving signal based on the PID control action.

[0064] The period of the PID control action can be determined based on other portions of the plurality of clocks (e.g., a master clock of the IC), which are associated with the Irq of the timer 130.

[0065] The driver 220a can generate a driving current corresponding to the driving signal based on the PID control action and output the driving current to the voice coil motor 230.

[0066] The lens module 210 can include a magnet (e.g., a permanent magnet, steel, etc.), and the magnet can provide a Lorentz force action / reaction to the lens module 210 based on the driving current flowing through the voice coil motor 230. Accordingly, the lens module 210 can move based on the driving signal and / or the driving current of the driver 220a.

[0067] The at least one Hall sensor 300 can detect the position of the lens module 210. As the number of Hall sensors 300 increases, the position detection range and / or the position detection resolution of the lens module 210 can be further increased. For example, the at least one Hall sensor 300 can be disposed in a coil-shaped aperture of the voice coil motor 230, and an IC can also be disposed in the aperture.

[0068] The IC can include at least one amplifier 310, and the at least one amplifier 310 can amplify a voltage difference between a positive terminal INP and a negative terminal INN of the at least one Hall sensor 300.

[0069] From the perspective of the ADC 100a, the at least one amplifier 310 can be at least one channel (CH1, CHN, CH1', and CHN'). The ADC 100a can convert at least one analog value of the at least one channel (CH1, CHN, CH1', and CHN') into at least one digital value (digital n bits).

[0070] Referring to Figure 1B , the analog-to-digital converter (ADC) 100b can include the driver 220b, and the driver 220b can include the PID controller 221b.

[0071] For example, the driver 220b can generate Irq, the PID controller 221b can be associated with the Irq, and the first and second ADC controllers (upper half / lower half of 120) can be provided with the Irq.

[0072] Referring to Figure 1C , the driver 220c can include the PID controller 221c, the digital-to-analog converter (iDAC) 222c, and the VCM actuator 223c, and can include the timer 130.

[0073] The timer 130 can provide the Irq to the PID controller 221c within the driver 220c, and can provide the Irq to the ADC 100c outside the driver 220c.

[0074] Figure 1D is a block diagram illustrating an optical image stabilization structure that can be included in an analog-digital conversion apparatus according to an embodiment.

[0075] When the lens module moves in another direction opposite to one direction, the optical image stabilization device or system can move the lens module or an image sensor on which light is incident through the lens module in the one direction, so that the sharpness of an image obtained from the image sensor is secured even though the lens module moves.

[0076] Referring to Figure 1DWhen the lens module moves due to an external environment (e.g., a camera user hand shake), the gyro sensor 400 can detect acceleration, and the integrator 410 integrates the acceleration and converts the acceleration into velocity. The filter 420 can control a DC offset and / or high frequency (e.g., a frequency exceeding 20 Hz) noise of the gyro sensor 400 and / or the integrator 410, and provide output information to the summer 350.

[0077] The analog-to-digital converter (ADC) 100d can provide negative feedback information corresponding to a position of the lens module 210 to the summer 350, and the PID controller 221d can create information of a Lorentz force magnitude to be applied to the lens module 210 by performing PID control based on a summation result of the summer 350. The digital-to-analog converter 222d can convert the information into an analog value, and the VCM actuator 223d can generate a driving current corresponding to the analog value, and the lens module 210 can move according to the driving current.

[0078] According to an embodiment, the analog-to-digital conversion apparatus can be applied to autofocus control of the lens module 210, and the ADC 100d and the driver (corresponding to the PID controller 221d) can be applied to driving and feedback of the autofocus control structure.

[0079] As the optical magnification of the lens of the lens module 210 increases, the lens barrel of the lens module 210 can become longer, and the number of the Hall sensors 300 can increase. As the number of the Hall sensors 300 increases, the timing control of the ADC 100d can become more complex, and the number of clocks used in the ADC 100d can increase.

[0080] According to an exemplary embodiment, the analog-to-digital conversion apparatus can synchronize a plurality of different clocks based on an Irq of an IC, and thus can more effectively handle an increased size or improved performance of the lens module 210 and / or the Hall sensor 300.

[0081] Further, according to an embodiment, the analog-to-digital conversion apparatus can perform a synchronization action based on an Irq of one IC, and the one IC can be more effectively disposed in an aperture of a voice coil motor. Thus, the overall size of a camera module including the analog-to-digital conversion apparatus and the lens module can be effectively reduced.

[0082] Figure 2A and Figure 2B is a timing diagram illustrating an optical image stabilization structure that can be included in the analog-to-digital conversion apparatus according to an embodiment.

[0083] Referring to Figure 2AA sampling clock (ADC sampling clock) corresponding to the ADC and a main clock (MCLK) of the IC can be different from each other. When the sampling clock (ADC sampling clock) is configured to correspond to the ADC, the main clock (MCLK) can be configured to correspond to the driver. When the sampling clock (ADC sampling clock) is configured to correspond to the first ADC, the main clock (MCLK) can be configured to correspond to the second ADC. A frequency difference and / or a phase difference between the ADC sampling clock and the main clock (MCLK) can be determined differently according to the design thereof.

[0084] Referring to Figure 2A When a value of an enable state signal (ADC_EN) is high, the ADC controller can operate in an enabled state, and when the value of the enable state signal (ADC_EN) is low, the ADC controller can not operate. The ADC controller can convert a unit analog value into a unit digital value at each sampling period of a conversion start time signal (ADC SOC). The sampling period can correspond to a total time of converting analog values of each of a plurality of channels (CH0, CH1, and CHN) into digital values. The plurality of channels (CH0, CH1, and CHN) can correspond to a plurality of Hall sensors. As the number of the plurality of channels (CH0, CH1, and CHN) increases, the sampling period can be longer, and thus the sampling period can be appropriately determined according to a required time, resolution, power consumption, etc.

[0085] The ADC controller can convert an analog value of one of the plurality of channels (CH0, CH1, and CHN) into a digital value at each period of a reset signal (Reset), and the number of the reset signal (Reset) corresponding to the sampling period can correspond to the number of the plurality of channels (CH0, CH1, and CHN). The ADC controller can provide the reset signal (Reset) to the ADC modulator.

[0086] The reset signal (Reset) can have a reset hold at a time after converting an analog value of a last channel (CHN) of the plurality of channels (CH0, CH1, and CHN) into a digital value, and the reset hold can be associated with a value of the conversion start time signal (ADC SOC).

[0087] Referring to Figure 2B The ADC modulator can output an output value (SDM_OUT) in an Nth period of the reset signal (Reset). Figures 1A-1C The decimation controller shown in FIG. 11 can filter the output value (SDM_OUT) of the ADC modulator to output an N-bit digital value (Decimation Filter OUT).

[0088] The N-bit digital value (Decimation Filter OUT) can be stored in a channel corresponding to Figures 1A-1CThe corresponding memory is located in the register shown. The channel correspondence in the register can be a channel sequence, and the channel sequence can be provided to the ADC controller and / or ADC modulator.

[0089] Figure 3 This is a timing diagram showing the synchronization of the enable state signal (ADC_EN) and the conversion start time signal (ADC SOC) of the analog-to-digital converter according to an embodiment.

[0090] refer to Figure 3 The enable state signal (ADC_EN) and the conversion start time signal (ADC SOC) can be associated, and the driver's PID timing signal (PID cycle) can be associated with the IC's timer (TIMER0). The conversion start time can be synchronized at the time the enable state changes. Alternatively, the PID timing signal (PID cycle) can be replaced by the conversion start time signal of the second ADC, and the conversion start time signal (ADC SOC) can correspond to the first ADC.

[0091] The period of the PID timing signal (PID cycle) and the period of the conversion start time signal (ADC SOC) can be correlated with each other, which can be based on the Irq of the IC's timer (TIMER 0). Since the timing of providing Irq can be determined by the user, the timing of ADC operation can be flexibly determined.

[0092] Figure 4 and Figure 5 This is a timing diagram showing the timing of the change of the enable state signal (ADC_EN) of the analog-to-digital converter based on Irq according to an embodiment.

[0093] refer to Figure 4 The ADC period (ADC cycle) corresponding to the conversion start time signal can be synchronized with the driver's PID timing signal (PID cycle) and / or the IC's timer (TIMER 0) via Irq sync. Alternatively, the PID timing signal (PID cycle) can be replaced by the conversion start time signal of the second ADC, and the conversion start time signal (ADC SOC) can correspond to the first ADC.

[0094] For example, the driver's PID timing signal (PID period) and / or the IC's timer (TIMER0) can be communicated via Irq. Figures 1A-1C The CDC's delay counter signal is synchronized. The ADC can convert a unit analog value into a unit digital value in each sampling period, starting from a time point determined by a control delay based on the delay counter signal.

[0095] refer to Figure 5The timer (TIMER 1) associated with the driver's PID timing signal (PID period) and / or the IC's timer (TIMER 0) can be synchronized with the enable status signal (ADC_EN) via Irq. Alternatively, the PID timing signal (PID period) can be replaced by the conversion start time signal of the second ADC, and the conversion start time signal (ADC SOC) can correspond to the first ADC.

[0096] Since the enable state signal (ADC_EN) and the conversion start time signal (ADC SOC) can be synchronized with each other, the ADC controller can control the ADC modulator based on the time point when the enable state signal (ADC_EN) changes.

[0097] Figure 6 This is a timing diagram showing the timing points at which Irq itself is used as the conversion start time signal (ADC SOC) of the analog-to-digital converter according to the embodiment.

[0098] refer to Figure 6 The IC's timer (TIMER 0) and / or driver's PID cycle signal and conversion start time signal (ADC SOC) can be synchronized with the master clock (MCLK) via Irq. Alternatively, the PID cycle signal can be replaced by the conversion start time signal of the second ADC, and the conversion start time signal (ADC SOC) can correspond to the first ADC.

[0099] In other words, the reference time point of the conversion start time signal (ADC SOC) can be determined based on the time point at which the ADC controller receives Irq, and Irq can directly trigger the conversion start time signal (ADC SOC). Therefore, the ADC can be smoothly synchronized.

[0100] Figure 7A and Figure 7B This is a block diagram illustrating the synchronization between at least one first channel and at least one second channel of a first analog-to-digital converter and a second analog-to-digital converter according to an embodiment.

[0101] refer to Figure 7A and Figure 7B The ADC controller channel sequencer 1 and the ADC controller channel sequencer 2 may be shared in at least a portion of the register, the ADC controller, and the ADC modulator, respectively.

[0102] Since ADC controller channel sequencers 1 and 2 can be independent of each other, the order relationship of multiple channels of ADC controller channel sequencers 1 and 2 can be appropriately determined according to their design.

[0103] As described above, according to the embodiments disclosed herein, the analog-to-digital conversion device can reduce noise and achieve high resolution based on the reduced noise. Furthermore, because the timing configuration / control can be more refined and / or precise, overall performance (e.g., signal-to-noise ratio, conversion speed, resolution, power consumption, reliability, etc.) can be further improved.

[0104] Figure 1 to Figure 7BThe ADCs 100a to 100d, decimation controller 115, ADC controller 120, CDC 121, mean and amplitude stop filters 122, register 125, timer 130, drivers 220a to 220c, PID controllers 221b to 221d, iDACs 222c and 222d, VCM actuators 223c and 223d, summer 350, integrator 410, and LPF / HPF filter 420 that perform the operations described in this application are implemented by hardware components configured to perform the operations performed by hardware components described in this application. Where appropriate, examples of hardware components that can be used to perform the operations described in this application include controllers, sensors, generators, drivers, memories, comparators, arithmetic logic units, adders, subtractors, multipliers, dividers, integrators, and any other electronic components configured to perform the operations described in this application. In other examples, one or more hardware components performing the operations described in this application are implemented by computing hardware, such as by one or more processors or computers. The processor or computer may be implemented by one or more processing elements (such as logic gate arrays, controllers, and arithmetic logic units), digital signal processors, microcomputers, programmable logic controllers, field-programmable gate arrays, programmable logic arrays, microprocessors, or any other means or combination of means configured to respond to and execute instructions in a defined manner to achieve desired results. In one example, the processor or computer includes one or more memories storing, or connected to, the instructions or software executed by the processor or computer. The hardware components implemented by the processor or computer can execute instructions or software, such as an operating system (OS) and one or more software applications running on the OS, to perform the operations described in this application. The hardware components may also access, manipulate, process, create, and store data in response to executing instructions or software. For simplicity, the singular terms "processor" or "computer" are used to describe the examples described in this application. However, in other examples, multiple processors or computers may be used, or a processor or computer may include multiple processing elements or multiple types of processing elements, or both. For example, a single hardware component or two or more hardware components may be implemented by a single processor or two or more processors or a processor and a controller. One or more hardware components may be implemented by one or more processors or a processor and a controller, and one or more other hardware components may be implemented by one or more other processors or another processor and another controller. One or more processors or a processor and a controller may implement a single hardware component or two or more hardware components.Hardware components may have any one or more different processing configurations, examples of which include a single processor, a standalone processor, a parallel processor, a single instruction single data (SISD) multiprocessing, a single instruction multiple data (SIMD) multiprocessing, multiple instruction single data (MISD) multiprocessing, and multiple instruction multiple data (MIMD) multiprocessing.

[0105] Figure 1 to Figure 7B The methods for performing the operations described in this application are executed by computing hardware, such as by one or more processors or computers executing instructions or software to perform the operations described in this application. For example, a single operation or two or more operations may be performed by a single processor, two or more processors, or a processor and a controller. One or more operations may be performed by one or more processors or a processor and a controller, and one or more other operations may be performed by one or more other processors or another processor and another controller. One or more processors or a processor and a controller may perform a single operation or two or more operations.

[0106] Instructions or software that control computing hardware (e.g., one or more processors or computers) to implement hardware components and perform the methods described above can be written as computer programs, code segments, instructions, or any combination thereof to individually or collectively instruct or configure one or more processors or computers to operate as a machine or special-purpose computer to perform operations performed by the hardware components and methods described above. In one example, the instructions or software include machine code that is directly executed by one or more processors or computers, such as machine code generated by a compiler. In another example, the instructions or software include high-level code that is executed by one or more processors or a computer using an interpreter. The instructions or software can be written in any programming language based on the block diagrams and flowcharts shown in the accompanying drawings and the corresponding descriptions in the specification, which disclose algorithms for performing operations performed by the hardware components and methods described above.

[0107] Instructions or software that control computing hardware (e.g., one or more processors or computers) to implement hardware components and perform the methods described above, along with any associated data, data files, and data structures, may be recorded, stored, or fixed in or on one or more non-transitory computer-readable storage media. Examples of non-transitory computer-readable storage media include read-only memory (ROM), random access memory (RAM), flash memory, CD-ROM, CD-R, CD+R, CD-RW, CD+RW, DVD-ROM, DVD-R, DVD+R, DVD-RW, DVD+RW, DVD-RAM, BD-ROM, BD-R, BD-R LTH, BD-RE, magnetic tape, floppy disk, magneto-optical data storage device, optical data storage device, hard disk, solid-state drive, and any other means configured to store instructions or software and any associated data, data files, and data structures in a non-transitory manner and to provide the instructions or software and any associated data, data files, and data structures to one or more processors or computers such that one or more processors or computers can execute the instructions. In one example, instructions or software, along with any associated data, data files, and data structures, are distributed across a network-connected computer system, such that the instructions or software, along with any associated data, data files, and data structures, are stored, accessed, and executed in a distributed manner by one or more processors or computers.

[0108] While this disclosure includes specific examples, it will be apparent upon understanding the disclosure of this application that various changes in form and detail may be made to these examples without departing from the spirit and scope of the appended claims and their equivalents. The examples described herein should be interpreted in a descriptive sense only and not for limiting purposes. The description of features or aspects in each example should be considered applicable to similar features or aspects in other examples. Suitable results may also be obtained if the described techniques are performed in a different order, and / or if components in the described system, architecture, apparatus, or circuit are combined in different ways and / or replaced or supplemented with other components or their equivalents. Therefore, the scope of this disclosure is not limited by specific embodiments but by the claims and their equivalents, and all variations within the scope of the claims and their equivalents should be understood to be included in this disclosure.

Claims

1. An analog-to-digital converter, comprising: An analog-to-digital converter, included in an integrated circuit and configured to operate based on a sampling clock that is part of a plurality of clocks; as well as A driver, included in the integrated circuit and configured to operate based on another portion of the plurality of clocks, and to generate a drive signal based on the digital value output from the analog-to-digital converter. The analog-to-digital converter and the driver are synchronized with each other based on the interrupt request of the integrated circuit.

2. The analog-to-digital converter according to claim 1, wherein, The interrupt request is a timer interrupt request from the integrated circuit.

3. The analog-to-digital converter according to claim 1, wherein, The analog-to-digital converter includes: An analog-to-digital converter modulator configured to convert an analog value into a digital value based on the sampling clock; and An analog-to-digital converter controller is configured to determine whether the analog-to-digital converter is in an enabled state based on the interrupt request, and to control the analog-to-digital converter modulator based on the time point at which the enabled state changes.

4. The analog-to-digital converter according to claim 3, wherein, The analog-to-digital converter controller is further configured to control the conversion timing of the analog-to-digital converter modulator based on a conversion start time signal having a unit analog-to-digital conversion cycle, and The conversion start time indicated by the conversion start time signal is synchronized at the time when the enable state changes.

5. The analog-to-digital converter according to claim 1, wherein, The analog-to-digital converter includes: An analog-to-digital converter modulator configured to convert an analog value into a digital value based on the sampling clock; and An analog-to-digital converter controller is configured to control the conversion timing of the analog-to-digital converter modulator based on a conversion start time signal having a unit analog-to-digital conversion cycle. Specifically, the reference time point for determining the conversion start time signal is based on the time point at which the analog-to-digital converter controller receives the interrupt request.

6. The analog-to-digital converter according to claim 1, wherein, The analog-to-digital converter includes: An analog-to-digital converter modulator configured to sequentially convert at least one analog value input from at least one channel into the digital value; and An analog-to-digital converter controller is configured to generate a reset signal corresponding to the conversion timing of at least one analog value of the analog-to-digital converter modulator based on a conversion start time signal having a period for converting the at least one analog value to the digital value, and to provide the reset signal to the analog-to-digital converter modulator.

7. The analog-to-digital converter according to claim 6, wherein, The at least one channel corresponds to at least one Hall sensor.

8. The analog-to-digital converter according to claim 1, wherein, The driver is further configured to perform proportional-integral-derivative (PID) control actions based on the digital values, and to generate the drive signal based on the PID control actions. The period of the proportional-integral-derivative control action is determined based on other portions of the plurality of clocks, and the other portions of the plurality of clocks are associated with the interrupt request.

9. The analog-to-digital converter according to claim 8, wherein, The driver is also configured to generate a drive current corresponding to the drive signal based on the proportional-integral-derivative control action, and to output the drive current to the voice coil motor.

10. The analog-to-digital converter according to claim 1, wherein, The analog-to-digital converter includes: A first analog-to-digital converter, configured to convert a first analog value into a first digital value based on a first sampling clock of the sampling clock; and A second analog-to-digital converter, configured to convert a second analog value into a second digital value based on a second sampling clock of the sampling clock; and The first analog-to-digital converter and the second analog-to-digital converter synchronize with each other based on the interrupt request.

11. An analog-to-digital converter, comprising: A first analog-to-digital converter is included in an integrated circuit and configured to convert a first analog value into a first digital value based on a first sampling clock that constitutes a plurality of clocks; as well as A second analog-to-digital converter, included in an integrated circuit, is configured to convert a second analog value into a second digital value based on a second sampling clock that constitutes another part of the plurality of clocks. The first analog-to-digital converter and the second analog-to-digital converter are configured to synchronize with each other based on the interrupt request of the integrated circuit.

12. The analog-to-digital converter according to claim 11, wherein, The interrupt request is a timer interrupt request from the integrated circuit.

13. The analog-to-digital converter according to claim 11, wherein, The first analog-to-digital converter includes: A first analog-to-digital converter modulator, configured to convert the first analog value into the first digital value based on the first sampling clock; and A first analog-to-digital converter (ADC) controller is configured to determine whether the first ADC controller is in a first enabled state based on the interrupt request, and is configured to control the first ADC modulator based on the time point at which the first enabled state changes. The second analog-to-digital converter includes: A second analog-to-digital converter modulator, configured to convert the second analog value into the second digital value based on the second sampling clock; and The second analog-to-digital converter controller determines whether the second analog-to-digital converter controller is in a second enabled state based on the interrupt request, and is configured to control the second analog-to-digital converter modulator based on the time point when the second enabled state changes.

14. The analog-to-digital converter according to claim 13, wherein, The first analog-to-digital converter controller is further configured to control the conversion timing of the first analog-to-digital converter modulator based on a first conversion start time signal having a first unit analog-to-digital conversion cycle. The conversion start time indicated by the first conversion start time signal is synchronized at the time when the first enable state changes. The second analog-to-digital converter controller is further configured to control the conversion timing of the second analog-to-digital converter modulator based on a second conversion start time signal having a second unit analog-to-digital conversion cycle, and The transition start time indicated by the second transition start time signal is synchronized at the time when the second enable state changes.

15. The analog-to-digital converter according to claim 11, wherein, The first analog-to-digital converter includes: A first analog-to-digital converter modulator, configured to convert the first analog value into the first digital value based on the first sampling clock; and A first analog-to-digital converter controller is configured to control the conversion timing of the first analog-to-digital converter modulator based on a first conversion start time signal having a first unit analog-to-digital conversion cycle. The second analog-to-digital converter includes: A second analog-to-digital converter modulator, configured to convert the second analog value into the second digital value based on the second sampling clock; and The second analog-to-digital converter controller is configured to control the conversion timing of the second analog-to-digital converter modulator based on a second conversion start time signal having a second unit analog-to-digital conversion cycle. Specifically, the reference time point for determining the first conversion start time signal is determined based on the time point at which the first analog-to-digital converter controller receives the interrupt request, and Specifically, the reference time point for determining the second conversion start time signal is determined based on the time point at which the second analog-to-digital converter controller receives the interrupt request.

16. The analog-to-digital converter according to claim 11, wherein, The first analog-to-digital converter includes: A first analog-to-digital converter modulator is configured to sequentially convert at least one first analog value input from at least one first channel into the first digital value; and A first analog-to-digital converter controller is configured to generate a first reset signal corresponding to the conversion timing of at least one first analog value of the first analog converter modulator based on a first conversion start time signal having a period for converting the at least one first analog value to the first digital value, and to provide the first reset signal to the first analog-to-digital converter modulator. The second analog-to-digital converter includes: A second analog-to-digital converter modulator is configured to sequentially convert at least one second analog value input from at least one second channel into the second digital value; and The second analog-to-digital converter controller is configured to generate a second reset signal corresponding to the conversion timing of at least one second analog value of the second analog converter modulator based on a second conversion start time signal having a period for converting the at least one second analog value to the second digital value, and to provide the second reset signal to the second analog-to-digital converter modulator.

17. A camera module, comprising: Lens module; A sensor is configured to detect the position of the lens module and generate analog values ​​based on the detected position of the lens module; as well as Integrated circuits, including: An analog-to-digital converter configured to convert the analog value into a digital value based on a sampling clock that constitutes part of a plurality of clocks; and The driver is configured to operate based on another portion of the plurality of clocks and to generate a drive signal based on the digital value output from the analog-to-digital converter to move the lens module. The analog-to-digital converter and the driver are synchronized with each other based on the interrupt request of the integrated circuit.

18. The camera module according to claim 17, wherein, The interrupt request is a timer interrupt request from the integrated circuit.

19. The camera module according to claim 17, wherein, The analog-to-digital converter is also configured to determine whether it is in an enabled state based on the interrupt request, and The analog-to-digital converter is configured to control the conversion of the analog value to the digital value based on the time point at which the enable state changes.

20. The camera module according to claim 17, wherein, The driver is further configured to perform proportional-integral-derivative (PID) control actions based on the digital values, and to generate the drive signal based on the PID control actions. The period of the proportional-integral-derivative control action is determined based on other portions of the plurality of clocks, and the other portions of the plurality of clocks are associated with the interrupt request.

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