Delta sigma type analog / digital converter and analog / digital conversion system

Abstract

A delta sigma type ADC (1) is provided with a quantizer (30) operating at a prescribed sampling frequency (fs), an FIR filter (40) connected to the quantizer (30), and a DAC (50). A feedback path for the quantizer (30) is structured by the FIR filter (40) and the DAC (50). A reference signal for the DAC (50) is supplied from a reference signal source (60) chopping at a frequency lower than the prescribed sampling frequency (fs).

Description

Delta-sigma type analog-to-digital converter and analog-to-digital conversion system

[0001] This disclosure relates to a delta-sigma type analog-to-digital converter and an analog-to-digital conversion system.

[0002] Delta-sigma modulators are widely used in the field of battery management systems, but aging fluctuations in the reference voltage are undesirable as they result in gain variations in the delta-sigma modulator, so a method to suppress aging fluctuations in the reference voltage is needed. In recent years, electrochemical impedance spectroscopy (EIS) has been proposed to estimate the degradation state of lithium-ion secondary batteries, but this requires measurements in the low-frequency range (e.g., 1 mHz to 1 Hz), and the measurement accuracy may deteriorate due to fluctuations caused by flicker noise in the reference voltage.

[0003] To suppress aging variations and low-frequency flicker noise, chopping the reference voltage is a possible approach. Chopping the reference voltage reduces manufacturing variations and suppresses aging variations. At the same time, flicker noise is also reduced, improving measurement accuracy, especially in the low-frequency range.

[0004] However, if the reference voltage supplied to the delta-sigma modulator is chopped, the quantization noise is intermodulated at the chopping frequency, degrading the signal-to-noise ratio.

[0005] In response to this, a method has been proposed to prevent the deterioration of the signal-to-noise ratio by controlling the chopping frequency of the reference voltage according to the output of the delta-sigma modulator, in order to prevent intermodulation due to the chopping frequency (see Patent Document 1).

[0006] Special Publication No. 2008-501279

[0007] However, in the technology disclosed in Patent Document 1, the output of the reference voltage changes according to the output of the delta-sigma modulator. Therefore, the reference voltage cannot be shared among multiple delta-sigma modulators used in fields such as image sensors or battery management systems, which leads to the problem of increased area and power consumption.

[0008] Therefore, this disclosure provides a delta-sigma modulator and the like that can share a reference voltage among multiple delta-sigma modulators and prevent intermodulation by chopping of the reference voltage.

[0009] The delta-sigma type analog-to-digital converter according to this disclosure is a delta-sigma type analog-to-digital converter comprising: a quantizer operating at a predetermined sampling frequency; an FIR filter connected to the quantizer; and a digital-to-analog converter, wherein the FIR filter and the digital-to-analog converter constitute a feedback path to the quantizer, and the reference signal of the digital-to-analog converter is supplied from a reference signal source that performs chopping at a frequency lower than the predetermined sampling frequency.

[0010] The analog-to-digital conversion system according to this disclosure comprises a plurality of delta-sigma type analog-to-digital converters, and is characterized in that the reference signals of each of the plurality of delta-sigma type analog-to-digital converters are supplied from a single reference signal source that performs chopping at a frequency lower than a predetermined sampling frequency.

[0011] These comprehensive or specific embodiments may be implemented as systems, methods, or integrated circuits, or as any combination of systems, methods, or integrated circuits.

[0012] According to one aspect of this disclosure, a delta-sigma type analog-to-digital converter can be shared among multiple delta-sigma modulators, and intermodulation due to chopping of the reference voltage can be prevented.

[0013] This is a configuration diagram showing an example of a delta-sigma type analog-to-digital converter according to Embodiment 1. This is a graph showing the frequency characteristics of the chopper clock and the attenuation characteristics of the FIR filter. This is a configuration diagram showing an example of a delta-sigma type analog-to-digital converter according to a modified example of Embodiment 1. This is a diagram for explaining the FIR filter. This is a diagram for explaining the FIR filter. This is a configuration diagram showing an example of a reference signal source. This is a configuration diagram showing an example of a reference signal source. This is a configuration diagram showing an example of a reference signal source. This is a configuration diagram showing a specific example of a bandgap reference circuit. This is a configuration diagram of a delta-sigma type analog-to-digital converter according to a modified example of Embodiment 1, when N=4. This is a graph showing the frequency characteristics of the chopper clock in the modified example of Embodiment 1 when N=4 and the sampling frequency is 1MHz. This is a graph showing the attenuation characteristics of the FIR filter in the modified example of Embodiment 1 when N=4 and the sampling frequency is 1MHz. This is a configuration diagram showing an example of an adder, an integrator and chopping circuit in a loop filter, and a DAC. This is a timing chart of each operating signal of the circuit in Figure 9A. This is a truth table of the switches of the DAC in Figure 9A. This is a configuration diagram showing an example of an adder, an integrator and chopping circuit in a loop filter, and another example of a DAC. This is the truth table for the switches of the DAC in Figure 10A. This is a configuration diagram showing an example of a delta-sigma type analog-to-digital converter according to Embodiment 2. This is a diagram to explain the quantizer when quantized with multiple bits (e.g., 2 bits (4 values)). This is a table showing the output codes corresponding to the 4 values. This is a diagram to explain the DAC and FIR filter when quantized with 2 bits. This is a configuration diagram showing an example of an adder, an integrator and chopping circuit in a loop filter, and a DAC when quantized with 2 bits. This is a diagram to explain the DEM control circuit and DEM circuit when quantized with 2 bits. This is a DEM rotation table. This is a diagram to explain DEM control using DWA (Data Weighted Averageing). This is a configuration diagram showing an example of a delta-sigma type analog-to-digital converter according to Embodiment 3. This is a graph showing the frequency characteristics of the DEM clock when N=8 and the sampling frequency is 1MHz in Embodiment 3.This graph shows the attenuation characteristics of the FIR filter in Embodiment 3 when N = 8 and the sampling frequency is 1 MHz. This is a configuration diagram showing an example of an analog-to-digital conversion system according to Embodiment 4.

[0014] The embodiments will be described in detail below with reference to the drawings.

[0015] The embodiments described below are all general or specific examples. The numerical values, shapes, materials, components, arrangement and connection configurations of components, steps, and the order of steps shown in the following embodiments are examples only and are not intended to limit this disclosure.

[0016] (Embodiment 1) The delta-sigma type analog-to-digital converter according to Embodiment 1 will be described below.

[0017] Figure 1 is a configuration diagram showing an example of a delta-sigma type analog-to-digital converter (hereinafter referred to as ADC1) according to Embodiment 1. A reference signal source 60 is shown in Figure 1, but the reference signal source 60 may or may not be provided in ADC1.

[0018] The ADC1 is a delta-sigma type analog-to-digital converter and includes a quantizer 30 that operates at a predetermined sampling frequency (hereinafter referred to as the sampling frequency fs), an FIR filter 40 connected to the quantizer 30, and a digital-to-analog converter (DAC) 50. The ADC1 also includes an adder 10 and an integrator. For example, the ADC1 includes a loop filter 20 that includes an integrator. The FIR filter 40 and the DAC 50 constitute a feedback path to the quantizer 30. The reference signal for the DAC 50 is supplied from a reference signal source 60 that performs chopping at a frequency lower than the sampling frequency fs. The chopping frequency, which is the frequency at which the reference signal source 60 performs chopping, is, for example, the value obtained by dividing the sampling frequency fs by 2N, where N is an integer of 1 or more.

[0019] For example, the sampling frequency fs and the chopping frequency of the reference signal are generated by a synchronized clock signal source. In other words, the clock of the quantizer 30 of ADC1 and the clock of the reference signal source 60 may be synchronized.

[0020] ADC1 differs from a typical delta-sigma ADC in that the reference signal for DAC50 is supplied from a reference signal source 60 that chops at a frequency lower than the sampling frequency fs of quantizer 30, and that it includes an FIR filter 40. The following explanation will focus on the differences from a typical delta-sigma ADC.

[0021] As mentioned above, the aging variation of the reference voltage VREF of the reference signal is undesirable as it results in gain variation of ADC1, so a method is needed to suppress the aging variation of the reference voltage VREF. In recent years, a method using EIS has been proposed, but it requires measurement in the low-frequency range, and the measurement accuracy may deteriorate due to fluctuations caused by flicker noise in the reference voltage VREF. Therefore, the reference signal source 60 chops the reference voltage VREF in order to suppress aging variation and low-frequency flicker noise. The chopping performed by the reference signal source 60 allows the use of a reference voltage VREF with suppressed manufacturing variations and flicker noise, thereby suppressing gain variation and fluctuations in the low-frequency range.

[0022] On the other hand, if the reference voltage VREF supplied to the DAC 50 is chopped, the quantization noise may be intermodulated at the chopping frequency, potentially degrading the signal-to-noise ratio. In response to this, the FIR filter 40 provided in the feedback path can reduce the intermodulation caused by the chopping frequency.

[0023] Details of each component shown in Figure 1 will be explained in the modified examples of Embodiment 1 described later.

[0024] Figure 2 is a graph showing the frequency characteristics of the chopper clock and the attenuation characteristics of the FIR filter 40.

[0025] For example, the delay coefficient of the FIR filter 40 is set in correlation with the chopping frequency fs / 2N of the reference signal. Specifically, the correlation between the delay coefficient of the FIR filter 40 and the chopping frequency fs / 2N of the reference signal may be a proportional relationship. More specifically, as shown in FIG. 2, the poles of the transfer function of the FIR filter 40 may coincide with the chopping frequency fs / N of the reference signal. For example, when N increases, the chopping frequency fs / 2N decreases, and N of the FIR filter 40 increases. Also, when N of the FIR filter increases, the position of the pole becomes smaller. These relationships are also included in the above proportional relationship.

[0026] As shown in the upper part of FIG. 2, a tone is generated by frequency modulation within the feedback loop of the ADC1, but as shown in the lower part of FIG. 2, the FIR filter 40 can reduce the influence.

[0027] In the ADC1, since the method disclosed in Patent Document 1, such as controlling the chopping frequency of the reference voltage VREF according to the output of the delta-sigma modulator, is not performed, the reference voltage VREF can be shared among a plurality of delta-sigma modulators. Therefore, the reference voltage VREF can be shared among a plurality of delta-sigma modulators, and intermodulation due to chopping of the reference voltage VREF can be prevented.

[0028] (Modification Example of Embodiment 1) Next, the ADC1 according to the modification example of Embodiment 1 will be described.

[0029] FIG. 3 is a configuration diagram showing an example of the ADC1 according to the modification example of Embodiment 1.

[0030] As shown in FIG. 3, the ADC1 may further include a delay compensation circuit 70 and a DAC 80.

[0031] For example, the output of the FIR filter 40 is 1.5 bits (three values). For example, the FIR filter 40 is represented by {1 + z^(-N)} / 2. This means that the FIR filter 40 outputs data according to the output OUT of the current quantizer 30 and the data obtained by delaying the output OUT by N samples. The values that {1 + z^(-N)} / 2 can take are three values of -1, 0, and +1 regardless of the delay value. The details of the FIR filter 40 will be described using FIGS. 4A and 4B.

[0032] FIGS. 4A and 4B are diagrams for explaining the FIR filter 40.

[0033] FIG. 4A is a rewritten version of the FIR filter 40 shown in FIG. 3. z^(-N) represents an N-sample delay. For example, when N = 1 (i.e., in the case of z^(-1)), it can be realized by delaying by 1 sample with a single-stage flip-flop, and when N = 4 (i.e., in the case of z^(-4)), it can be realized by delaying by 4 samples with a four-stage flip-flop.

[0034] FIG. 4B shows OUT, OUT*z^(-1), and OUT*{1 + z^(-1)} in the case of z^(-1). As shown in FIG. 4B, OUT*z^(-1) is the value obtained by delaying OUT by 1 sample, and OUT*{1 + z^(-1)} has three values of -1, 0, and +1.

[0035] As shown in FIG. 3, the reference signal source 60 can suppress the influence of the offset Vofs caused by the secular change of the reference voltage VREF, etc., by performing chopping at the chopping frequency fs / 2N. The details of the reference signal source 60 will be described using FIGS. 5A to 5C.

[0036] FIGS. 5A to 5C are configuration diagrams showing an example of the reference signal source 60.

[0037] As shown in Figures 5A to 5C, the reference signal source 60 includes a bandgap reference circuit 61 (hereinafter referred to as the BGR circuit 61). Details of the BGR circuit 61 will be explained later in Figure 6. The reference signal source 60 also includes a switch circuit 111 and a differential amplifier 112. Note that the BGR circuit 61 makes modulation by DEM (Dynamic Element Matching) operation easier to understand, so the following explanation will describe an example in which the reference signal source 60 includes the BGR circuit 61, but the reference signal source 60 does not have to include the BGR circuit 61. For example, the reference signal source 60 may be realized by resistive voltage division or voltage application from an external terminal.

[0038] The differential amplifier 112 has a non-inverting input terminal to which the output voltage VBGR of the BGR circuit 61 is input via the switch circuit 111, and an inverting input terminal to which the reference voltage VREF, which is the output voltage of the differential amplifier 112, is input via the switch circuit 111. The differential amplifier 112 is a buffer circuit that amplifies the difference between the voltage input to the non-inverting input terminal and the voltage input to the inverting input terminal and outputs it as the reference voltage VREF. The differential amplifier 112, in accordance with the chopper clock, changes the connection configuration of the internal circuit 112a in synchronization with the switching operation of the switch circuit 111 so that it performs the same amplification operation whether the non-inverting input terminal and the inverting input terminal are functionally swapped or not.

[0039] The switch circuit 111 is a switch circuit that periodically swaps the voltage input to the non-inverting input terminal of the differential amplifier 112 and the voltage input to the inverting input terminal of the differential amplifier 112 using the output voltage VBGR and the reference voltage VREF, in accordance with the chopper clock. By performing chopping in the differential amplifier 112, the effect of the offset (Vofs2) of the differential amplifier 112 can be suppressed. Specifically, +Vofs2 and -Vofs2 are generated periodically, and the effect of the offset can be suppressed by taking the average of these.

[0040] As shown in Figure 5A, the BGR circuit 61 may be driven by a chopper clock with a chopping frequency of fs / 2N, and the sampling frequency fs and the driving frequency fs / 2N of the BGR circuit 61 may be generated by synchronized clock signal sources. In other words, the clock of the quantizer 30 of the ADC1 and the clock of the BGR circuit 61 may be synchronized. Alternatively, as shown in Figures 5B and 5C, the BGR circuit 61 may be driven by a chopper clock or DEM (Dynamic Element Matching) clock with a frequency different from the chopping frequency fs / 2N, and the sampling frequency fs and the driving frequency fs / 2N of the BGR circuit 61 may be generated by different, unsynchronized clock signal sources. In other words, the clock of the quantizer 30 of the ADC1 and the clock of the BGR circuit 61 do not have to be synchronized.

[0041] If the clock of the quantizer 30 and the clock of the BGR circuit 61 are not synchronized, an LPF (low-pass filter) 113 may be provided between the BGR circuit 61 and the switch circuit 111 in the path connecting the BGR circuit 61 and the non-inverting input terminal of the differential amplifier 112, as shown in Figure 5B. The LPF 113 is, for example, an SCF (switched capacitor filter) or an analog filter.

[0042] Furthermore, if the clock of the quantizer 30 and the clock of the BGR circuit 61 are not synchronized, an external capacitor 114 may be provided between the BGR circuit 61 and the switch circuit 111 in the path connecting the BGR circuit 61 and the non-inverting input terminal of the differential amplifier 112, as shown in Figure 5C.

[0043] In the circuit configuration shown in Figure 5A, the offset of the BGR circuit 61 (Vofs1) and the offset of the differential amplifier 112 (Vofs2) are output periodically superimposed. On the other hand, in the circuit configurations shown in Figures 5B and 5C, the effect of the BGR circuit 61 offset is attenuated by a filter such as the LPF 113 or capacitor 114, so there is no problem even if a chopper clock or DEM clock is input to the BGR circuit 61, and the offset of the differential amplifier 112 (Vofs2) is output periodically to the ADC1.

[0044] Next, a specific example of the BGR circuit 61 will be explained using Figure 6.

[0045] Figure 6 is a configuration diagram showing a specific example of the BGR circuit 61. In addition to the BGR circuit 61, Figure 6 also shows a switch selection circuit 101, a switch circuit 111, and a differential amplifier 112.

[0046] The BGR circuit 61 includes a DEM circuit 102, a first current source 105a, a second current source 105b, a first switch circuit 106, a first resistive element 107a, a second resistive element 107b, a second switch circuit 108, and a differential amplifier 109 and a temperature coefficient adjustment circuit 110.

[0047] The DEM circuit 102 consists of a group of diode characteristic elements 103 and a group of switches 104 which are composed of multiple switches that connect the anode portions of the multiple diode characteristic elements constituting the group of diode characteristic elements 103 to a connection point V1 for generating a reference voltage V1 or a connection point V3 for generating a reference voltage V3.

[0048] The diode characteristic element group 103 is composed of multiple diode characteristic elements, each having one end (cathode) connected to a common (in this case, ground). A diode characteristic element is an element that functionally has diode characteristics consisting of an anode and a cathode, such as a diode or an NPN bipolar transistor with a collector and base connected. In this embodiment, the base-emitter voltage of an NPN bipolar transistor with a collector and base connected is used as the bandgap voltage.

[0049] The switch selection circuit 101 outputs a DEM control signal that controls the on / off state of each switch constituting the switch group 104. The switch selection circuit 101 may also be included in the DEM circuit 102.

[0050] The DEM circuit 102 repeatedly performs the operation of selecting from the diode characteristic element group 103 a first diode characteristic element group consisting of a parallel connection of m diode characteristic elements (an integer greater than or equal to 1) and a second diode characteristic element group consisting of a parallel connection of n diode characteristic elements (an integer greater than or equal to 2). This operation is repeated within a certain period while changing the combination of the m diode characteristic elements and the n diode characteristic elements to be selected.

[0051] The first current source 105a, the second current source 105b, the first switch circuit 106, the first resistor element 107a, the second resistor element 107b, the second switch circuit 108, and the differential amplifier 109 generate an output voltage VBGR based on the difference between the current density of the current flowing through the first diode characteristic element group and the current density of the current flowing through the second diode characteristic element group (in other words, the difference in the averaged diode characteristic voltage (i.e., bandgap voltage)).

[0052] The first current source 105a and the second current source 105b are both variable current sources, one end of which is connected to the power supply voltage VDD, and which output currents of the same magnitude to each other according to the output voltage of the differential amplifier 109. The first current source 105a and the second current source 105b output currents of a magnitude adjusted to apply negative feedback to the differential amplifier 109.

[0053] The first switch circuit 106 is a circuit that periodically switches between the first current source 105a and the second current source 105b, in accordance with the chopping clock 1, between the current source that supplies current to the first diode characteristic element group and the current source that supplies current to the second diode characteristic element group.

[0054] The first resistive element 107a and the second resistive element 107b have the same resistance value and are current limiting elements inserted into the path through which current flows to the first diode characteristic element group via the switch group 104 (hereinafter referred to as the "first path"), and current limiting elements inserted into the path through which current flows to the second diode characteristic element group via the switch group 104 (hereinafter referred to as the "second path").

[0055] The differential amplifier 109 has a non-inverting input terminal and an inverting input terminal to which a voltage V1 (i.e., a first voltage at the connection point V1 between the first resistor 107a and the switch group 104) that depends on the current density of the current flowing through the first diode characteristic element group and a voltage V2 (i.e., a second voltage at the connection point V2 between the second resistor 107b and the temperature coefficient adjustment circuit 110) that depends on the current density of the current flowing through the second diode characteristic element group is input via the second switch circuit 108. The differential amplifier amplifies the difference between the voltage input to the non-inverting input terminal and the voltage input to the inverting input terminal and outputs it. The differential amplifier 109, in accordance with the chopping clock 2, changes the connection configuration of the internal circuit 109a in synchronization with the switching operation of the second switch circuit 108 so that it performs the same amplification operation whether the non-inverting input terminal and the inverting input terminal are functionally swapped or not.

[0056] The second switch circuit 108 is a switch circuit that periodically swaps the voltage input to the non-inverting input terminal of the differential amplifier 109 and the voltage input to the inverting input terminal of the differential amplifier 109 between voltage V1 and voltage V2, in accordance with the chopping clock 2.

[0057] The temperature coefficient adjustment circuit 110 is a variable resistor connected in series with the second resistor element 107b, and is adjusted to a resistance value that brings the temperature coefficient of the output voltage VBGR generated by the BGR circuit 61 closer to zero.

[0058] In the first path including connection point V1, the current output from the first current source 105a or the second current source 105b flows through the first resistive element 107a via the first switch circuit 106, and further flows through the first diode characteristic element group, which is composed of m diode characteristic elements connected in parallel, selected by the switch group 104 of the DEM circuit 102.

[0059] On the other hand, in the second path including connection point V2, the current output from the second current source 105b or the first current source 105a flows through the first switch circuit 106 to the second resistive element 107b and the temperature coefficient adjustment circuit 110, and further flows through the second diode characteristic element group, which is composed of n diode characteristic elements connected in parallel, selected by the switch group 104 of the DEM circuit 102.

[0060] Here, the voltage V1 at connection point V1 is the averaged diode characteristic voltage of the first diode characteristic element group, while the voltage V2 at connection point V2 is the averaged diode characteristic voltage of the second diode characteristic element group (the third voltage at connection point V3) plus the voltage drop across the temperature coefficient adjustment circuit 110.

[0061] These voltages V1 and V2 are input to the differential amplifier 109 via the second switch circuit 108, and the output voltage from the differential amplifier 109 is negatively fed back to adjust the output currents of the first current source 105a and the second current source 105b.

[0062] The voltage at the connection point between the first switch circuit 106 and the second resistor element 107b is output as the output voltage VBGR from the BGR circuit 61 and input to the differential amplifier 112 via the switch circuit 111. Voltage fluctuations (noise) caused by the switching operation in the DEM circuit 102, the first switch circuit 106, and the second switch circuit 108 are suppressed in the switch circuit 111 and the differential amplifier 112, and the voltage is input to the ADC1 as the reference voltage VREF.

[0063] This BGR circuit 61 makes it possible to generate a reference voltage with excellent temperature characteristics.

[0064] The delay compensation circuit 70 is a circuit that compensates for the delay caused by the inclusion of the FIR filter 40 in the feedback path. The delay compensation circuit 70 constitutes a compensatory feedback path for the quantizer 30. Unlike the feedback path composed of the FIR filter 40 and the DAC 50, the compensatory feedback path is a path that connects the output of the quantizer 30 to the loop filter 20. For example, the delay compensation circuit 70 compensates for the delay of the FIR filter 40 so that the transfer function of the ADC 1 before the insertion of the FIR filter 40 and the transfer function after the insertion of the FIR filter 40 approximate or match. In other words, the delay compensation circuit 70 is a circuit that returns or approximates the transfer function of the feedback path to the transfer function before the insertion of the FIR filter 40. For example, when the loop filter 20 shown in Figure 7, which will be described later, is provided, the delay compensation circuit 70 can be expressed by an equation such as {z^(-1)(1-z^(-N))} / 2. The DAC 80 basically has the same function as the DAC 50. The output of the DAC 80 is input to the loop filter 20, which performs delay compensation for the FIR filter 40.

[0065] Next, we will explain ADC1 in the case of a sampling frequency fs = 1 MHz and N = 4.

[0066] Figure 7 is a configuration diagram of ADC1 according to a modified example of Embodiment 1, in the case where N=4.

[0067] The loop filter 20 includes switch circuits 21 and 23, integrators 22 and 25, and adders 24 and 26. Note that the configuration of the loop filter 20 shown in Figure 7 is just one example, and there are various configurations of the loop filter 20, such as feedback type or feedforward type.

[0068] Integrator 22 is, for example, a delayed integrator, and integrator 25 is, for example, a non-delayed integrator. Integrator 22 is an integration circuit that integrates the difference between the input signal and the feedback signal at adder 10, and also functions as an LPF. Integrator 25 has the same function as integrator 22, and by providing integrator 25 in addition to integrator 22, the order of the delta-sigma modulator can be increased. Switch circuits 21 and 23 are chopping switches for the differential amplifier used in integrator 22. The same switches as in switch circuits 21 and 23 may also be applied to integrator 25.

[0069] The loop filter 20 includes an integrator, which includes a chopping circuit. For example, the chopping frequency of the integrator is a frequency that is proportional to or inversely proportional to the chopping frequency of the reference signal of the reference signal source 60. This reduces variations in the integrator in the ADC1.

[0070] Figure 8A is a graph showing the frequency characteristics of the chopper clock in a modified example of Embodiment 1, where N=4 and the sampling frequency is 1 MHz. Figure 8A is the spectrum of the reference signal of the reference signal source 60.

[0071] Figure 8B is a graph showing the attenuation characteristics of the FIR filter 40 in a modified example of Embodiment 1, where N = 4 and the sampling frequency is 1 MHz.

[0072] As shown in Figure 8A, a reference signal including tones at 125 kHz and 375 kHz is supplied from the reference signal source 60 to the ADC1, causing quantization noise and intermodulation within the feedback loop. However, as shown in Figure 8B, the FIR filter 40 can reduce these effects. In addition, odd-order harmonics occur in the chopping clock in Embodiment 1, and the poles of the FIR filter 40 correspond to these harmonics.

[0073] Next, the details of the adder 10, the integrator and chopping circuit in the loop filter 20, and the DAC 50 when the input signal to ADC1 is bipolar will be explained using Figures 9A to 9C.

[0074] FIG. 9A is a configuration diagram showing an example of an adder 10, an integrator and a chopping circuit in a loop filter 20, and a DAC 50.

[0075] FIG. 9B is a timing chart of each operation signal of the circuit in FIG. 9A.

[0076] FIG. 9C is a truth table of the switches of the DAC 50 in FIG. 9A.

[0077] The part A shown in FIG. 9A corresponds to the part A in FIG. 7 and shows an integrator and a chopping circuit. Since a 1-bit signal becomes 1.5 bits (three values) by passing through the FIR filter 40, the DAC 50 corresponds to three values (-1, 0, +1). As shown in FIG. 9B, φ1 and φ2 are signals of the sampling frequency fs, respectively, and have different polarities from each other. The DAC 50 realizes a feedback function by performing subtraction or addition according to the value of the quantization output (Dn). Dn (D ０ , D ＋１ , D －１ ) is selected according to whether the output of the FIR filter 40 is one of three values (-1, 0, +1).

[0078] As shown in FIG. 9C, when OUT is -1 and OUT*z^(-4) is -1, OUT*{1 + z^(-4)}, which is the output of the FIR filter 40, becomes -1, and D ＋１ = 0, D ０ = 0, D －１ = 1. Note that 1 indicated by Dn means switch on, and 0 indicates switch off. Also, when OUT is -1 and OUT*z^(-4) is 1, or when OUT is 1 and OUT*z^(-4) is -1, OUT*{1 + z^(-4)}, which is the output of the FIR filter 40, becomes 0, and D ＋１ = 0, D ０ = 1, D －１ = 0. Also, when OUT is 1 and OUT*z^(-4) is 1, OUT*{1 + z^(-4)}, which is the output of the FIR filter 40, becomes 1, and D ＋１ [[ID=三十二]] = 1, D ０ = 0, D －１= 0. The switches corresponding to φ1 and φ2 shown in Figure 9A are controlled according to the sampling frequency fs, D ０ , D ＋１ , D －１ The corresponding switch is controlled according to the three values ​​of the output of the FIR filter 40.

[0079] Next, the details of the adder 10, the integrator and chopping circuit in the loop filter 20, and the DAC 50 when the input signal to ADC1 is unipolar will be explained using Figures 10A and 10B.

[0080] Figure 10A is a diagram showing another example of the adder 10, the integrator and chopping circuit in the loop filter 20, and the DAC 50.

[0081] Figure 10B is the truth table for the switches of the DAC50 in Figure 10A.

[0082] In the case of a unipolar input, the DAC50 performs only subtraction depending on the value of the quantized output (Dn). As shown in Figure 10B, by changing the switch control between the cases where OUT is -1 and OUT*z^(-4) is 1 and OUT is 1 and OUT*z^(-4) is -1, the divided capacitances are selected equally. Specifically, when OUT is -1 and OUT*z^(-4) is 1, D ＋１ [0] = 1, D ＋１ [1] = 0, D ０ [0] = 0, D ０ [1] = 1, and capacity Cr1 is selected. If OUT is 1 and OUT * z^(-4) is -1, then D ＋１ [0] = 0, D ＋１ [1] = 1, D ０ [0] = 1, D ０ [1] = 0, and the capacitance Cr2 is selected. This suppresses the breakdown of the linearity of the DAC50.

[0083] (Embodiment 2) In Embodiment 1, an ADC1 that performs quantization with 1 bit (binary) was described, but this disclosure can also be applied to a multi-bit ADC that performs quantization with 3 or more values. Hereinafter, a multi-bit ADC to which this disclosure is applied will be described as Embodiment 2.

[0084] Figure 11A is a configuration diagram showing an example of a delta-sigma type analog-to-digital converter (hereinafter referred to as ADC2) according to Embodiment 2.

[0085] Figure 11B is a diagram illustrating the quantizer 30 when quantized with multiple bits (for example, 2 bits (4 values)).

[0086] Figure 11C is a table showing the output codes corresponding to the four values.

[0087] Figure 11D is a diagram illustrating the DAC 50 and FIR filter 40 when quantized with 2 bits.

[0088] For example, when quantizing with 2 bits (4 values), the quantizer 30 outputs three 1-bit data (OUT[0], OUT[1], OUT[2]) as shown in Figure 11B. As shown in Figure 11C, the output becomes a thermometer code, and there are four of them. This is because the quantizer 30 is simply a flash ADC, and the code is output according to the magnitude of the signal. As shown in Figure 11D, the FIR filter 40 has three FIR filters 40a, 40b, and 40c corresponding to the three 1-bit data (OUT[0], OUT[1], OUT[2]), and the DAC 50 has three DACs 50a, 50b, and 50c corresponding to the three FIR filters 40a, 40b, and 40c. The delay compensation circuit 70 has three delay compensation circuits corresponding to three 1-bit data (OUT[0], OUT[1], OUT[2]), and the DAC 80 has three DACs corresponding to the three delay compensation circuits.

[0089] When quantizing with an N-value, the quantizer 30 outputs N-1 1-bit data, the FIR filter 40 has N-1 FIR filters, the DAC 50 has N-1 DACs, the delay compensation circuit 70 has N-1 delay compensation circuits, and the DAC 80 has N-1 DACs. Even when quantizing with an N-value, the input to each DAC is 1.5 bits, and the configuration of each DAC is the same as that described in Figure 4A.

[0090] Note that ADC2 does not necessarily need to include the delay compensation circuit 70 and DAC80.

[0091] Next, the details of the adder 10, the integrator and chopping circuit in the loop filter 20, the DAC 50, the DEM control circuit 91, and the DEM circuit 92 in the multi-bit ADC2 will be explained using Figures 12A to 12D.

[0092] Figure 12A is a diagram showing an example of an adder 10, an integrator and chopping circuit in a loop filter 20, and a DAC 50 (DAC 50a, 50b, and 50c) when quantized with 2 bits.

[0093] Figure 12B is a diagram illustrating the DEM control circuit 91 and DEM circuit 92 when quantized with 2 bits.

[0094] Figure 12C is a DEM rotation table.

[0095] Figure 12D is a diagram illustrating DEM control using DWA (Data Weighted Averaging).

[0096] The part A shown in Figure 12A corresponds to the part A in Figure 7 and shows the integrator and chopping circuit. Dn[0](D ０ [0], D ＋１ [0], D －１ [0]) is determined according to OUT[0] and OUT[0]*z^(-N). Dn[1](D for controlling the switch of DAC50b ０ [1], D ＋１ [1], D －１ [1]) is determined according to OUT[1] and OUT[1]*z^(-N). Dn[2] (D for controlling the switch of DAC50c ０ [2], D ＋１ [2], D －１ [2]) is determined according to OUT[2] and OUT[2]*z^(-N).

[0097] As shown in Figures 12B and 12C, the DEM control circuit 91 generates a pointer Prt[2:0] according to the value of OUT[2:0] and controls the DEM circuit 92 using DWA as shown in Figure 12D. The DEM circuit 92 is simply a switching circuit. Due to errors in the capacitance values ​​of the DACs 50a to 50c (Cr0 to Cr2) during the manufacturing process, linearity deteriorates if each capacitance is not selected equally. The purpose of DEM is to select elements equally. There are various DEM methods, and Figure 12D is an example of the DWA algorithm. By using DWA for DEM control, the number of times each of the DACs 50a to 50c (Cr0 to Cr2) is selected can be made equal.

[0098] (Embodiment 3) Next, a delta-sigma type analog-to-digital converter according to Embodiment 3 will be described.

[0099] Figure 13 is a configuration diagram showing an example of a delta-sigma type analog-to-digital converter (hereinafter referred to as ADC3) according to Embodiment 3.

[0100] In Embodiment 3, the reference signal source 60a performs DEM operation, and the chopping frequency of the reference signal is correlated with the dynamic element matching frequency (DEM frequency). For example, if one cycle of the DEM is fs / N, the chopping frequency is fs / 2^(M-1), where M is a natural number less than or equal to N-1. In this case, the chopping frequency is a power of 2. The chopper clock of the integrator in the loop filter 20 is also based on this. Other aspects are the same as in the modified embodiment of Embodiment 1. The following will focus on the differences. Note that the ADC3 does not necessarily have to include the delay compensation circuit 70 and the DAC 80.

[0101] The reference signal for the DAC 50 is supplied from a reference signal source 60a that performs DEM at a frequency lower than the sampling frequency fs. The DEM frequency, which is the frequency at which the reference signal source 60a performs DEM, is, for example, the value obtained by dividing the sampling frequency fs by N.

[0102] For example, the sampling frequency fs and the DEM frequency of the reference signal are generated by a synchronized clock signal source. In other words, the clock of the quantizer 30 of the ADC3 and the clock of the reference signal source 60a may be synchronized.

[0103] The reference signal source 60a performs DEM operation and chopping operation. DEM operation reduces diode mismatch, suppressing manufacturing variations, aging variations, and temperature characteristic variations. The DEM operation and chopping operation performed by the reference signal source 60a allow the use of a reference voltage VREF with suppressed manufacturing variations and flicker noise, and suppress gain variations and fluctuations in the low-frequency range.

[0104] On the other hand, when DEM is performed, quantization noise can be intermodulated at the DEM frequency, potentially degrading the signal-to-noise ratio. In response to this, the FIR filter 40 provided in the feedback path can reduce intermodulation due to the chopping frequency.

[0105] For example, the delay coefficient of the FIR filter 40 is set in correlation with the DEM frequency fs / N of the reference signal. Specifically, the correlation between the delay coefficient of the FIR filter 40 and the DEM frequency fs / N of the reference signal may be proportional. More specifically, the poles of the transfer function of the FIR filter 40 may coincide with the DEM frequency fs / N of the reference signal.

[0106] In Embodiment 3, the output of the FIR filter 40 is 2 bits or more, not 1.5 bits (3 values). For example, the output of the FIR filter 40 is proportional to the frequency divider N, and specifically becomes an (N+1) value. Since the output of the quantizer 30 is not multi-bit, the DEM circuit 92 is not required, as in Embodiment 2. For example, in Embodiment 3, the FIR filter 40 is expressed as z^(-1){1 + z^(-1) + z^(-2) + ... + z^(-(N-1))} / N.

[0107] For example, the chopping frequency of the integrator included in the loop filter 20 is a frequency that is proportional to or inversely proportional to the DEM frequency of the reference signal of the reference signal source 60a. This reduces variations in the integrator in the ADC3 as well.

[0108] Figure 14A is a graph showing the frequency characteristics of the DEM clock in Embodiment 3 when N = 8 and the sampling frequency is 1 MHz. Figure 14A is the spectrum of the reference signal of the reference signal source 60a.

[0109] Figure 14B is a graph showing the attenuation characteristics of the FIR filter 40 in Embodiment 3 when N = 8 and the sampling frequency is 1 MHz.

[0110] As shown in Figure 14A, reference signals including tones at 125 kHz, 250 kHz, 375 kHz, and 500 kHz are supplied from the reference signal source 60a to the ADC3, causing quantization noise and intermodulation within the feedback loop. However, as shown in Figure 14B, the FIR filter 40 can reduce these effects. Furthermore, in Embodiment 3, harmonics of the DEM clock occur at integer multiples of the fundamental frequency, and the poles of the FIR filter 40 correspond to these frequencies.

[0111] (Embodiment 4) Next, an analog-to-digital conversion system according to Embodiment 4 will be described.

[0112] Figure 15 is a configuration diagram showing an example of an analog-to-digital conversion system 100 according to Embodiment 4.

[0113] The analog-to-digital conversion system 100 comprises a plurality of delta-sigma type analog-to-digital converters according to Embodiment 1, a modified version of Embodiment 1, Embodiment 2, or Embodiment 3. Figure 15 shows an example in which the analog-to-digital conversion system 100 comprises a plurality of ADCs 1 according to Embodiment 1. The analog-to-digital conversion system 100 receives the reference signals for each of the DACs 50 of the plurality of delta-sigma type analog-to-digital converters from a single reference signal source 60 that performs chopping or DEM operation at a frequency lower than the sampling frequency fs. This provides an analog-to-digital conversion system 100 that can share a reference voltage among multiple delta-sigma modulators and prevent intermodulation by chopping or DEM of the reference voltage.

[0114] (Other Embodiments) Embodiments have been described above as examples of the technology relating to this disclosure. However, the technology relating to this disclosure is not limited thereto and can be applied to embodiments that are modified, replaced, added to, or omitted as appropriate. For example, the following modified examples are also included in one embodiment of this disclosure.

[0115] In the above embodiment, each component included in the delta-sigma type analog-to-digital converter may be configured as dedicated hardware.

[0116] Some or all of the functions of the delta-sigma type analog-to-digital converter according to the above embodiment are typically implemented as an integrated circuit (LSI). These may be individually integrated on a single chip, or some or all of them may be integrated on a single chip. Furthermore, the implementation is not limited to an LSI; it may also be implemented using dedicated circuits or general-purpose processors. An FPGA (Field Programmable Gate Array) that can be programmed after LSI manufacturing, or a reconfigurable processor that can reconfigure the connections and settings of circuit cells inside the LSI, may also be used.

[0117] Furthermore, if advances in semiconductor technology or other derived technologies lead to the emergence of integrated circuit technologies that can replace LSIs, then naturally, these technologies may be used to integrate each component included in delta-sigma type analog-to-digital converters into integrated circuits.

[0118] Furthermore, this disclosure also includes forms obtained by applying various modifications to the embodiments that a person skilled in the art could conceive, and forms realized by arbitrarily combining the components and functions of each embodiment without departing from the spirit of this disclosure.

[0119] (Note) The above description of embodiments discloses the following technology.

[0120] (Technology 1) A delta-sigma type analog-to-digital converter comprising a quantizer operating at a predetermined sampling frequency, an FIR filter connected to the quantizer, and a digital-to-analog converter, wherein the FIR filter and the digital-to-analog converter constitute a feedback path to the quantizer, and the reference signal of the digital-to-analog converter is supplied from a reference signal source that performs chopping at a frequency lower than the predetermined sampling frequency.

[0121] According to this method, a reference voltage with manufacturing variations and flicker noise suppressed by chopping can be used, gain variations and fluctuations in the low-frequency range are suppressed, and intermodulation due to the chopping frequency can be reduced by an FIR filter provided in the feedback path. Furthermore, since the method disclosed in Patent Document 1, which controls the chopping frequency of the reference voltage according to the output of the delta-sigma modulator, is not performed, the reference voltage can be shared among multiple delta-sigma modulators. Therefore, the reference voltage can be shared among multiple delta-sigma modulators, and intermodulation due to chopping of the reference voltage can be prevented.

[0122] (Technology 2) The delta-sigma type analog-to-digital converter according to Technology 1, characterized in that the predetermined sampling frequency and the chopping frequency of the reference signal are generated by a synchronized clock signal source.

[0123] Thus, the quantizer clock and the reference signal source clock may be synchronized.

[0124] (Technology 3) The delta-sigma type analog-to-digital converter according to Technology 1 or 2, characterized in that the delay coefficient of the FIR filter is set in correlation with the chopping frequency of the reference signal.

[0125] (Technology 4) A delta-sigma type analog-to-digital converter according to any one of Techniques 1 to 3, characterized in that the correlation between the delay coefficient of the FIR filter and the chopping frequency of the reference signal is proportional.

[0126] (Technical 5) A delta-sigma type analog-to-digital converter according to any one of Technical 1 to 4, characterized in that the poles of the transfer function of the FIR filter coincide with the chopping frequency of the reference signal.

[0127] By designing the FIR filter in this way, intermodulation due to the chopping frequency can be reduced.

[0128] (Technology 6) A delta-sigma type analog-to-digital converter according to any one of Techniques 1 to 5, characterized by comprising an integrator including a chopping circuit.

[0129] (Technical 7) The delta-sigma type analog-to-digital converter according to Technical 6, characterized in that the chopping frequency of the integrator is a frequency that is proportional to or inversely proportional to the chopping frequency of the reference signal.

[0130] According to this, variations can also be reduced in the integrator of a delta-sigma type analog-to-digital converter.

[0131] (Technical 8) A delta-sigma type analog-to-digital converter according to any one of Technical 1 to 7, characterized in that it is equipped with a delay compensation circuit, the delay compensation circuit constitutes a compensation feedback path to the quantizer, and the compensation feedback path is different from the feedback path.

[0132] (Technical 9) The delta-sigma type analog-to-digital converter according to Technical 8, characterized in that the delay compensation circuit performs delay compensation of the FIR filter such that the transfer function of the delta-sigma type analog-to-digital converter before insertion of the FIR filter approximates or matches the transfer function after insertion of the FIR filter.

[0133] According to this, it is possible to compensate for the delay caused by the insertion of an FIR filter in the feedback path.

[0134] (Technical 10) A delta-sigma type analog-to-digital converter according to any one of Technical 1 to 9, characterized in that the reference signal source has a bandgap reference circuit.

[0135] According to this method, it is possible to generate a reference voltage with excellent temperature characteristics.

[0136] (Technical 11) The delta-sigma type analog-to-digital converter according to Technical 10, characterized in that the predetermined sampling frequency and the drive frequency of the bandgap reference circuit are generated by a synchronized clock signal source.

[0137] Thus, the clock of the quantizer and the clock of the bandgap reference circuit may be synchronized.

[0138] (Technical 12) The delta-sigma type analog-to-digital converter according to Technical 10, characterized in that the predetermined sampling frequency and the driving frequency of the bandgap reference circuit are generated by different, unsynchronized clock signal sources.

[0139] Thus, the clock of the quantizer and the clock of the bandgap reference circuit do not need to be synchronized.

[0140] (Technical 13) A delta-sigma type analog-to-digital converter according to any one of Technical 1 to 12, characterized in that the output of the FIR filter is 1.5 bits.

[0141] Thus, the output of the FIR filter may be 1.5 bits.

[0142] (Technical 14) The delta-sigma type analog-to-digital converter according to any one of Technical 1 to 12, characterized in that the reference signal source performs dynamic element matching operation, and the chopping frequency of the reference signal is correlated with the dynamic element matching frequency.

[0143] According to this, the present disclosure is applicable not only to chopping of reference voltages but also to DEMs.

[0144] (Technical 15) The delta-sigma type analog-to-digital converter according to Technical 14, characterized in that the output of the FIR filter is 2 bits or more.

[0145] Thus, the output of the FIR filter may be 2 bits.

[0146] (Technical 16) An analog-to-digital conversion system comprising a plurality of delta-sigma type analog-to-digital converters described in any of Technical 1 to 15, wherein the reference signals of each of the plurality of delta-sigma type analog-to-digital converters are supplied from a single reference signal source that chops at a frequency lower than the predetermined sampling frequency.

[0147] This allows for the sharing of a reference voltage among multiple delta-sigma modulators and provides an analog-to-digital conversion system that prevents intermodulation due to chopping of the reference voltage.

[0148] This disclosure can be applied to image sensors or battery management systems, etc.

[0149] 1, 2, 3 ADC 10, 24, 26 Adder 20 Loop filter 21, 23, 111 Switch circuit 22, 25 Integrator 30 Quantizer 40, 40a, 40b, 40c FIR filter 50, 50a, 50b, 50c, 80 DAC 60, 60a Reference signal source 61 BGR circuit 70 Delay compensation circuit 91 DEM control circuit 92 DEM circuit 100 Analog-to-digital conversion system 101 Switch selection circuit 102 DEM circuit 103 Diode characteristic element group 104 Switch group 105a First current source 105b Second current source 106 First switch circuit 107a First resistor element 107b Second resistor element 108 Second switch circuit 109, 112 Differential amplifier 109a, 112a Internal circuitry 110 Temperature coefficient adjustment circuit 113 LPF 114 Capacitance

Claims

1. A delta-sigma type analog-to-digital converter comprising: a quantizer operating at a predetermined sampling frequency; an FIR filter connected to the quantizer; and a digital-to-analog converter, wherein the FIR filter and the digital-to-analog converter constitute a feedback path to the quantizer, and the reference signal of the digital-to-analog converter is supplied from a reference signal source that performs chopping at a frequency lower than the predetermined sampling frequency.

2. The delta-sigma type analog-to-digital converter according to claim 1, characterized in that the predetermined sampling frequency and the chopping frequency of the reference signal are generated by a synchronized clock signal source.

3. The delta-sigma type analog-to-digital converter according to claim 1 or 2, characterized in that the delay coefficient of the FIR filter is set in correlation with the chopping frequency of the reference signal.

4. The delta-sigma type analog-to-digital converter according to any one of claims 1 to 3, characterized in that the correlation between the delay coefficient of the FIR filter and the chopping frequency of the reference signal is proportional.

5. The delta-sigma type analog-to-digital converter according to any one of claims 1 to 4, characterized in that the poles of the transfer function of the FIR filter coincide with the chopping frequency of the reference signal.

6. A delta-sigma type analog-to-digital converter according to any one of claims 1 to 5, characterized by comprising an integrator including a chopping circuit.

7. The delta-sigma type analog-to-digital converter according to claim 6, characterized in that the chopping frequency of the integrator is a frequency that is proportional to or inversely proportional to the chopping frequency of the reference signal.

8. A delta-sigma type analog-to-digital converter according to any one of claims 1 to 7, comprising a delay compensation circuit, wherein the delay compensation circuit constitutes a compensation feedback path to the quantizer, and the compensation feedback path is different from the feedback path.

9. The delta-sigma type analog-to-digital converter according to claim 8, characterized in that the delay compensation circuit performs delay compensation of the FIR filter such that the transfer function of the delta-sigma type analog-to-digital converter before insertion of the FIR filter approximates or matches the transfer function after insertion of the FIR filter.

10. The delta-sigma type analog-to-digital converter according to any one of claims 1 to 9, characterized in that the reference signal source has a bandgap reference circuit.

11. The delta-sigma type analog-to-digital converter according to claim 10, characterized in that the predetermined sampling frequency and the drive frequency of the bandgap reference circuit are generated by a synchronized clock signal source.

12. The delta-sigma type analog-to-digital converter according to claim 10, characterized in that the predetermined sampling frequency and the drive frequency of the bandgap reference circuit are generated by different, unsynchronized clock signal sources.

13. The delta-sigma type analog-to-digital converter according to any one of claims 1 to 12, characterized in that the output of the FIR filter is 1.5 bits.

14. The delta-sigma type analog-to-digital converter according to any one of claims 1 to 12, characterized in that the reference signal source performs dynamic element matching operation, and the chopping frequency of the reference signal is correlated with the dynamic element matching frequency.

15. The delta-sigma type analog-to-digital converter according to claim 14, characterized in that the output of the FIR filter is 2 bits or more.

16. An analog-to-digital conversion system comprising a plurality of delta-sigma type analog-to-digital converters according to any one of claims 1 to 15, wherein the reference signals of each of the plurality of delta-sigma type analog-to-digital converters are supplied from a single reference signal source that performs chopping at a frequency lower than the predetermined sampling frequency.

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