Ring transmission using clock wake-up inhibition

Abstract

An integrated circuit (IC) device includes a ring transport having a plurality of nodes and a wire interconnect coupling the plurality of nodes into a ring. The wire interconnect includes a wire for conveying a clock wake-up signal around the ring transport in advance of data signaling representing a data packet. Each node is to switch from a clock-gated state to a timed state in response to receiving a clock wake-up signal. The ring transport further includes a sleep controller coupled to a select node of the plurality of nodes. The sleep controller is to configure the select node into a clock-suppressed state for a specified duration in response to identifying an idle condition on the ring transport through monitoring of the wire. While in the clock-suppressed state, the node suppresses further conveyance of any clock wake-up signal received at the select node.

Description

Background Technology

[0001] Integrated circuit (IC) devices typically use ring transmissions to transfer data and commands between various components connected to the ring transmission. A common ring transmission configuration employs a clock wake-up signal that leads each data packet by one or more clock cycles in the ring transmission. Receiving the clock wake-up signal at a node in the ring transmission activates a phase to prepare for receiving subsequent packets. However, such a clock wake-up signal can often loop around the ring transmission indefinitely, eventually making each node constantly timed. This prevents nodes from entering low-power modes, thus causing the ring transmission to consume excessive power. Attached Figure Description

[0002] The present disclosure will be better understood by referring to the accompanying drawings, which will make it readily apparent to those skilled in the art to the many features and advantages of the disclosure. The same reference numerals are used in different drawings to indicate similar or identical items.

[0003] Figure 1 This is a block diagram illustrating an integrated circuit (IC) device with a double-buffered loop transmission and a sleep controller according to some embodiments of the present disclosure.

[0004] Figure 2 A more detailed illustration is provided based on the embodiments described in this disclosure. Figure 1 A diagram of the nodes and sleep controller in a ring transmission.

[0005] Figure 3 This is a flowchart illustrating a method as part of a representative state diagram of some embodiments according to the present disclosure, the state diagram representing Figure 1 and Figure 2 Operation of the sleep controller. Detailed Implementation

[0006] Clock allocation for components used in ring transmissions typically consumes considerable power, and this power consumption is exacerbated by conventional implementations where erroneous clock wake-up signals loop indefinitely through the ring transmission, resulting in a continuously timingd ring transmission filled with clock wake-up signals. The following disclosure describes a system and technique for reducing power consumption in ring transmissions by implementing a sleep controller to suppress or "suppress" erroneous clock wake-up signals through the ring transmission. In suppressing these erroneous clock wake-up signals, the nodes in the ring transmission can switch to a non-timing state when the ring transmission is idle, thus reducing the node's power consumption.

[0007] In at least one embodiment, the ring transmission includes multiple nodes connected in a ring via a wire interconnect consisting of multiple lines, including lines for control signaling and lines for data signaling. A sleep controller is connected to a selected node and operates to control the node's operations regarding forwarding or "retransmitting" clock wake-up signals received at the node. The sleep controller monitors the wire interconnect at the controlled node for clock wake-up signals and data packets. After a specified idle duration at the node (during which the node does not receive data traffic), the sleep controller configures the node into an active clock suppression state, in which the node is controlled to suppress any received clock wake-up signals (i.e., avoid forwarding any received clock wake-up signals). In at least one embodiment, the sleep controller maintains the node in this clock suppression state for a duration sufficient to clear any erroneous clock wake-up signals propagating around the ring transmission. After the specified duration of the clock suppression state, the sleep controller enters a sleep state that allows the node to forward any newly received clock wake-up signals, and if a data packet follows the clock wake-up signal, the sleep controller resumes to an active state where the node is controlled for effective operation.

[0008] In this way, the sleep controller reacts by controlling the nodes to proactively clear erroneous clock wake-up signals from the ring transmission after an idle period, and then restores the nodes to a state where they can respond to new clock wake-up signals appearing on the ring transmission, which may indicate that data traffic has restarted on the ring transmission. This proactive clock wake-up signal suppression allows the ring transmission to switch to a practically idle state in the absence of erroneous clock signals, so nodes can remain in a non-timing state during this idle period with correspondingly reduced power consumption.

[0009] Figure 1 The illustration shows an integrated circuit (IC) device 100 with a loop transmission 102 employing active clock wake-up suppression according to some embodiments. The IC device 100 may include a single IC chip, such as a system-on-a-chip (SoC), application-specific integrated circuit (ASIC), etc., or multiple IC chips mounted on a common substrate, circuit board, or other carrier, such as a multi-chip module (MCM). Examples of the IC device 100 include a central processing unit (CPU), a graphics processing unit (GPU), an accelerated processing unit (APU), a digital signal processor (DSP), or other processors, as well as other systems typically implemented on one or more IC chips.

[0010] The ring transmission 102 includes a plurality of nodes 104, such as the four nodes 104-1 to 104-4 depicted, which are connected in a ring shape by wire interconnects 106, such that control and data signaling are transmitted node-to-node, unidirectional in a unidirectional ring implementation (e.g., clockwise 108), or in either direction in a bidirectional ring implementation. This control and data signaling continues to loop around the ring shape until it is consumed or suppressed at one of the nodes 104. Each node 104 is connected to one or more components 110 of the IC device 100, such as components 110-1 to 110-4 respectively connected to nodes 104-1 to 104-4. These components 110 operate to perform one or both of the following: injecting data traffic into the ring transmission 102 via the respective node 104 for transmission to one or more other nodes 104, or consuming data traffic transmitted by the ring transmission 102 from another node 104. Component 110 includes any of the various elements of IC device 100, such as processing elements, storage elements, bus or interface elements, input / output device elements, etc.

[0011] Node 104 and component 110 are timed based on a ring clock signal 112 (also referred to herein as “RING_CLK” 112) distributed between node 104 and component 110 via a clock distribution tree 114. The ring clock signal 112 can be, for example, the system clock of IC device 100, or a clock derived from and specific to the ring transmission 102. If the ring transmission 102 and associated component 110 remain active and are therefore timed for the entire duration of at least minimum power supply to IC device 100, considerable power will be consumed by the clock distribution tree 114 and its clock sink. To avoid this unnecessary power consumption, the ring transmission 102 employs a clock wake-up scheme, where node 104 and component 110, timed by RING_CLK 112, are clock-gated between packet transmissions on the ring transmission 102. Therefore, when a node is ready to transmit a data packet on ring transmission 102, the node inserts a clock wake-up signal 116, also referred to herein as “CLK_EN” 116, which precedes the signaling indicating the data packet by a specified number of clock cycles (e.g., 1 clock cycle). Thus, the node 104 receiving the clock wake-up signal 116 responds by switching from a clock-gated state to a timing state, the switching being performed by deactivating the clock gating at node 104 and one or more associated components 110, and thus preparing to receive and process data packets following the clock wake-up signal 116.

[0012] While this clock wake-up signaling allows node 104 to immediately receive data traffic from upstream and facilitates low-power clock-gated idle states between packets, the clock wake-up signaling typically causes the entire loop transmission 102 to be continuously timed and thus never enter a low-power idle state. For illustration, unless the receiving node can determine that a given packet is being consumed at the next node, it cannot signal to the next node that the given clock wake-up signal should not be propagated further. Therefore, a clock wake-up signal leading the packet can remain in the loop transmission after subsequent packets have been consumed and removed, and thus the loop transmission 102 can eventually be "filled" by the clock wake-up signal, effectively causing the loop transmission 102 to be continuously timed. One workaround for this erroneous clock wake-up signal is to implement additional wiring and logic to calculate at a given node whether a received packet will be consumed and will not propagate further at the next node, and to use faster circuitry and wiring to get the indicator to the next node more quickly and timely to enable its clock. However, such wiring and logic are often impractical or consume enough power to offset the energy savings achievable with a clock wake-up scheme.

[0013] To mitigate the impact of erroneous clock wake-up signals without relying on additional higher-power wiring and logic at each node, in at least one embodiment, the ring transmission 102 employs a sleep controller 118 at a selected node in node 104 (e.g., node 104-1 in the illustrated example). In at least one embodiment, the sleep controller 118 operates to enter an active clock suppression state in response to an idle condition at the associated node 104-1. Such an idle condition includes, for example, node 104-1 being idle for a specified duration. In this active clock suppression state, the sleep controller 118 controls node 104-1 to suppress the forwarding of any received clock wake-up signal 116, i.e., "suppresses" any received clock wake-up signal 116 until a valid data packet is received or the specified duration has elapsed. If a valid data packet is received while in the active clock suppression state, the sleep controller 118 ceases control of node 104-1 to suppress the received clock wake-up signal 116 and enters a normal active state. If the specified duration has elapsed, the sleep controller 118 enters a sleep state, where node 104-1 is no longer controlled to actively suppress the received clock wake-up signal 116 (that is, node 104-1 is allowed to forward the clock wake-up signal 116), and thus node 104-1 can return to the active state in response to the clock wake-up signal 116 and subsequent data packets. In this method, effectively suppressing the clock wake-up signal 116 at node 104-1 for the specified duration allows node 104-1 and the sleep controller 118 to remove any erroneous clock wake-up signals 116 from the ring transmission 102, and thus enters a sleep state, where the next received clock wake-up signal 116 should be a valid clock wake-up signal 116 preceding the data packet, thereby signaling to the ring transmission 102 that it has returned to active data transmission.

[0014] Figure 2 This is based on more detailed illustrations of some implementation schemes. Figure 1 The diagram shows the node 104-1 of the ring transmission 102 and the sleep controller 118. For ease of illustration, regarding the clockwise direction 108 ( Figure 1 The unidirectional loop configuration for transmitting signaling over the network is described for node 104-1 and sleep controller 118. For the bidirectional loop configuration, it will be understood that the components and operations described below can be replicated for control and data signaling traveling in the opposite direction (e.g., counterclockwise).

[0015] In one embodiment, the line interconnect 106 includes multiple lines (also commonly referred to as traces, leads, wires, etc.), including lines for control signaling and lines for data signaling. The lines for data signaling include K data lines 202 carrying K data bits (bits D0 to DK-1) of a data packet in parallel (K>=1), or, for differential signaling implementations, 2*K data lines 202. The lines for control signaling include a valid line 204 for carrying a valid (VALID) signal for the data packet, which is asserted along with data inserted on the K data lines to signal the status of the data lines 202 indicating valid data. The lines for control signaling also include a CLK_EN line 206 for transmitting a clock wake-up signal 116 (e.g., a pulse or other temporary assertion of the CLK_EN line 206) leading the corresponding data packet insertion on the data lines 202 by a specified number of clock cycles (e.g., one clock cycle). Node 104, including node 104-1, implements repeater 205, which buffers, amplifies, and forwards signaling received at the input of node 104 on line interconnect 106. In one embodiment, repeater 205 is implemented as a plurality of digital buffers 208, one for each line of the line interconnect, with the input of each digital buffer 208 connected to a corresponding upstream line segment on the input side of node 104 and the output connected to a corresponding downstream line segment on the output side of node 104. Although a single-digital-buffer-per-line implementation is shown, repeater 205 can be implemented using other circuit configurations using the guidelines provided herein. Each of nodes 104 also includes a sliding buffer 212, which is arranged on the input side (as shown) or the output side of node 104. Sliding buffer 212 includes dual buffers 214, 216, multiplexing / demultiplexing circuitry 218, 220, and a controller 224, and operates to buffer incoming data packets received on data line 202 for forwarding downstream. The double buffers 214 and 216 allow the sliding buffer 212 to buffer incoming data packets while processing previously received data packets for subsequent downstream transmission.

[0016] Each node 104 also includes a node interface 225, which acts as an interface between the node's line interconnect 106 and one or more components 110 of the node. The node interface 225 is coupled to various lines of the line interconnect 106 and operates to inject packets of data received from component 110 into the ring transmission 102 for transmission to downstream nodes, while controlling the CLK_EN line 206 and the valid line 204 to provide a clock wake-up signal 116 leading the injected packets and valid signaling indicating the status of valid data on the data line 202. On the receiving side, the node interface 225 operates to receive the clock wake-up signal 116 at the input of the CLK_EN line 206 and, in response, disables any clock gating applied to the ring clock signal 112 at node 104 or one or more components 110, so that node 104 and one or more components 110 are activated and timed in a timely manner to receive packets expected after receiving the clock wake-up signal 116. If such a packet does exist, the node interface 225 operates to determine whether the packet is intended for the component 110 associated with the node, and if so, provides a copy of the packet's data to the intended component 110.

[0017] Turning to sleep controller 118, in one embodiment, this component includes a state machine 226 and a set of countdown timers, including an idle timer 228 and a suppressor timer 230, timed by a ring clock signal 112 or a clock derived therefrom. State machine 226 will be implemented using hard-coded logic, programmable logic, a processor executing firmware or hardware, or a combination thereof. State machine 226 has: an input coupled to the input side of CLK_EN line 206 for monitoring the reception of clock wake-up signal 116 at node 104-1; an input coupled to the input side of valid line 204 for monitoring the reception of valid data packets at node 104-1 (the assertion signal of valid line 204 indicates that the “data” transmitted by data line 202 is valid); and an output providing sleep signal 232, which controls digital buffer 208 of CLK_EN line 206 such that if sleep signal 232 is asserted (i.e., SLEEP = 1) and no valid data packet is received (i.e., VALID = 0), digital buffer 208 is effectively disabled, and therefore no received clock wake-up signal 116 is retransmitted while in this state (i.e., any received clock wake-up signal 116 is suppressed or “suppressed”). In the illustrated embodiment, this configuration is implemented using an AND gate 234 disposed between the upstream segment of the CLK_EN line 206 and the input of the digital buffer 208. The AND gate 234 includes an inverted input for receiving the inverted representation of the sleep signal 232, an input coupled to the upstream segment of the CLK_EN line 206, and an output that acts as an input to the digital buffer 208 of the CLK_EN line 206. In other embodiments, different logical implementations are used in accordance with the teachings provided herein.

[0018] The operation of state machine 226 during the operation of control node 104-1 is represented by the state diagram 240 shown, which includes four operating states: active state 242, idle state 244, clock suppression state 246, and sleep state 248. State machine 226 monitors the CLK_EN line 206 and active line 204 as described above to detect the presence of clock wake-up signal 116 (CLK_EN) and data traffic through node 104-1. When active data traffic is present, state machine 226 remains in active state 242, during which sleep signal 232 is not asserted (or deasserted), and therefore allows any received clock wake-up signal 116 to be forwarded by repeater 205. If a clock wake-up signal 116 without subsequent data packets is received, state machine 226 enters idle state 244. Similar to active state 242, in the idle state, sleep signal 232 is not asserted, and therefore allows the received clock wake-up signal 116 to be forwarded to downstream nodes. After a specified idle condition occurs, such as after a first specified duration in idle state 244 (as measured by idle timer 228 if no data traffic is received at node 104-1), state machine 226 enters clock suppression state 246. While in clock suppression state 246, sleep controller 118 actively suppresses any clock wake-up signals 116 received at node 104-1 by asserting sleep signal 232, which in turn effectively disables digital buffer 208 on CLK_EN line 206. This, in turn, prevents repeater 205 from retransmitting any received clock wake-up signals 116 received at the input side of node 104-1.

[0019] State machine 226 remains in clock-suppressed state 246 for a second specified duration unless data traffic is received at node 104-1 (as measured by suppressor timer 230). In one embodiment, this second specified duration is selected or otherwise specified to represent a duration intended to allow any erroneous clock wake-up signal 116 present in the ring transmission 102 to reach node 104-1 and subsequently be suppressed before entering sleep state 248. If data traffic is received while in clock-suppressed state 246 and before the second specified duration expires, state machine 226 returns to active state. Otherwise, while in sleep state 248, node 104-1 switches to clock-gated state and state machine 226 releases sleep signal 232 to allow repeater 205 to propagate any received clock wake-up signal 116 downstream. If clock wake-up signal 116 is received and the signal is followed by a data packet, state machine 226 returns to active state 242. If clock wake-up signal 116 is received and no subsequent data packet is received, state machine 226 returns to idle state 244.

[0020] Figure 3 The diagram illustrates a more detailed description of the idle clock suppression-sleep state transition method 300 implemented by the sleep controller 118 for a state machine 226, based on some embodiments. Note that although some blocks are in Figure 3 The diagrams are illustrated in a given order, but the processes represented by these blocks can be executed simultaneously or in different orders. Block 302 indicates that state machine 226 enters idle state 244 after detecting the reception of clock wake-up signal 116 without any data packets following. In response to entering idle state 244, in block 304, state machine 226 resets idle timer 228 to a value M representing a first specified duration, which can be fixed or programmable and specified based on any of a variety of considerations, such as considerations from modeling the operation of ring transmission 102, or based on real-time feedback during the actual operation of ring transmission 102. Idle timer 228 then counts down from M with each cycle of ring clock signal 112. While idle timer 228 has not yet expired, in block 306, state machine 226 monitors for the reception of any data packets at node 104-1. If a data packet is received, then in block 308, state machine 226 returns to active state 242. Otherwise, as determined in block 310, when M cycles have elapsed since entering idle state 244 (i.e., idle timer 228 has expired), in block 312, state machine 226 enters clock suppression state 246.

[0021] In response to entering the clock suppression state, at block 314, state machine 226 resets suppression timer 230 to a value N representing a second specified duration, which may be fixed or programmable. In at least one embodiment, value N is set sufficiently to allow time (measured in clock cycles) for suppressing all erroneous clock wake-up signals 116 present on the ring transmission 102 at node 104-1. For example, if clock wake-up signals 116 require 20 clock cycles to complete a loop around the ring transmission 102, value N may be set to a value slightly greater than 20, such as 22, to allow sufficient time for any given erroneous clock wake-up signal 116 on the ring transmission 102 to reach node 104-1 so that the signal can be suppressed. Once reset to value N, suppression timer 230 counts down from N with each cycle of the ring clock signal 112.

[0022] Further in response to entering clock suppression state 246, in block 316, state machine 226 asserts sleep signal 232. The assertion of sleep signal 232 then configures digital buffer 208 on CLK_EN line 206 to avoid retransmission of any received clock wake-up signal 116, and thus suppresses or otherwise inhibits any erroneous clock wake-up signal 116 received at node 104-1 while in clock suppression state 246.

[0023] As indicated by decision block 318, state machine 226 monitors the elapsed timer 230 (i.e., whether N clock cycles have elapsed since entering clock suppression state 246). If the suppression timer 230 has expired, then in block 320, state machine 226 enters sleep state 248 and releases sleep signal 232. With sleep signal 232 released in sleep state 248, digital buffer 208 is activated and thus able to forward any clock wake-up signal 116 received from upstream node 104 to downstream node 104. Therefore, in block 322, state machine 226 monitors the reception of data packets at node 104-1, and in block 324, state machine 226 monitors the reception of clock wake-up signals 116 that do not have subsequent data packets. If a data packet is received at node 104-1 while in sleep state 248, then in block 308, state machine 226 resumes to active state 242. If a clock wake-up signal 116 without subsequent data packets is received at node 104-1 while the state is in sleep state 248, then at block 302, the state machine returns to idle state 244.

[0024] Returning to block 318, when the second specified cycle has not yet passed while in clock suppression state 246, state machine 226 monitors the reception of data packets in block 326. Recall that in the active, idle, and sleep states, there is no active clock wake-up signal suppression. Thus, when a data packet is received at node 104-1 in any of these states, the clock wake-up signal preceding the data packet is forwarded by repeater 205, and the received data packet is processed in the next clock cycle as usual. However, in clock suppression state 246, the clock wake-up signal is suppressed at node 104-1. Therefore, if a data packet is detected at node 104-1 in block 326, this means that the clock wake-up signal preceding the data packet is suppressed, and therefore the data packet cannot be processed and transmitted downstream immediately because there is no retransmitted clock wake-up signal preceding the data packet. Instead, node 104-1 generates a new clock wake-up signal 116 to precede the retransmitted data packet toward downstream node 104-2.

[0025] Therefore, in response to receiving a data packet while in clock suppression state 246, in block 328, the data packet is buffered in one of the double buffers 214, 216 of the sliding buffer 212. In block 330, the sleep signal 232 is deactivated to reactivate the tri-state digital buffer 208 on the CLK_EN line 206, and in block 332, the state machine 226 generates a clock wake-up signal 116 to be transmitted by the tri-state digital buffer 208 via the CLK_EN line 206 to the downstream node 104-2. For the clock cycle following the generation of the clock wake-up signal 116, in block 334, the sliding buffer outputs the buffered data packet on the data line 202 and asserts the valid line 204 to forward the data packet and valid signal downstream after the generated clock wake-up signal. Furthermore, since there is a delay due to the need to recreate the suppressed clock wake-up signal 116 before the data packet can be retransmitted, another data packet may be received during this process. In this way, the sliding buffer 212 uses another buffer to temporarily store the received second data packet until the first data packet has been transmitted. At this point, the second data packet can be provided to be forwarded to the next node 104-2 in the same way, and so on.

[0026] In some implementations, the devices and techniques described above are implemented in systems comprising one or more integrated circuit (IC) devices (also referred to as integrated circuit packages or microchips), such as those referenced above. Figures 1 to 3 The described IC device 100. Electronic design automation (EDA) and computer-aided design (CAD) software tools are frequently used in the design and manufacture of these IC devices. These design tools are typically represented as one or more software programs. The one or more software programs include code executable by a computer system to manipulate the computer system to operate on code representing a circuit of one or more IC devices to perform at least a portion of a process for designing or adapting a manufacturing system for manufacturing the circuit. This code includes instructions, data, or a combination of instructions and data. Software instructions representing design or manufacturing tools are typically stored in a computer-readable storage medium accessible by a computing system. Similarly, code representing one or more stages of the design or manufacture of the IC device is stored in and accessed from the same computer-readable storage medium or different computer-readable storage media.

[0027] Computer-readable storage media include any non-transitory storage medium or combination of non-transitory storage media that can be accessed by a computer system during use to provide instructions and / or data to the computer system. Such storage media include, but are not limited to, optical media (e.g., compressed optical discs (CDs), digital versatile optical discs (DVDs), Blu-ray discs), magnetic media (e.g., floppy disks, magnetic tapes, or magnetic hard disk drives), volatile memory (e.g., random access memory (RAM) or cache), non-volatile memory (e.g., read-only memory (ROM) or flash memory), or microelectromechanical systems (MEMS) based storage media. Computer-readable storage media may be embedded in a computing system (e.g., system RAM or ROM), permanently attached to a computing system (e.g., magnetic hard disk drive), removably attached to a computing system (e.g., optical disc or USB-based flash memory), or coupled to a computer system via a wired or wireless network (e.g., network accessible storage device (NAS)).

[0028] In some implementations, certain aspects of the techniques described above are implemented by one or more processors of a processing system executing software. The software includes one or more sets of executable instructions stored or otherwise tangibly embodied on a non-transitory computer-readable storage medium. The software may include instructions and certain data that, when executed by the one or more processors, manipulate the one or more processors to perform one or more aspects of the techniques described above. The non-transitory computer-readable storage medium may include, for example, disk or optical disc storage devices, solid-state storage devices such as flash memory, caches, random access memory (RAM), or one or more other non-volatile memory devices. The executable instructions stored on the non-transitory computer-readable storage medium may present source code, assembly language code, object code, or other instruction formats that are interpreted or otherwise executable by one or more processors.

[0029] According to one aspect, a method includes monitoring, at a node of a ring transmission of an integrated circuit (IC) device, a line for transmitting a clock wake-up signal around the ring transmission. The method further includes configuring the node into a clock-suppressed state for a first specified duration in response to identifying an idle condition on the ring transmission through the monitoring of the line, wherein while in the clock-suppressed state, the node suppresses further transmission of any clock wake-up signal received at the node. In some embodiments, the method further includes, at each of a plurality of nodes in the ring transmission, switching from a clock-gated state to a timing state in response to receiving a clock wake-up signal at the node.

[0030] According to another aspect, an IC device includes a ring transmission having a plurality of nodes and a line interconnect coupling the plurality of nodes into a ring, the line interconnect including lines configured to transmit clock wake-up signals around the ring transmission. The ring transmission also includes a sleep controller coupled to a selected node among the plurality of nodes, wherein the sleep controller, in response to identifying an idle condition on the ring transmission through monitoring of the lines, configures the selected node into a clock-suppressed state for a first specified duration, wherein while in the clock-suppressed state, the node suppresses further transmission of any clock wake-up signals received at the selected node. In some embodiments, each of the plurality of nodes is configured to switch from a clock-gated state to a timing state in response to receiving a clock wake-up signal at the node. Furthermore, in some embodiments, the idle condition includes a second specified duration elapsed from receiving a clock wake-up signal without subsequent data packets at the selected node. Furthermore, in some embodiments, the first specified duration is represented by a first specified number of clock cycles of a clock signal used for timing the ring transmission, the first specified number of clock cycles having a corresponding duration at least equal to the duration required for the clock wake-up signal to circulate the ring transmission, and the second specified duration is represented by a second specified number of clock cycles of the clock signal. Additionally, in some embodiments, the sleep controller configures the selected node into a sleep state in response to the elapsed first specified duration and the absence of any data traffic received at the selected node while in the clock suppression state, wherein, while in the sleep state, the selected node is allowed to forward clock wake-up signals received at the selected node.

[0031] According to another aspect, a device includes a ring transmission configured to transmit data packets among a plurality of nodes, each node being selectively timed by a clock signal and each data packet following a clock wake-up signal in the ring transmission. A selected node among the plurality of nodes is configured to be idle for a first specified duration in response to the ring transmission, and to suppress any clock wake-up signals received at the selected node for a second specified duration following the first specified duration.

[0032] It should be noted that not all activities or elements described in the general description above are required, a particular activity or device may not be necessary, and one or more other activities may be performed, or elements other than those described may be included. Furthermore, the order in which the activities are listed is not necessarily the order in which they are performed. Additionally, the concepts have been described with reference to specific embodiments. However, those skilled in the art will understand that various modifications and changes may be made without departing from the scope of this disclosure as set forth in the appended claims. Therefore, this specification and drawings are to be regarded as illustrative rather than restrictive, and all such modifications are intended to be included within the scope of this disclosure.

[0033] The benefits, other advantages, and solutions to problems have been described above with reference to specific embodiments. However, the benefits, advantages, and solutions to problems described, as well as any features that may bring about or make more prominent any benefit, advantage, or solution to a problem, should not be construed as being critical, essential, or necessary features of any or all claims. Furthermore, the specific embodiments disclosed above are merely illustrative, as the disclosed subject matter can be modified and practiced in different but equivalent ways that will be readily apparent to those skilled in the art who have benefited from the teachings herein. Except as described in the appended claims, no limitation is intended on the details of the constructions or designs shown herein. Therefore, it is apparent that the specific embodiments disclosed above can be altered or modified, and all such variations are considered to be within the scope of the disclosed subject matter. Therefore, the protection sought herein is as set forth in the appended claims.

Claims

1. A method comprising: monitoring, at a node of a ring transport of an integrated circuit device, a line used to convey a clock wake-up signal around the ring transport; and in response to identifying, through the monitoring of the line, an idle condition on the ring transport, configuring the node into a clock-inhibited state for a first specified duration, wherein while in the clock-inhibited state, the node inhibits further conveyance of any clock wake-up signal received at the node, wherein the idle condition comprises a second specified duration elapsing from receipt of a clock wake-up signal at the node without a subsequent data packet.

2. The method of claim 1, further comprising: at each node of a plurality of nodes of the ring transport, in response to receiving a clock wake-up signal at the node, switching from a clock-gated state to a timing state.

3. The method of claim 1, further comprising: configuring the first specified duration to be a first specified number of clock periods of a clock signal used to time the ring transport, the first specified number of clock periods having respective durations at least equal to a duration required for a clock wake-up signal to loop around the ring transport; and configuring the second specified duration to be a second specified number of clock periods of the clock signal.

4. The method of claim 1, further comprising: in response to elapsing of the first specified duration and no receipt of any data traffic at the node while in the clock-inhibited state, configuring the node into a sleep state.

5. The method of claim 1, further comprising: in response to receiving a first data packet at the node while in the clock-inhibited state: buffering the first data packet at a first buffer of a sliding buffer at the node; generating a clock wake-up signal at the node and conveying the clock wake-up signal to a next node in the ring transport; and conveying the first data packet from the first buffer to the next node after conveying the generated clock wake-up signal.

6. The method of claim 5, further comprising: in response to receiving a second data packet at the node while buffering the first data packet: buffering the second data packet at a second buffer of the sliding buffer; and conveying the second data packet to the next node after conveying the first data packet.

7. An integrated circuit device comprising: a ring transport comprising: a plurality of nodes; a line interconnect coupling the plurality of nodes into a ring, the line interconnect including a line configured to convey a clock wake-up signal around the ring transport; and a clocking circuit coupled to the line interconnect and configured to monitor the line for the clock wake-up signal. a sleep controller coupled to a selected node of the plurality of nodes, wherein the sleep controller is to configure the selected node into a clock-inhibited state for a first specified duration responsive to identifying an idle condition on the ring transmission through monitoring of the line, wherein while in the clock-inhibited state, the node inhibits further transmission of any clock wake-up signal received at the selected node, wherein the idle condition comprises a second specified duration elapsing from receipt of a clock wake-up signal at the node without a subsequent data packet.

8. The integrated circuit device of claim 7, wherein: each node of the plurality of nodes is configured to switch from a clock-gated state to a timing state responsive to receipt of a clock wake-up signal at the node.

9. The integrated circuit device of claim 7, wherein: the first specified duration is represented by a first specified number of clock periods of a clock signal used to time the ring transmission, the first specified number of clock periods having a respective duration at least equal to a duration required for a clock wake-up signal to ring the ring transmission; and the second specified duration is represented by a second specified number of clock periods of the clock signal.

10. The integrated circuit device of claim 7, wherein: the sleep controller is to configure the selected node into a sleep state responsive to elapsing of the first specified duration and no receipt of any data traffic at the selected node while in the clock-inhibited state, wherein while in the sleep state, the selected node is permitted to forward a clock wake-up signal received at the selected node.

11. The integrated circuit device of claim 7, wherein: responsive to receipt of a first data packet at the selected node while in the clock-inhibited state, the selected node is to: cache the first data packet at a first buffer of a sliding buffer at the selected node; generate a clock wake-up signal at the selected node and transmit the clock wake-up signal to a next node in the ring transmission; and transmit the first data packet from the first buffer to the next node after transmitting the generated clock wake-up signal.

12. The integrated circuit device of claim 11, wherein: responsive to receipt of a second data packet at the selected node while caching the first data packet, the selected node is to: cache the second data packet at a second buffer of the sliding buffer; and transmit the second data packet to the next node after transmitting the first data packet.

13. The integrated circuit device of claim 7, wherein the integrated circuit device comprises a processor.

14. A device, the device comprising: a ring transmission configured to transmit data packets between a plurality of nodes, each node selectively timed by a clock signal and a clock wake-up signal preceding each data packet in the ring transmission; and wherein a selected node of the plurality of nodes is configured to, in response to the ring transmission being in an idle state for a first specified duration, suppress any clock wake-up signal received at the selected node during a second specified duration after the first specified duration, wherein the idle state comprises the first specified duration elapsing from receiving a clock wake-up signal at the selected node without a subsequent data packet.

15. The device of claim 14, wherein: each node of the plurality of nodes is configured to, in response to receiving a clock wake-up signal at the node, switch from a clock-gated state to a timed state.

16. The device of claim 14, wherein: the second specified duration is represented by a second specified number of clock cycles of the clock signal, the second specified number of clock cycles having a respective duration that is at least equal to a duration required for a clock wake-up signal to circulate the ring transmission; and the first specified duration is represented by a first specified number of clock cycles of the clock signal.

17. The device of claim 14, wherein: in response to receiving a first data packet at the selected node while suppressing clock wake-up signals, the selected node is to: cache the first data packet in a first buffer of a sliding buffer at the selected node; generate a clock wake-up signal at the selected node and transmit the clock wake-up signal to a next node in the ring transmission; and transmit the first data packet from the first buffer to the next node after transmitting the generated clock wake-up signal.

18. The device of claim 17, wherein: in response to receiving a second data packet at the selected node while caching the first data packet, the selected node is to: cache the second data packet in a second buffer of the sliding buffer; and transmit the second data packet to the next node after transmitting the first data packet.

19. The device of claim 14, wherein the device comprises a processor.

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