An embedded multi-interface data acquisition and processing device

Abstract

The present invention belongs to the technical field of data acquisition and processing terminal equipment, and specifically relates to an embedded multi-interface data acquisition and processing device, which includes: an embedded hardware mainboard, a main embedded hardware platform and multiple sub-embedded hardware platforms arranged on the embedded hardware mainboard; the main embedded hardware platform is connected to the multiple sub-embedded hardware platforms via a CAN-FD bus, each sub-embedded hardware platform is connected to a corresponding external device, and the data collected by each sub-embedded hardware platform is sent to the main embedded hardware platform for processing or in response to instructions from the main embedded platform.

Description

Technical Field

[0001] The present invention belongs to the technical field of data acquisition and processing terminal equipment, and in particular relates to an embedded multi-interface data acquisition and processing device. Background Art

[0002] The manufacturing industry is currently in a critical period of transformation and upgrading. Next-generation information technology is closely integrating with manufacturing technologies, and various IoT applications are becoming widespread. Interconnecting production equipment has become a trend in industrial automation. With production equipment serving as information perception nodes, the IoT environment encompasses tens of thousands of data nodes, each of which updates data during business hours. However, due to the complete dispersion of data, nodes support varying data transmission protocols, making data collection and querying challenging.

[0003] In the fields of industrial automation, automotive electronics, sensor networks, etc., there are functional requirements for computing and control, data acquisition, and communication between devices. Various types of application requirements usually require customized hardware design. For example, the commonly used industrial control equipment communication interfaces are RS-232, RS-485, RS-422, CAN and network. Due to the different interface protocols and the incompatibility of the protocols of various communication structures, operations and information interaction between heterogeneous networks are difficult, which leads to increased production costs and reduces the speed of hardware product iteration and upgrade. Therefore, there is currently no data acquisition and processing equipment that can support multiple interface types. Summary of the Invention

[0004] In order to solve the above-mentioned defects in the prior art, the present invention proposes an embedded multi-interface data acquisition and processing device, which is characterized in that the device includes: an embedded hardware mainboard and a main embedded hardware platform and multiple sub-embedded hardware platforms arranged on the embedded hardware mainboard; the main embedded hardware platform is connected to the multiple sub-embedded hardware platforms through a CAN-FD bus, each sub-embedded hardware platform is connected to a corresponding external device, and the data collected by each sub-embedded hardware platform is sent to the main embedded hardware platform for processing or in response to instructions from the main embedded platform.

[0005] As one of the improvements to the above technical solution, the main embedded hardware platform and the multiple sub-embedded hardware platforms are all embedded hardware platforms;

[0006] A central processing unit is provided on the embedded hardware platform, and a CAN-FD bus communication interface with dual isolation of power supply and signal is provided on the central processing unit;

[0007] The central processing unit is also connected to an RS232-RS485-RS422 centralized communication interface for connecting external devices, which is used to provide any one of the interface levels in RS232 interface mode, RS485 interface mode or RS422 interface mode;

[0008] The central processing unit is also connected to an EEPROM chip with an I2C interface for storing parameter configuration data of the embedded hardware platform;

[0009] The central processor is also connected to a Flash chip with a QSPI interface for storing status data and log data of the embedded hardware platform during operation;

[0010] The central processing unit is also connected to a first connector for connecting external devices, which is used to provide a UART interface, an I2C interface, and an SPI interface; the TTL level UART interface, SPI interface, I2C interface, and several GPIO pins of the central processing unit are led out to the first connector;

[0011] The central processing unit is also connected to a second connector for connecting external devices, which is used to provide UART interface, SPI interface and RMII interface; the TTL level UART interface, SPI interface, RMII interface and several GPIO pins of the central processing unit are led out to the second connector.

[0012] As one of the improvements of the above technical solution, the RS232-RS485-RS422 centralized communication interface includes a multi-functional interface chip and a third connector. The signal side of the multi-functional interface chip has a TTL level pin configuration on the interface side to realize any interface level of RS232, RS485, and RS422.

[0013] As one of the improvements to the above technical solution, the multifunctional interface chip provides any one of the interface levels including RS232 interface mode, RS485 interface mode or RS422 interface mode through the pin configuration of the signal side connected to the central processing unit. When the central processing unit has multiple USART interfaces, USARTn represents the nth group of interfaces; its specific configuration structure is as follows:

[0014] Functional configuration structure of RS232 interface mode: The CPU configures the 11th pin of the multi-function interface chip to a low level through the GPIO pin. At this time, the logic output USARTn_TX pin and the logic input USARTn_RX pin of the CPU are connected to the 16th and 7th pins of the multi-function interface chip respectively. The 5th and 14th pins of the multi-function interface chip serve as the output and input of the RS232 interface level respectively.

[0015] Functional configuration structure of RS485 interface mode: The central processing unit configures the 11th pin of the multi-function interface chip to a high level through the GPIO pin, and configures the 12th pin of the multi-function interface chip to a high level through the GPIO pin. At this time, the logic output USARTn_TX pin and the logic input USARTn_RX pin of the central processing unit are connected to the 16th pin and the 8th pin of the multi-function interface chip respectively; the USARTn_DE pin of the central processing unit is connected to the 15th pin of the multi-function interface chip as the input / output control signal of the RS485 interface, and the 6th pin and the 5th pin of the multi-function interface chip are used as the positive and negative differential input / output of the RS485 interface level;

[0016] Functional configuration structure of RS422 interface mode: The central processing unit configures the 11th pin of the multi-function interface chip to a high level through the GPIO pin, and configures the 12th pin of the multi-function interface chip to a low level through the GPIO pin. At this time, the logic output USARTn_TX pin and the logic input USARTn_RX pin of the central processing unit are connected to the 16th pin and the 8th pin of the multi-function interface chip respectively. The 13th pin and the 14th pin of the multi-function interface chip are the differential input positive and the differential input negative of the RS422 level respectively. The 6th pin and the 5th pin of the multi-function interface chip are used as the differential output positive and the differential output negative of the RS422 level respectively.

[0017] The central processing unit has a pin multiplexing function, and at least two pins can be configured as the same USARTn_RX logic input function, and the two pins are respectively connected to the seventh pin and the eighth pin of the multi-function interface chip.

[0018] As one of the improvements to the above technical solution, the multifunctional interface chip provides the interface level of the RS232 interface mode through the pin configuration of the signal side connected to the central processing unit. The interface mode configuration needs to be performed by the central processing unit. The specific process is as follows:

[0019] Read the EEPROM chip and determine that the current working mode of the centralized interface is the RS232 interface mode according to the configuration parameters of the RS232 interface mode;

[0020] Configure the CPU pin connected to the 11th pin of the multi-function interface chip as GPIO function and output low level;

[0021] Configure the CPU pin connected to the 16th pin of the multi-function interface chip to function as USARTn_TX, as the logic output of USART;

[0022] Configure the CPU pin connected to the seventh pin of the multi-function interface chip to function as USARTn_RX, which serves as the logic input of the USART.

[0023] As one of the improvements to the above technical solution, the multifunctional interface chip provides the interface level of the RS485 interface mode through the pin configuration of the signal side connected to the central processing unit, and the specific process is as follows:

[0024] Read the EEPROM chip and determine that the current centralized interface working mode is RS485 mode according to the RS485 interface mode configuration parameters;

[0025] Configure the CPU pin connected to the 11th pin of the multi-function interface chip as GPIO function and output high level;

[0026] Configure the CPU pin connected to the 12th pin of the multi-function interface chip as GPIO function and output high level;

[0027] Configure the CPU pin connected to the 16th pin of the multi-function interface chip to function as USARTn_TX, as the logic output of USART;

[0028] Configure the CPU pin connected to the eighth pin of the multi-function interface chip to function as USARTn_RX, which serves as the logic input of the USART.

[0029] Configure the CPU pin connected to the 15th pin of the multi-function interface chip as USARTn_DE function, and enable the RS485 driver of USART.

[0030] As one of the improvements to the above technical solution, the multifunctional interface chip provides the interface level of the RS422 interface mode through the pin configuration of the signal side connected to the central processing unit, and the specific process is as follows:

[0031] Read the EEPROM chip and determine that the current centralized interface working mode is RS422 mode according to the RS422 interface mode configuration parameters;

[0032] Configure the CPU pin connected to the 11th pin of the multi-function interface chip as GPIO function and output high level;

[0033] Configure the CPU pin connected to the 12th pin of the multi-function interface chip as GPIO function and output low level;

[0034] Configure the CPU pin connected to the 16th pin of the multi-function interface chip to function as USARTn_TX, as the logic output of USART;

[0035] Configure the CPU pin connected to the eighth pin of the multi-function interface chip to function as USARTn_RX, which serves as the logic input of the USART.

[0036] As one of the improvements of the above technical solution, the power supply is divided into two power domains through DC / DC conversion, which include: an interface power domain and a platform power domain;

[0037] The interface power domain and the platform power domain are electrically isolated and do not share a common ground. The power supply mode adopted is isolated power supply.

[0038] As one of the improvements of the above technical solution, the central processing unit is connected to the Flash chip via a QSPI interface; the central processing unit is connected to the EEPROM chip via an I2C interface, and both the Flash chip and the EEPROM chip are used to store data.

[0039] The beneficial effects of the present invention compared with the prior art are:

[0040] 1. The device of the present invention can simultaneously connect multiple sub-embedded hardware platforms through the CAN FD bus interface of the main embedded platform to establish a long-distance, anti-interference, real-time and high-speed bus communication system; the main embedded platform in the device can obtain distributed sensor data through the sub-embedded platforms and their expansion circuits, and control controllers such as switches connected to the sub-embedded platform expansion circuits; during the iterative upgrade of the sensor function or controller function in each sub-embedded hardware platform, only the corresponding expansion circuit needs to be redesigned, without changing the main hardware and software structure, thus reducing the time and economic costs of the upgrade; when the device needs to expand functions, it can be conveniently achieved by increasing the number of sub-embedded platforms and their expansion circuits.

[0041] 2. The embedded hardware platform in the device of the present invention can support multiple interface expansions and interface function conversions. Through a centralized interface, it can provide any one of RS232, RS485, and RS422 interface functions, thereby optimizing the interface and reducing interface complexity. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 It is a structural diagram of an embedded hardware platform in an embedded multi-interface data acquisition and processing device of the present invention;

[0043] Figure 2 It is a structural schematic diagram of an embedded multi-interface data conversion device of the present invention;

[0044] Figure 3(a) is a schematic diagram of the power supply domain of the CAN-FD bus interface chip interface;

[0045] Figure 3(b) is a schematic diagram of the isolation transformation from the interface power domain to the platform power domain;

[0046] Figure 4This is a schematic diagram of the CAN-FD bus interface chip power / signal dual isolation;

[0047] Figure 5 This is a schematic diagram of the electrical connections of the multi-interface chip;

[0048] Figure 6(a) shows the interference connection mode between the multi-interface chip and the central processing unit;

[0049] Figure 6(b) shows the interference-free connection mode between the multi-interface chip and the central processing unit;

[0050] Figure 7 It is a flow chart of the configuration method of RS232-RS485-RS422 centralized communication interface and central processing unit.

[0051] Reference numerals:

[0052] 1. First pin 2. Second pin

[0053] 3. Third pin 4. Fourth pin

[0054] 5. Fifth pin 6. Sixth pin

[0055] 7. Seventh pin 8. Eighth pin

[0056] 9. Ninth pin 10. Tenth pin

[0057] 11. 11th pin 12. 12th pin

[0058] 13, 13th pin 14, 14th pin

[0059] 15, the fifteenth pin 16, the sixteenth pin

[0060] 17, 17th pin 18, 18th pin

[0061] 19, 19th pin 20, 20th pin

[0062] 25, 25th pin 86, 86th pin

[0063] 87, eighty-seventh pin DETAILED DESCRIPTION

[0064] The present invention will now be further described with reference to the accompanying drawings.

[0065] like Figure 1As shown, the present invention provides an embedded multi-interface data acquisition and processing device, characterized in that the device includes: an embedded hardware industrial control mainboard and a main embedded hardware platform and multiple sub-embedded hardware platforms arranged on the embedded hardware industrial control mainboard; the main embedded hardware platform is connected to the multiple sub-embedded hardware platforms via a CAN-FD bus, each sub-embedded hardware platform is connected to a corresponding external device, and the data collected by each sub-embedded hardware platform is sent to the main embedded hardware platform for processing or in response to instructions from the main embedded platform.

[0066] In this embodiment, if Figure 1 As shown, the number of the multiple sub-embedded hardware platforms is 3, namely the first sub-embedded hardware platform, the second sub-embedded hardware platform and the third sub-embedded hardware platform; wherein, the first sub-embedded hardware platform is connected to the external temperature sensor expansion circuit through the provided I2C interface, for collecting temperature data of the Internet data center (IDC) computer room; the second sub-embedded hardware platform is connected to the external humidity sensor expansion circuit through the SPI interface, for collecting humidity data of the IDC computer room; the third sub-embedded hardware platform is connected to the external air volume regulating valve controller drive circuit through the provided RS485 interface, for controlling the air volume of the air conditioner in the computer room, to ensure the normal operation and smooth operation of the IDC computer room.

[0067] Wherein, the main embedded hardware platform and the multiple sub-embedded hardware platforms are all embedded hardware platforms;

[0068] like Figure 2 As shown, a central processing unit is provided on the embedded hardware platform, and a CAN-FD bus communication interface with dual isolation of power supply and signal is provided on the central processing unit for realizing long-distance anti-interference communication;

[0069] The central processing unit is also connected to an RS232-RS485-RS422 centralized communication interface for connecting external devices, which is used to provide any one of the interface levels in RS232 interface mode, RS485 interface mode or RS422 interface mode;

[0070] The central processing unit is also connected to an EEPROM chip with an I2C interface for storing parameter configuration data of the embedded hardware platform;

[0071] The central processor is also connected to a Flash chip with a QSPI interface for storing status data and log data of the embedded hardware platform during operation;

[0072] The central processing unit is also connected to a first connector for facilitating connection of external devices, and is used to provide a UART interface, an I2C interface, an SPI interface, and several GPIOs; the TTL-level UART interface, SPI interface, I2C interface, and several GPIO pins of the central processing unit are led out to the first connector, providing external interface function expansion, thereby improving the interface function expansion capability and interface conversion capability;

[0073] The CPU is also connected to a second connector for connecting external devices, which is used to provide a UART interface, an SPI interface, an RMII interface, and several GPIOs. The TTL-level UART interface, SPI interface, RMII interface, and several GPIO pins of the CPU are led out to the second connector to provide external interface function expansion, thereby improving the interface function expansion capability and interface conversion capability. Figure 2 and Figure 3(a) 、 3(b) As shown, +5V, +3.3V and the corresponding GND are also extended to the first connector and the second connector for powering the expansion circuit.

[0074] The first and second connectors can achieve functional expansion and provide multi-interface type conversion to facilitate the collection of different data. Among them, multiple UART interfaces, multiple SPI interfaces, I2C interfaces, and RMII interfaces serve as expansion interfaces, improving the functional expansion and interface conversion capabilities of the embedded hardware platform.

[0075] The central processing unit (CPU) is an STM32H743VI ARM Cortex-M7 architecture microcontroller with a clock speed of up to 480MHz. It features a double-precision floating-point unit and DSP instructions, and integrates 2MB of Flash and 1MB of RAM, meeting a variety of application requirements, including data processing. The CPU is the control and processing core of the embedded hardware platform, and all functions provided by the embedded hardware platform are implemented through the microcontroller's on-chip program.

[0076] The CAN-FD bus communication interface with dual power and signal isolation adopts the ISO1042DW chip, which has 5000VRMS internal isolation for up to 1 minute and complies with the UL 1577 standard. It can prevent noise currents on the data bus or other circuits from entering the local area and interfering with or damaging sensitive circuits. Combined with the isolated power supply design of the embedded hardware platform, it can effectively improve the anti-interference capability of the embedded hardware platform.

[0077] The model of the Flash chip with a QSPI interface is GD25S512MDFx, which provides a storage space of up to 512Mbits and can be used to record status data and log data of the embedded hardware platform during operation.

[0078] The model of the EEPROM chip with an I2C interface is BL24C512A-PA, which provides 512 kbits of storage space and can be used to store parameter configuration data of an embedded hardware platform or record relatively small amounts of data.

[0079] The RS232-RS485-RS422 centralized communication interface includes: a multifunctional interface chip and a third connector; the multifunctional interface chip is a MAX3160EEAP, and the multifunctional interface chip has a TTL level pin configuration on the signal side to provide any one of the interface levels of the RS232 interface mode, the RS485 interface mode, or the RS422 interface mode on the interface side, thereby improving the interface integration of the hardware platform and making the circuit structure more compact;

[0080] The RS232-RS485-RS422 centralized communication interface also uses the same third connector in conjunction with a multifunctional interface chip to meet the external connection requirements of the RS232 interface, the RS485 interface and the RS422 interface.

[0081] The RS232-RS485-RS422 centralized communication interface is realized by the multi-function interface chip MAX3160EEAP and its connector. Its function configuration method is provided by the central processing unit, which optimizes the interface design. The multi-function interface chip MAX3160EEAP provides any one of the interface levels including RS232 interface mode, RS485 interface mode or RS422 interface mode through the pin configuration of the signal side connected to the central processing unit STM32H743VI. Figure 5 As shown, its specific configuration structure is as follows:

[0082] Functional configuration structure of RS232 interface mode: The central processing unit STM32H743VI configures the eleventh pin 11 of the multi-function interface chip MAX3160EEAP to a low level through the PD2_RS_MODE network signal (i.e., the PCB trace connected through the GPIO pin). At this time, the USART2_TX signal and the USART2_RX_232 signal serve as the TTL level logic output and logic input of the central processing unit STM32H743VI, respectively, and are connected to the sixteenth pin 16 and the seventh pin 7 of the multi-function interface chip, respectively. The fifth pin 5 and the fourteenth pin 14 of the multi-function interface chip MAX3160EEAP serve as the output and input of the RS232 interface level, respectively.

[0083] Functional configuration structure of RS485 interface mode: the central processing unit STM32H743VI configures the eleventh pin 11 of the multi-function interface chip MAX3160EEAP to a high level through the PD2_RS_MODE network signal (i.e., the PCB trace connected through the GPIO pin), and configures the twelfth pin 12 of the multi-function interface chip MAX3160EEAP to a high level through the HDPLX network signal. At this time, the USART2_TX signal and the USART2_RX422 signal serve as the TTL level logic output and logic input of the central processing unit STM32H743VI, respectively, and are connected to the sixteenth pin 16 and the eighth pin 8 of the multi-function interface chip respectively; the USART2_DE signal serves as the input / output control signal of the RS485 interface and is connected to the fifteenth pin 15 of the multi-function interface chip. The sixth pin 6 and the fifth pin 5 of the multi-function interface chip MAX3160EEAP constitute the differential signal of the RS485 interface level, i.e., the positive and negative of the differential input / output;

[0084] Functional configuration structure of RS422 interface mode: The central processor STM32H743VI configures the eleventh pin 11 of the multi-function interface chip MAX3160EEAP to a high level through the PD2_RS_MODE network signal (i.e., the PCB trace connected through the GPIO pin), and configures the twelfth pin 12 of the multi-function interface chip MAX3160EEAP to a low level through the HDPLX network signal. At this time, the USART2_TX and USART2_RX422 signals serve as the TTL level logic output and logic input of the central processor STM32H743VI, respectively, and are connected to the sixteenth pin 16 and the eighth pin 8 of the multi-function interface chip, respectively. The thirteenth pin 13 and the fourteenth pin 14 of the multi-function interface chip MAX3160EEAP are the differential input positive and differential input negative of the RS422 level, respectively. The sixth pin 6 and the fifth pin 5 of the multi-function interface chip MAX3160EEAP serve as the differential output positive and differential output negative of the RS422 level, respectively.

[0085] Among them, in RS232, RS485, RS422 modes, the TTL level logic input of the multi-function interface chip MAX3160EEAP is T1IN, corresponding to the sixteenth pin 16 of the multi-function interface chip MAX3160EEAP. Figure 6(a) 、 6(b)As shown, pin 16 of the multifunction interface chip MAX3160EEAP is connected to pin 86 of the STM32H743VI CPU, and pin 86 of the STM32H743VI is configured as USART2_TX. However, the TTL-level logic output pins of the multifunction interface chip MAX3160EEAP vary depending on the mode. When the multifunction interface chip MAX3160EEAP is configured in RS232 interface mode, its TTL-level output is pin 7, R1OUT. When the multifunction interface chip MAX3160EEAP is configured in RS485 or RS422 interface mode, its TTL-level output is pin 8, R2OUT.

[0086] If the multi-function interface chip shown in FIG6 (a) is connected to the central processing unit circuit, since both pin 7 R1OUT and pin 8 R2OUT are outputs, the two outputs correspond to the same USART2_RX signal input, which is bound to affect the normal operation of the central processing unit STM32H743VI. In the present invention, the feature of the central processing unit STM32H743VI pin function reuse is cleverly utilized to solve the problem of multiple outputs connecting to the same input causing conflicts. Specifically, as shown in FIG6 (b), since pin 87 of the central processing unit STM32H743VI can also be configured as the USART2_RX function like pin 25, in the circuit structure, pin 7 R1OUT is connected to pin 25 of the central processing unit STM32H743VI, and pin 8 R2OUT is connected to pin 87 of the central processing unit STM32H743VI. According to the configuration parameters in the EEPROM, when using the RS232 interface mode function, the 25th pin of the central processor STM32H743VI is configured as the USART2_RX function, and the 87th pin of the central processor STM32H743VI is configured as the GPIO input. When using the RS485 or RS422 interface mode function, the 25th pin of the central processor STM32H743VI is configured as the GPIO input, and the 87th pin of the central processor STM32H743VI is configured as the USART2_RX function. At this point, the centralized interface of RS232, RS485, and RS422 is realized through the function configuration of the central processor.

[0087] like Figure 7 As shown, the multifunctional interface chip provides the interface level of the RS232 interface mode through the pin configuration of the signal side connected to the central processing unit. The interface mode configuration also needs to be performed by the central processing unit. The specific process is as follows:

[0088] Read the EEPROM chip and determine that the current working mode of the centralized interface is the RS232 interface mode according to the configuration parameters of the RS232 interface mode;

[0089] The CPU pin connected to the eleventh pin 11 of the multi-function interface chip is configured as a general purpose input and output (GPIO) function, and outputs a low level;

[0090] Configure the CPU pin connected to the sixteenth pin 16 of the multi-function interface chip to function as USARTn_TX, i.e., USART logic output;

[0091] The CPU pin connected to the seventh pin 7 of the multi-function interface chip is configured as USARTn_RX function, that is, USART logic input.

[0092] like Figure 7 As shown, the multifunctional interface chip provides the interface level of the RS485 interface mode through the pin configuration of the signal side connected to the central processing unit, and the specific process is as follows:

[0093] Read the EEPROM chip and determine that the current centralized interface working mode is RS485 mode according to the RS485 interface mode configuration parameters;

[0094] Configure the CPU pin connected to the eleventh pin 11 of the multi-function interface chip to have a GPIO function and output a high level;

[0095] Configure the CPU pin connected to the twelfth pin 12 of the multi-function interface chip as a GPIO function and output a high level;

[0096] Configure the CPU pin connected to the sixteenth pin 16 of the multi-function interface chip to function as USARTn_TX, i.e., USART logic output;

[0097] Configure the CPU pin connected to the eighth pin 8 of the multi-function interface chip to function as USARTn_RX, i.e., USART logic input;

[0098] The CPU pin connected to the fifteenth pin 15 of the multi-function interface chip is configured as USARTn_DE function, that is, the RS485 driver of USART is enabled.

[0099] like Figure 7 As shown, the multifunctional interface chip provides the interface level of the RS422 interface mode through the pin configuration of the signal side connected to the central processing unit, and the specific process is as follows:

[0100] Read the EEPROM chip and determine that the current centralized interface working mode is RS422 mode according to the RS422 interface mode configuration parameters;

[0101] Configure the CPU pin connected to the eleventh pin 11 of the multi-function interface chip to have a GPIO function and output a high level;

[0102] Configure the CPU pin connected to the twelfth pin 12 of the multi-function interface chip as a GPIO function and output a low level;

[0103] Configure the CPU pin connected to the sixteenth pin 16 of the multi-function interface chip to function as USARTn_TX, i.e., USART logic output;

[0104] The CPU pin connected to the eighth pin 8 of the multi-function interface chip is configured as the USARTn_RX function, ie, the USART logic input.

[0105] The power supply is divided into two power domains through DC / DC (i.e., direct current to direct current) conversion, including: an interface power domain, or external power domain; and a platform power domain, or internal power domain.

[0106] The interface power domain and the platform power domain are electrically isolated and do not share a common ground. The power supply mode adopted is isolated power supply, which avoids or reduces the introduction of external power supply noise.

[0107] Specifically, if Figure 3(a) and 3(b) As shown, VIN / +5VCAN and its corresponding AGND (i.e. Figure 3(a) and 3(b) The triangle symbol in the figure represents the interface power domain, i.e., the external power domain. +5V / +3.3V and its corresponding GND represent the platform power domain, i.e., the internal power domain. These two power domains do not share a common ground in the circuit and are electrically isolated.

[0108] Among them, the internal power supply +5V is converted from the external power supply VIN through the DC / DC isolation power supply U7, +3.3V is converted from +5V through the linear power supply U8; +5VCAN is converted from VIN through the linear power supply U6.

[0109] like Figure 4 As shown, +5VCAN powers the interface side pin 8 of the CAN-FD bus interface chip ISO1042DW (i.e., U4), and the signal side pin 1 of U4 is powered by the same +3.3V as the STM32H743VI.

[0110] Figure 3(a) and 3(b) ,as well as Figure 4 The CAN-FD bus communication interface circuit shown achieves dual isolation of power supply and signal. Combined with the filtering design of the CAN-FD bus communication interface signal, it can effectively improve the anti-interference capability of the embedded hardware platform.

[0111] The central processing unit STM32H743VI is connected to the Flash chip GD25S512MDFx through a QSPI interface; the central processing unit STM32H743VI is connected to the EEPROM chip BL24C512A-PA through an I2C interface. Both the Flash chip and the EEPROM chip are used to store data.

[0112] Finally, it should be noted that the above embodiments are intended only to illustrate the technical solutions of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the embodiments, it should be understood by those skilled in the art that modifications or equivalent substitutions to the technical solutions of the present invention do not depart from the spirit and scope of the technical solutions of the present invention and are intended to be encompassed by the claims of the present invention.

Claims

1. An embedded multi-interface data acquisition and processing device, characterized in that: The device includes: an embedded hardware mainboard, a main embedded hardware platform and multiple sub-embedded hardware platforms arranged on the embedded hardware mainboard; the main embedded hardware platform is connected to the multiple sub-embedded hardware platforms via a CAN-FD bus, each sub-embedded hardware platform is connected to a corresponding external device, and the data collected by each sub-embedded hardware platform is sent to the main embedded hardware platform for processing or in response to instructions from the main embedded platform; The main embedded hardware platform and the multiple sub-embedded hardware platforms are all embedded hardware platforms; a central processing unit is provided on the embedded hardware platform, and the central processing unit is connected to an RS232-RS485-RS422 centralized communication interface for facilitating connection of external devices, and is used to provide any one interface level in RS232 interface mode, RS485 interface mode or RS422 interface mode; The RS232-RS485-RS422 centralized communication interface includes a multifunctional interface chip; The multifunctional interface chip provides any one of the interface levels including RS232 interface mode, RS485 interface mode or RS422 interface mode through the pin configuration of the signal side connected to the central processing unit. When the central processing unit has multiple USART interfaces, USARTn represents the nth group of interfaces. Its specific configuration structure is as follows: Functional configuration structure of RS232 interface mode: The central processing unit configures the eleventh pin (11) of the multi-function interface chip to a low level through the GPIO pin. At this time, the logic output USARTn_TX pin and the logic input USARTn_RX pin of the central processing unit are connected to the sixteenth pin (16) and the seventh pin (7) of the multi-function interface chip respectively. The fifth pin (5) and the fourteenth pin (14) of the multi-function interface chip serve as the output and input of the RS232 interface level respectively. Functional configuration structure of RS485 interface mode: the central processing unit configures the eleventh pin (11) of the multi-function interface chip to a high level through the GPIO pin, and configures the twelfth pin (12) of the multi-function interface chip to a high level through the GPIO pin. At this time, the logic output USARTn_TX pin and the logic input USARTn_RX pin of the central processing unit are connected to the sixteenth pin (16) and the eighth pin (8) of the multi-function interface chip respectively; the USARTn_DE pin of the central processing unit is connected to the fifteenth pin (15) of the multi-function interface chip as the input / output control signal of the RS485 interface, and the sixth pin (6) and the fifth pin (5) of the multi-function interface chip are used as the positive and negative differential input / output of the RS485 interface level; Functional configuration structure of RS422 interface mode: the central processing unit configures the eleventh pin (11) of the multi-function interface chip to a high level through the GPIO pin, and configures the twelfth pin (12) of the multi-function interface chip to a low level through the GPIO pin. At this time, the logic output USARTn_TX pin and the logic input USARTn_RX pin of the central processing unit are respectively connected to the sixteenth pin (16) and the eighth pin (8) of the multi-function interface chip, the thirteenth pin (13) and the fourteenth pin (14) of the multi-function interface chip are respectively the differential input positive and the differential input negative of the RS422 level, and the sixth pin (6) and the fifth pin (5) of the multi-function interface chip are respectively the differential output positive and the differential output negative of the RS422 level; The central processing unit has a pin multiplexing function, and at least two pins can be configured as the same USARTn_RX logic input function, and the two pins are respectively connected to the seventh pin (7) and the eighth pin (8) of the multi-function interface chip.

2. The embedded multi-interface data acquisition and processing device according to claim 1, characterized in that: The central processing unit is provided with a CAN-FD bus communication interface with dual isolation of power supply and signal; The central processing unit is also connected to an EEPROM chip with an I2C interface for storing parameter configuration data of the embedded hardware platform; The central processor is also connected to a Flash chip with a QSPI interface for storing status data and log data of the embedded hardware platform during operation; The central processing unit is also connected to a first connector for connecting external devices, which is used to provide a UART interface, an I2C interface, and an SPI interface; the TTL level UART interface, SPI interface, I2C interface, and several GPIO pins of the central processing unit are led out to the first connector; The central processing unit is also connected to a second connector for connecting external devices, which is used to provide UART interface, SPI interface and RMII interface; the TTL level UART interface, SPI interface, RMII interface and several GPIO pins of the central processing unit are led out to the second connector.

3. The embedded multi-interface data acquisition and processing device according to claim 2, characterized in that: The signal side of the multifunctional interface chip has TTL level pins configured on the interface side to realize any one of RS232, RS485, and RS422 interface levels.

4. The embedded multi-interface data acquisition and processing device according to claim 2, characterized in that: The multifunctional interface chip provides the interface level of the RS232 interface mode through the pin configuration of the signal side connected to the central processing unit. The interface mode configuration needs to be performed by the central processing unit. The specific process is as follows: Read the EEPROM chip and determine that the current working mode of the centralized interface is the RS232 interface mode according to the configuration parameters of the RS232 interface mode; The central processing unit pin connected to the eleventh pin (11) of the multi-function interface chip is configured as a GPIO function and outputs a low level; Configure the central processing unit pin connected to the sixteenth pin (16) of the multi-function interface chip to function as USARTn_TX, as the logic output of USART; The CPU pin connected to the seventh pin (7) of the multi-function interface chip is configured as the USARTn_RX function, which serves as the logic input of the USART.

5. The embedded multi-interface data acquisition and processing device according to claim 2, characterized in that: The multifunctional interface chip provides the interface level of the RS485 interface mode through the pin configuration of the signal side connected to the central processing unit, and the specific process is as follows: Read the EEPROM chip and determine that the current centralized interface working mode is RS485 mode according to the RS485 interface mode configuration parameters; The central processing unit pin connected to the eleventh pin (11) of the multi-function interface chip is configured as a GPIO function and outputs a high level; The central processing unit pin connected to the twelfth pin (12) of the multi-function interface chip is configured as a GPIO function and outputs a high level; Configure the central processing unit pin connected to the sixteenth pin (16) of the multi-function interface chip to function as USARTn_TX, as the logic output of USART; Configure the CPU pin connected to the eighth pin (8) of the multi-function interface chip to function as USARTn_RX, as the logic input of the USART; The CPU pin connected to the fifteenth pin (15) of the multi-function interface chip is configured as the USARTn_DE function, which is used as the RS485 driver enable of the USART.

6. The embedded multi-interface data acquisition and processing device according to claim 2, characterized in that: The multifunctional interface chip provides the interface level of the RS422 interface mode through the pin configuration of the signal side connected to the central processing unit, and the specific process is as follows: Read the EEPROM chip and determine that the current centralized interface working mode is RS422 mode according to the RS422 interface mode configuration parameters; The central processing unit pin connected to the eleventh pin (11) of the multi-function interface chip is configured as a GPIO function and outputs a high level; The central processing unit pin connected to the twelfth pin (12) of the multi-function interface chip is configured as a GPIO function and outputs a low level; Configure the central processing unit pin connected to the sixteenth pin (16) of the multi-function interface chip to function as USARTn_TX, as the logic output of USART; The CPU pin connected to the eighth pin (8) of the multi-function interface chip is configured as the USARTn_RX function, which serves as the logic input of the USART.

7. The embedded multi-interface data acquisition and processing device according to claim 2, characterized in that: The power supply is divided into two power domains through DC / DC conversion, including: an interface power domain and a platform power domain; The interface power domain and the platform power domain are electrically isolated and do not share a common ground. The power supply mode adopted is isolated power supply.

8. The embedded multi-interface data acquisition and processing device according to claim 2, characterized in that: The central processing unit is connected to the Flash chip via a QSPI interface; the central processing unit is connected to the EEPROM chip via an I2C interface, and both the Flash chip and the EEPROM chip are used to store data.

Images