Methods to improve wafer warpage, semiconductor device fabrication methods and semiconductor devices

Abstract

This disclosure provides a method for improving wafer warpage, a semiconductor device fabrication method, and a semiconductor device. The method for improving wafer warpage includes: providing a warped wafer; wherein the wafer experiences edge-down warpage due to ion implantation or etching processes performed on its front side, and the warpage at each location increases with the distance between that location and the center of the wafer; performing ion implantation on the back side of the wafer to form a plurality of annular ion implantation regions spaced apart and centered on the center of the wafer, thereby canceling out the stress generated by the back-side ion implantation and the front-side ion implantation or etching processes; wherein the radial width of each annular ion implantation region increases with the distance between that region and the center of the wafer. This method can precisely eliminate wafer warpage caused by the front-side processes, avoiding significant impact on subsequent processes.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor device technology, specifically to a method for improving wafer warpage, a semiconductor device fabrication method, and a semiconductor device. Background Technology

[0002] Silicon carbide (SiC) materials possess advantages such as wide bandgap, high thermal conductivity, high breakdown field strength, and high saturation velocity, making them ideal for fabricating high-temperature, high-power semiconductor devices. SiC-based power devices can fully leverage their high-temperature, high-frequency, and low-loss characteristics, making them highly promising for applications in high-voltage, high-temperature, high-frequency, high-power, and high-radiation fields.

[0003] However, in the manufacturing process of SiC-based power semiconductor devices, many core processes such as ion implantation and dry etching can generate significant stress on the wafer, causing considerable warping. Wafer warping can have disastrous effects on subsequent processes, such as ineffective focusing and insufficient exposure and development in subsequent photolithography processes; in addition, high wafer warping also increases the risk of wafer cracking and fragmentation. Summary of the Invention

[0004] To address the aforementioned issues, this disclosure provides a method for improving wafer warpage, a semiconductor device fabrication method, and a semiconductor device, thereby resolving the technical problem in the prior art where wafer warpage has a significant impact on subsequent processes.

[0005] In a first aspect, this disclosure provides a method for improving wafer warpage, comprising:

[0006] A warped wafer is provided; wherein the wafer warps downward at its edges due to an ion implantation or etching process performed on its front side, and the degree of warping at each location of the wafer increases with the increase of the distance between itself and the center of the wafer;

[0007] Ion implantation is performed on the back side of the wafer to form a plurality of annular ion implantation regions spaced apart from the center of the wafer, thereby offsetting the stress generated by back-side ion implantation and front-side ion implantation or etching processes; wherein the radial width of each annular ion implantation region increases as its distance from the center of the wafer increases.

[0008] According to an embodiment of this disclosure, preferably, in the above-described method for improving wafer warpage, the inner diameter of the annular ion implantation region closest to the center of the wafer is greater than or equal to one-tenth of the wafer diameter and less than or equal to one-half of the wafer diameter.

[0009] According to embodiments of this disclosure, preferably, in the above-described method for improving wafer warpage, the spacing between any two adjacent annular ion implantation regions is equal.

[0010] According to an embodiment of the present disclosure, preferably, in the above-described method for improving wafer warpage, the spacing between two adjacent annular ion implantation regions increases as their distance from the center of the wafer increases.

[0011] According to an embodiment of this disclosure, preferably, in the above-described method for improving wafer warpage, the spacing between two adjacent annular ion implantation regions is greater than 0 and less than half the wafer diameter.

[0012] According to embodiments of this disclosure, preferably, in the above-described method for improving wafer warpage, the radial width of the annular ion implantation region is greater than 0 and less than or equal to nine-twentieths of the wafer diameter.

[0013] According to an embodiment of this disclosure, preferably, in the above-described method for improving wafer warpage, ion implantation is performed on the back side of the wafer to form a plurality of annular ion implantation regions spaced apart from the center of the wafer on the back side, thereby offsetting the stress generated by back-side ion implantation and front-side ion implantation or etching processes, including the following steps:

[0014] A mask layer is deposited on the back side of the wafer;

[0015] The mask layer is patterned to form a mask pattern; wherein the mask pattern includes a circular first pattern located at the center of the wafer, and a plurality of annular second patterns arranged at intervals with the center of the wafer as the center, the second patterns being located around the first pattern and spaced apart from the first pattern;

[0016] Using the mask pattern as an ion implantation mask, ion implantation is performed on the back side of the wafer to form several annular ion implantation regions spaced apart from the center of the wafer on the back side, thereby canceling out the stress generated by the back side ion implantation and the front side ion implantation or etching process.

[0017] Remove the mask pattern.

[0018] Secondly, this disclosure provides a method for fabricating a semiconductor device, comprising:

[0019] Provide one wafer;

[0020] An ion implantation or etching process is performed on the front side of the wafer to form a front structure required to constitute a semiconductor device; wherein the wafer warps downward at its edges due to the ion implantation or etching process performed on its front side, and the degree of warping at each location of the wafer increases with the increase of the distance between the location and the center of the wafer.

[0021] Ion implantation is performed on the back side of the wafer to form a plurality of annular ion implantation regions spaced apart from the center of the wafer, thereby canceling out the stress generated by the back side ion implantation and the front side ion implantation or etching process; wherein, the radial width of each annular ion implantation region increases as its distance from the center of the wafer increases.

[0022] Return to the step of performing ion implantation or etching on the front side of the wafer until all ion implantation and etching processes that need to be performed on the front side of the wafer are completed;

[0023] The back side of the wafer is thinned to remove the annular ion implantation region and retain the wafer of a predetermined thickness.

[0024] According to embodiments of this disclosure, preferably, in the above-described semiconductor device fabrication method, the inner diameter of the annular ion implantation region closest to the center of the wafer is greater than or equal to one-tenth of the wafer diameter and less than or equal to one-half of the wafer diameter.

[0025] According to embodiments of this disclosure, preferably, in the above-described semiconductor device fabrication method, the spacing between any two adjacent annular ion implantation regions is equal.

[0026] According to an embodiment of the present disclosure, preferably, in the above-described semiconductor device fabrication method, the spacing between two adjacent annular ion implantation regions increases as the distance between them and the center of the wafer increases.

[0027] According to embodiments of this disclosure, preferably, in the above-described semiconductor device fabrication method, the spacing between two adjacent annular ion implantation regions is greater than 0 and less than half the diameter of the wafer.

[0028] According to embodiments of this disclosure, preferably, in the above-described semiconductor device fabrication method, the radial width of the annular ion implantation region is greater than 0 and less than or equal to nine-twentieths of the wafer diameter.

[0029] According to an embodiment of this disclosure, preferably, in the above-described semiconductor device fabrication method, ion implantation is performed on the back side of the wafer to form a plurality of annular ion implantation regions spaced apart from the center of the wafer on the back side, thereby offsetting the stress generated by the back side ion implantation and the front side ion implantation or etching process, including the following steps:

[0030] A mask layer is deposited on the back side of the wafer;

[0031] The mask layer is patterned to form a mask pattern; wherein the mask pattern includes a circular first pattern located at the center of the wafer, and a plurality of annular second patterns arranged at intervals with the center of the wafer as the center, the second patterns being located around the first pattern and spaced apart from the first pattern;

[0032] Using the mask pattern as an ion implantation mask, ion implantation is performed on the back side of the wafer to form several annular ion implantation regions spaced apart from the center of the wafer on the back side, thereby canceling out the stress generated by the back side ion implantation and the front side ion implantation or etching process.

[0033] Remove the mask pattern.

[0034] Thirdly, this disclosure provides a semiconductor device fabricated using the silicon carbide device fabrication method described in any one of the second aspects.

[0035] By adopting the above technical solution, at least the following technical effects can be achieved:

[0036] (1) The stress generated by back ion implantation and front process cancels each other out, which can accurately eliminate wafer warpage caused by front process and avoid significant impact on subsequent processes.

[0037] (2) This method fully considers the distribution of wafer warpage and improves wafer warpage in a targeted manner without causing reverse wafer warpage.

[0038] (3) This method is simple, convenient, low-cost and easy to implement. Attached Figure Description

[0039] The accompanying drawings are provided to further illustrate the present disclosure and form part of the specification. They are used together with the following detailed description to explain the present disclosure, but do not constitute a limitation thereof. In the drawings:

[0040] Figure 1 This is a schematic flowchart illustrating an exemplary embodiment of the present disclosure of a method for improving wafer warpage;

[0041] Figures 2-8This is a cross-sectional structure and a back-side bottom view schematic diagram showing the relevant steps of a method for improving wafer warpage, as illustrated in an exemplary embodiment of this disclosure.

[0042] Figure 9 This is a schematic flowchart illustrating a semiconductor device fabrication method according to an exemplary embodiment of this disclosure;

[0043] In the accompanying drawings, the same parts are referred to by the same reference numerals, and the drawings are not drawn to scale. Detailed Implementation

[0044] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings and examples, thereby enabling a full understanding and implementation of how this disclosure uses technical means to solve technical problems and achieve corresponding technical effects. The embodiments of this disclosure and the various features within them can be combined with each other without conflict, and the resulting technical solutions are all within the protection scope of this disclosure. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.

[0045] It should be understood that although the terms “first,” “second,” “third,” etc., may be used to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, area, layer, or part from another element, component, area, layer, or part. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or part discussed below may be referred to as the second element, component, area, layer, or part.

[0046] It should be understood that spatial relation terms such as "above," "located above," "below," "located below," etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as "below other elements" will be oriented "above" other elements or features. Therefore, the exemplary terms "below" and "below" can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0047] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0048] Embodiments of this disclosure are described herein with reference to cross-sectional views that serve as schematic diagrams of ideal embodiments (and intermediate structures). Thus, variations in the shape shown can be anticipated due to, for example, fabrication techniques and / or tolerances. Therefore, embodiments of this disclosure should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, fabrication. For example, implanted regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implanted to non-implanted regions. Similarly, buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of regions of the device and are not intended to limit the scope of this disclosure.

[0049] To fully understand this disclosure, detailed structures and steps will be presented in the following description to illustrate the technical solutions proposed in this disclosure. Preferred embodiments of this disclosure are described in detail below; however, in addition to these detailed descriptions, this disclosure may have other implementations.

[0050] Example 1

[0051] Figure 1 This is a schematic flowchart illustrating a method for improving wafer warpage according to an embodiment of this disclosure. Figures 2-8 This is a cross-sectional structure and a back-side bottom view schematic diagram showing the relevant steps of a method for improving wafer warpage according to an embodiment of this disclosure. Below, referring to... Figure 1 and Figures 2-8 The following describes the detailed steps of an exemplary method for improving wafer warpage according to embodiments of the present disclosure.

[0052] like Figure 1 As shown, the method for improving wafer warpage in this embodiment includes the following steps:

[0053] Step S101: As Figure 2As shown, a warped wafer 100 is provided; wherein the wafer 100 is warped at the edge downward due to an ion implantation or etching process performed on its front side, and the degree of warping at each location of the wafer 100 increases with the increase of the distance between the location and the center of the wafer 100.

[0054] In other words, the warpage distribution of wafer 100 is as follows: there is basically no warpage at the center of wafer 100, and the warpage gradually increases with distance from the center of wafer 100, forming an inverted "bowl" shape. The front side 101 of wafer 100 is a convex surface, and the back side 102 of wafer 100 is a concave surface.

[0055] Step S102: Ion implantation is performed on the back side 102 of the wafer 100 to form a plurality of annular ion implantation regions 104 arranged at intervals with the center of the wafer 100 on the back side 102 of the wafer 100, so that the stress generated by the back side ion implantation and the front side ion implantation or etching process cancels each other out; wherein, the radial width W of each annular ion implantation region 104 increases as the distance between it and the center of the wafer 100 increases.

[0056] Specifically, step S102 includes the following steps:

[0057] S102a: As Figure 3 As shown, a mask layer 103 is deposited on the back side 102 of wafer 100;

[0058] S102b: As Figure 4 As shown, the mask layer 103 is patterned to form a mask pattern (not shown in the figure); wherein, the mask pattern includes a circular first pattern 1031 located at the center of the wafer 100, and a plurality of annular second patterns 1032 arranged at intervals with the center of the wafer 100 as the center, the second patterns 1032 being located around the first pattern 1031 and spaced apart from the first pattern 1031;

[0059] S102c: such as Figure 5 and 6 As shown, using a mask pattern as an ion implantation mask, ion implantation is performed on the back side 102 of the wafer 100 to form several annular ion implantation regions 104 spaced apart from the center of the wafer 100 on the back side 102 of the wafer 100, so that the stress generated by the back side ion implantation and the front side ion implantation or etching process can cancel each other out.

[0060] S102d: as Figure 7 and 8 As shown, remove the mask pattern.

[0061] Before the mask layer 103 is deposited on the back side 102 of wafer 100, wafer 100 needs to be cleaned by RCA.

[0062] The thickness of the mask layer 103 is greater than 1 micrometer.

[0063] In the back-side ion implantation step, the implanted ions can be N-type or P-type. The implantation dose for back-side ion implantation is 1E¹¹ / cm². 2 Up to 1E16 / cm 2 The injected energy ranges from 50 keV to 1000 keV.

[0064] Ion implantation in localized areas of the back side 102 of wafer 100 will generate certain stress on the back side 102. This stress is opposite in direction to the stress brought by the front side process, and they can cancel each other out, thereby eliminating wafer stress and ultimately improving wafer warpage.

[0065] Furthermore, since the warpage and stress increase with distance from the center of wafer 100, the radial width W of the ion implantation annular region on the back side 102 is designed to gradually increase from the center of wafer 100 towards the edge. This design method ensures that the stress generated on the back side 102 of wafer 100 gradually increases with distance from the center of wafer 100, which is consistent with the stress distribution on the front side 101 of wafer 100. This fully considers the warpage distribution of wafer 100 and can accurately offset the stress on the front side 101 of wafer 100, without causing reverse warpage of wafer 100 due to overcompensation of stress.

[0066] In the formed annular ion implantation region 104, the inner diameter D2 (i.e. the diameter of the first pattern 1031) of the annular ion implantation region 104 closest to the center of the wafer 100 is greater than or equal to one-tenth of the diameter D1 of the wafer 100 and less than or equal to one-half of the diameter D1 of the wafer 100, i.e., 1 / 10D1≤D2≤1 / 2D1.

[0067] The spacing d between any two adjacent annular ion implantation regions 104 can be equal, meaning that all annular ion implantation regions 104 are equally spaced. Alternatively, the spacing d between any two adjacent annular ion implantation regions 104 can be unequal. The spacing between two adjacent annular ion implantation regions 104 can increase as the distance between the two adjacent annular ion implantation regions 104 and the center of the wafer 100 increases. The specific value can be designed according to the warpage of the wafer 100.

[0068] The spacing d between two adjacent annular ion implantation regions 104 is greater than 0 and less than half of the diameter D1 of the wafer 100, i.e., 0 < d < 1 / 2D1.

[0069] The radial width W of the annular ion implantation region 104 is greater than 0 and less than or equal to nine-twentieths of the diameter D1 of the wafer 100, i.e., 0 < W ≤ 9 / 20D1.

[0070] It should be noted that in this embodiment, wafer 100 can be a SiC wafer or a wafer made of other materials.

[0071] This embodiment provides a method for improving wafer warpage. Ion implantation is performed on the back side 102 of wafer 100 to form several annular ion implantation regions 104 spaced apart and centered on the center of wafer 100. This allows the stress generated by back-side ion implantation to cancel out the stress generated by front-side ion implantation or etching processes. The radial width W of each annular ion implantation region 104 increases with its distance from the center of wafer 100. This method can precisely eliminate wafer warpage caused by front-side processes, avoiding significant impact on subsequent processes. This method fully considers the distribution of wafer warpage, specifically improving wafer warpage without causing reverse wafer warpage. This method is simple, convenient, low-cost, and easy to implement.

[0072] Example 2

[0073] Please see Figure 9 The SiC semiconductor device fabrication method of this embodiment includes the following steps:

[0074] Step S201: Provide a wafer.

[0075] The wafer can be (but is not limited to) a SiC wafer.

[0076] Step S202: Perform ion implantation or etching on the front side of the wafer to form the front structure required to constitute a semiconductor device; wherein the wafer warps downward at its edges due to the ion implantation or etching process performed on its front side, and the warping at each location of the wafer increases with the increase of the distance between it and the center of the wafer.

[0077] Specifically, ion implantation is performed on the front side of the wafer to form the source region or well region of a semiconductor device, or etching is performed on the front side of the wafer to form the gate structure or interlayer dielectric layer of a semiconductor device.

[0078] After ion implantation or etching on the front side, the warpage distribution of the wafer is as follows: there is basically no warpage at the center of the wafer, and the warpage gradually increases with distance from the center, forming an inverted "bowl" shape. The front side of the wafer is a raised surface, and the back side is a recessed surface.

[0079] Step S203: Ion implantation is performed on the back side of the wafer to form a plurality of annular ion implantation regions spaced apart from the center of the wafer, thereby canceling out the stress generated by the back side ion implantation and the front side ion implantation or etching process; wherein, the radial width W of each annular ion implantation region increases as the distance between it and the center of the wafer increases.

[0080] It should be noted that the schematic diagram of wafer warpage and back-side ion implantation process in this embodiment can be found in Embodiment 1.

[0081] Specifically, step S203 includes the following steps:

[0082] S203a: Deposit a mask layer on the back side of the wafer;

[0083] S203b: The mask layer is patterned to form a mask pattern; wherein the mask pattern includes a circular first pattern located at the center of the wafer, and a plurality of annular second patterns arranged at intervals with the center of the wafer as the center, the second patterns being located around the first pattern and spaced apart from the first pattern;

[0084] S203c: Using the mask pattern as an ion implantation mask, ion implantation is performed on the back side of the wafer to form a plurality of annular ion implantation regions spaced apart from the center of the wafer on the back side, thereby canceling out the stress generated by the back side ion implantation and the front side ion implantation or etching process.

[0085] S203d: Remove the mask pattern.

[0086] Before the mask layer is deposited on the back side of the wafer, the wafer needs to be cleaned by RCA.

[0087] The thickness of the mask layer is greater than 1 micrometer.

[0088] In the back-side ion implantation step, the implanted ions can be N-type or P-type. The implantation dose for back-side ion implantation is 1E¹¹ / cm². 2 Up to 1E16 / cm 2 The injected energy ranges from 50 keV to 1000 keV.

[0089] There is no ion implantation at the center of the wafer. Ion implantation in a local area on the back side of the wafer will generate a certain stress on the back side. This stress is opposite in direction to the stress brought by the front side process, and they can cancel each other out, thereby eliminating wafer stress and ultimately improving wafer warpage.

[0090] Furthermore, since the warpage and stress increase with distance from the wafer center, the radial width W of the back-side ion implantation ring region is designed to gradually increase from the wafer center to the wafer edge. This design method generates stress on the back side of the wafer that gradually increases with distance from the wafer center, consistent with the stress distribution on the front side of the wafer. It fully considers the distribution of wafer warpage and can accurately offset the stress on the front side of the wafer, preventing stress overcompensation that could lead to reverse wafer warpage.

[0091] In the formed annular ion implantation region, the inner diameter D2 (i.e., the diameter of the first pattern) of the annular ion implantation region closest to the center of the wafer is greater than or equal to one-tenth of the wafer diameter D1 and less than or equal to one-half of the wafer diameter D1, i.e., 1 / 10D1≤D2≤1 / 2D1.

[0092] The spacing d between any two adjacent annular ion implantation regions can be equal, meaning that the annular ion implantation regions are equally spaced. Alternatively, the spacing d between any two adjacent annular ion implantation regions can be unequal. The spacing between two adjacent annular ion implantation regions can increase as the distance between the region (the two adjacent annular ion implantation regions) and the center of the wafer increases, and can be specifically designed according to the wafer warpage.

[0093] The spacing d between two adjacent annular ion implantation regions is greater than 0 and less than half of the wafer diameter D1, i.e., 0 < d < 1 / 2D1.

[0094] The radial width W of the annular ion implantation region is greater than 0 and less than or equal to nine-twentieths of the wafer diameter D1, i.e., 0 < W ≤ 9 / 20D1.

[0095] Step S204: Return to the step of performing ion implantation or etching on the front side of the wafer until all ion implantation and etching processes that need to be performed on the front side of the wafer are completed.

[0096] That is, determine whether all the ion implantation and etching processes that need to be performed on the front side of the wafer have been completed. If not, return to step S202; if completed, execute step S205.

[0097] In other words, in this embodiment, after each ion implantation or etching process on the front side of the wafer, back-side ion implantation is performed to improve wafer warpage and thus prevent wafer warpage from affecting subsequent processes. That is, multiple back-side ion implantations are required throughout the entire fabrication process. Furthermore, before each front-side ion implantation or etching process, steps such as film deposition and photolithography may also be included.

[0098] Of course, wafer warpage can also be monitored during the front-side process. When the wafer warpage reaches a preset threshold (the maximum acceptable warpage for subsequent processes), the aforementioned back-side ion implantation process to improve wafer warpage is performed, and then the subsequent front-side processes continue, and so on, until all front-side processes are completed. Alternatively, the back-side ion implantation process can be performed after all front-side processes are completed. This can be configured according to actual needs.

[0099] Step S205: Thin the back side of the wafer to remove the annular ion implantation region and retain the wafer of a preset thickness.

[0100] In other words, the annular ion implantation region on the back side of the wafer can be removed during the wafer thinning process. The wafer thinning process usually uses chemical mechanical polishing, which generates less stress during the thinning process and will not cause wafer warping.

[0101] Typically, wafer backside thinning is performed after all frontside processes (including but not limited to ion implantation and etching) to thin the wafer to the desired thickness. In this embodiment, after all frontside processes (including but not limited to ion implantation and etching) are completed, the backside annular ion implantation region (formed to improve wafer warpage) is removed during wafer thinning, so that the backside annular ion implantation region does not affect the structure of the semiconductor device.

[0102] This embodiment provides a semiconductor device fabrication method. After the front-side ion implantation or etching process of a wafer, ion implantation is performed on the back side of the wafer to form several annular ion implantation regions spaced apart and centered on the wafer's center. This allows the stress generated by the back-side ion implantation to cancel out the stress generated by the front-side ion implantation or etching process. The radial width of each annular ion implantation region increases with its distance from the wafer's center. The back side of the wafer is then thinned to remove the annular ion implantation regions, retaining a wafer of a predetermined thickness. This method can precisely eliminate wafer warpage caused by the front-side process, avoiding significant impact on subsequent processes. This method fully considers the distribution of wafer warpage, specifically improving wafer warpage without causing reverse wafer warpage. The method is simple, convenient, low-cost, and easy to implement.

[0103] The above description is merely a preferred embodiment of this disclosure and is not intended to limit this disclosure. Various modifications and variations can be made to this disclosure by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

[0104] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit this disclosure. Any person skilled in the art to which this disclosure pertains may make any modifications and changes in form and detail of the implementation without departing from the spirit and scope of this disclosure; however, the scope of protection of this disclosure shall still be determined by the scope defined in the appended claims.

Claims

1. A method for improving wafer warpage, characterized in that, include: A warped wafer is provided; wherein the wafer warps downward at its edges due to an ion implantation or etching process performed on its front side, and the degree of warping at each location of the wafer increases with the increase of the distance between itself and the center of the wafer; Ion implantation is performed on the back side of the wafer to form a plurality of annular ion implantation regions spaced apart from the center of the wafer, thereby canceling out the stress generated by the back side ion implantation and the front side ion implantation or etching process; wherein, the radial width of each annular ion implantation region increases as the distance between it and the center of the wafer increases; the radial width of the annular ion implantation region is positively correlated with the warpage at various locations of the wafer; The inner diameter of the annular ion implantation region closest to the center of the wafer is greater than or equal to one-tenth of the wafer diameter and less than or equal to one-half of the wafer diameter; the spacing between two adjacent annular ion implantation regions is greater than 0 and less than one-half of the wafer diameter; the radial width of the annular ion implantation region is greater than 0 and less than or equal to nine-twentieths of the wafer diameter.

2. The method for improving wafer warpage according to claim 1, characterized in that, The spacing between any two adjacent annular ion implantation regions is equal.

3. The method for improving wafer warpage according to claim 1, characterized in that, The spacing between two adjacent annular ion implantation regions increases as their distance from the center of the wafer increases.

4. The method for improving wafer warpage according to claim 1, characterized in that, Ion implantation is performed on the back side of the wafer to form a plurality of annular ion implantation regions spaced apart from the center of the wafer, thereby canceling out the stress generated by the back side ion implantation and the front side ion implantation or etching process. This includes the following steps: A mask layer is deposited on the back side of the wafer; The mask layer is patterned to form a mask pattern; wherein the mask pattern includes a circular first pattern located at the center of the wafer, and a plurality of annular second patterns arranged at intervals with the center of the wafer as the center, the second patterns being located around the first pattern and spaced apart from the first pattern; Using the mask pattern as an ion implantation mask, ion implantation is performed on the back side of the wafer to form several annular ion implantation regions spaced apart from the center of the wafer on the back side, thereby canceling out the stress generated by the back side ion implantation and the front side ion implantation or etching process. Remove the mask pattern.

5. A method for fabricating a semiconductor device, characterized in that, include: Provide one wafer; An ion implantation or etching process is performed on the front side of the wafer to form a front structure required to constitute a semiconductor device; wherein the wafer warps downward at its edges due to the ion implantation or etching process performed on its front side, and the degree of warping at each location of the wafer increases with the increase of the distance between the location and the center of the wafer. Ion implantation is performed on the back side of the wafer to form a plurality of annular ion implantation regions spaced apart from the center of the wafer, thereby canceling out the stress generated by the back side ion implantation and the front side ion implantation or etching process; wherein, the radial width of each annular ion implantation region increases as the distance between it and the center of the wafer increases; the radial width of the annular ion implantation region is positively correlated with the warpage at various locations of the wafer; Return to the step of performing ion implantation or etching on the front side of the wafer until all ion implantation and etching processes that need to be performed on the front side of the wafer are completed; The back side of the wafer is thinned to remove the annular ion implantation region and retain the wafer of a predetermined thickness; The inner diameter of the annular ion implantation region closest to the center of the wafer is greater than or equal to one-tenth of the wafer diameter and less than or equal to one-half of the wafer diameter; the spacing between two adjacent annular ion implantation regions is greater than 0 and less than one-half of the wafer diameter; the radial width of the annular ion implantation region is greater than 0 and less than or equal to nine-twentieths of the wafer diameter.

6. The semiconductor device fabrication method according to claim 5, characterized in that, The spacing between any two adjacent annular ion implantation regions is equal.

7. The semiconductor device fabrication method according to claim 5, characterized in that, The spacing between two adjacent annular ion implantation regions increases as their distance from the center of the wafer increases.

8. The semiconductor device fabrication method according to claim 5, characterized in that, Ion implantation is performed on the back side of the wafer to form a plurality of annular ion implantation regions spaced apart from the center of the wafer, thereby canceling out the stress generated by the back side ion implantation and the front side ion implantation or etching process. This includes the following steps: A mask layer is deposited on the back side of the wafer; The mask layer is patterned to form a mask pattern; wherein the mask pattern includes a circular first pattern located at the center of the wafer, and a plurality of annular second patterns arranged at intervals with the center of the wafer as the center, the second patterns being located around the first pattern and spaced apart from the first pattern; Using the mask pattern as an ion implantation mask, ion implantation is performed on the back side of the wafer to form several annular ion implantation regions spaced apart from the center of the wafer on the back side, thereby canceling out the stress generated by the back side ion implantation and the front side ion implantation or etching process. Remove the mask pattern.

9. A semiconductor device, characterized in that, It is prepared by the method described in any one of claims 5 to 8.

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