Trench field effect transistor having longitudinal p-type source region and method of manufacturing the same

Abstract

The application provides a trench field effect transistor with longitudinal P-type source region, comprising: a substrate region, a drift region, a base region, a source region, a first trench region, a drain and a source; the drift region is connected with the substrate region, the direction of the substrate region pointing to the drift region is upward, the base region and the source region are sequentially arranged above the drift region; the first trench region is arranged at the side of the base region and is connected with the drift region, the base region and the source region respectively; the control gate and the shielding gate are sequentially arranged in the first trench region from top to bottom and are separated by the first insulating layer; the control gate is connected with the base region and the source region through the first insulating layer respectively, the shielding gate is connected with the drift region through the insulating layer; the N-type source region is arranged above the base region, and the P-type source region is arranged at the side opposite to the first trench region of the base region.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power semiconductor devices, in particular to a trench field effect transistor with longitudinal P-type source region and a preparation method thereof. BACKGROUND

[0002] Split Gate Trench (SGT) has been widely applied in important low-voltage fields such as power management. SGT has high channel density and good charge compensation effect. In addition, its shield gate structure effectively isolates the coupling between the control gate and the drain, thereby significantly reducing the transmission capacitance.

[0003] Therefore, SGT has lower specific on-resistance, smaller on-resistance and switching loss, and higher working frequency.

[0004] However, in the conventional SGT device, in order to suppress the substrate floating effect in the SGT device, a P-type doped source region and an N-type doped source region are arranged above the base region in the SGT. However, this arrangement of the source region causes two problems, the first of which is that sufficient area needs to be reserved above the base region to form the source region, thereby increasing the cross section of the SGT device; the second of which is that when the transistor is in forward high-voltage blocking or forward high-voltage conduction, the hole current flows through the base region channel to form a hole current sufficient to turn on the parasitic transistor, triggering the opening of the transistor.

[0005] Therefore, in order to reduce the cross section of the SGT device and improve the avalanche resistance of the SGT device, it is necessary to design a new type of shield gate trench field effect transistor with a source region structure. SUMMARY

[0006] In order to overcome the problems in the related art, the present application provides a trench field effect transistor with longitudinal P-type source region, comprising: a substrate region 1, a drift region 2, a base region 3, a source region 4, a first trench region 5, a drain 6 and a source 7.

[0007] The drift region 2 is connected to the substrate region 1, and the direction of the substrate region 1 pointing to the drift region 2 is upward, and the base region 3 and the source region 4 are sequentially arranged above the drift region 2.

[0008] The first trench region 5 is arranged on the side of the base region 3 and is connected to the drift region 2, the base region 3 and the source region 4, respectively.

[0009] The first trench area 5 comprises a shield gate 51, a control gate 52, a first insulating layer 53 and a metal gate; the control gate 52 and the shield gate 51 are sequentially arranged from top to bottom in the first trench area 5 and are separated by the first insulating layer 53; the control gate 52 is connected with the base area 3 and the source area 4 respectively through the first insulating layer 53, and the shield gate 51 is connected with the drift area 2 through the insulating layer;

[0010] The source area 4 is composed of an N-type source area 41 and a P-type source area 42, and the source area 4 is connected with the base area 3;

[0011] The N-type source area 41 is arranged above the base area 3, and the P-type source area 42 is arranged on the side opposite to the first trench area 5 of the base area 3; the source electrode 7 is connected with the source area 4; the drain electrode 6 is arranged below the substrate area 1; and the metal gate is arranged above the control gate 52.

[0012] In an embodiment, the trench type field effect transistor with longitudinal P-type source area further comprises a second trench area 8;

[0013] The second trench area 8 is arranged on the side opposite to the first trench area 5 of the base area 3, and the second trench area 8 is provided with a second insulating layer 81, the P-type source area 42 and the source electrode 7; the second insulating layer 81 and the source electrode 7 are sequentially arranged from bottom to top in the second trench area 8; the lower side of the second insulating layer 81 is connected with the drift area 2; and the side of the second insulating layer 81 is connected with the drift area 2;

[0014] The lower side of the source electrode 7 is connected with the second insulating layer 81; and the P-type source area 42 is arranged between the base area 3 and the source electrode 7.

[0015] In an embodiment, the cross section of the source electrode 7 is in "L" shape, and the source electrode 7 surrounds the source area 4.

[0016] In an embodiment, the doping concentration of the P-type source area 42 and the N-type source area 41 is heavy doping concentration.

[0017] In an embodiment, the doping type of the substrate area 1 is N-type doping, and the doping concentration of the substrate area 1 is heavy doping concentration;

[0018] The doping type of the drift area 2 is N-type doping, and the doping concentration of the drift area 2 is light doping concentration;

[0019] The doping type of the base area 3 is P-type doping, and the doping concentration of the base area 3 is medium doping concentration;

[0020] The doping concentration of the source region 4 is a heavily doped concentration; the doping concentration of the control gate 52 is a heavily doped concentration.

[0021] A second aspect of this application provides a method for fabricating a trench field-effect transistor with a vertical P-type source region, used to fabricate the trench field-effect transistor with a vertical P-type source region as described in any one of the first aspects of this application, comprising:

[0022] The substrate region is prepared using semiconductor materials;

[0023] A drift region is epitaxially formed on the substrate region;

[0024] A matrix region is formed on the drift region by ion implantation or diffusion.

[0025] An N-type source region is formed on the substrate region using an N-type doped semiconductor material;

[0026] A first trench is etched on one side of the drift region, the substrate region, and the source region;

[0027] Oxide, polysilicon, oxide and polysilicon are sequentially deposited in the first trench to form a shielding gate, a first insulating layer and a control gate; a metal gate is formed above the first trench.

[0028] A second trench is etched on the side of the drift region opposite to the first trench;

[0029] Within the second trench, a P-type source region is formed on the side of the substrate region by ion implantation; the P-type source region is connected above the N-type source region; the P-type source region and the N-type source region constitute a source region;

[0030] A source electrode is formed above the N-type source region and to the side of the P-type source region;

[0031] The drain is fabricated below the substrate region.

[0032] In one embodiment, prior to forming a P-type source region laterally to the substrate region via ion implantation, the method includes:

[0033] At the bottom of the second trench, an oxide layer is formed into a second insulating layer by ion implantation.

[0034] In one embodiment, forming a source electrode above and to the side of the source region includes:

[0035] The source electrode is formed by depositing metal above the second insulating layer; the source electrode connects the N-type source region and the P-type source region.

[0036] The technical solution provided in this application may include the following beneficial effects:

[0037] The first trench region is used to form a shield gate and a control gate. In the second trench region, a P-type source region is formed by P-type doping on the side of the base region, and an N-type source region is arranged above the base region. Therefore, the source region composed of the P-type source region and the N-type source region surrounds the base region from above and from the side. By the longitudinal P-type source region structure, the area above the base region can be used only to form the N-type source region. Therefore, the trench field effect transistor with the longitudinal P-type source region provided by the embodiment of the present application has a smaller cross section, and can further reduce the volume of the transistor.

[0038] It should be understood that the general description above and the following detailed description are only exemplary and explanatory, and cannot limit the present application. BRIEF DESCRIPTION OF DRAWINGS

[0039] The above and other objects, features and advantages of the present application will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings in which like reference characters refer to like parts throughout the figures, and in which:

[0040] Figure 1 is a structure schematic diagram of a trench field effect transistor with a longitudinal P-type source region shown in an embodiment of the present application;

[0041] Figure 2 is a structure schematic diagram of a trench field effect transistor of prior art shown in an embodiment of the present application;

[0042] Figure 3 is a flow schematic diagram of a preparation method of a trench field effect transistor with a longitudinal P-type source region shown in an embodiment of the present application;

[0043] Figure 4 is another flow schematic diagram of a preparation method of a trench field effect transistor with a longitudinal P-type source region shown in an embodiment of the present application. DETAILED DESCRIPTION

[0044] The preferred embodiments of the present application will be described in detail with reference to the drawings. Although the preferred embodiments of the present application are shown in the drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided to make the present application more thorough and complete, and to fully convey the scope of the present application to those skilled in the art.

[0045] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting. As used in this application and the appended claims, the singular forms "a," "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0046] It should be understood that, although the terms "first," "second," "third," etc. can be used herein to describe various information, the information should not be limited by these terms. These terms are only used to distinguish one piece of information from another. For example, a first information can also be termed a second information, similarly, a second information can also be termed a first information, without departing from the scope of the present application. Therefore, the features defined with "first," "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise specifically limited.

[0047] Embodiment one

[0048] To solve the above problems, the embodiment of the present application provides a trench field effect transistor with longitudinal P-type source region.

[0049] Figure 1 is a structural schematic diagram of the trench field effect transistor with longitudinal P-type source region shown in the embodiment of the present application;

[0050] As shown in Figure 1 , the trench field effect transistor with longitudinal P-type source region shown in the embodiment of the present application comprises:

[0051] a substrate region 1, a drift region 2, a base region 3, a source region 4, a first trench region 5, a drain 6 and a source 7;

[0052] The drift region 2 is connected with the substrate region 1, the direction of the substrate region 1 pointing to the drift region 2 is upward, the base region 3 and the source region 4 are sequentially arranged above the drift region 2;

[0053] The first trench region 5 is arranged at the side of the base region 3 and is connected with the drift region 2, the base region 3 and the source region 4 respectively;

[0054] The first trench area 5 comprises a shield gate 51, a control gate 52, a first insulating layer 53 and a metal gate; the control gate 52 and the shield gate 51 are sequentially arranged from top to bottom in the first trench area 5 and are separated by the first insulating layer 53; the control gate 52 is connected with the base area 3 and the source area 4 respectively through the first insulating layer 53, and the shield gate 51 is connected with the drift area 2 through the insulating layer;

[0055] The source area 4 is composed of an N-type source area 41 and a P-type source area 42, and the source area 4 is connected with the base area 3.

[0056] The N-type source area 41 is arranged above the base area 3, and the P-type source area 42 is arranged on the side opposite to the first trench area 5 of the base area 3; the source electrode 7 is connected with the source area 4; the drain electrode 6 is arranged below the substrate area 1; and the metal gate is arranged above the control gate 52.

[0057] In the embodiment of the present application, the substrate area 1 is N-type doped, and the doping concentration of the substrate area 1 is a heavy doping concentration; the drift area 2 is N-type doped, and the doping concentration of the drift area 2 is a light doping concentration; the base area 3 is P-type doped, and the doping concentration of the base area 3 is a medium doping concentration; the doping concentration of the source area 4 is a heavy doping concentration; and the doping concentration of the control gate 52 is a heavy doping concentration, and the doping type of the control gate 52 is P-type or N-type doping.

[0058] In the embodiment of the present application, the light doping concentration ranges from 1×10 15 cm -3 to 5×10 16 cm -3 ; the medium doping concentration ranges from 1×10 17 cm -3 to 5×10 18 cm -3 ; and the heavy doping concentration ranges from 1×10 19 cm -3 to 5×10 20 cm -3 .

[0059] In the embodiment of the present application, the doping type of the shield gate is P-type doping or N-type doping.

[0060] Further, the doping concentration of the doping type of the shield gate can be a heavy doping concentration or a medium doping concentration.

[0061] The embodiment of the present application forms a first groove area and a second groove area on two sides of the base area by grooving. The first groove area is used to form a shielding gate and a control gate. Meanwhile, in the second groove area, a P-type source area is formed by P-type doping on the side of the base area, and an N-type source area is arranged above the base area. Therefore, the source area composed of the P-type source area and the N-type source area surrounds the base area on the top and the side. By the longitudinal P-type source area structure, the top of the base area can be used only to form the N-type source area. Therefore, the trench type field effect transistor with the longitudinal P-type source area provided by the embodiment of the present application has a smaller cross section, and can further reduce the volume of the transistor.

[0062] Embodiment two

[0063] Based on the trench type field effect transistor with the longitudinal P-type source area in the embodiment one, since the source is arranged on the side of the base area, when the SGT is in the forward blocking, the power lines emitted by the positive charge of the depletion layer point to the source, which causes the breakdown voltage between the drift area and the source to be lower than the standard breakdown voltage of the SGT.

[0064] Therefore, in order to improve the breakdown voltage of the trench type field effect transistor with the longitudinal P-type source area, the embodiment of the present application further provides another trench type field effect transistor with the longitudinal P-type source area, as shown in Figure 1 , which comprises:

[0065] a substrate area 1, a drift area 2, a base area 3, a source area 4, a first groove area 5, a drain 6 and a source 7;

[0066] The drift area 2 is connected with the substrate area 1, the base area 3 and the source area 4 are arranged in sequence above the drift area 2, and the direction in which the substrate area 1 points to the drift area 2 is the top;

[0067] The first groove area 5 is arranged on the side of the base area 3 and is connected with the drift area 2, the base area 3 and the source area 4 respectively;

[0068] The first groove area 5 comprises a shielding gate 51, a control gate 52, a first insulating layer 53 and a metal gate, the control gate 52 and the shielding gate 51 are arranged in sequence from top to bottom in the first groove area 5 and are separated by the first insulating layer 53, the control gate 52 is connected with the base area 3 and the source area 4 through the first insulating layer 53, and the shielding gate 51 is connected with the drift area 2 through the insulating layer;

[0069] The source area 4 is composed of an N-type source area 41 and a P-type source area 42, and the source area 4 is connected with the base area 3;

[0070] The N-type source region 41 is disposed above the substrate region 3, and the P-type source region 42 is disposed on the side of the substrate region 3 opposite to the first trench region 5; the source electrode 7 is connected to the source region 4; the drain electrode 6 is disposed below the substrate region 1; and the metal gate is disposed above the control gate 52.

[0071] In the actual SGT manufacturing process, the trench field-effect transistor with a vertical P-type source region shown in the embodiments of this application further includes: a second trench region 8;

[0072] In this embodiment of the application, in order to set the P-type source region on the side of the substrate region, a first trench region and a second trench region are etched on both sides of the substrate region respectively.

[0073] Among them, such as Figure 1 As shown, a second insulating layer 81, the P-type source region 42, and the source electrode 7 are disposed within the second trench region 8; the second insulating layer 81 and the source electrode 7 are disposed sequentially from bottom to top within the second trench region 8. The drift region 2 is connected below the second insulating layer 81; the drift region 2 is connected to the side of the second insulating layer 81. Further, since the P-type source region and the N-type source region are respectively disposed on the side and top of the substrate region, the source electrode is deposited on the second insulating layer by ion implantation, and the second insulating layer is connected below the source electrode. Simultaneously, the P-type source region is disposed between the substrate region and the source electrode.

[0074] The source electrode 7 has an "L" shaped cross-section and surrounds the source region 4.

[0075] Figure 2 This is a schematic diagram of the structure of a prior art shielded gate field-effect transistor as shown in the embodiments of this application.

[0076] like Figure 2 As shown, in a traditional SGT, when the transistor is in forward blocking mode, a PN junction is formed at the interface between the drift region and the substrate region. The depletion layer in the PN junction is a high-resistance region, and there exists an electric field pointing from the drift region to the substrate region. Furthermore, due to the non-uniform ionization integral between points A and B in a traditional SGT, the breakdown voltage of the SGT is reduced.

[0077] Therefore, in this embodiment of the application, a second insulating layer is provided in the second trench region.

[0078] Due to the presence of the second insulating layer, the electric field lines emitted from the depletion layer in the drift region cannot directly enter the source, reducing the electric field at point A in the SGT structure while increasing the electric field near point B. The reduction in the electric field strength at point A makes the ionization integral at the boundary between the substrate region and the drift region more uniform, which helps to improve the breakdown voltage of the device.

[0079] Meanwhile, the first groove region and the second groove region are respectively etched on two side surfaces of the base region by means of grooving. The first groove region is used for forming the shield gate and the control gate. Meanwhile, in the second groove region, the side of the base region is formed into a P-type source region by P-type doping, and the N-type source region is arranged above the base region. Therefore, the source region composed of the P-type source region and the N-type source region surrounds the base region above and on the side of the base region. By means of the longitudinal P-type source region structure, the area above the base region can be used only for forming the N-type source region. Therefore, the trench field effect transistor with the longitudinal P-type source region provided in the embodiment has a smaller cross section, and can further reduce the volume of the transistor.

[0080] Embodiment three

[0081] Corresponding to the trench field effect transistor with the longitudinal P-type source region shown in the embodiment one, the application further provides a preparation method of the trench field effect transistor with the longitudinal P-type source region and corresponding embodiments.

[0082] Figure 3 FIG. 1 is a flowchart of the preparation method of the trench field effect transistor with the longitudinal P-type source region provided in the embodiment.

[0083] Referring to Figure 3 , the preparation method of the trench field effect transistor with the longitudinal P-type source region comprises the following steps.

[0084] 301, preparing a substrate region by using a semiconductor material;

[0085] In the embodiment, the substrate region is prepared by using an N-type heavily doped semiconductor material, that is, the doping type of the substrate region is N-type doping, and the doping concentration of the substrate region is a heavily doped concentration.

[0086] 302, epitaxially forming a drift region on the substrate region;

[0087] In the embodiment, different epitaxial processes can be used according to actual needs, including but not limited to: vapour phase epitaxy (VPE) or chemical vapor deposition (CVD).

[0088] 303, forming a base region on the drift region by means of ion implantation or diffusion;

[0089] The ion implantation process is a process of doping silicon material. In actual application, the power device product is placed at one end of the ion implanter, and the doping ion source is arranged at the other end of the ion implanter. At the end of the doping ion source, the doping body atoms are ionized, so as to have a certain charge, and are accelerated to a super-high speed by an electric field, so as to penetrate the surface layer of the product, and use the momentum of the atoms to implant the doping atoms into the power device to form a doping region.

[0090] The diffusion process is a process of doping pure impurity atoms on the surface of silicon material. In actual application, diborane or phosphine is usually used as the ion source, and the pure impurity atoms are doped into the surface of the silicon material by using the intermittent diffusion or replacement diffusion mode.

[0091] It should be noted that the preparation method of the base region is not strictly limited in the embodiments of the present application, and in actual process, the preparation of the base region can be completed according to actual needs by using different processes.

[0092] 304, forming an N-type source region on the base region by using an N-type doped semiconductor material;

[0093] 305, etching a first groove on one side of the drift region, the base region and the source region;

[0094] 306, sequentially depositing oxide, polysilicon, oxide and polysilicon in the first groove to form a shielding gate, a first insulating layer and a control gate; and forming a metal gate above the first groove;

[0095] Preferably, in the embodiments of the present application, oxide, P-type medium-doped polysilicon, oxide and heavily doped polysilicon are sequentially deposited in the groove to form the shielding gate, the insulating layer and the control gate.

[0096] 307, etching a second groove on the side of the drift region opposite to the first groove;

[0097] In the embodiments of the present application, the groove is etched on one side of the drift region by using a photolithography process, and the residual photoresist is removed by wet etching or dry etching.

[0098] 308, forming a P-type source region on the side of the base region in the second groove by ion implantation;

[0099] In the embodiments of the present application, the P-type source region is connected to the N-type source region above the P-type source region; and the P-type source region and the N-type source region form a source region.

[0100] 309, forming a source electrode above the N-type source region and on the side of the P-type source region;

[0101] 310, manufacturing a drain electrode below the substrate region.

[0102] The embodiment of the present application forms the first groove area and the second groove area on the two side surfaces of the base area by grooving. The first groove area is used to form the shield gate and the control gate. Meanwhile, in the second groove area, the side of the base area is formed into a P-type source area by P-type doping, and the N-type source area is arranged above the base area. Therefore, the source area composed of the P-type source area and the N-type source area surrounds the base area above and on the side of the base area. By the longitudinal P-type source area structure, the area above the base area can be used only to form the N-type source area. Therefore, the trench type field effect transistor with the longitudinal P-type source area provided by the embodiment of the present application has a smaller cross section, and can further reduce the volume of the transistor.

[0103] Embodiment four

[0104] Corresponding to the trench type field effect transistor with the longitudinal P-type source area shown in the embodiment two, the present application further provides another preparation method of the trench type field effect transistor with the longitudinal P-type source area.

[0105] Figure 4 The figure is a flow diagram of the preparation method of the trench type field effect transistor with the longitudinal P-type source area shown in the embodiment of the present application.

[0106] Referring to Figure 4 The preparation method of the shield gate trench type field effect transistor comprises the following steps.

[0107] 401, preparing a substrate area with a semiconductor material;

[0108] 402, epitaxially forming a drift area on the substrate area;

[0109] 403, forming a base area on the drift area by ion implantation or diffusion;

[0110] 404, forming an N-type source area on the base area with an N-type doped semiconductor material;

[0111] 405, etching a first groove on one side of the drift area, the base area and the source area;

[0112] 406, sequentially depositing oxide, polysilicon, oxide and polysilicon in the first groove to form a shield gate, a first insulating layer and a control gate; and forming a metal gate above the first groove;

[0113] 407, etching a second groove on the side of the drift area opposite to the first groove;

[0114] 408, forming a second insulating layer by ion implantation of oxide;

[0115] 409. Forming a P-type source region by ion implantation on the side of the substrate region in the second trench;

[0116] In the embodiments of the present application, the P-type source region is connected with the N-type source region above the P-type source region; and the P-type source region and the N-type source region form a source region.

[0117] 410. Depositing metal on the second insulating layer to form the source electrode; the source electrode is connected with the N-type source region and the P-type source region;

[0118] 411. Forming a source electrode on the N-type source region and on the side of the P-type source region;

[0119] 412. Forming a drain electrode below the substrate region.

[0120] In the embodiments of the present application, a second trench is etched on the side of the substrate region, and a second insulating layer is arranged in the second trench. Due to the presence of the second insulating layer, the electric lines emitted by the depletion layer of the drift region are difficult to directly enter the source electrode, which reduces the electric field at point A in the transistor structure and increases the electric field near point B. The reduction of the electric field intensity at point A makes the ionization integral at the junction of the substrate region and the drift region more uniform, which helps to improve the breakdown voltage of the device.

[0121] The above has described the embodiments of the present application, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes are obvious to those skilled in the art without departing from the scope and spirit of the described embodiments. The selection of the terms used herein is intended to best explain the principles, practical application, or improvement of the technology in the market of the embodiments, or to enable other ordinary skilled persons in the art to understand the embodiments disclosed herein.

Claims

1. A trench field-effect transistor having a vertical P-type source region, characterized in that, include: Substrate region (1), drift region (2), substrate region (3), source region (4), first trench region (5), drain (6), and source (7); The drift region (2) is connected to the substrate region (1), with the direction from the substrate region (1) to the drift region (2) as the top, and the substrate region (3) and the source region (4) are sequentially disposed above the drift region (2); The first trench region (5) is located on the side of the substrate region (3) and is connected to the drift region (2), the substrate region (3) and the source region (4) respectively; The first trench region (5) includes a shielding gate (51), a control gate (52), a first insulating layer (53), and a metal gate; the control gate (52) and the shielding gate (51) are arranged sequentially from top to bottom in the first trench region (5) and separated by the first insulating layer (53); the control gate (52) is connected to the substrate region (3) and the source region (4) respectively through the first insulating layer (53), and the shielding gate (51) is connected to the drift region (2) through the insulating layer; The source region (4) is composed of an N-type source region (41) and a P-type source region (42), and the source region (4) is connected to the matrix region (3). The N-type source region (41) is disposed above the substrate region (3), and the P-type source region (42) is disposed on the side of the substrate region (3) opposite to the first trench region (5); the source electrode (7) is connected to the source region (4); the drain electrode (6) is disposed below the substrate region (1); The metal gate is disposed above the control gate (52); It also includes: the second trench area (8); The second trench region (8) is disposed on the side opposite to the first trench region (5) of the substrate region (3), and the second trench region (8) is provided with a second insulating layer (81), the P-type source region (42) and the source electrode (7). The second insulating layer (81) and the source electrode (7) are arranged sequentially from bottom to top in the second trench region (8); The drift region (2) is connected below the second insulating layer (81); the drift region (2) is connected to the side of the second insulating layer (81). The second insulating layer (81) is connected below the source electrode (7); the P-type source region (42) is disposed between the substrate region (3) and the source electrode (7); The cross-section of the source electrode (7) is "L" shaped, and the source electrode (7) surrounds the source region (4). A P-type source region (42) is formed on the side of the substrate region (3) by ion implantation; the P-type source region (42) is connected above the N-type source region (41).

2. The trench field-effect transistor with a vertical P-type source region according to claim 1, characterized in that, The doping concentrations of the P-type source region (42) and the N-type source region (41) are both heavily doped.

3. The trench field-effect transistor with a vertical P-type source region according to claim 1, characterized in that, The substrate region (1) is N-type doped, and the doping concentration of the substrate region (1) is a heavy doping concentration. The drift region (2) is N-type doped, and the doping concentration of the drift region (2) is light doping concentration; The substrate region (3) is P-type doped, and the doping concentration of the substrate region (3) is medium. The doping concentration of the source region (4) is a heavily doped concentration; the doping concentration of the control gate (52) is a heavily doped concentration.

4. A method for fabricating a trench field-effect transistor with a vertical P-type source region, characterized in that, For fabricating a trench field-effect transistor having a vertical P-type source region as described in any one of claims 1 to 3, comprising: The substrate region is prepared using semiconductor materials; A drift region is epitaxially formed on the substrate region; A matrix region is formed on the drift region by ion implantation or diffusion. An N-type source region is formed on the substrate region using an N-type doped semiconductor material; A first trench is etched on one side of the drift region, the substrate region, and the source region; Oxide, polysilicon, oxide and polysilicon are sequentially deposited in the first trench to form a shielding gate, a first insulating layer and a control gate; a metal gate is formed above the first trench. A second trench is etched on the side of the drift region opposite to the first trench; The P-type source region and the N-type source region constitute the source region; A source electrode is formed above the N-type source region and to the side of the P-type source region; The drain is fabricated below the substrate region.

5. The method for fabricating a trench field-effect transistor with a vertical P-type source region according to claim 4, characterized in that, The formation of a source electrode above and to the side of the source region includes: The source electrode is formed by depositing metal above the second insulating layer; the source electrode connects the N-type source region and the P-type source region.

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