Substrate for electronic devices, field-effect transistor, and method for manufacturing a substrate for electronic devices

Abstract

The substrate (1) for electronic devices has a first diamond single crystal layer (2) and a second diamond single crystal layer (4) on top of it. The first diamond single crystal layer (2) has a nitrogen concentration of less than 20 ppb, a boron concentration of less than 0.01 ppb, a surface orientation of (001) plane orientation of ±3.0° or less on the surface (2A), and a surface roughness Ra of 30 nm or less on the surface (2A). The second diamond single crystal layer (4) has a nitrogen concentration of less than 20 ppb, a boron concentration of 2.0 ppb or more and less than 20 ppb, a surface orientation of (001) plane orientation of ±3.0° or less on the surface (4A), a surface roughness Ra of 30 nm or less on the surface (4A), and a thickness of the second diamond single crystal layer (4) is 50 nm or more and 400 nm or less. The surface (4A) is hydrogen-terminated by being covered with hydrogen, and an NO2 adsorption surface (6) is formed by the adsorption of NO2.

Description

[Technical Field]

[0001] The present invention relates to a substrate for electronic devices, a field-effect transistor, and a method for manufacturing an electronic device substrate. This application claims priority based on Japanese Patent Application No. 2024-155348, filed in Japan on September 9, 2024, and the contents of that application are incorporated herein by reference. [Background technology]

[0002] Non-patent document 1 discloses a field-effect transistor 100 using diamond, having the structure shown in Figure 23. This field-effect transistor 100 has a (001) plane orientation CVD-synthesized single-layer diamond single crystal layer 102, and the nitrogen concentration of this diamond single crystal layer 102 is 1 × 10⁻¹⁶ 14 cm -3 (Less than 0.568 ppb), boron concentration is 6 × 10⁻⁶ 15 cm -3 The concentration is approximately 34 ppb. The surface of the diamond single crystal layer 102 is mainly (001) plane orientation, and the surface of the diamond single crystal layer 102 is hydrogen-terminated by hydrogen plasma treatment, and furthermore, NO2 is adsorbed on the hydrogen-terminated surface to form an NO2 adsorption surface 104.

[0003] A source electrode 106 is formed on a first region of the NO2 adsorption surface 104, a gate insulating film 110B and a gate electrode 112 are formed on a second region of the NO2 adsorption surface 104, and a drain electrode 108 is formed on a third region of the NO2 adsorption surface 104, thereby constituting a field-effect transistor 100. The gate insulating film 110B is part of the insulating film 110, and the insulating film 110 has passivation layers 110C and 110A that cover the source electrode 106 and the drain electrode 108. Non-Patent Documents 2 and 3 also describe field-effect transistors with a structure almost identical to that of Non-Patent Document 1.

[0004] By the way, the field effect transistors shown in Non-Patent Documents 1 to 3 all had the following problems.

[0005] (1) Generation of gate leakage current FIG. 24 is a graph linearly showing the relationship between the drain-source voltage (V GS ) and the drain current (I DS ) when the gate-source voltage (V D ) is changed from -3V to 12V in the field effect transistor shown in Non-Patent Documents 1 to 3. As indicated by the arrow in the graph, a positive drain current (I D ) is measured when the drain-source voltage is near 0V. This is the current that flows from the drain electrode 106 to the gate electrode 112 through the gate insulating film 110B in the structure shown in FIG. 23, and is called the gate leakage current. As indicated by the arrow (A) in FIG. 23, when a gate-source voltage is applied in the vicinity of 0V of the drain-source voltage, current flows through the gate insulating film 110B that should originally be an insulator, resulting in this phenomenon. This gate leakage current causes further damage to the gate insulating film 110B during operation and leads to the deterioration of the characteristics of the field effect transistor over time. This problem is also reported in Non-Patent Document 2 and Fig. 2(a) in the document.

[0006] (2) Generation of drain leakage current Also, in the field effect transistors shown in Non-Patent Documents 1 to 3, as shown in FIG. 25 where the drain current is logarithmically displayed, a negative drain current (I GS ) that is not very dependent on the gate-source voltage (V D ) flows in the range where the gate-source voltage is from 0V to 12V. This current is called the drain leakage current. As shown by the arrow (B) in FIG. 23, even when a reverse gate voltage is applied, the drain current does not become zero, so a high ON / OFF current ratio required for power semiconductor applications cannot be obtained. This problem is reported in Fig. 5(a) of Non-Patent Document 2.

[0007] (3) Short operating life Furthermore, in the field-effect transistors as disclosed in Non-Patent Documents 1 to 3, in relation to the above (1) and (2), there was a problem of short operating life. FIG. 26 is a graph of the continuous operation performance of the field-effect transistor published in Non-Patent Document 3, and it is reported in this graph that the life of the field-effect transistor was only 14.3 hours. Thus, in the conventional technology, there was a problem of short life and it could not be put into practical use. In Patent Document 1 and Non-Patent Documents 4 and 5, solutions to these problems have not been obtained.

Prior Art Documents

Patent Documents

[0008]

Patent Document 1

Non-Patent Documents

[0009]

Non-Patent Document 1

Non-Patent Document 2

Non-Patent Document 3

[0010] The present invention has been made in view of the above circumstances, and aims to provide an electronic device substrate, a field-effect transistor, and a method for manufacturing an electronic device substrate that, when used in the manufacture of a field-effect transistor, can suppress the generation of gate leakage current and drain leakage current, improve output characteristics, and manufacture a device with a long operating life. [Means for solving the problem]

[0011] A substrate for an electronic device according to a first aspect of the present invention comprises a first diamond single crystal layer and a second diamond single crystal layer formed on the surface of the first diamond single crystal layer, wherein the first diamond single crystal layer has a nitrogen concentration of 1.0 ppb or more and a boron concentration of 5.0 ppb or more, the absolute value of the tilt angle of the surface orientation of the first diamond single crystal layer from the (001) plane orientation is 3.0° or less, and the surface roughness Ra of the surface of the first diamond single crystal layer is less than 30 nm. The second diamond single crystal layer has a nitrogen concentration of less than 0.1 ppb and a boron concentration of less than 5.0 ppb, and the second diamond single crystal layerThe surface orientation of the second diamond single crystal has an absolute value of 3.0° or less of the inclination angle from the (001) plane orientation. layer The surface roughness Ra of the aforementioned surface is 30 nm or less, the thickness of the second diamond single crystal layer is 50 nm or more and 1600 nm or less, the surface of the second diamond single crystal layer is hydrogen-terminated by being covered with hydrogen and has p-type conductivity, and an NO2 adsorption surface is formed on the hydrogen-terminated surface of the second diamond single crystal layer by adsorption of NO2.

[0012] According to the first embodiment, an extremely thin second diamond single crystal layer with a thickness of 50 nm or more and 1600 nm or less is formed on a first diamond single crystal layer with high nitrogen and boron concentrations. By setting the nitrogen concentration of this second diamond single crystal layer to less than 0.1 ppb, the boron concentration to less than 5.0 ppb, the plane orientation to mainly be (001) plane orientation, and the surface roughness Ra to 30 nm or less, a channel, which is a region through which the current flowing between the drain and source passes, can be formed in the second diamond single crystal layer when, for example, a field-effect transistor is manufactured using an electronic device substrate. By forming a channel in the second diamond single crystal layer having an impurity concentration, surface roughness, and thickness that makes it difficult for gate leakage current to flow, it is possible to suppress gate leakage current and drain leakage current, thereby improving output characteristics and extending the lifespan of the field-effect transistor. Furthermore, by defining the impurity concentration, plane orientation, and surface roughness Ra of the first diamond single crystal layer as described above, it becomes easy to form such a high-purity and high-precision second diamond single crystal layer.

[0013] In the first embodiment, more preferably, the first diamond single crystal layer has a nitrogen concentration of 2.0 ppb or more and 1000 ppb or less, a boron concentration of 6.0 ppb or more and 50 ppb or less, and the surface roughness Ra of the surface of the first diamond single crystal layer is less than 20 nm. The second diamond single crystal layer has a nitrogen concentration of 0.01 ppb or more and less than 0.1 ppb, and a boron concentration of 0.01 ppb or more and less than 5.0 ppb, and the second diamond single crystal layer The surface roughness Ra of the aforementioned surface may be 20 nm or less, and the thickness of the second diamond single crystal layer may be 50 nm or more and 400 nm or less.

[0014] A substrate for an electronic device according to a second aspect of the present invention comprises a first diamond single crystal layer and a second diamond single crystal layer formed on the surface of the first diamond single crystal layer, wherein the first diamond single crystal layer has a nitrogen concentration of 0.1 ppb or more and a boron concentration of 1.0 ppb or more, the absolute value of the tilt angle of the surface orientation of the first diamond single crystal layer from the (001) plane orientation is 3.0° or less, and the surface roughness Ra of the surface of the first diamond single crystal layer is 30 nm or less. The second diamond single crystal layer has a nitrogen concentration of less than 0.1 ppb and a boron concentration of less than 1.0 ppb, and the second diamond single crystal layer The surface orientation of the second diamond single crystal has an absolute value of 3.0° or less of the inclination angle from the (001) plane orientation. layer The surface roughness Ra of the aforementioned surface is 30 nm or less, the thickness of the second diamond single crystal layer is 50 nm or more and 400 nm or less, the surface of the second diamond single crystal layer is hydrogen-terminated by being covered with hydrogen and has p-type conductivity, and furthermore, an NO2 adsorption surface is formed on the hydrogen-terminated surface of the second diamond single crystal layer by adsorption of NO2.

[0015] According to the second embodiment, an extremely thin second diamond single crystal layer with a thickness of 50 nm or more and 400 nm or less is formed on a first diamond single crystal layer with high concentrations of nitrogen and boron. By setting the nitrogen concentration of this second diamond single crystal layer to less than 0.1 ppb, the boron concentration to less than 1.0 ppb, the plane orientation to mainly be (001) plane orientation, and the surface roughness Ra to 30 nm or less, a channel, which is a region through which the current flowing between the drain and source passes, can be formed in the second diamond single crystal layer when, for example, a field-effect transistor is manufactured using an electronic device substrate. By forming a channel in the second diamond single crystal layer having an impurity concentration, surface roughness, and thickness that makes it difficult for gate leakage current to flow, it is possible to suppress gate leakage current and drain leakage current, thereby improving output characteristics and extending the lifespan of the field-effect transistor. Furthermore, by defining the impurity concentration, plane orientation, and surface roughness Ra of the first diamond single crystal layer as described above, it becomes easy to form the high-purity and high-precision second diamond single crystal layer described above.

[0016] In a second embodiment, more preferably, the first diamond single crystal layer has a nitrogen concentration of 0.2 ppb or more and 1000 ppb or less, a boron concentration of 2.0 ppb or more and 50 ppb or less, and the surface roughness Ra of the surface of the first diamond single crystal layer is less than 20 nm. The second diamond single crystal layer has a nitrogen concentration of 0.01 ppb or more and less than 0.1 ppb, and a boron concentration of 0.01 ppb or more and less than 1.0 ppb, and the second diamond single crystal layer The surface roughness Ra of the aforementioned surface may be 20 nm or less, and the thickness of the second diamond single crystal layer may be 50 nm or more and 200 nm or less.

[0017] A substrate for an electronic device according to a third aspect of the present invention comprises a first diamond single crystal layer and a second diamond single crystal layer formed on the surface of the first diamond single crystal layer, wherein the first diamond single crystal layer has a nitrogen concentration of less than 20 ppb and a boron concentration of less than 0.01 ppb, the absolute value of the tilt angle of the surface orientation of the first diamond single crystal layer from the (001) plane orientation is 3.0° or less, and the surface roughness Ra of the surface of the first diamond single crystal layer is 30 nm or less. The second diamond single crystal layer has a nitrogen concentration of less than 20 ppb and a boron concentration of 2.0 ppb or more and less than 20 ppb, and the second diamond single crystal layer The surface orientation of the second diamond single crystal has an absolute value of 3.0° or less of the inclination angle from the (001) plane orientation. layer The surface roughness Ra of the aforementioned surface is 30 nm or less, the thickness of the second diamond single crystal layer is 50 nm or more and 400 nm or less, the surface of the second diamond single crystal layer is hydrogen-terminated by being covered with hydrogen and has p-type conductivity, and furthermore, an NO2 adsorption surface is formed on the hydrogen-terminated surface of the second diamond single crystal layer by adsorption of NO2.

[0018] According to the third embodiment, a very thin second diamond single crystal layer with a thickness of 50 nm or more and 400 nm or less is formed on a first diamond single crystal layer with high concentrations of nitrogen and boron. By setting the nitrogen concentration of this second diamond single crystal layer to less than 20 ppb, the boron concentration to 2.0 ppb or more and less than 20 ppb, the plane orientation to be mainly (001) plane orientation, and the surface roughness Ra to 30 nm or less, a channel, which is a region through which the current flowing between the drain and source passes, can be formed in the second diamond single crystal layer when, for example, a field-effect transistor is manufactured using an electronic device substrate. By forming a channel in the second diamond single crystal layer having an impurity concentration, surface roughness, and thickness that makes it difficult for gate leakage current to flow, it is possible to suppress gate leakage current and drain leakage current, thereby improving output characteristics and extending the life of the field-effect transistor. Furthermore, by defining the impurity concentration, plane orientation, and surface roughness Ra of the first diamond single crystal layer as described above, it becomes easy to form a second diamond single crystal layer of such high purity and precision.

[0019] More preferably, in the third embodiment, the first diamond single crystal layer has a nitrogen concentration of 0.2 ppb or more and 20 ppb or less, a boron concentration of 0.001 ppb or more and less than 0.01 ppb, and the surface roughness Ra of the surface of the first diamond single crystal layer is less than 20 nm, and the second diamond single crystal layer has a nitrogen concentration of 0.2 ppb or more and less than 20 ppb, a boron concentration of 2.0 ppb or more and 10 ppb or less, and the second diamond single crystal layer The surface roughness Ra of the aforementioned surface is 20 nm or less, and the thickness of the second diamond single crystal layer is 50 nm or more and 200 nm or less. However, it is not limited to these ranges.

[0020] A field-effect transistor according to a fourth aspect of the present invention is characterized by comprising an electronic device substrate according to any of the first to third aspects, a source electrode formed on a first region of the NO2 adsorption surface of the second diamond single crystal layer, a gate insulating film formed on a second region of the NO2 adsorption surface of the second diamond single crystal layer, a gate electrode formed on the gate insulating film, and a drain electrode formed on a third region of the NO2 adsorption surface of the second diamond single crystal layer.

[0021] According to the field-effect transistor of the fourth aspect of the present invention, as described above, by forming a channel in a second diamond single crystal layer having an impurity concentration, surface roughness, and thickness that makes it difficult for gate leakage current to flow, it is possible to suppress gate leakage current and drain leakage current, thereby improving output characteristics and extending the lifespan of the field-effect transistor.

[0022] An integrated circuit element according to a fifth aspect of the present invention is an integrated circuit element comprising an electronic device substrate according to any of the first to third aspects and a plurality of field-effect transistors formed on the electronic device substrate, wherein the field-effect transistor comprises a source electrode formed on a first region of the NO2 adsorption surface of the second diamond single crystal layer, a gate insulating film formed on a second region of the NO2 adsorption surface of the second diamond single crystal layer, a gate electrode formed on the gate insulating film, and a drain electrode formed on a third region of the NO2 adsorption surface of the second diamond single crystal layer.

[0023] In the integrated circuit element according to the fifth aspect of the present invention, gate leakage current can be suppressed by forming a channel in a second diamond single crystal layer having an impurity concentration, surface roughness, and thickness that makes it difficult for gate leakage current to flow. Furthermore, drain leakage current can be suppressed, improving output characteristics and extending the lifespan of the field-effect transistor. This structure also facilitates the integration of the elements.

[0024] A method for manufacturing an electronic device substrate according to a sixth aspect of the present invention is to prepare a first diamond single crystal layer having a nitrogen concentration of 1.0 ppb or more, a boron concentration of 5.0 ppb or more, a surface orientation such that the absolute value of the tilt angle from the (001) plane orientation is 3.0° or less, and a surface roughness Ra of the surface is 30 nm or less, and then, on the first diamond single crystal layer, a reaction gas containing hydrocarbon gas and hydrogen gas, and nitrogen gas and boron gas as dopants is introduced by plasma CVD, while the first diamond The temperature of the single crystal layer is 650°C or higher and 950°C or lower, the pressure of the reaction gas is 40 Torr or higher and 60 Torr or lower, the ratio of the hydrocarbon gas flow rate to the hydrogen gas flow rate (hydrocarbon gas flow rate / hydrogen gas flow rate) is 1:200 to 1:50, the nitrogen concentration is less than 0.1 ppb, the boron concentration is less than 5.0 ppb, the absolute value of the tilt angle of the surface orientation from the (001) plane orientation is 3.0° or less, the surface roughness Ra is 30 nm or less, and the thickness is 50 nm or higher and 1600 nm or less. 2nd The present invention is characterized by forming a diamond single crystal layer, hydrogen-terminating the surface of the second diamond single crystal layer to impart p-type conductivity, contacting the surface of the second diamond single crystal layer with NO2 gas, and adsorbing NO2 onto the hydrogen-terminated surface to form an NO2 adsorption surface.

[0025] A method for manufacturing an electronic device substrate according to a seventh aspect of the present invention is to prepare a first diamond single crystal layer having a nitrogen concentration of 0.1 ppb or more, a boron concentration of 1.0 ppb or more, a surface orientation such that the absolute value of the tilt angle from the (001) plane orientation is 3.0° or less, and a surface roughness Ra of the surface is 30 nm or less. On the first diamond single crystal layer, a reaction gas containing hydrocarbon gas, hydrogen gas, and nitrogen gas and boron gas as dopants is introduced by plasma CVD, while the temperature of the first diamond single crystal layer is set to 650°C or more and 950°C or less, the pressure of the reaction gas is set to 40 Torr or more and 60 Torr or less, and the ratio of the flow rate of the hydrocarbon gas to the flow rate of the hydrogen gas (flow rate of the hydrocarbon gas / flow rate of the hydrogen gas) is set to 1:200 to 1:50. The invention is characterized by forming a second diamond single crystal layer having a nitrogen concentration of less than 0.1 ppb, a boron concentration of less than 1.0 ppb, a surface orientation such that the absolute value of the tilt angle from the (001) plane orientation is 3.0° or less, a surface roughness Ra of 30 nm or less, and a thickness of 50 nm or more and 400 nm or less; hydrogen terminating the surface of the second diamond single crystal layer to impart p-type conductivity; contacting the surface of the second diamond single crystal layer with NO2 gas; and adsorbing NO2 onto the hydrogen-terminated surface to form an NO2 adsorption surface.

[0026] A method for manufacturing an electronic device substrate according to the eighth aspect of the present invention is to prepare a first diamond single crystal layer having a nitrogen concentration of less than 20 ppb, a boron concentration of less than 0.01 ppb, a surface orientation having an absolute value of the tilt angle from the (001) plane orientation of 3.0° or less, and a surface roughness Ra of the surface of 30 nm or less, and then introduce a reaction gas containing hydrocarbon gas, hydrogen gas, and nitrogen gas and boron gas as dopants onto the first diamond single crystal layer by plasma CVD, while maintaining the temperature of the first diamond single crystal layer at 650°C or higher and 950°C or lower, the pressure of the reaction gas at 40 Torr or higher and 60 Torr or lower, and the ratio of the flow rate of the hydrocarbon gas to the flow rate of the hydrogen gas (flow rate of the hydrocarbon gas / flow rate of the hydrogen gas) at 1:200 to 1:50. The invention is characterized by forming a second diamond single crystal layer having a nitrogen concentration of less than 20 ppb, a boron concentration of 2.0 ppb or more and less than 20 ppb, a surface orientation having an absolute value of the tilt angle from the (001) plane orientation of 3.0° or less, a surface roughness Ra of 30 nm or less, and a thickness of 50 nm or more and 400 nm or less; hydrogen terminating the surface of the second diamond single crystal layer to impart p-type conductivity; contacting the surface of the second diamond single crystal layer with NO2 gas; and adsorbing NO2 onto the hydrogen-terminated surface to form an NO2 adsorption surface.

[0027] According to the method for manufacturing an electronic device substrate according to any of the sixth to eighth aspects of the present invention, it is possible to efficiently manufacture an electronic device substrate having the excellent characteristics described above. In the sixth aspect, a more preferred range similar to that of the first aspect is adopted. In the seventh aspect, a more preferred range similar to that of the second aspect is adopted. In the eighth aspect, a more preferred range similar to that of the third aspect is adopted. [Effects of the Invention]

[0028] According to the present invention, by forming a channel in a second diamond single crystal layer having an impurity concentration, surface roughness, and thickness that makes it difficult for leakage current to flow, which is formed on a first diamond single crystal layer having a high concentration of nitrogen and boron, it is possible to suppress gate leakage current and drain leakage current, thereby improving output characteristics and extending the life of the field-effect transistor. Furthermore, by defining the impurity concentration, surface orientation, and surface roughness Ra of the first diamond single crystal layer as described above, it is easy to form a second diamond single crystal layer of such high purity and precision. [Brief explanation of the drawing]

[0029] [Figure 1] This is a cross-sectional enlarged view of a substrate for an electronic device according to an embodiment of the present invention. [Figure 2] This is an enlarged cross-sectional view of a field-effect transistor according to an embodiment of the present invention. [Figure 3] This is an enlarged cross-sectional view showing a method for manufacturing a field-effect transistor according to an embodiment of the present invention. [Figure 4] This is an enlarged cross-sectional view showing a method for manufacturing a field-effect transistor according to an embodiment of the present invention. [Figure 5] This is an enlarged cross-sectional view showing a method for manufacturing a field-effect transistor according to an embodiment of the present invention. [Figure 6] This graph shows the gate leakage characteristics of the field-effect transistor according to Embodiment 1 of the present invention. [Figure 7] This graph shows the drain leakage characteristics of the field-effect transistor in Example 1. [Figure 8] This graph shows the results of the lifespan test of the field-effect transistor in Example 1. [Figure 9] This graph shows the output characteristics of the field-effect transistor in Comparative Example 1. [Figure 10] This graph shows the output characteristics of the field-effect transistor in Comparative Example 2. [Figure 11] This graph shows the output characteristics of the field-effect transistor in Example 2. [Figure 12] This graph shows the output characteristics of the field-effect transistor in Example 3. [Figure 13] This graph shows the output characteristics of the field-effect transistor in Example 4. [Figure 14] This graph shows the output characteristics of the field-effect transistor in Example 5. [Figure 15] This graph shows the output characteristics of the field-effect transistor in Comparative Example 3. [Figure 16] This graph shows the output characteristics of the field-effect transistor in Comparative Example 4. [Figure 17] This graph shows the off-voltage (VBR) characteristics of the field-effect transistors of Examples 2-5 and Comparative Examples 2-4. [Figure 18] This graph shows the ID-to-thickness d-dependent characteristics of the field-effect transistors in Examples 2-5 and Comparative Examples 1-4. [Figure 19] This graph shows the thickness d-dependent characteristics of RON for field-effect transistors in Examples 2-5 and Comparative Examples 1-4. [Figure 20] This graph shows the thickness d-dependent characteristics of the VBR of the field-effect transistors in Examples 2-5 and Comparative Examples 1-4. [Figure 21] This graph shows the gate leakage characteristics of the field-effect transistor in Example 6. [Figure 22] This graph shows the drain leakage characteristics of the field-effect transistor in Example 6. [Figure 23] This is a magnified cross-sectional view of a conventional field-effect transistor. [Figure 24]This graph shows the gate leakage of a field-effect transistor based on conventional technology. [Figure 25] This graph shows the drain leakage of a field-effect transistor based on conventional technology. [Figure 26] This graph shows the service life of a field-effect transistor using conventional technology. [Figure 27] This graph shows the measurement results by secondary ion mass spectrometry, illustrating the depth-direction distribution of nitrogen and boron concentrations in the electronic device substrate 1 of Example 7. [Figure 28] This graph shows the output characteristics of the diamond field-effect transistor in Example 7. [Figure 29] This graph shows the high-frequency small-signal characteristics of the diamond field-effect transistor of Example 7. [Modes for carrying out the invention]

[0030] The following describes embodiments of the electronic device substrate, field-effect transistor, and method for manufacturing the electronic device substrate according to the present invention, using the drawings. Note that the dimensions of the parts shown in the drawings do not reflect the dimensions of the actual product.

[0031] [Electronic device substrate according to the first embodiment] Figure 1 is an enlarged cross-sectional view showing one embodiment of an electronic device substrate according to the present invention, the electronic device substrate 1 having a first diamond single crystal layer 2 and a second diamond single crystal layer 4 formed on the surface of the first diamond single crystal layer 2.

[0032] The first diamond single crystal layer 2 used in the first embodiment has a nitrogen concentration of 1.0 ppb or more and a boron concentration of 5.0 ppb or more. If the nitrogen concentration of the first diamond single crystal layer 2 is less than 1.0 ppb and / or the boron concentration is less than 5.0 ppb, channels will also be formed within the first diamond single crystal layer 2, reducing the effect of forming channels only within the second diamond single crystal layer 4 and increasing the cost of the substrate 1 for electronic devices. The nitrogen concentration of the first diamond single crystal layer 2 may more preferably be 2.0 ppb or more and 1000 ppb or less, and the boron concentration may more preferably be 6.0 ppb or more and 50 ppb or less. Nitrogen concentrations below 20 ppb can be measured using secondary ion mass spectrometry (SIMS), which has a low detection limit, while nitrogen concentrations above 20 ppb can be measured using electron spin resonance (ESR), also known as electron paramagnetic resonance (EPR), which has a relatively high detection limit but good sensitivity.

[0033] The nitrogen and boron concentrations in a diamond single crystal can be measured using well-known secondary ion mass spectrometry (SIMS) or electron spin resonance (ESR) methods.

[0034] The plane orientation of surface 2A of the first diamond single crystal layer 2 is such that the absolute value of the tilt angle from the (001) plane orientation is 3.0° or less. If the absolute value of the tilt angle exceeds 3.0°, it becomes difficult to align the plane orientation of the second diamond single crystal layer 4 to the (001) plane orientation with high precision. The absolute value of the tilt angle may be between 0.3° and 3.0°. For measuring the plane orientation in a diamond single crystal, the backscattered electron diffraction pattern method (EBSP method) using a scanning electron microscope (SEM) can be used.

[0035] The surface roughness Ra of surface 2A of the first diamond single crystal layer 2 is 30 nm or less. If the surface roughness Ra of surface 2A exceeds 30 nm, it becomes difficult to sufficiently reduce the roughness and orientation disorder of surface 4A of the second diamond single crystal layer 4, which may hinder device manufacturing. The surface roughness Ra of surface 2A may more preferably be 20 nm or less. There is no particular lower limit to the surface roughness Ra of surface 2A, but since making it too small incurs extra costs, the surface roughness Ra may be 1.0 nm or more. For measuring the surface roughness of the diamond single crystal, well-known stylus-type surface roughness measuring instruments, non-contact measuring devices such as white light interferometry, and atomic force microscopes can be used.

[0036] The second diamond single crystal layer 4 has a nitrogen concentration of less than 0.1 ppb and a boron concentration of less than 5.0 ppb. If the nitrogen concentration is 0.1 ppb or higher and / or the boron concentration is greater than 5.0 ppb, current will flow through the impurities, and the gate leakage current suppression and / or drain leakage current suppression effect of the second diamond single crystal layer 4 will become insufficient. The nitrogen concentration of the second diamond single crystal layer 4 may more preferably be 0.01 ppb or higher and less than 0.1 ppb, and the boron concentration may more preferably be 0.01 ppb or higher and less than 5.0 ppb.

[0037] The plane orientation of the second diamond single crystal layer 4 has an absolute tilt angle of 3.0° or less from the (001) plane orientation. If the absolute tilt angle exceeds 3.0°, it becomes difficult to ensure high performance as a field-effect transistor. A smaller absolute tilt angle is preferable, but since this is costly, the absolute tilt angle may be 0.3° or more.

[0038] The surface roughness Ra of surface 4A of the second diamond single crystal layer 4 is 30 nm or less. If the surface roughness Ra of surface 4A exceeds 30 nm, it may cause problems in device manufacturing. The surface roughness Ra of surface 4A may more preferably be 20 nm or less. There is no particular lower limit to the surface roughness Ra of surface 4A, but since making it too small would incur extra costs, the surface roughness Ra may be 1.0 nm or more.

[0039] The thickness d of the second diamond single crystal layer 4 is 50 nm or more and 1600 nm or less. If the thickness d is less than 50 nm, it becomes difficult to keep most of the channel within the second diamond single crystal layer 4, and the gate leakage current suppression and / or drain leakage current suppression effect of the present invention becomes insufficient. On the other hand, if the thickness d exceeds 1600 nm, the channel width becomes too large, and again the gate leakage current suppression and / or drain leakage current suppression effect becomes insufficient. The thickness d of the second diamond single crystal layer 4 may more preferably be 50 nm or more and 400 nm.

[0040] The surface 4A of the second diamond single crystal layer 4, for example, by exposure to a hydrogen plasma, is covered with hydrogen atoms, and the ends of the carbon atoms are hydrogen-terminated, resulting in p-type conductivity. In diamond, P acts as a donor and B acts as an acceptor impurity, but their respective ionization energies are 0.58 and 0.37 eV, which are more than an order of magnitude higher than the thermal energy at room temperature (26 meV). Therefore, the ionization rate due to impurities is extremely low, and the carrier concentration necessary for device operation cannot be obtained. By hydrogen-termining the surface 4A of the second diamond single crystal layer 4, the surface 4A acquires p-type conductivity, and the conductivity required for the device is obtained.

[0041] On the surface 4A of the hydrogen-terminated second diamond single crystal layer 4, NO2 is further adsorbed, forming an NO2 adsorption surface 6. By adsorbing NO2 in monomolecular form on the hydrogen-terminated surface 4A, the hole concentration on surface 4A can be significantly increased compared to the case of hydrogen termination alone, thereby obtaining the conductivity required for the device.

[0042] According to the first embodiment of the electronic device substrate 1 having the above configuration, an extremely thin second diamond single crystal layer 4 with a thickness of 50 nm or more and 1600 nm or less is formed on a first diamond single crystal layer 2 with high concentrations of nitrogen and boron. By setting the nitrogen concentration of this second diamond single crystal layer 4 to less than 0.1 ppb, the boron concentration to less than 5.0 ppb, the plane orientation to mainly be (001) plane orientation, and the surface roughness Ra to 30 nm or less, when a field-effect transistor is manufactured using the electronic device substrate 1, for example, a channel, which is the region through which the current flowing between the drain and source passes, can be mainly formed in the second diamond single crystal layer 4. By forming a channel in the second diamond single crystal layer 4 having an impurity concentration, surface roughness, and thickness that makes it difficult for gate leakage current to flow, it is possible to suppress gate leakage current and drain leakage current, thereby improving output characteristics and extending the lifespan of the field-effect transistor. Furthermore, by defining the impurity concentration, surface orientation, and surface roughness Ra of the first diamond single crystal layer 2 as described above, it becomes easier to form the second diamond single crystal layer 4 with the high purity and precision described above.

[0043] [Electronic device substrate according to the second embodiment] Since the electronic device substrate of the second embodiment has the same basic structure as the first embodiment, we will again use Figure 1 to explain it. In this second embodiment, the parameters of each part differ from those of the first embodiment, so we will explain the differences in particular, and refer to the explanation of the first embodiment for other points.

[0044] In the second embodiment, the first diamond single crystal layer 2 has a nitrogen concentration of 0.1 ppb or more and a boron concentration of 1.0 ppb or more. If the nitrogen concentration of the first diamond single crystal layer 2 is less than 0.1 ppb and / or the boron concentration is less than 1.0 ppb, the effect of forming channels only within the second diamond single crystal layer 4 is reduced, and it becomes necessary to specially purify the raw material gas, such as methane gas or hydrogen gas (reduce impurities), which increases the cost of the substrate 1 for electronic devices. More preferably, the nitrogen concentration of the first diamond single crystal layer 2 may be 0.2 ppb or more and 1000 ppb or less, and the boron concentration may be 2.0 ppb or more and 50 ppb or less.

[0045] In the second embodiment, the second diamond single crystal layer 4 has a nitrogen concentration of less than 0.1 ppb and a boron concentration of less than 1.0 ppb. If the nitrogen concentration is 0.1 ppb or higher and / or the boron concentration is 1.0 ppb or higher, current will flow through the impurities, and the gate leakage current suppression and / or drain leakage current suppression effect of the second diamond single crystal layer 4 will be insufficient. The nitrogen concentration of the second diamond single crystal layer 4 may more preferably be 0.01 ppb or higher and less than 0.1 ppb, and the boron concentration may more preferably be 0.01 ppb or higher and less than 1.0 ppb.

[0046] In the second embodiment, the surface orientation and surface roughness Ra of the surface 2A of the first diamond single crystal layer 2 may be the same as in the first embodiment, so the explanation will be used accordingly.

[0047] In the second embodiment, the thickness d of the second diamond single crystal layer 4 is 50 nm or more and 400 nm or less. If the thickness d is less than 50 nm, it becomes difficult to keep most of the channel within the second diamond single crystal layer 4, and the gate leakage current suppression and / or drain leakage current suppression effect of the present invention becomes insufficient. On the other hand, if the thickness d exceeds 400 nm, the channel thickness becomes too large, and again the gate leakage current suppression and / or drain leakage current suppression effect becomes insufficient. The thickness d of the second diamond single crystal layer 4 may more preferably be 50 nm or more and 200 nm or less.

[0048] In the second embodiment, the surface 4A of the second diamond single crystal layer 4 is hydrogen-terminated by being covered with hydrogen, thereby possessing p-type conductivity. Furthermore, NO2 is adsorbed onto the hydrogen-terminated surface 4A, forming an NO2 adsorption surface 6. These configurations are common to those of the first embodiment, so the explanation will be based on that.

[0049] According to the second embodiment, an extremely thin second diamond single crystal layer 4, with a thickness of 50 nm or more and 400 nm or less, is formed on a first diamond single crystal layer 2 with high concentrations of nitrogen and boron. The nitrogen concentration of this second diamond single crystal layer 4 is set to less than 0.1 ppb, the boron concentration to less than 1.0 ppb, the plane orientation is mainly (001) plane orientation, and the surface roughness Ra is set to 30 nm or less. As a result, when a field-effect transistor is manufactured using an electronic device substrate, for example, a channel, which is the region through which the current flowing between the drain and source passes, can be formed in the second diamond single crystal layer 4. By forming a channel in the second diamond single crystal layer 4, which has an impurity concentration, surface roughness, and thickness that makes it difficult for gate leakage current to flow, it is possible to suppress gate leakage current and drain leakage current, thereby improving output characteristics and extending the lifespan of the field-effect transistor. Furthermore, by defining the impurity concentration, surface orientation, and surface roughness Ra of the first diamond single crystal layer 2 as described above, it becomes easier to form the second diamond single crystal layer 4 with the high purity and precision described above.

[0050] [Electronic device substrate according to the third embodiment] The electronic device substrate of the third embodiment has the same basic structure as the first and second embodiments, so we will again use Figure 1 to explain it. In this third embodiment, the parameters of each part differ from those of the first and second embodiments, so we will explain the differences in particular, and refer to the explanations of the first and second embodiments for other points.

[0051] In the third embodiment, the first diamond single crystal layer 2 has a nitrogen concentration of less than 20 ppb and a boron concentration of less than 0.01 ppb. If the nitrogen concentration of the first diamond single crystal layer 2 is 20 ppb or more and / or the boron concentration is 0.01 ppb or more, current will flow through the impurities, reducing the effect of forming channels only within the second diamond single crystal layer 4, and increasing the cost of the substrate 1 for electronic devices. More preferably, the nitrogen concentration of the first diamond single crystal layer 2 may be 0.2 ppb or more and less than 20 ppb, and the boron concentration may be 0.001 ppb or more and less than 0.01 ppb.

[0052] In the third embodiment, the second diamond single crystal layer 4 has a nitrogen concentration of less than 20 ppb and a boron concentration of 2.0 ppb or more and less than 20 ppb. If the nitrogen concentration is 20 ppb or more and / or the boron concentration is less than 2.0 ppb or 20 ppb or more, current will flow through the impurities, and the gate leakage current suppression effect and / or drain leakage current suppression effect of the second diamond single crystal layer 4 will be insufficient. The nitrogen concentration of the second diamond single crystal layer 4 may more preferably be 0.2 ppb or more and less than 20 ppb, and the boron concentration may more preferably be 2.0 ppb or more and 10 ppb or less.

[0053] In the third embodiment, the surface orientation and surface roughness Ra of the surface 2A of the first diamond single crystal layer 2 may be the same as in the first and second embodiments, so their descriptions will be referenced.

[0054] In the third embodiment, the thickness d of the second diamond single crystal layer 4 is 50 nm or more and 400 nm or less. If the thickness d is less than 50 nm, it becomes difficult to keep most of the channel within the second diamond single crystal layer 4, and the gate leakage current suppression and / or drain leakage current suppression effect of the present invention becomes insufficient. On the other hand, if the thickness d exceeds 400 nm, the channel thickness becomes too large, and again the gate leakage current suppression and / or drain leakage current suppression effect becomes insufficient. The thickness d of the second diamond single crystal layer 4 may more preferably be 50 nm or more and 200 nm or less.

[0055] In the third embodiment, the surface 4A of the second diamond single crystal layer 4 is hydrogen-terminated by being covered with hydrogen, thereby possessing p-type conductivity. Furthermore, NO2 is adsorbed onto the hydrogen-terminated surface 4A, forming an NO2 adsorption surface 6. These configurations are common to those of the first and second embodiments, so the explanation will be based on the previous description.

[0056] According to the third embodiment, a very thin second diamond single crystal layer 4, with a thickness of 50 nm or more and 400 nm or less, is formed on a first diamond single crystal layer 2 having a nitrogen concentration of less than 20 ppb and a boron concentration of less than 0.01 ppb. The nitrogen concentration of this second diamond single crystal layer 4 is less than 20 ppb, the boron concentration is 2.0 ppb or more and less than 20 ppb, the surface orientation is mainly (001) orientation, and the surface roughness Ra is 30 nm or less. As a result, when a field-effect transistor is manufactured using an electronic device substrate, for example, a channel, which is the region through which the current flowing between the drain and source passes, can be formed in the second diamond single crystal layer 4. By forming a channel in the second diamond single crystal layer 4, which has an impurity concentration, surface roughness, and thickness that makes it difficult for gate leakage current to flow, it is possible to suppress gate leakage current and drain leakage current, thereby improving output characteristics and extending the lifespan of the field-effect transistor. Furthermore, by defining the impurity concentration, surface orientation, and surface roughness Ra of the first diamond single crystal layer 2 as described above, it becomes easier to form the second diamond single crystal layer 4 with the high purity and precision described above.

[0057] [Field-effect transistor of the fourth embodiment] The field-effect transistor of the fourth embodiment, as shown in Figure 2, is manufactured using an electronic device substrate 1 of any of the first to third embodiments, and comprises a source electrode 8 formed on a first region of the NO2 adsorption surface 6 on the second diamond single crystal layer 4, a gate insulating film 12B formed on a second region of the NO2 adsorption surface 6 of the second diamond single crystal layer 4 that is different from the first region, a gate electrode 14 formed on the gate insulating film 12B, and a drain electrode 10 formed on a third region of the NO2 adsorption surface 6 of the second diamond single crystal layer 4 that is different from the first and second regions. A passivation film 12C is formed on the source electrode 8, and a passivation film 12A is formed on the drain electrode 10. In this embodiment, the passivation film 12A, the gate insulating film 12B, and the passivation film 12C are formed as the same insulating layer 12.

[0058] The shapes of the first to third regions formed on the electronic device substrate 1 may be the same as those of a conventional field-effect transistor, and the shapes of the source electrode 8, gate electrode 14, and drain electrode 10 may also be the same as those of a conventional field-effect transistor. The materials of the source electrode 8, gate electrode 14, and drain electrode 10 may be the same as those of conventional field-effect transistors, for example, Au or Al, and their thickness is not limited, but is generally 50 nm or more and 500 nm or less, and more preferably 100 nm or more and 400 nm or less.

[0059] The material and thickness of the insulating layer 12 may be the same as those of conventional field-effect transistors, and the material of the insulating layer 12 may be, for example, Al2O3, SiO2, HfO2, etc. The thickness of the insulating layer 12 is not limited, but is generally 8 nm or more and 160 nm or less, and more preferably 12 nm or more and 80 nm or less.

[0060] According to the field-effect transistor of the fourth embodiment, as described above, by forming a channel in the second diamond single crystal layer 4 which has an impurity concentration, surface roughness, and thickness that makes it difficult for gate leakage current to flow, it is possible to suppress gate leakage current and drain leakage current, thereby obtaining good output characteristics and extending the life of the field-effect transistor.

[0061] [Integrated circuit of the fifth embodiment] The fifth embodiment of the integrated circuit element comprises an electronic device substrate 1 according to any of the first to third embodiments, and a plurality of field-effect transistors formed on the electronic device substrate 1, wherein each field-effect transistor comprises, similar to the third embodiment, a source electrode 8 formed on a first region of the NO2 adsorption surface 6 of the second diamond single crystal layer 4, a gate insulating film 12B formed on a second region of the NO2 adsorption surface 6 of the second diamond single crystal layer 4, a gate electrode 14 formed on the gate insulating film 12B, and a drain electrode 10 formed on a third region of the NO2 adsorption surface 6 of the second diamond single crystal layer 4. The integrated circuit element may also include other electrical circuit elements (resistors, capacitors, inductors, diodes, other semiconductor elements, wiring, etc.) in addition to field-effect transistors.

[0062] In the fifth embodiment of the integrated circuit element, by forming a channel in the second diamond single crystal layer 4 having an impurity concentration, surface roughness, and thickness that makes it difficult for gate leakage current to flow, it is possible to suppress gate leakage current and drain leakage current, thereby obtaining good output characteristics and extending the lifespan of the field-effect transistor.

[0063] [Manufacturing method for electronic device substrate according to the sixth embodiment] The sixth embodiment of the method for manufacturing an electronic device substrate is a method for manufacturing an electronic device substrate according to the first embodiment, and comprises the steps shown in Figures 3 to 5.

[0064] [Deposition process for the second diamond single crystal layer 4] First, a first diamond single crystal layer 2 is prepared. The first diamond single crystal layer 2 may be a commercially available product or may be fixed on some kind of substrate. The first diamond single crystal layer 2 used in the fifth embodiment has a nitrogen concentration of 1.0 ppb or more, a boron concentration of 5.0 ppb or more, the absolute value of the tilt angle of the surface orientation of surface 2A from the (001) plane orientation is 3.0° or less, and the surface roughness Ra of surface 2A is 30 nm or less. Details and more preferred ranges of the first diamond single crystal layer 2 are described in reference to the description of the first embodiment.

[0065] A second diamond single crystal layer 4 is formed on the surface 2A of the first diamond single crystal layer 2A by plasma CVD, while introducing a reaction gas containing hydrocarbon gases such as CH4, hydrogen gas, and trace amounts of nitrogen and boron gas as dopants, at a temperature of 650°C or higher and 950°C or lower, a reaction gas pressure of 40 Torr or higher and 60 Torr or lower, and a ratio of hydrocarbon gas flow rate to hydrogen gas flow rate (hydrogen gas flow rate / hydrogen gas flow rate) of 1:50 to 1:200. By not introducing nitrogen gas and boron gas into the reaction gas, the nitrogen concentration in the second diamond single crystal layer 4 is set to less than 0.1 ppb, and by adjusting the boron gas concentration in the reaction gas, the boron concentration in the second diamond single crystal layer 4 is set to less than 5.0 ppb.

[0066] The surface orientation of the second diamond single crystal layer 4's surface 4A is controlled to reflect the surface orientation of the first diamond single crystal layer 2, so that the absolute value of the tilt angle from the (001) plane orientation is 3.0° or less. Furthermore, the surface roughness Ra of the surface 4A of the second diamond single crystal layer 4 is controlled to be 30 nm or less, reflecting the surface roughness of the surface 2A of the first diamond single crystal layer 2. The thickness of the second diamond single crystal layer 4 is set to be between 50 nm and 1600 nm by controlling the deposition time. The surface 4A of the second diamond single crystal layer 4 is exposed to hydrogen plasma, causing the carbon atoms on the outermost surface to undergo hydrogen termination, thereby imparting p-type conductivity. Details of the second diamond single crystal layer 4 are described with reference to the description of the first embodiment.

[0067] [1. NO2 doping process / Figure 3(a)] As described above, an NO2 adsorption surface 6 is formed on the hydrogen-terminated second diamond single crystal layer 4. As shown in Figure 3(a), NO2 gas diluted with nitrogen gas is brought into contact with the hydrogen-terminated surface 4A of the second diamond single crystal layer 4, and NO2 is adsorbed onto the hydrogen-terminated surface to form an NO2 adsorption surface 6. The NO2 gas used in this step is diluted with nitrogen gas, and the NO2 gas concentration may be 5 ppm to 10% by volume fraction, and more preferably 1% to 10%. In addition to nitrogen, helium and argon may also be used as dilution gases. The temperature of the second diamond single crystal layer 4 during the reaction is not limited, but may be 0 to 240°C or 10 to 120°C.

[0068] [2. Au deposition process / Figure 3(b)] An Au layer 20, which will serve as an electrode, is formed on the second diamond single crystal layer 4 on which the NO2 adsorption surface 6 is formed. The thickness of the Au layer 20 is adjusted to match the thickness of the source electrode 8 and drain electrode 10 that are to be formed in the end. Details will be described with reference to the third embodiment. Various deposition apparatuses, sputtering apparatuses, etc., can be used to form the Au layer 20.

[0069] [3. Resist spin coating process / Figure 3(c)] A resist layer 22 is formed on the second diamond single crystal layer 4 on which the Au layer 20 is formed, using a spin-coating apparatus. The resist used for the resist layer 22 can be a commonly used type, and the method of forming the resist layer 22 and its thickness can be the same as in conventional semiconductor device manufacturing methods.

[0070] [4. Masking and Development Process / Figure 3(d)] The resist layer 22 is exposed and developed using a photomask having an electrode pattern, using light (g-line to EUV) or an electron beam to etch the solubilized resist removal portion 24 of the resist layer 22, thereby forming an electrode pattern with the remaining resist layer 22. The methods and conditions for exposure, development, and resist removal may be the same as those for conventional semiconductor device manufacturing methods.

[0071] [5. Au etching process / Figure 4(a)] By dissolving the Au layer 20 in the area corresponding to the resist removal section 24 through the resist removal section 24 that constitutes the electrode pattern, and removing the Au from the Au removal section 26, the portions that will become the source electrode 8 and the drain electrode 10 are formed. The method and conditions for dissolving the Au layer 20 may be the same as those for conventional semiconductor device manufacturing methods.

[0072] [6. Resist Removal Process / Figure 4(b)] Remove any remaining resist on the source electrode 8 and drain electrode 10 to expose them.

[0073] [7. Re-NO2 doping process / Figure 4(c)] In areas other than the source electrode 8 and drain electrode 10, NO2 gas diluted with nitrogen gas is brought into contact with the NO2 adsorption surface 6 on the second diamond single crystal layer 4 to increase the NO2 concentration on the NO2 adsorption surface 6 at the contact points. This step is performed to replenish the NO2 that has decreased due to the time elapsed since the initial NO2 doping step. The contact conditions for the NO2 gas may be the same as those described in "1. NO2 Doping Step".

[0074] [8. Al2O3 layer deposition process / Figure 4(d)] An Al2O3 layer is deposited to a certain thickness on the source electrode 8, drain electrode 10, and Au removal section 26 to form an insulating layer 12. Other insulating materials mentioned above may be used instead of Al2O3. This process forms a passivation film 12A on the source electrode 8, a passivation film 12C on the drain electrode 10, and a gate insulating film 12B on the Au removal section 26. The insulating layer 12 is described in the previous explanation.

[0075] [9. Au deposition process / Figure 5(a)] An Au layer 28 is formed on the insulating layer 12 to a certain thickness by a vapor deposition method or sputtering method. The thickness of the Au layer 28 is determined to be the thickness required for the gate electrode 14. The gate electrode 14 is described in the previous explanation.

[0076] [10. Resist Process / Figure 5(b)] A resist layer 30 is formed on the Au layer 28 using a spin-coating apparatus or the like. The resist used for the resist layer 30 can be a commonly used type, and the method of forming the resist layer 30 and its thickness can be the same as in conventional semiconductor device manufacturing methods.

[0077] [11. Masking and Development Process / Figure 5(c)] The resist layer 30 is exposed and developed using a photomask with an electrode pattern, using light (g-line to EUV) or an electron beam to etch the solubilized resist removal portion of the resist layer 30, thereby forming the gate electrode 14 pattern with the remaining resist layer 30. The methods and conditions for exposure, development, and resist removal may be the same as those for conventional semiconductor device manufacturing methods.

[0078] [12. Au Etching Process / Figure 5(d)] The Au layer 28 at the corresponding location is dissolved through the resist removal section that constitutes the pattern of the gate electrode 14, thereby forming the portion that will become the gate electrode 14. The method and conditions for dissolving the Au layer 28 may be the same as those for conventional semiconductor device manufacturing methods.

[0079] According to the manufacturing method of the fifth embodiment having the above configuration, it is possible to efficiently manufacture substrates for electronic devices and field-effect transistors having excellent characteristics, as in the first embodiment.

[0080] [Method for manufacturing an electronic device substrate according to the seventh embodiment] The manufacturing method of the seventh embodiment is a method for manufacturing a substrate for an electronic device according to the second embodiment, and the basic process is the same as that of the manufacturing method of the sixth embodiment, so we will again explain it with reference to Figures 3 to 5. In this seventh embodiment, the parameters of each part differ from those of the sixth embodiment, so we will explain the differences in particular, and refer to the explanation of the sixth embodiment for other points.

[0081] The first diamond single crystal layer 2 used in the manufacturing method for an electronic device substrate according to the seventh embodiment has a nitrogen concentration of 0.1 ppb or more, a boron concentration of 1.0 ppb or more, the absolute value of the tilt angle of the surface orientation of surface 2A from the (001) plane orientation is 3.0° or less, and the surface roughness Ra of surface 2A is 30 nm or less. This point differs from the sixth embodiment. For other manufacturing conditions, refer to the description of the sixth embodiment. For preferred ranges, refer to the description of the second embodiment.

[0082] According to the manufacturing method of the seventh embodiment, it is possible to efficiently manufacture substrates for electronic devices and field-effect transistors having the excellent characteristics described above.

[0083] [Method for manufacturing an electronic device substrate according to the 8th embodiment] The manufacturing method of the eighth embodiment is a method for manufacturing a substrate for an electronic device according to the third embodiment, and the basic process is the same as that of the manufacturing methods of the sixth and seventh embodiments, so we will again explain it with reference to Figures 3 to 5. In this eighth embodiment, the parameters of each part differ from those of the sixth and seventh embodiments, so we will explain the differences in particular, and refer to the explanations of the sixth and seventh embodiments for other points.

[0084] The first diamond single crystal layer 2 used in the manufacturing method for an electronic device substrate according to the eighth embodiment has a nitrogen concentration of less than 20 ppb and a boron concentration of less than 0.01 ppb. This differs from the sixth and seventh embodiments. For other manufacturing conditions, refer to the descriptions of the sixth and seventh embodiments. For preferred ranges, refer to the description of the third embodiment.

[0085] According to the manufacturing method of the eighth embodiment, it is possible to efficiently manufacture substrates for electronic devices and field-effect transistors having the excellent characteristics described above.

[0086] Although embodiments of the present invention have been described above, the present invention is not limited to these embodiments. It is also possible to rearrange the configurations of each embodiment, add other configurations of well-known technologies, or omit some configurations of well-known technologies. [Examples]

[0087] Next, the present invention will be described in more detail with reference to examples, but the present invention is not limited to these examples. For clarity, please refer to the symbols in the figures.

[0088] [Example 1] A diamond single crystal substrate 1 and a field-effect transistor according to Example 1 were manufactured by the following method. An optical-grade first diamond single crystal layer 2 (commercially available) was prepared with a thickness of 500 μm, a nitrogen concentration of 500 ppb, a boron concentration of 25 ppb, a surface 2A orientation of (001) ±1.0°, and a surface roughness Ra of 10 nm for surface 2A. The first diamond single crystal layer 2 did not have a support substrate, and the size of the first diamond single crystal layer 2 was 4.5 mm × 4.5 mm × thickness 0.5 mm.

[0089] The first diamond single crystal layer 2 was placed in a microwave plasma CVD apparatus (product name: SDS-5200, manufactured by Cornes Technology Co., Ltd.), with the temperature of the first diamond single crystal layer 2 set to 750°C, the reaction gas pressure set to 50 Torr, and the CH4 gas flow rate set to 3 ccm(cm).3 The H2 gas flow rate was 300 ccm ( / min), and nitrogen and boron gases were intentionally not used. Under microwave power of 750W, a 100nm thick, substantially nitrogen-free second diamond single crystal layer 4 was deposited.

[0090] The obtained second diamond single crystal layer 4 had a thickness (d) of 100 nm, a nitrogen concentration below the detection limit of 1.0 ppb, a boron concentration below 5.0 ppb, a surface orientation confirmed by X-ray diffraction as (001) orientation, and a slight tilt angle of ±1.0°. The surface roughness measured by atomic force microscopy was 1.0 nm. Surface 4A of the second diamond single crystal layer 4 was covered with hydrogen and exhibited p-type conductivity due to hydrogen termination.

[0091] Next, as shown in Figure 3(a), at 700°C, a reaction gas obtained by diluting 2% NO2 with N2 gas was supplied to the microwave plasma CVD apparatus at a pressure of 50 Torr for 2 minutes, bringing the NO2 into contact with the hydrogen-terminated surface 4A of the second diamond single crystal layer 4 to form an NO2 adsorption surface. In this state, it was considered that NO2 molecules were adsorbed in a monolayer form on the hydrogen-terminated surface 4A.

[0092] Next, a 50 nm Au layer 20 was deposited by vacuum deposition as shown in Figure 3(b) to form a resist layer 22 as shown in Figure 3(c), the resist layer 22 was masked and developed as shown in Figure 3(d) to form an electrode pattern, the Au layer 20 was etched as shown in Figure 4(a), and the resist layer 22 was removed as shown in Figure 4(b) to form the source electrode 8 and drain electrode 10.

[0093] Next, as shown in Figure 4(c), re-doping with NO2 was performed to replenish the amount of NO2 adsorbed on the NO2 adsorption surface 6 where the gate insulating film 12B is formed. The conditions for re-doping with NO2 were the same as those for the NO2 doping process. Next, as shown in Figure 4(d), an insulating layer 12 was formed by depositing 16 nm of Al2O3 using an atomic layer deposition (ALD) apparatus. The insulating layer 12 includes a passivation film 12A, a gate insulating film 12B, and a passivation film 12C. Next, using the same ALD apparatus, a 50 nm Au layer 28 was deposited as shown in Figure 5(a), a resist layer 30 was formed as shown in Figure 5(b), the resist was masked and developed as shown in Figure 5(c), and a gate electrode 14 was formed as shown in Figure 5(d). This completed the field-effect transistor.

[0094] The field-effect transistor of Example 1 was set in a characteristic tester and a performance test was performed. The results are shown in the graphs in Figures 6 to 8. Figures 6 and 7 show the gate-source voltage (V) of the field-effect transistor of Example 1. GS When the drain-source voltage (V) is varied from -7V to 11V, DS ) and drain current (I D The relationship between the two is shown, with Figure 6 representing the drain current linearly and Figure 7 representing the drain current logarithmically.

[0095] As is clear from comparing Figure 6 with Figure 24, which shows the characteristics of the conventional technology, in the field-effect transistor of Example 1, when the drain-source voltage is near 0V, a positive drain current (I D No gate leakage current was measured, indicating that no gate leakage current was present. Therefore, the risk of damage to the gate insulating film 12B was reduced. This indicated that no gate leakage current path was formed within the second diamond single crystal layer 4.

[0096] As is clear from comparing Figure 7 with Figure 25, which shows the characteristics of the prior art, the field-effect transistor of Example 1 exhibits a negative drain current (I) that is independent of the gate-source voltage. DNo current flowed, and the drain leakage current was almost eliminated. Therefore, it was found that a high ON / OFF current ratio, necessary for power semiconductor applications, could be obtained. This indicated that no drain leakage current path was formed inside the second diamond single crystal layer 4.

[0097] Figure 8 shows the drain current (I) when the field-effect transistor of Example 1 is operated for a long period of time. D (Upper graph) and gate current (I G The graph below shows the time characteristics. It was operated for 1728 hours, but there was no degradation (I D decrease, I G No increase was observed. The effect was significant when compared to Figure 26, which shows the lifespan of the conventional technology.

[0098] [Examples 2-5, Comparative Examples 1-4] Although the structure was the same as in Example 1, the film thickness d of the second diamond single crystal layer 4 was changed to 0 nm (Figure 9: Comparative Example 1), 25 nm (Figure 10: Comparative Example 2), 50 nm (Figure 11: Example 2), 100 nm (Figure 12: Example 3), 200 nm (Figure 13: Example 4), 400 nm (Figure 14: Example 5), 800 nm (Figure 15: Comparative Example 3), and 1600 nm (Figure 16: Comparative Example 4). Field-effect transistors were fabricated under all other conditions, and their output characteristics were measured.

[0099] When the film thickness d of the second diamond single crystal layer 4 is increased, the drain current value (I D As the on-resistance (R) increases, ON It was found that the drain-source resistance (when the FET is ON) decreases. However, Comparative Example 1 was I D Low 、 R ON There is a problem that the value is high, and comparative example 2 is I D Low 、 R ON There is a problem that the value is high, and comparative example 3 is V BR There is a problem that the value is low, and comparative example 4 is V BR The problem was that the voltage was low, causing drain leakage current.

[0100] Figure 17 shows the off-voltage (V) for Examples 2-5 and Comparative Examples 2-4. BR This is the result of measuring the characteristics. As the film thickness d of the second diamond single crystal layer 4 increases, the off-voltage (V) BR It was found that the value increased.

[0101] Figures 18-20 show the results for Examples 2-5 and Comparative Examples 1-4. D , R ON、 V BR This plots the dependence on the thickness d. D The optimal thickness was d ≥ 200 nm. ON The optimal thickness was d ≥ 200 nm. BR A thickness of d = 200 nm was optimal.

[0102] [Example 6] An electronic device substrate 1 and a field-effect transistor of Example 6, corresponding to the second embodiment, were manufactured by the following method. A first diamond single crystal layer 2 (commercially available) was prepared with a thickness of 500 μm, a nitrogen concentration of 0.5 ppb, a boron concentration of 2.5 ppb, a surface 2A orientation of (001) ±1.0°, and a surface roughness Ra of 5 nm. The first diamond single crystal layer 2 did not have a support substrate, and the size of the first diamond single crystal layer 2 was 4.5 mm × 4.5 mm × thickness 0.5 mm.

[0103] The first diamond single crystal layer 2 was placed in a microwave plasma CVD apparatus (Cornes Technology Co., Ltd., product name: SDS5200S), the temperature of the first diamond single crystal layer 2 was set to 750°C, the reaction gas pressure to 50 Torr, and the CH4 gas flow rate to 3 ccm(cm). 3 The H2 gas flow rate was 300 ccm ( / min), and no nitrogen or boron gases were used. Under microwave power of 750W, a 100nm thick nitrogen-containing second diamond single crystal layer was epitaxially grown.

[0104] The obtained second diamond single crystal layer had a thickness (d) of 100 nm, a nitrogen concentration of 0.08 ppb, a boron concentration of 0.5 ppb, a surface orientation of (001) plane orientation ±1.0° measured by backscatter electron diffraction pattern method (EBSP) using a scanning electron microscope (SEM), and a surface roughness of 1 nm measured by white light interferometry. Surface 4A of the second diamond single crystal layer 4 was covered with hydrogen and exhibited p-type conductivity due to hydrogen termination.

[0105] Next, as shown in Figure 3(a), at 120°C, a reaction gas obtained by diluting 2% NO2 with N2 gas to 2% was supplied to the microwave plasma CVD apparatus at a pressure of 760 Torr for 2 minutes, bringing the NO2 into contact with the hydrogen-terminated surface 4A of the second diamond single crystal layer 4 to form an NO2 adsorption surface. In this state, it was considered that NO2 molecules were adsorbed in a monolayer form on the hydrogen-terminated surface 4A.

[0106] Next, a 50 nm Au layer 20 was deposited by vacuum deposition as shown in Figure 3(b) to form a resist layer 22 as shown in Figure 3(c), the resist layer 22 was masked and developed as shown in Figure 3(d) to form an electrode pattern, the Au layer 20 was etched as shown in Figure 4(a), and the resist layer 22 was removed as shown in Figure 4(b) to form the source electrode 8 and drain electrode 10.

[0107] Next, as shown in Figure 4(c), re-doping with NO2 was performed to replenish the amount of NO2 adsorbed on the NO2 adsorption surface 6 where the gate insulating film 12B is formed. The conditions for re-doping with NO2 were the same as those for the NO2 doping process. Next, as shown in Figure 4(d), an insulating layer 12 was formed by depositing 16 nm of Al2O3 using an atomic layer deposition (ALD) apparatus. The insulating layer 12 includes a passivation film 12A, a gate insulating film 12B, and a passivation film 12C. Next, using the same ALD apparatus, a 50 nm Au layer 28 was deposited as shown in Figure 5(a), a resist layer 30 was formed as shown in Figure 5(b), the resist was masked and developed as shown in Figure 5(c), and a gate electrode 14 was formed as shown in Figure 5(d). This completed the field-effect transistor.

[0108] The field-effect transistor of Example 6 was set in a characteristic tester and a performance test was performed. The results are shown in the graphs in Figures 21 and 22. Figures 21 and 22 show the gate-source voltage (V) of the field-effect transistor of Example 6. GS When the drain-source voltage (V) is varied from -7V to 41V, DS ) and drain current (I D The relationship between the two is shown, with Figure 21 representing the drain current linearly and Figure 22 representing the drain current logarithmically.

[0109] As is clear from comparing Figure 21 with Figure 24, which shows the characteristics of the conventional technology, in the field-effect transistor of Example 6, when the drain-source voltage is near 0V, a negative drain current (I D No gate leakage current was measured, indicating that no gate leakage current was present. Therefore, the risk of damage to the gate insulating film 12B was reduced. This indicated that no gate leakage current path was formed within the second diamond single crystal layer 4.

[0110] As is clear from comparing Figure 22 with Figure 25, which shows the characteristics of the prior art, the field-effect transistor of Example 6 exhibits a positive drain current (I) that is independent of the gate-source voltage. D No current flowed, and the drain leakage current was almost eliminated. Therefore, it was found that a high ON / OFF current ratio, which is necessary for power semiconductor applications, can be obtained. Although a channel was formed inside the second diamond single crystal layer 4, it was shown that no drain leakage current path was created.

[0111] [Example 7] An electronic device substrate 1 and a field-effect transistor of Example 7, which corresponds to the third embodiment, were manufactured by the following method. A first diamond single crystal layer 2 (commercially available) was prepared with a thickness of 500 μm, a nitrogen concentration of 10 ppb, a boron concentration of 0.05 ppb, a surface 2A orientation of (001) ±1.0°, and a surface roughness Ra of 5 nm. The first diamond single crystal layer 2 did not have a support substrate, and the size of the first diamond single crystal layer 2 was 4.5 mm × 4.5 mm × thickness 0.5 mm.

[0112] The first diamond single crystal layer 2 was placed in a microwave plasma CVD apparatus (Cornes Technology Co., Ltd., product name: SDS5200S), the temperature of the first diamond single crystal layer 2 was set to 650°C, the reaction gas pressure to 50 Torr, and the CH4 gas flow rate to 3 ccm(cm). 3 The H2 gas flow rate was 300 ccm ( / min), and no nitrogen or boron gases were used. A 500 nm thick second diamond single crystal layer was epitaxially grown under microwave power of 750 W.

[0113] The obtained second diamond single crystal layer had a thickness (d) of 500 nm, a nitrogen concentration of 20 ppb, and a boron concentration of 10 ppb. The surface orientation measured by backscatter electron diffraction pattern spectroscopy (EBSP) using a scanning electron microscope (SEM) was (001) plane orientation ±1.0°, and the surface roughness measured by white light interferometry was 1 nm. Surface 4A of the second diamond single crystal layer 4 was covered with hydrogen and exhibited p-type conductivity due to hydrogen termination.

[0114] Figure 27 shows the depth distribution of nitrogen and boron concentrations in the electronic device substrate 1 of Example 7, measured by secondary ion mass spectrometry. In the depth direction, the surface position of the second diamond single crystal layer 4 is set to 0 nm.

[0115] In the first diamond single crystal layer 2 of Example 7, the nitrogen concentration was below the detection limit (20 ppb) by electron spin resonance (ESR) spectroscopy, and the boron concentration was below the detection limit (0.01 ppb). In the second diamond single crystal layer 4, the nitrogen concentration was below the detection limit (20 ppb) by EPR spectroscopy, and the boron concentration gradually increased from 2.0 ppb to 20 ppb towards the surface.

[0116] Next, using the electronic device substrate 1 of Example 7, an NO2 adsorption surface was formed under the same conditions as in Example 6. Then, a 50 nm Au layer 20 was deposited by vacuum deposition as shown in Figure 3(b) to form a resist layer 22 as shown in Figure 3(c). As shown in Figure 3(d), the resist layer 22 was masked and developed to form an electrode pattern. As shown in Figure 4(a), the Au layer 20 was etched, and as shown in Figure 4(b), the resist layer 22 was removed to form the source electrode 8 and drain electrode 10.

[0117] Furthermore, as shown in Figure 4(c), re-doping with NO2 was performed to replenish the amount of NO2 adsorbed on the NO2 adsorption surface 6 where the gate insulating film 12B was to be formed. The conditions for re-doping with NO2 were the same as those for the NO2 doping process. Next, as shown in Figure 4(d), an atomic layer deposition (ALD) apparatus was used to deposit 16 nm of Al2O3 to form an insulating layer 12. The insulating layer 12 includes a passivation film 12A, a gate insulating film 12B, and a passivation film 12C.

[0118] Next, using the same ALD apparatus, a 50 nm Au layer 28 was deposited as shown in Figure 5(a), a resist layer 30 was formed as shown in Figure 5(b), the resist was masked and developed as shown in Figure 5(c), and a gate electrode 14 was formed as shown in Figure 5(d). This completed the field-effect transistor of Example 7.

[0119] The field-effect transistor of Example 7 was set in the same characteristic tester used in Example 5, and a performance test was performed. The results are shown in the graphs in Figures 28 and 29. Figure 28 shows the gate-source voltage (V) of the field-effect transistor of Example 7. GS When the voltage is varied from -7V to 15V, the drain-source output voltage (V) DS ) and the drain current (I D The relationship between the two is shown. Figure 29 is a graph showing the relationship between the operating frequency (GHz), current gain (dB), and power gain (dB) when tested in the field-effect transistor of Example 7 under the conditions of VGS = 5.5V and VDS = -40V.

[0120] As shown in Figure 28, the field-effect transistor of Example 7 obtained excellent characteristic values, with a characteristic on-resistance (Ron) of 26.73 Ω mm and a maximum drain current (IDMX) of 553 mA / mm.

[0121] Furthermore, according to the high-frequency small-signal characteristics of the field-effect transistor of Example 7 shown in Figure 29, the current gain cutoff frequency (fT) was 15 GHz, and the power gain cutoff frequency (fMAX) was 120 GHz. These performance characteristics were considered to be among the world's best at the time of measurement. [Industrial applicability]

[0122] According to the present invention, channels can be formed in a second diamond single crystal layer having an impurity concentration, surface roughness, and thickness that makes it difficult for leakage current to flow. This suppresses gate leakage current and drain leakage current, thereby improving output characteristics and extending the lifespan of the field-effect transistor. Furthermore, by defining the impurity concentration, surface orientation, and surface roughness Ra of the first diamond single crystal layer as described above, it is easy to form a second diamond single crystal layer with such high purity and precision. [Explanation of Symbols]

[0123] 1. Substrate for electronic devices 2. First diamond single crystal layer 2A Surface of the first diamond single crystal layer 4 Second diamond single crystal layer 4A Surface of the second diamond single crystal layer 6 NO2 adsorption surface d. Thickness of the second diamond single crystal layer 8. Source electrode 10 Drain electrode 12 Insulating layer 12A Passivation film 12B Gate insulating film 12C Passivation film 14 Electrode gate 20 Au layer 22 Resist layer 24 Resist removal section 26 Au removal section 28 Au layer 30 Resist layer

Claims

1. The first diamond single crystal layer, The first diamond single crystal layer has a second diamond single crystal layer formed on its surface, The first diamond single crystal layer has a nitrogen concentration of 1.0 ppb or more, a boron concentration of 5.0 ppb or more, the plane orientation of the surface of the first diamond single crystal layer has an absolute tilt angle from the (001) plane orientation of 3.0° or less, and the surface roughness Ra of the surface of the first diamond single crystal layer is 30 nm or less. The second diamond single crystal layer has a nitrogen concentration of less than 0.1 ppb, a boron concentration of less than 5.0 ppb, the absolute value of the tilt angle of the surface orientation of the second diamond single crystal layer from the (001) plane orientation is 3.0° or less, the surface roughness Ra of the surface of the second diamond single crystal layer is 30 nm or less, and the thickness of the second diamond single crystal layer is 50 nm or more and 1600 nm or less. The surface of the second diamond single crystal layer is hydrogen-terminated by being covered with hydrogen and has p-type conductivity, and NO is present on the surface of the hydrogen-terminated second diamond single crystal layer. ２ NO is adsorbed ２ A substrate for electronic devices characterized by having an adsorption surface.

2. The first diamond single crystal layer, The first diamond single crystal layer has a second diamond single crystal layer formed on its surface, The first diamond single crystal layer has a nitrogen concentration of 0.1 ppb or more, a boron concentration of 1.0 ppb or more, the absolute value of the tilt angle of the surface orientation of the first diamond single crystal layer from the (001) plane orientation is 3.0° or less, and the surface roughness Ra of the surface of the first diamond single crystal layer is 30 nm or less. The second diamond single crystal layer has a nitrogen concentration of less than 0.1 ppb, a boron concentration of less than 1.0 ppb, the absolute value of the tilt angle of the surface orientation of the second diamond single crystal layer from the (001) plane orientation is 3.0° or less, the surface roughness Ra of the surface of the second diamond single crystal layer is 30 nm or less, and the thickness of the second diamond single crystal layer is 50 nm or more and 400 nm or less. The surface of the second diamond single crystal layer is hydrogen-terminated by being covered with hydrogen, thereby having p-type conductivity, and furthermore, NO is present on the surface of the hydrogen-terminated second diamond single crystal layer. ２ NO is adsorbed ２ A substrate for electronic devices characterized by having an adsorption surface.

3. The first diamond single crystal layer, The first diamond single crystal layer has a second diamond single crystal layer formed on its surface, The first diamond single crystal layer has a nitrogen concentration of less than 20 ppb, a boron concentration of less than 0.01 ppb, the absolute value of the tilt angle of the surface orientation of the first diamond single crystal layer from the (001) plane orientation is 3.0° or less, and the surface roughness Ra of the surface of the first diamond single crystal layer is 30 nm or less. The second diamond single crystal layer has a nitrogen concentration of less than 20 ppb, a boron concentration of 2.0 ppb or more and less than 20 ppb, the absolute value of the tilt angle of the surface orientation of the second diamond single crystal layer from the (001) plane orientation is 3.0° or less, the surface roughness Ra of the surface of the second diamond single crystal layer is 30 nm or less, and the thickness of the second diamond single crystal layer is 50 nm or more and 400 nm or less. The surface of the second diamond single crystal layer is hydrogen-terminated by being covered with hydrogen, thereby having p-type conductivity, and furthermore, NO is present on the surface of the hydrogen-terminated second diamond single crystal layer. ２ NO is adsorbed ２ A substrate for electronic devices characterized by having an adsorption surface.

4. A substrate for an electronic device according to any one of claims 1 to 3, The NO of the second diamond single crystal layer ２ A source electrode formed on the first region of the adsorption surface, The NO of the second diamond single crystal layer ２ A gate insulating film formed on the second region of the adsorption surface, A gate electrode formed on the gate insulating film, The NO of the second diamond single crystal layer ２ A field effect transistor comprising a drain electrode formed on a third region of the adsorption surface.

5. An integrated circuit element comprising an electronic device substrate according to any one of claims 1 to 3, and a plurality of field-effect transistors formed on the electronic device substrate, The aforementioned field-effect transistor is The NO of the second diamond single crystal layer ２ A source electrode formed on the first region of the adsorption surface, The NO of the second diamond single crystal layer ２ A gate insulating film formed on the second region of the adsorption surface, A gate electrode formed on the gate insulating film, The NO of the second diamond single crystal layer ２ An integrated circuit element characterized by comprising a drain electrode formed on a third region of the adsorption surface.

6. A first diamond single crystal layer is prepared, having a nitrogen concentration of 1.0 ppb or more, a boron concentration of 5.0 ppb or more, a surface orientation such that the absolute value of the tilt angle from the (001) plane orientation is 3.0° or less, and a surface roughness Ra of the surface is 30 nm or less. A second diamond single crystal layer is formed on the first diamond single crystal layer by plasma CVD, while introducing a reaction gas containing hydrocarbon gas, hydrogen gas, and nitrogen and boron gas as dopants, with the temperature of the first diamond single crystal layer being 650°C or higher and 950°C or lower, the pressure of the reaction gas being 40 Torr or higher and 60 Torr or lower, and the ratio of the hydrocarbon gas flow rate to the hydrogen gas flow rate (hydrocarbon gas flow rate / hydrogen gas flow rate) being 1:200 to 1:50, the nitrogen concentration being less than 0.1 ppb, the boron concentration being less than 5.0 ppb, the absolute value of the tilt angle of the surface orientation from the (001) plane orientation being 3.0° or lower, the surface roughness Ra being 30 nm or lower, and the thickness being 50 nm or higher and 1600 nm or lower. The surface of the second diamond single crystal layer is hydrogen-terminated to impart p-type conductivity. Next, NO is applied to the surface of the second diamond single crystal layer. ２ When gas is brought into contact with the hydrogen-terminated surface, NO ２ Adsorbing NO ２ A method for manufacturing a substrate for electronic devices, characterized by forming an adsorption surface.

7. A first diamond single crystal layer is prepared, having a nitrogen concentration of 0.1 ppb or more, a boron concentration of 1.0 ppb or more, a surface orientation such that the absolute value of the tilt angle from the (001) plane orientation is 3.0° or less, and a surface roughness Ra of the surface is 30 nm or less. A second diamond single crystal layer is formed on the first diamond single crystal layer by plasma CVD, while introducing a reaction gas containing hydrocarbon gas, hydrogen gas, and nitrogen and boron gas as dopants, with the temperature of the first diamond single crystal layer being 650°C or higher and 950°C or lower, the pressure of the reaction gas being 40 Torr or higher and 60 Torr or lower, and the ratio of the hydrocarbon gas flow rate to the hydrogen gas flow rate (hydrocarbon gas flow rate / hydrogen gas flow rate) being 1:200 to 1:50, the nitrogen concentration being less than 0.1 ppb, the boron concentration being less than 1.0 ppb, the absolute value of the tilt angle of the surface orientation from the (001) plane orientation being 3.0° or lower, the surface roughness Ra being 30 nm or lower, and the thickness being 50 nm or higher and 400 nm or lower. The surface of the second diamond single crystal layer is hydrogen-terminated to impart p-type conductivity. Next, NO is applied to the surface of the second diamond single crystal layer. ２ When gas is brought into contact with the hydrogen-terminated surface, NO ２ Adsorbing NO ２ A method for manufacturing a substrate for electronic devices, characterized by forming an adsorption surface.

8. A first diamond single crystal layer is prepared, having a nitrogen concentration of less than 20 ppb, a boron concentration of less than 0.01 ppb, a surface orientation such that the absolute value of the tilt angle from the (001) plane orientation is 3.0° or less, and a surface roughness Ra of the surface is 30 nm or less. A second diamond single crystal layer is formed on the first diamond single crystal layer by plasma CVD, while introducing a reaction gas containing hydrocarbon gas, hydrogen gas, and nitrogen and boron gas as dopants, with the temperature of the first diamond single crystal layer being 650°C or higher and 950°C or lower, the pressure of the reaction gas being 40 Torr or higher and 60 Torr or lower, and the ratio of the flow rate of the hydrocarbon gas to the flow rate of the hydrogen gas (flow rate of the hydrocarbon gas / flow rate of the hydrogen gas) being 1:200 to 1:50, the nitrogen concentration being less than 20 ppb, the boron concentration being 2.0 ppb or higher and less than 20 ppb, the absolute value of the tilt angle of the surface orientation from the (001) plane orientation being 3.0° or lower, the surface roughness Ra being 30 nm or lower, and the thickness being 50 nm or higher and 400 nm or lower. The surface of the second diamond single crystal layer is hydrogen-terminated to impart p-type conductivity. Next, NO is applied to the surface of the second diamond single crystal layer. ２ When gas is brought into contact with the hydrogen-terminated surface, NO ２ Adsorbing NO ２ A method for manufacturing a substrate for electronic devices, characterized by forming an adsorption surface.

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