An ultra-high-speed dynamic current integration sampling circuit

Abstract

The present invention provides an ultra-high-speed dynamic current integration sampling and holding circuit, which converts the input signal from a voltage form to a current form with a linear relationship through a discharge sampling circuit; each state control circuit forms different control states according to the logical timing of its own input, and charges and discharges the sampling capacitor connected to itself under different control states, completing the ultra-low power consumption current integration sampling and holding process of the differential analog input signal to achieve an anti-aliasing effect. The discharge sampling circuit of the present invention can improve the linearity of sampling, and the input signal is directly connected to the input tube gate to realize the input buffer function. At the same time, the dynamic implementation method makes the static power consumption of the circuit zero, realizing ultra-low power consumption sampling. Therefore, the present invention saves the anti-aliasing filter and input buffer at the front end of the sampling circuit, and no bootstrap switch is required inside the circuit. At the same time, there is no static power consumption, which can simplify the circuit structure and reduce the overall power consumption.

Description

Technical Field

[0001] The invention belongs to the field of analog-to-digital converters, and in particular relates to an ultra-high-speed dynamic current integration type sampling circuit. Background Art

[0002] As an important module in the mixed signal system, the analog-to-digital converter is a bridge connecting the analog world and the digital world. The sampling and holding circuit, as the front-end module of the analog-to-digital converter, is even more crucial.

[0003] In order to suppress out-of-band interference, technicians added an anti-aliasing filter in front of the traditional voltage sampling and holding circuit based on the Nyquist sampling principle. When adding the anti-aliasing filter, an input buffer is also required to increase the input impedance. The addition of the filter and input buffer brings greater power consumption to the traditional voltage sampling and holding circuit. Summary of the invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides an ultra-high-speed dynamic current integration sampling circuit. The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0005] An ultra-high-speed dynamic current integration type sampling and holding circuit provided by the present invention comprises: a discharge sampling circuit, an N-way state control circuit and an N-way sampling capacitor;

[0006] The output of each state control circuit is connected to a sampling capacitor, and the input of each state control circuit is commonly connected to the output of the discharge sampling circuit;

[0007] A discharge sampling circuit, used for converting a differential analog input signal from a voltage form to a current form;

[0008] Wherein, the differential analog input signal in the form of current forms a linear relationship with the differential analog input signal in the form of voltage;

[0009] Each state control circuit is used to form different control states according to the logic timing of its own input, and to charge and discharge the sampling capacitor connected to itself in different control states, so as to complete the ultra-low power consumption sampling and holding process of the differential analog input signal;

[0010] Each control state circuit forms a channel for the signal processing process in the form of current, and multiple control state circuits are controlled by multiple logic timings to form control states to achieve time domain interleaving of multiple channels.

[0011] Optionally, the discharge sampling circuit includes: a main input differential pair consisting of two low threshold voltage NMOS tubes, an auxiliary input differential pair consisting of two medium threshold voltage NMOS tubes, and two source negative feedback resistors;

[0012] The gates of the two low threshold voltage NMOS tubes are respectively connected to an analog input signal to buffer the analog input signal, and the two analog input signals form a differential.

[0013] Optionally, the control state formed by the state control circuit includes a reset phase, a sampling phase and a holding phase.

[0014] In the reset state, each state control circuit charges the directly connected sampling capacitor to the same as the power supply voltage VDD; in the sampling stage, each state control circuit discharges the directly connected sampling capacitor through the discharge sampling circuit; in the holding stage, the sampling capacitor directly connected to each state control circuit is disconnected from the state control circuit and the discharge sampling circuit to achieve a fully dynamic charging and discharging mode, so that the static power consumption of the ultra-high-speed dynamic current integration sampling and holding circuit is zero, thereby achieving ultra-low power consumption sampling.

[0015] Optionally, the discharge sampling circuit includes: a first MOS tube M1, a second MOS tube M2, a third MOS tube M3, a fourth MOS tube M4, a first resistor RD1 and a second resistor RD2;

[0016] The source of the first MOSFET M1 is connected to the drain of the third MOSFET M3 and one end of the first resistor RD1; the gate of the first MOSFET M1 is connected to the gate of the third MOSFET M3 as the first input end to access the first input signal VINN; the gate of the second MOSFET M2 is connected to the gate of the fourth MOSFET M4 as the second input end to access the second input signal VINP; the drains of the first MOSFET M1 and the second MOSFET M2 are respectively connected to a state control circuit, and the other end of the first resistor RD1 and the other end of the first resistor RD1 are connected together to access the power ground;

[0017] The first MOS transistor M1 and the second MOS transistor M2 form a main input differential pair; the third MOS transistor M3 and the fourth MOS transistor M4 form an auxiliary input differential pair, and the first input signal VINN and the second input signal VINP form a differential.

[0018] Among them, the state control circuit controls the discharge sampling time to be a fixed time t int , the voltage on each sampling capacitor during the hold phase is

[0019] Among them, V in Indicates the input signal voltage, G m represents the transconductance of the discharge sampling circuit, C s Represents the capacitance of the sampling capacitor, and VDD represents the power supply voltage.

[0020] Optionally, the state control circuit has N channels, the i-th control state circuit includes: a fifth MOS tube MN1i, a sixth MOS tube MN2i, a seventh MOS tube MP1i and an eighth MOS tube MP2i, and each i-th sampling capacitor includes: a first sampling capacitor CS1i and a second sampling capacitor CS2i;

[0021] Among them, the gate of the fifth MOS tube MN1i is connected to the control clock CKS i The gate of the sixth MOS tube MN2i is connected to the control clock CKS i , the source of the fifth MOSFET MN1i is connected to the drain of the first MOSFET M1 in the discharge sampling circuit, the source of the sixth MOSFET MN2i is connected to the drain of the second MOSFET M2 in the discharge sampling circuit, the drain of the fifth MOSFET MN1i is connected to the source of the seventh MOSFET MP1i and one end of the first sampling capacitor CS1i, the drain of the sixth MOSFET MN2i is connected to the drain of the eighth MOSFET MP2i and one end of the second sampling capacitor CS2i, the drain of the seventh MOSFET MP1i and the source of the eighth MOSFET MP2i are connected to the power supply voltage VDD, the gates of the seventh MOSFET MP1i and the eighth MOSFET MP2i are connected to the charging reset clock CKRi, and the other end of the first sampling capacitor CS1i and the other end of the second sampling capacitor CS2i are connected to the power ground.

[0022] The seventh MOS tube MP1i is a PMOS tube, and the eighth MOS tube MP2i is a NMOS tube.

[0023] Optional, each i-way state control circuit control clock CKS i The control clock CKS of each i+1 state control circuit i+1 The phase difference is the reciprocal of the overall sampling frequency of the ultra-high-speed dynamic current integration type sampling and holding circuit, and the high-level pulse width of each control clock is the same.

[0024] Beneficial effects of the present invention:

[0025] 1. The ultra-high-speed dynamic current integration type sampling and holding circuit provided by the present invention is based on the circuit integration sampling principle and can achieve anti-aliasing effect without the need for a pre-anti-aliasing filter, thereby effectively suppressing out-of-band interference;

[0026] 2. The ultra-high-speed dynamic current integration type sampling and holding circuit provided by the present invention can realize the input buffer function because the analog input signal directly acts on the input tube gate;

[0027] 3. The ultra-high-speed dynamic current integration type sampling and holding circuit provided by the present invention realizes a dynamic charging and discharging mode, so that the static power consumption of the circuit is zero, and ultra-low power consumption sampling is realized;

[0028] 4. The ultra-high-speed dynamic current integration type sampling and holding circuit provided by the present invention adopts auxiliary input technology and source negative feedback technology to improve the accuracy of the sampling and holding circuit. In addition, the present invention does not require a bootstrap switch and is suitable for multi-channel time domain interleaving technology.

[0029] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 This is a schematic diagram of the overall application of the ultra-high-speed dynamic current integration type sampling and holding circuit provided by the present invention;

[0031] Figure 2 This is an internal schematic diagram of the ultra-high-speed dynamic current integration type sampling and holding circuit provided by the present invention;

[0032] Figure 3 A multi-channel timing diagram of the ultra-high-speed dynamic current integration type sampling and holding circuit provided by the present invention;

[0033] Figure 4 This is an ideal frequency response diagram of the ultra-high-speed dynamic current integration type sampling and holding circuit provided by the present invention. DETAILED DESCRIPTION

[0034] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0035] like Figure 1 As shown, an ultra-high-speed dynamic current integration type sampling and holding circuit provided by the present invention comprises: a discharge sampling circuit, N-channel state control circuits and N-channel sampling capacitors;

[0036] The output of each state control circuit is connected to a sampling capacitor, and the input of each state control circuit is commonly connected to the output of the discharge sampling circuit;

[0037] A discharge sampling circuit, used for converting a differential analog input signal from a voltage form to a current form;

[0038] Wherein, the differential analog input signal in the form of current forms a linear relationship with the differential analog input signal in the form of voltage;

[0039] It is worth noting that the main function of the discharge sampling circuit of the present invention is to convert the differential analog input signal in voltage form from voltage form to current form. In practical applications, voltage source control conversion or other circuit conversion can be used. As long as the circuit of the present invention can be implemented, the present invention is not limited here.

[0040] Each state control circuit is used to form different control states according to the logic timing of its own input, and to charge and discharge the sampling capacitor connected to itself in different control states, so as to complete the ultra-low power consumption sampling and holding process of the differential analog input signal;

[0041] Each control state circuit forms a channel for the signal processing process in the form of current, and multiple control state circuits are controlled by multiple logic timings to form control states to achieve time domain interleaving of multiple channels.

[0042] The present invention provides an ultra-high-speed dynamic current integration sampling and holding circuit, which converts the input signal from a voltage form to a current form with a linear relationship through a discharge sampling circuit; each state control circuit forms different control states according to the logical timing of its own input, and charges and discharges the sampling capacitor connected to itself under different control states, completing the ultra-low power consumption current integration sampling and holding process of the differential analog input signal to achieve an anti-aliasing effect. The discharge sampling circuit of the present invention can improve the linearity of sampling, and the input signal is directly connected to the input tube gate to realize the input buffer function. At the same time, the dynamic implementation method makes the static power consumption of the circuit zero, realizing ultra-low power consumption sampling. Therefore, the present invention saves the anti-aliasing filter and input buffer at the front end of the sampling circuit, and no bootstrap switch is required inside the circuit. At the same time, there is no static power consumption, which can simplify the circuit structure and reduce the overall power consumption.

[0043] In one embodiment, the discharge sampling circuit includes: a main input differential pair consisting of two low threshold voltage NMOS transistors, an auxiliary input differential pair consisting of two medium threshold voltage NMOS transistors, and two source negative feedback resistors;

[0044] The gates of the two low threshold voltage NMOS tubes are respectively connected to an analog input signal to buffer the analog input signal, and the two analog input signals form a differential.

[0045] In one embodiment, the control state formed by the state control circuit includes a reset phase, a sampling phase, and a holding phase.

[0046] In the reset state, each state control circuit charges the directly connected sampling capacitor to the same as the power supply voltage VDD; in the sampling stage, each state control circuit discharges the directly connected sampling capacitor through the discharge sampling circuit; in the holding stage, the sampling capacitor directly connected to each state control circuit is disconnected from the state control circuit and the discharge sampling circuit to achieve a fully dynamic charging and discharging mode, so that the static power consumption of the ultra-high-speed dynamic current integration sampling and holding circuit is zero, thereby achieving ultra-low power consumption sampling.

[0047] Among them, the state control circuit controls the discharge sampling time to be a fixed time t int, the voltage on each sampling capacitor during the hold phase is

[0048] Among them, V in Indicates the input signal voltage, G m represents the transconductance of the discharge sampling circuit, C s Represents the capacitance of the sampling capacitor, and VDD represents the power supply voltage.

[0049] like Figure 2 As shown, the discharge sampling circuit of the present invention includes: a first MOS tube M1, a second MOS tube M2, a third MOS tube M3, a fourth MOS tube M4, a first resistor RD1 and a second resistor RD2;

[0050] The source of the first MOSFET M1 is connected to the drain of the third MOSFET M3 and one end of the first resistor RD1; the gate of the first MOSFET M1 is connected to the gate of the third MOSFET M3 as the first input end to access the first input signal VINN; the gate of the second MOSFET M2 is connected to the gate of the fourth MOSFET M4 as the second input end to access the second input signal VINP; the drains of the first MOSFET M1 and the second MOSFET M2 are respectively connected to a state control circuit, and the other end of the first resistor RD1 and the other end of the first resistor RD1 are connected together to access the power ground;

[0051] The first MOS transistor M1 and the second MOS transistor M2 form a main input differential pair; the third MOS transistor M3 and the fourth MOS transistor M4 form an auxiliary input differential pair, and the first input signal VINN and the second input signal VINP form a differential.

[0052] It is worth noting that the discharge sampling circuit of the present invention can be composed of a main input differential pair consisting of two low threshold voltage NMOS tubes, an auxiliary input differential pair consisting of two medium threshold voltage NMOS tubes and two source negative feedback resistors, which can ensure that the ultra-high-speed dynamic current integration sampling circuit has a higher input linearity and improve the sampling accuracy; and because the analog input signal is directly connected to the gates of the four MOS tubes for buffering, the input buffer circuit can be saved.

[0053] refer to Figure 2 , the state control circuit has N channels, the i-th control state circuit includes: a fifth MOS tube MN1i, a sixth MOS tube MN2i, a seventh MOS tube MP1i and an eighth MOS tube MP2i, and each i-th sampling capacitor includes: a first sampling capacitor CS1i and a second sampling capacitor CS2i;

[0054] Among them, the gate of the fifth MOS tube MN1i is connected to the control clock CKS i The gate of the sixth MOS tube MN2i is connected to the control clock CKSi , the source of the fifth MOSFET MN1i is connected to the drain of the first MOSFET M1 in the discharge sampling circuit, the source of the sixth MOSFET MN2i is connected to the drain of the second MOSFET M2 in the discharge sampling circuit, the drain of the fifth MOSFET MN1i is connected to the source of the seventh MOSFET MP1i and one end of the first sampling capacitor CS1i, the drain of the sixth MOSFET MN2i is connected to the drain of the eighth MOSFET MP2i and one end of the second sampling capacitor CS2i, the drain of the seventh MOSFET MP1i and the source of the eighth MOSFET MP2i are connected to the power supply voltage VDD, the gates of the seventh MOSFET MP1i and the eighth MOSFET MP2i are connected to the charging reset clock CKRi, and the other end of the first sampling capacitor CS1i and the other end of the second sampling capacitor CS2i are connected to the power ground.

[0055] The seventh MOS tube MP1i is a PMOS tube, and the eighth MOS tube MP2i is a NMOS tube.

[0056] It is worth noting that: Mi (i = 1 ~ 4) and RD are discharge sampling circuits, (MP1i, MP2i, MN1i, MN2i (i = 1 ~ N) are state control circuits for each channel, CKSi (i = 1 ~ N) is the control clock input for discharge of each channel, and CKRi (i = 1 ~ N) is the control clock input for charging of each channel. The present invention adopts a 1×N two-stage structure, the first stage is a common discharge sampling circuit, and the input signal is directly connected to the gate of the Mi (i = 1 ~ 4) input tube; the second stage adopts N parallel state control circuits to control the connection state of the subsequent sampling capacitor and the discharge sampling circuit and the power supply circuit; the voltage maintained on the sampling capacitor can be directly connected to the analog-to-digital converter for use, and the DAC capacitor of the subsequent ADC can also be directly used as a sampling capacitor. At the same time, the switches of its state control circuit are NMOS tubes and PMOS tubes, and there is no need to use bootstrap switches, thereby reducing the complexity of the circuit. The present invention uses the current integral sampling principle to perform current integral sampling on the analog input signal, which can achieve anti-aliasing effect.

[0057] Figure 3 The overall timing diagram of the multi-channel ultra-high-speed dynamic current integration type sampling and holding circuit during the implementation of the present invention is given. Figure 3 As shown in the figure, CKSi (i=1~N) is the control clock for the discharge sampling of each channel, and CKRi (i=1~N) is the charge reset clock for each channel. When CKSi and CKRi are both low, the i-th channel is in the charge reset state; when CKSi and CKRi are both high, the i-th channel is in the discharge sampling state; when CKSi is low and CKRi is high, the i-th channel is in the hold state. Among them, the reset state of each channel must be strictly completed before the sampling state.

[0058] When the i-th channel is in the charging reset state, MP1i and MP2i are turned on, MN1i and MN2i are turned off, and the sampling capacitors CS1i and CS2i are charged to the power supply voltage VDD; when the i-th channel is in the discharging sampling state, MP1i and MP2i are turned off, MN1i and MN2i are turned on, and the sampling capacitors CS1i and CS2i are discharged under the linear control of the input signal; when the i-th channel is in the holding state, MP1i, MP2i, MN1i, and MN2i are turned off, and the sampling capacitors CS1i and CS2i are kept at the voltage state after discharge. In the three states, there is no conduction path between the power supply voltage and GND, and the power consumption comes from the charging and discharging of the sampling capacitors, and there is only dynamic power consumption.

[0059] In one embodiment, the control clock (CKS) of each i-way state control circuit i ) and the control clock (CKS) of each i+1 state control circuit i+1 ) is the reciprocal of the overall sampling frequency of the ultra-high-speed dynamic current integration type sampling and holding circuit, and the high-level pulse width of each control clock is the same.

[0060] It is worth noting that: in order to improve the processing speed of the ultra-high-speed dynamic current integration type sampling and holding circuit; there can be a strict phase difference between CKSi (i = 1 ~ N), and the phase difference between two adjacent clocks is the reciprocal of the overall sampling frequency of the ultra-high-speed dynamic current integration type sampling and holding circuit, so as to achieve the effect of time domain interleaving. Figure 4 As shown, the high-level pulse width of CKSi (i=1~N) must be strictly consistent in each channel and be an appropriate fixed value tint to achieve the effect of current sampling filtering.

[0061] The ultra-high-speed dynamic current integration type sampling and holding circuit of the present invention is designed for a multi-channel time-domain interleaved analog-to-digital converter, and can directly realize the anti-aliasing filtering function and effectively suppress out-of-band interference; at the same time, no input buffer structure is required, which reduces the complexity and power consumption of the circuit, and is suitable for multi-channel time-domain interleaving, thereby improving the speed of the analog-to-digital converter.

[0062] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0063] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0064] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0065] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. An ultra-high-speed dynamic current integration type sampling and holding circuit, characterized in that: include: A discharge sampling circuit, an N-channel state control circuit and an N-channel sampling capacitor; Wherein, the output of each state control circuit is connected to a sampling capacitor, and the input of each state control circuit is commonly connected to the output of the discharge sampling circuit; The discharge sampling circuit is used to convert the differential analog input signal from a voltage form to a current form; Wherein, the differential analog output signal in the form of current forms a linear relationship with the differential analog input signal in the form of voltage; Each state control circuit is used to form different control states according to the logic timing of its own input, and to charge and discharge the sampling capacitor connected to itself in different control states, so as to complete the ultra-low power consumption sampling and holding process of the differential analog input signal; Among them, each control state circuit forms a channel for the signal processing process in the form of current, and multiple control state circuits are controlled by multiple logic timings to form control states to realize time domain interleaving of multiple channels; the control state formed by the state control circuit includes a reset stage, a sampling stage, and a holding stage. In the reset state, each state control circuit charges the directly connected sampling capacitor to the same as the power supply voltage VDD; in the sampling stage, each state control circuit discharges the directly connected sampling capacitor through the discharge sampling circuit; in the holding stage, the sampling capacitor directly connected to each state control circuit is disconnected from the state control circuit and the discharge sampling circuit to realize a fully dynamic charging and discharging mode, so that the static power consumption of the ultra-high-speed dynamic current integration type sampling and holding circuit is zero, and ultra-low power consumption sampling is realized; The discharge sampling circuit comprises: a main input differential pair consisting of two low threshold voltage NMOS tubes, an auxiliary input differential pair consisting of two medium threshold voltage NMOS tubes, and two source negative feedback resistors; The gates of the two low threshold voltage NMOS tubes are respectively connected to an analog input signal to buffer the analog input signal, and the two analog input signals form a differential.

2. The ultra-high-speed dynamic current integration type sample-and-hold circuit according to claim 1, characterized in that: The discharge sampling circuit comprises: a first MOS tube (M1), a second MOS tube (M2), a third MOS tube (M3), a fourth MOS tube (M4), a first resistor (RD1) and a second resistor (RD2); The source of the first MOSFET (M1) is connected to the drain of the third MOSFET (M3) and one end of the first resistor (RD1); the gate of the first MOSFET (M1) is connected to the gate of the third MOSFET (M3) as a first input end to receive a first input signal (VINN); the gate of the second MOSFET (M2) is connected to the gate of the fourth MOSFET (M4) as a second input end to receive a second input signal (VINP); the drains of the first MOSFET (M1) and the second MOSFET (M2) are respectively connected to a state control circuit, and the other end of the first resistor (RD1) and the other end of the first resistor (RD1) are connected together to receive a power ground; The first MOS transistor (M1) and the second MOS transistor (M2) form a main input differential pair; the third MOS transistor (M3) and the fourth MOS transistor (M3) form an auxiliary input differential pair, and the first input signal (VINN) and the second input signal (VINP) form a differential.

3. The ultra-high-speed dynamic current integration type sample-and-hold circuit as claimed in claim 2, characterized in that: The state control circuit controls the discharge sampling time to a fixed time t int , the voltage on each sampling capacitor during the hold phase is Among them, V in Indicates the input signal voltage, G m represents the transconductance of the discharge sampling circuit, C s Represents the capacitance of the sampling capacitor, and VDD represents the power supply voltage.

4. The ultra-high-speed dynamic current integration type sampling and holding circuit as claimed in claim 2, characterized in that: The state control circuit has N circuits, the i-th control state circuit includes: a fifth MOS tube (MN1i), a sixth MOS tube (MN2i), a seventh MOS tube (MP1i) and an eighth MOS tube (MP2i), and each i-th sampling capacitor includes: a first sampling capacitor (CS1i) and a second sampling capacitor (CS2i); The gate of the fifth MOS tube (MN1i) is connected to the control clock CKS i The gate of the sixth MOS tube (MN2i) is connected to the control clock CKS i The source of the fifth MOSFET (MN1i) is connected to the drain of the first MOSFET (M1) in the discharge sampling circuit, the source of the sixth MOSFET (MN2i) is connected to the drain of the second MOSFET (M2) in the discharge sampling circuit, the drain of the fifth MOSFET (MN1i) is connected to the source of the seventh MOSFET (MP1i) and one end of the first sampling capacitor (CS1i), the drain of the sixth MOSFET (MN2i) is connected to the drain of the eighth MOSFET (MP2i) and one end of the second sampling capacitor (CS2i), the drain of the seventh MOSFET (MP1i) and the source of the eighth MOSFET (MP2i) are connected to the power supply voltage VDD, the gates of the seventh MOSFET (MP1i) and the eighth MOSFET (MP2i) are connected to the charging reset clock CKRi, and the other end of the first sampling capacitor (CS1i) and the other end of the second sampling capacitor (CS2i) are connected to the power ground.

5. The ultra-high-speed dynamic current integration type sample-and-hold circuit as claimed in claim 4, characterized in that: The seventh MOS tube (MP1i) is a PMOS tube, and the eighth MOS tube (MP2i) is a NMOS tube.

6. The ultra-high-speed dynamic current integration type sample-and-hold circuit as claimed in claim 4, characterized in that: The control clock CKS of each i-way state control circuit i The control clock CKS of each i+1 state control circuit i+1 The phase difference is the reciprocal of the overall sampling frequency of the ultra-high-speed dynamic current integration type sampling and holding circuit, and the high-level pulse width of each control clock is the same.

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