Low-frequency signal receiving device

Abstract

The invention provides a low-frequency signal receiving device, belongs to the technical field of low-frequency communication, and designs a large-gain isolation direct amplification and variable center frequency band-pass filter to replace a traditional frequency conversion receiver, so that the scale of a circuit is effectively reduced to 1 / 3 of that of the original frequency conversion receiver; front isolation amplification is designed, the two-stage automatic gain circuit has high-sensitivity 16 dB to 126 dB large dynamic range receiving capacity, isolation segmentation amplification is designed, a frequency-adjustable narrow-band filter is inserted in the middle of cascade connection of the two-stage automatic gain circuit in a penetrating mode to prevent circuit self-excitation, and direct large gain amplification stability is improved. The bandwidth of the two-stage frequency-adjustable narrow-band filter ranges from 400 Hz to 1200 Hz, the gradient coefficient is smaller than 4, and out-of-band interference can be effectively restrained. A 10dB-80dB amplifier is designed in front of a frequency-adjustable narrow-band filter, so that the noise of an LTC1068-25 switched capacitor filter is overcome, and the received noise of the whole machine is smaller than 5nV / Hz1 / 2. According to the invention, light, stable and miniaturized underwater receiving capability is realized, and the antenna is suitable for application scenarios with high requirements on power consumption and space, such as UUV and the like.

Description

Technical Field

[0001] The present invention relates to the technical field of low-frequency communication, and in particular to a low-frequency signal receiving device. Background Art

[0002] Low-frequency (10kHz-100kHz) radio propagates in the earth-ionosphere waveguide, has stable propagation, is not affected by nuclear explosions and ionosphere disturbances, has low attenuation in the atmosphere (-3dB / 1000km), can penetrate deep seawater and the earth, and is suitable for long-distance underwater communication and ground-penetrating communication. After long-distance transmission and seawater attenuation, the low-frequency signal itself is already very weak, so a receiver with high sensitivity and high linearity is crucial for low-frequency communication, among which the RF front-end design is of great significance as the first functional module of the receiver to process the signal.

[0003] At present, the RF front end of most low-frequency receivers (low-frequency signal receiving devices) mainly adopts a frequency-converting superheterodyne structure, which first tunes and amplifies the received low-frequency signal, filters it through a pre-selection filter, and then mixes it to convert the RF signal into a fixed intermediate frequency. It is then filtered through a crystal filter and automatically gain-amplified, and finally converted into a digital signal through an ADC chip and sent to the DSP for processing.

[0004] The LC tuning, frequency conversion circuit, and crystal filter used in this type of low-frequency receiver will cause large insertion losses and are large in size, which is far from meeting the strict space and power consumption requirements of small underwater platforms such as UUVs. Summary of the invention

[0005] The present invention provides a low-frequency signal receiving device, which is used to solve the defects of the low-frequency signal receiving device in the prior art, that is, the low-frequency signal receiving device has a large insertion loss and a large volume, and is difficult to meet the requirements of a small underwater platform.

[0006] The present invention provides a low-frequency signal receiving device, comprising: a preamplifier unit, a narrowband filter amplifier unit and a digital signal processing unit connected in sequence;

[0007] The preamplifier unit comprises an isolated power supply and a passive filter circuit, a controllable pre-attenuation circuit and a pre-isolation amplifier circuit which are connected in sequence; wherein the pre-isolation amplifier circuit is respectively connected to the isolated power supply and the first automatic gain circuit of the narrowband filter amplifier unit;

[0008] The narrowband filter amplification unit comprises a first automatic gain circuit, a first frequency-adjustable narrowband filter, a second automatic gain circuit, a second frequency-adjustable narrowband filter, a differential amplifier circuit, an effective value detection circuit and a clock circuit; wherein the first automatic gain circuit, the first frequency-adjustable narrowband filter, the second automatic gain circuit and the second frequency-adjustable narrowband filter are connected in sequence; the output of the second frequency-adjustable narrowband filter is respectively connected to the effective value detection circuit and the differential amplifier circuit; the effective value detection circuit is also respectively connected to the first automatic gain circuit and the second automatic gain circuit; the clock circuit is respectively connected to the first frequency-adjustable narrowband filter and the second frequency-adjustable narrowband filter;

[0009] The digital signal processing unit is respectively connected with the effective value detection circuit, the differential amplifier circuit, the clock circuit and the controllable pre-attenuation circuit.

[0010] According to a low-frequency signal receiving device provided by the present invention, the passive filtering circuit includes: a Butterworth bandpass filter.

[0011] According to a low-frequency signal receiving device provided by the present invention, a controllable pre-attenuation circuit is composed of attenuators with different attenuation values ​​and a switching relay; the controllable pre-attenuation circuit changes the currently used attenuator by switching the relay under the control of a digital signal processing unit.

[0012] According to a low-frequency signal receiving device provided by the present invention, the pre-isolation amplifier circuit includes a matching transformer, at least one low-noise amplifier, and an isolation transformer connected in sequence.

[0013] According to a low-frequency signal receiving device provided by the present invention, the first automatic gain circuit and the second automatic gain circuit share a programmable gain amplifier chip;

[0014] The input forward control terminals of the first automatic gain circuit and the second automatic gain circuit are connected together and connected to the effective value detection circuit;

[0015] Input inverting control terminals of the first automatic gain circuit and the second automatic gain circuit are connected together and connected to a reference voltage.

[0016] According to a low-frequency signal receiving device provided by the present invention, the first frequency-adjustable narrowband filter and the second frequency-adjustable narrowband filter share a switched capacitor filter chip.

[0017] According to a low-frequency signal receiving device provided by the present invention, the digital signal processing unit includes a DSP, an FPGA, a dual-channel ADC circuit, a crystal oscillator and a DDS clock circuit;

[0018] One ADC input of the dual-channel ADC circuit is connected to the effective value detection circuit, another ADC input of the dual-channel ADC circuit is connected to the differential amplifier circuit, and both outputs of the dual-channel ADC circuit are connected to the FPGA;

[0019] The FPGA is connected to the DSP and the DDS clock circuit respectively, and the DDS clock circuit is connected to the crystal oscillator, another ADC input and the clock circuit in the narrow-band filter amplifier unit respectively.

[0020] According to a low-frequency signal receiving device provided by the present invention, the model of the programmable gain amplifier chip is AD600.

[0021] According to a low-frequency signal receiving device provided by the present invention, the model of the switched capacitor filter chip is an LTC1068 series chip.

[0022] The present invention provides a low-frequency signal receiving device. According to the software radio design concept, a large-gain isolation direct amplifier and a variable center frequency bandpass filter are designed to replace the traditional frequency conversion receiver. An AD600 and an LTC1068-25 chip realize two-stage automatic gain and two-stage frequency adjustable narrowband filtering, which effectively reduces the scale of the circuit to 1 / 3 of the original frequency conversion receiver; the design of the pre-isolation amplifier and the two-stage automatic gain circuit has a high-sensitivity 16dB to 126dB large dynamic range receiving capability, and the isolation segmented amplification is designed. A frequency adjustable narrowband filter is inserted in the middle of the two-stage automatic gain circuit cascade to prevent the circuit from self-excitation, thereby improving the stability of the direct large-gain amplification. The bandwidth of the two-stage frequency adjustable narrowband filter is 400Hz to 1200Hz, and the steepness coefficient is less than 4, which can effectively suppress out-of-band interference; a 10dB-80dB amplifier is designed before the frequency adjustable narrowband filter to overcome the noise of the LTC1068-25 switch capacitor filter and achieve a receiving noise of the whole machine of less than 5nV / Hz. 1 / 2 The present invention realizes lightweight, stable and miniaturized underwater receiving capability, and is suitable for application scenarios such as UUV that have high requirements on power consumption and space. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0024] Figure 1 It is a schematic diagram of the framework of the low-frequency signal receiving device provided by the present invention;

[0025] Figure 2It is a schematic diagram of the passive filtering circuit provided by the present invention;

[0026] Figure 3 It is a schematic diagram of the pre-isolation amplifier circuit provided by the present invention;

[0027] Figure 4 It is a block diagram of the composition of the narrowband amplification and filtering unit provided by the present invention;

[0028] Figure 5 It is a principle diagram of the frequency-adjustable narrowband filter provided by the present invention;

[0029] Figure 6 It is a block diagram of the digital signal processing unit provided by the present invention;

[0030] Figure 7 It is a schematic diagram of the digital signal processing flow provided by the present invention. DETAILED DESCRIPTION

[0031] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0032] It should be noted that in the description of the embodiments of the present invention, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. Unless otherwise clearly specified and limited, the terms "installed", "connected" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be an indirect connection through an intermediate medium, or it can be a connection between the two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to the specific circumstances.

[0033] The terms "first", "second", etc. in this application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of the same type, and the number of objects is not limited. For example, the first object can be one or more.

[0034] Combine the following Figure 1-Figure 7 A low-frequency signal receiving device provided by an embodiment of the present invention is described.

[0035] Figure 1 is a schematic diagram of the framework of the low-frequency signal receiving device provided by the present invention, such as Figure 1 As shown, it mainly includes a preamplifier unit, a narrowband filter amplifier unit and a digital signal processing unit connected in sequence.

[0036] The preamplifier unit mainly includes an isolated power supply and a passive filter circuit, a controllable pre-attenuation circuit and a pre-isolated amplifier circuit which are connected in sequence; wherein the pre-isolated amplifier circuit is respectively connected to the isolated power supply and the first automatic gain circuit of the narrowband filter amplifier unit.

[0037] The narrowband filter amplifier unit mainly includes an AGC circuit 1 (a first automatic gain circuit), a frequency adjustable narrowband filter 1 (a first frequency adjustable narrowband filter), an AGC circuit 2 (a second automatic gain circuit), a frequency adjustable narrowband filter 2 (a second frequency adjustable narrowband filter), a differential amplifier circuit, an effective value detection circuit (which can be an effective value detector) and a clock circuit.

[0038] The digital signal processing unit is respectively connected with the effective value detection circuit, the differential amplifier circuit, the clock circuit and the controllable pre-attenuation circuit.

[0039] The gain range of the preamplifier unit is 10dB-40dB, the gain range of AGC circuit 1 and AGC circuit 2 are both 0-40dB, and the gain of the differential amplifier circuit is 6dB, so the gain range of the whole machine is 16dB-126dB, and the maximum 10nV signal can be amplified to 20mV. In the usual frequency conversion superheterodyne receiving design, the large gain is decomposed into two parts: the RF amplification gain and the intermediate frequency amplification gain, which reduces the RF amplification gain and the intermediate frequency amplification gain, and improves the stability of the large gain amplification of the whole machine; the non-frequency conversion direct amplification of the present invention has a maximum gain of 126dB, creates a design of isolated segmented amplification, and improves the stability of direct large gain amplification.

[0040] The preamplifier unit and the narrowband filter amplifier unit are analog circuits, and these two units jointly occupy one 3UPXI slot. The analog circuit of the frequency conversion superheterodyne low-frequency receiving device occupies three 3UPXI slots. The preamplifier unit and the narrowband filter amplifier unit of the present invention occupy only 1 / 3 of the slots of the traditional frequency conversion superheterodyne.

[0041] Consider frequency adjustable narrowband filter noise up to 10μV / Hz 1 / 2 , with a maximum amplification gain of 80dB before the frequency-adjustable narrowband filter, so that the noise of the frequency-adjustable narrowband filter converted to the noise at the signal input end is 1nV / Hz 1 / 2, for overall noise 5nV / Hz 1 / 2 The impact is very small.

[0042] The key parts of the above-mentioned low-frequency signal receiving device are described one by one below.

[0043] (1) Preamplifier unit

[0044] The gain range of the preamplifier unit is 10dB-40dB, of which the pre-isolation amplifier gain is 40dB and the controllable pre-attenuation is 0-30dB. The pre-isolation amplifier is isolated from the subsequent AGC circuit 1 and AGC circuit 2 through the transformer output to prevent self-excited oscillation of large gain amplification.

[0045] The passive filter circuit can be a Butterworth bandpass filter composed of a 3rd order low pass filter and a 3rd order high pass filter. The Butterworth filter has the advantages of balanced characteristics in terms of linear phase, attenuation slope and loading characteristics. The 3dB bandwidth is 10kHz-40kHz. The principle block diagram is as follows Figure 2 As shown, Figure 2 This is the principle diagram of the passive filter circuit provided by the present invention. The passive filter circuit mainly filters out industrial interference below 10kHz and radio interference above 40kHz, and the stopband attenuation reaches 30dB at frequencies of 6kHz and 100kHz. The values ​​of the main components of the passive filter are as follows:

[0046] L1=698μH, C1=56nF, C2=109nF;

[0047] L2=373μH, L3=247μH, C3=164nF.

[0048] As an optional embodiment, the controllable pre-attenuation circuit is composed of attenuators with different attenuation values ​​and switching relays; the controllable pre-attenuation circuit changes the attenuator currently in use by switching relays under the control of the digital signal processing unit.

[0049] Specifically, the controllable pre-attenuation circuit consists of 0dB, 10dB, 20dB attenuators and switching relays. The isolated IO control bus controls the switching relay, which can form four attenuation values ​​of 0dB, 10dB, 20dB and 30dB. The attenuation step value is 10dB. Its main function is to provide attenuation in strong signal conditions to prevent pre-isolation amplification and subsequent amplification saturation.

[0050] As an optional embodiment, the pre-isolation amplifier circuit includes a matching transformer, at least one low-noise amplifier, and an isolation transformer connected in sequence.

[0051] Specifically, Figure 3 is a schematic diagram of the pre-isolation amplifier circuit provided by the present invention, such as Figure 3As shown in the figure, the pre-isolation amplifier circuit consists of a matching transformer T1, two-stage low-noise amplifiers A1 and A2, and an isolation transformer T2. The matching transformer gain is 10dB, and the amplifier gains of A1 and A2 are 20dB and 10dB respectively. A1 and A2 are designed with OP27 operational amplifiers with a 3nV / Hz 1 / 2 Input noise, matching transformer T1 ratio is 1:3, isolation transformer T2 ratio is 1:1. To reduce the added noise of A1 amplifier resistor, R2, R3 values ​​are 10Ω, 100Ω, R4, R5 values ​​are 1kΩ, 2.4kΩ, the equivalent input noise of the pre-isolation amplifier is no more than 1.8nV / Hz 1 / 2 .

[0052] The isolated power supply provides isolated ±9V power supply to A1 and A2, matching transformer T1 isolates the input signal, isolation transformer T2 isolates the output signal, and the isolated IO control bus isolates the digital ground of the digital signal processing unit. Therefore, the pre-isolation amplifier circuit realizes isolation from the analog signal ground and power supply of the narrow-band filter amplifier unit, preventing the overall high-gain signal from being fed back to the pre-amplifier unit through the signal ground and power supply, improving the stability of the high-gain amplification of the whole machine, and avoiding the high-gain self-excited oscillation of the whole machine.

[0053] (2) Narrowband filter amplifier unit

[0054] 2.1) Block diagram of narrowband filter amplifier unit

[0055] Figure 4 is a block diagram of the narrowband amplification and filtering unit provided by the present invention, such as Figure 4 As shown, the first automatic gain circuit (AGC circuit 1), the first frequency adjustable narrowband filter (frequency adjustable narrowband filter 1), the second automatic gain circuit (AGC circuit 2), and the second frequency adjustable narrowband filter (frequency adjustable narrowband filter 2) are connected in sequence; the output of the second frequency adjustable narrowband filter (frequency adjustable narrowband filter 2) is respectively connected to the effective value detection circuit and the differential amplifier circuit; the effective value detection circuit is also respectively connected to the first automatic gain circuit and the second automatic gain circuit; the clock circuit is respectively connected to the first frequency adjustable narrowband filter and the second frequency adjustable narrowband filter.

[0056] Among them, AGC circuit 1 and AGC circuit 2 respectively realize 40dB automatic gain, each requiring 1 / 2 AD600 chip; frequency adjustable narrowband filter 1 and frequency adjustable narrowband filter 2 respectively filter out interference outside the receiving frequency, each requiring 1 / 2 LTC1068-25; therefore, 1 AD600 chip and 1 LTC1068-25 chip constitute the core composition of the narrowband filter amplification unit, which is the basis of soft-free miniaturized low-frequency reception.

[0057] The maximum gain of the preamplifier unit and the AGC circuit 1 before the frequency adjustable narrowband filter 1 is 40dB respectively, and the gain after the two is 80dB, so the noise requirement of the frequency adjustable narrowband filter 1 is reduced to no more than 10μV / Hz. 1 / 2 That's it.

[0058] The differential amplifier circuit converts the frequency-adjustable narrowband filter output from single-ended to differential output, enhances the anti-interference capability of the ADC input, and provides a 6dB gain.

[0059] 2.2) AGC circuit 1 and AGC circuit 2

[0060] The present invention requires that the automatic gain control has a dynamic range of 80dB. Usually, the automatic gain range of a single AGC cable is 40dB, so the AGC circuit is cascaded. The present invention adopts a two-stage variable gain amplifier circuit AGC circuit 1 and AGC circuit 2 cascaded to achieve automatic gain control with a dynamic range of 80dB. A frequency adjustable narrowband filter 1 is inserted between the cascade of AGC circuit 1 and AGC circuit 2 to improve the stability of 80dB direct amplification and prevent circuit self-excitation.

[0061] AGC circuit 1 and AGC circuit 2 use the AD600 integrated chip produced by the American AD company for circuit design. AD600 is a dual-channel, low-noise, wide-band VGA chip with precise gain control (i.e., programmable gain amplifier chip). The chip is dual-channel and consists of two-stage amplifiers. The gain of each stage of the amplifier can be controlled separately, and its gain range is 0 to 40dB. The bandwidth is from DC to 34MHz, and the input noise is as low as 1.4nV / Hz 1 / 2 ; High gain accuracy, error less than 0.3dB. AD600 uses X-AMP topology, each channel is mainly composed of an operational amplifier with a fixed gain of 42dB and a passive voltage-controlled device with an adjustable attenuation factor of 40dB.

[0062] The signal first enters the input end of the voltage-controlled attenuator (i.e., a passive voltage-controlled device with adjustable attenuation multiple), and the attenuation multiple of the voltage-controlled attenuator is determined by the output voltage VG of the effective value detection circuit. The value of VG is controlled by the external input voltage, and its size is (C1H-C1L). The built-in voltage-controlled attenuator has an attenuation range of 0 to 40dB, and the value of VG is like the probe of a sliding rheostat. When it slides to a certain point in the voltage-controlled attenuator, the input signal will be attenuated by the corresponding value.

[0063] When the reference voltage is 0.625V, the AGC circuit gain G formula is as follows:

[0064] G=32VG(1)

[0065] When VG is equal to 0, the attenuation value of the voltage-controlled attenuator is 40dB, the amplifier gain is 40dB, and the gains of AGC circuit 1 and AGC circuit 2 are both 0dB; when VG is equal to 0.625V, the attenuation value of the voltage-controlled attenuator is 20dB, the amplifier gain is 40dB, and the gains of AGC circuit 1 and AGC circuit 2 are both 20dB; when VG is equal to 1.25V, the attenuation value of the voltage-controlled attenuator is 0dB, the amplifier gain is 40dB, and the gains of AGC circuit 1 and AGC circuit 2 are both 40dB. When the voltage range of VG is between 0V and 1.25V, the entire circuit can achieve linear gain control.

[0066] Through this gain control scheme, the signal is first attenuated, and the internal operational amplifier does not need to process the signal with a large level first, so it can well avoid saturation distortion caused by excessive signal. At the same time, using a high-speed operational amplifier to adjust the gain control can also ensure a faster response speed of the control circuit. For the fixed gain operational amplifier at the output end, choosing an operational amplifier with a wide bandwidth ensures the wide bandwidth of the control circuit.

[0067] AGC circuit 1 and AGC circuit 2 share one AD600 chip, and adopt parallel control mode, connecting the input positive control terminals C1H and C2H of the two channels together and connecting to the control voltage VG; at the same time, the input reverse control terminals C1L and C2L of the two channels are also connected together and connected to the reference voltage 0.625V. Since the input terminals of the two channels are completely connected in parallel, the gain changes of the two channels are also synchronized. After the output and input of the two channels are connected in series, the gain change amplitude of the whole circuit is twice that of a single channel, which can be expressed as the total gain of the system is G = 2*(32VG), in dB. Therefore, the parallel mode can use a smaller control voltage to obtain a larger gain control.

[0068] 2.3) Frequency-adjustable narrowband filter 1 and frequency-adjustable narrowband filter 2

[0069] The present invention selects a monolithic LTC1068 series switch capacitor filter chip with a lower noise level as a frequency-adjustable narrowband filter. The performance of each chip in the LTC1068 series is shown in Table 1. The LTC1068-25 chip can meet the design requirements of a 4Hz-140kHz bandpass filter, and the LTC1068 and LTC1068-50 chips can meet the design requirements of a bandpass filter below 30kHz. The center frequency of the bandpass filter of the present invention is 10kHz-40kHz, which exceeds 30kHz, so the LTC1068-25 switch capacitor filter chip is selected to design a frequency-adjustable narrowband filter. The LTC1068-25 integrates 4 identical second-order switch capacitor filters internally, and the center frequency of each second-order filter is adjusted by an external 25-fold clock, and then a high-order filter can be formed using 4 second-order filter modules. The typical noise value of LTC1068-25 is 200μVrms. Compared with digital circuits, it has low noise characteristics, but compared with analog low noise circuits, the noise is still relatively large. Calculated based on a 400Hz bandwidth, the unit bandwidth noise is 10μV / Hz. 1 / 2 .

[0070] Frequency-adjustable narrowband filter 1 and frequency-adjustable narrowband filter 2 each require 1 / 2 LTC1068-25 chip; direct digital frequency synthesizer AD9832 and related devices constitute a clock circuit to provide the LTC1068-25 chip with an external clock signal that is 25 times the receiving frequency. For an operating frequency of 10kHz-40kHz, the clock circuit provides a clock frequency of 250kHz-1000kHz.

[0071] Table 1 Performance of each chip in the LTC1068 series

[0072]

[0073]

[0074] Figure 5 The schematic diagram of the frequency adjustable narrowband filter provided by the present invention is shown in FIG. Figure 5 As shown, it is an integrated circuit filter mainly composed of a switching capacitor and an operational amplifier. The basic principle is to adjust the switching frequency at both ends of the capacitor to change the equivalent resistance of the circuit, thereby achieving the function of changing the filter parameters.

[0075] Frequency tunable filters are mainly realized by switching capacitors, which are composed of MOS switches, MOS capacitors and MOS op amps. The effect of MOS capacitors with high-speed MOS switches is equivalent to connecting a resistor between two points. By changing the switching frequency of the MOS switch, the size of the resistor can be changed, thereby changing the cutoff frequency or center frequency of the filter, overcoming the disadvantage that the frequency of analog active filters is difficult to change.

[0076] Due to the advantages of MOS devices in speed, integration and precision, the parameters of the filter can be accurately adjusted. The main disadvantage is that the switching device will bring greater circuit noise and the operating frequency of the switching device has certain limitations and cannot process high-frequency signals.

[0077] Since the frequency of the narrowband filter can be changed by changing the output frequency of the clock circuit, the frequency-adjustable narrowband filter has a wide operating frequency range and a fast operating frequency adjustment speed. Compared with the crystal filter, the insertion loss is small, the ripple in the passband is small, and the attenuation in the stopband is large, which makes the filter have good noise filtering performance, and the switched capacitor filter can better meet the needs.

[0078] according to Figure 5 The performance of the designed frequency-adjustable narrowband filter is shown in Table 2. The 3dB bandwidth of the narrowband filter at the center frequency of 15kHz is 428Hz, which can meet the reception requirement of a channel rate of 400bit / s; the 3dB bandwidth of the center frequency of 30kHz is 855Hz, which can meet the reception requirement of a channel rate of 800bit / s; both are less than 3% of the center frequency, which is a relatively rational narrowband reception bandwidth; the 30dB stopband bandwidth is not greater than 11% of the center frequency, and the filter steepness coefficient is less than 4.

[0079] Table 2 Frequency adjustable narrowband filter performance

[0080] Frequency 15kHz 20kHz 25kHz 30kHz 3dB passband bandwidth 428Hz 571Hz 713Hz 855Hz 50dB stopband bandwidth 1390Hz 2250Hz 2830Hz 3320Hz Steepness coefficient 3.25 3.94 3.97 3.88

[0081] (3) Digital signal processing unit

[0082] The digital signal processing unit includes a DSP, an FPGA, a dual-channel ADC circuit, a crystal oscillator and a DDS clock circuit; one ADC input of the dual-channel ADC circuit is connected to the effective value detection circuit, the other ADC input of the dual-channel ADC circuit is connected to the differential amplifier circuit, and both outputs of the dual-channel ADC circuit are connected to the FPGA; the FPGA is respectively connected to the DSP and the DDS clock circuit, and the DDS clock circuit is respectively connected to the crystal oscillator, the other ADC input and the clock circuit in the narrow-band filter amplifier unit.

[0083] Specifically, Figure 6 is a block diagram of the digital signal processing unit provided by the present invention, such as Figure 6 As shown in the figure, the digital signal processing unit is mainly composed of TMS320C67XXDSP, FPGA, dual-channel ADC, high-stability crystal oscillator, DDS clock circuit, etc., with DSP and FPGA chips as the core, completing the main functions of signal synchronization, demodulation, decoding, etc. One ADC is used for main signal sampling with a sampling rate of 512kHz, and one ADC is used to sample the DC signal output by the effective value detection for the pre-attenuator IO control.

[0084] Figure 7 It is a schematic diagram of the digital signal processing flow provided by the present invention, such as Figure 7 As shown in the figure, the input signal is sampled by ADC with a sampling rate of 512kHz. ADC transmits the data to FPGA for digital down-conversion first, and the digital local oscillator frequency value is the operating frequency of 10kHz-40kHz. The data sampling rate of digital down-conversion is still the same as the original sampling rate, which is 512kHz. The FIR filter at the back stage cannot reach this processing rate at all, so data extraction is required. The core of data extraction is CIC (cascaded integrator comb), HB and FIR filters.

[0085] The FPGA performs large decimation using CIC (cascaded integrator comb) and HB (half-band) filter extractors to reduce the data rate, which is then filtered by FIR; FIR800, FIR400, FIR200, FIR100, and FIR50 correspond to FIR filters at different channel rates of 800bit / s, 400bit / s, 200bit / s, 100bit / s, and 50bit / s, respectively.

[0086] The AD sampling rate is 512kHz. 32 sampling points are required for each channel bit during MSK demodulation. The decimation multiples after data acquisition are shown in Table 3. Multiplication in the decimation scheme indicates cascading. For example, when the channel rate is 200bit / s, the decimation scheme is 20*2*2, which indicates a 20-fold decimation and two 2-fold cascades. The data rates at 800bit / s, 400bit / s, 200bit / s, 100bit / s, and 50bit / s are 25.6kbit / s, 12.8kbit / s, 6.4kbit / s, 3.2kbit / s, and 1.6kbit / s, respectively.

[0087] Table 3. Decimation schemes at different channel rates

[0088] Channel Rate Demodulation rate Extraction multiple Extraction scheme 800 25600 20 20 400 12800 40 20*2 200 6400 80 20*2*2 100 3200 160 20*2*2*2 50 1600 320 20*2*2*2*2

[0089] FPGA transmits the extracted data to DSP, which performs MSK demodulation and synchronization on the data. After signal synchronization, the data is transmitted to DSP for message demodulation, phase estimation calculation and decoding, and finally the decoded message is sent out through the network interface.

[0090] The present invention provides a low-frequency signal receiving device. According to the software radio design concept, a large-gain isolation direct amplifier and a variable center frequency bandpass filter are designed to replace the traditional frequency conversion receiver. An AD600 and an LTC1068-25 chip realize two-stage automatic gain and two-stage frequency adjustable narrowband filtering, which effectively reduces the scale of the circuit to 1 / 3 of the original frequency conversion receiver; the design of the pre-isolation amplifier and the two-stage automatic gain circuit has a high-sensitivity 16dB to 126dB large dynamic range receiving capability, and the isolation segmented amplification is designed. A frequency adjustable narrowband filter is inserted in the middle of the two-stage automatic gain circuit cascade to prevent the circuit from self-excitation, thereby improving the stability of the direct large-gain amplification. The bandwidth of the two-stage frequency adjustable narrowband filter is 400Hz to 1200Hz, and the steepness coefficient is less than 4, which can effectively suppress out-of-band interference; a 10dB-80dB amplifier is designed before the frequency adjustable narrowband filter to overcome the noise of the LTC1068-25 switch capacitor filter and achieve a receiving noise of the whole machine of less than 5nV / Hz. 1 / 2 The present invention realizes lightweight, stable and miniaturized underwater receiving capability, and is suitable for application scenarios such as UUV that have high requirements on power consumption and space.

[0091] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A low frequency signal receiving device, It is characterized in that include: A preamplifier unit, a narrowband filter amplifier unit and a digital signal processing unit connected in sequence; The preamplifier unit comprises an isolated power supply and a passive filter circuit, a controllable pre-attenuation circuit and a pre-isolation amplifier circuit which are connected in sequence; wherein the pre-isolation amplifier circuit is respectively connected to the isolated power supply and the first automatic gain circuit of the narrowband filter amplifier unit; The narrowband filter amplification unit comprises a first automatic gain circuit, a first frequency-adjustable narrowband filter, a second automatic gain circuit, a second frequency-adjustable narrowband filter, a differential amplifier circuit, an effective value detection circuit and a clock circuit; wherein the first automatic gain circuit, the first frequency-adjustable narrowband filter, the second automatic gain circuit and the second frequency-adjustable narrowband filter are connected in sequence; the output of the second frequency-adjustable narrowband filter is respectively connected to the effective value detection circuit and the differential amplifier circuit; the effective value detection circuit is also respectively connected to the first automatic gain circuit and the second automatic gain circuit; the clock circuit is respectively connected to the first frequency-adjustable narrowband filter and the second frequency-adjustable narrowband filter; The digital signal processing unit is respectively connected with the effective value detection circuit, the differential amplifier circuit, the clock circuit and the controllable pre-attenuation circuit.

2. The low-frequency signal receiving device according to claim 1, It is characterized in that The passive filtering circuit includes: a Butterworth bandpass filter.

3. The low-frequency signal receiving device according to claim 1, It is characterized in that The controllable pre-attenuation circuit is composed of attenuators with different attenuation values ​​and switching relays; the controllable pre-attenuation circuit changes the attenuator currently in use by switching the relays under the control of the digital signal processing unit.

4. The low-frequency signal receiving device according to claim 1, It is characterized in that The pre-isolation amplifier circuit comprises a matching transformer, at least one low noise amplifier, and an isolation transformer which are connected in sequence.

5. The low-frequency signal receiving device according to claim 1, It is characterized in that The first automatic gain circuit and the second automatic gain circuit share a programmable gain amplifier chip; The input forward control terminals of the first automatic gain circuit and the second automatic gain circuit are connected together and connected to the effective value detection circuit; Input inverting control terminals of the first automatic gain circuit and the second automatic gain circuit are connected together and connected to a reference voltage.

6. The low-frequency signal receiving device according to claim 1, It is characterized in that Also includes: The first frequency-adjustable narrowband filter and the second frequency-adjustable narrowband filter share a switched capacitor filter chip.

7. The low-frequency signal receiving device according to claim 1, It is characterized in that The digital signal processing unit includes a DSP, an FPGA, a dual-channel ADC circuit, a crystal oscillator and a DDS clock circuit; One ADC input of the dual-channel ADC circuit is connected to the effective value detection circuit, another ADC input of the dual-channel ADC circuit is connected to the differential amplifier circuit, and both outputs of the dual-channel ADC circuit are connected to the FPGA; The FPGA is connected to the DSP and the DDS clock circuit respectively, and the DDS clock circuit is connected to the crystal oscillator, another ADC input and the clock circuit in the narrow-band filter amplifier unit respectively.

8. The low-frequency signal receiving device according to claim 5, It is characterized in that The model of the programmable gain amplifier chip is AD600.

9. The low-frequency signal receiving device according to claim 6, It is characterized in that The model of the switched capacitor filter chip is the LTC1068 series chip.

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