Signal line electromigration inspection method and device, electronic device and storage medium

Abstract

A signal line electromigration inspection method, a signal line electromigration inspection device, an electronic device, and a non-transitory computer-readable storage medium. The signal line electromigration inspection method is applied to integrated circuit design, wherein the integrated circuit design includes a top-level design and multiple sub-designs. The signal line electromigration inspection method includes: generating multiple boundary model files corresponding one-to-one to the multiple sub-designs, wherein each boundary model file includes description information of multiple interactive elements in the sub-design corresponding to the boundary model file, and the multiple interactive elements are used to enable the sub-design to interact with the top-level design and / or the multiple sub-designs other than the sub-design corresponding to the boundary model file; obtaining a description file corresponding to the top-level design; and performing a signal line electromigration inspection on the top-level design based on the multiple boundary model files and the description file corresponding to the top-level design.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a signal line electromigration inspection method, a signal line electromigration inspection device, an electronic device, and a non-transitory computer-readable storage medium. Background Art

[0002] As the preparation process continues to advance, process accuracy increases, process line width continues to shrink, the integration of chip design continues to increase, and the current density per unit line width gradually increases. The demand for reliability has posed severe challenges to the scale and iteration time of chip signal line electromigration inspection. Summary of the Invention

[0003] At least one embodiment of the present disclosure provides a signal line electromigration inspection method, which is applied to integrated circuit design, wherein the integrated circuit design includes a top-level design and multiple sub-designs, and the signal line electromigration inspection method includes: generating multiple boundary model files corresponding one-to-one to the multiple sub-designs, wherein each boundary model file includes description information of multiple interactive elements in the sub-design corresponding to the boundary model file, and the multiple interactive elements are used to enable the sub-design to interact with the top-level design and / or sub-designs in the multiple sub-designs except the sub-design corresponding to the boundary model file; obtaining a description file corresponding to the top-level design; and performing signal line electromigration inspection on the top-level design based on the multiple boundary model files and the description file corresponding to the top-level design.

[0004] For example, in the signal line electromigration inspection method provided in at least one embodiment of the present disclosure, for the i-th sub-design among the multiple sub-designs, the i-th sub-design includes multiple logic units, multiple boundary signal connection nets and multiple pins, i is a positive integer, the multiple logic units include at least one boundary driving unit and at least one boundary receiving unit, the multiple pins include at least one boundary input pin and at least one boundary output pin, each boundary signal connection net is used to connect a boundary input pin and a boundary receiving unit or to connect a boundary output pin and a boundary driving unit, and the multiple interactive elements in the i-th sub-design include the at least one boundary driving unit, the at least one boundary receiving unit, the at least one boundary input pin, the at least one boundary output pin and the multiple boundary signal connection nets.

[0005] For example, in the signal line electromigration inspection method provided by at least one embodiment of the present disclosure, the i-th sub-design also includes at least one feedthrough connection net, the multiple pins also include at least one feedthrough input pin and at least one feedthrough output pin, each feedthrough connection net represents a connection net directly connected from a feedthrough input pin of the i-th sub-design to a feedthrough output pin, and the multiple interactive elements in the i-th sub-design also include the at least one feedthrough connection net, the at least one feedthrough input pin and the at least one feedthrough output pin.

[0006] For example, in the signal line electromigration inspection method provided in at least one embodiment of the present disclosure, a plurality of boundary model files corresponding one-to-one to the plurality of sub-designs are generated, including: obtaining a plurality of description files corresponding one-to-one to the plurality of sub-designs; and generating the plurality of boundary model files based on the plurality of description files corresponding one-to-one to the plurality of sub-designs.

[0007] For example, in the signal line electromigration inspection method provided by at least one embodiment of the present disclosure, the multiple boundary model files are generated based on multiple description files corresponding one-to-one to the multiple sub-designs, including: for each sub-design: deleting the description information corresponding to the elements in each sub-design except for the multiple interactive elements in each sub-design from the description file corresponding to each sub-design, so as to obtain the boundary model file corresponding to each sub-design.

[0008] For example, in the signal line electromigration inspection method provided in at least one embodiment of the present disclosure, multiple boundary model files corresponding one-to-one to the multiple sub-designs are generated, including: for each sub-design: obtaining description information of the multiple interactive elements in each sub-design to obtain the boundary model file corresponding to each sub-design.

[0009] For example, the signal line electromigration inspection method provided by at least one embodiment of the present disclosure further includes: acquiring multiple description files corresponding to the multiple sub-designs respectively; and performing signal line electromigration inspection on each sub-design based on the description file corresponding to each sub-design.

[0010] For example, in the signal line electromigration inspection method provided by at least one embodiment of the present disclosure, the description file corresponding to the top-level design is configured to be able to call multiple description files corresponding to the multiple sub-designs respectively.

[0011] For example, in the signal line electromigration inspection method provided in at least one embodiment of the present disclosure, the description file corresponding to the top-level design is a design exchange format file.

[0012] At least one embodiment of the present disclosure provides a signal line electromigration inspection device, which is applied to integrated circuit design, wherein the integrated circuit design includes a top-level design and multiple sub-designs, and the signal line electromigration inspection device includes: an acquisition unit, configured to acquire a description file corresponding to the top-level design; a generation unit, configured to generate multiple boundary model files corresponding one-to-one to the multiple sub-designs, wherein each boundary model file includes description information of multiple interactive elements in the sub-design corresponding to the boundary model file, and the multiple interactive elements are used to enable the sub-design to interact with the top-level design and / or sub-designs in the multiple sub-designs except the sub-design corresponding to the boundary model file; and an inspection unit, configured to perform signal line electromigration inspection on the top-level design based on the multiple boundary model files and the description file corresponding to the top-level design.

[0013] At least one embodiment of the present disclosure provides an electronic device, comprising: a memory, which non-transitorily stores computer-executable instructions; and a processor, configured to execute the computer-executable instructions, wherein the computer-executable instructions, when executed by the processor, implement the signal line electromigration inspection method according to any embodiment of the present disclosure.

[0014] At least one embodiment of the present disclosure provides a non-transitory computer-readable storage medium, wherein the non-transitory computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are executed by a processor, the signal line electromigration inspection method according to any embodiment of the present disclosure is implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0016] Figure 1 A schematic flow chart of a signal line electromigration inspection method provided in at least one embodiment of the present disclosure;

[0017] Figure 2 A schematic structural diagram of a sub-design provided for at least one embodiment of the present disclosure;

[0018] Figure 3 A schematic diagram of a top-level design structure provided for at least one embodiment of the present disclosure;

[0019] Figure 4 A schematic diagram of a signal line electromigration inspection device provided by at least one embodiment of the present disclosure;

[0020] Figure 5A schematic diagram of an electronic device provided in at least one embodiment of the present disclosure;

[0021] Figure 6 A schematic diagram of a non-transitory computer-readable storage medium provided for at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0022] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0023] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0024] In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of some known functions and components.

[0025] As chip (i.e., integrated circuit) designs continue to grow in scale and the number of compute nodes within them surges, demands on the capabilities of electronic design automation (EDA) tools and server storage are increasing. This is especially true for full-chip signal line electromigration signoff checks for ultra-large-scale designs requiring high performance and computing power, such as those for CPUs (central processing units) and GPUs (graphics processing units). The design capacity often exceeds the capacity limits of the EDA tools, leading to inability to support the tools and excessively long iteration times. This is an increasingly common problem.

[0026] Typically, chip designs are divided into multiple layers based on design scale and strategy. For example, a chip design can include both a top-level design and a bottom-level design. Signal line electromigration checking for a chip design involves flattening the entire chip design from top to bottom. This means that both the top-level and bottom-level designs are read into the tool to perform a comprehensive signal line electromigration check. Due to the large computational scale of chip designs, iteration times are lengthy, and storage capacity is consumed. If the chip design exceeds the tool's capacity limit, the tool will be unable to perform checks on the chip design, causing the tool process to crash.

[0027] The hierarchical processing method is a method in which the top-level design and bottom-level design of a chip design are checked for signal electromigration separately. When performing a signal line electromigration signoff check on the top-level design, the top-level design and bottom-level design are read into the tool for checking, and the EDA tool is set to use top-only mode. Top-only mode indicates a mode in which the EDA tool checks signal line electromigration. In this top-only mode, the EDA tool only performs signal line electromigration checks on signal nets (signal nets) with complete logical and physical connections defined in the top-level design's Design Exchange Format (DEF) file. Therefore, when the tool is set to use top-only mode, electromigration checks are performed on signal lines within the top-level design and on the interactive signal lines between the top-level design and the bottom-level design. However, even if the signal line electromigration checks are performed separately for the top-level design and the bottom-level design, the processing time for the top-level design in top-only mode is still very long, and the storage capacity is very large. When the top-level design and the bottom-level design are fully read into the tool, if the read data exceeds the tool's capacity limit, the signal line electromigration check of the top-level design cannot be completed, causing the tool process to crash.

[0028] At least one embodiment of the present disclosure provides a signal line electromigration inspection method. The signal line electromigration inspection method is applied to integrated circuit design, wherein the integrated circuit design includes a top-level design and multiple sub-designs. The signal line electromigration inspection method includes: generating multiple boundary model files corresponding to the multiple sub-designs, wherein each boundary model file includes description information of multiple interactive elements in the sub-design corresponding to the boundary model file, and the multiple interactive elements are used to enable the sub-design to interact with the top-level design and / or multiple sub-designs other than the sub-design corresponding to the boundary model file; obtaining a description file corresponding to the top-level design; and performing a signal line electromigration inspection on the top-level design based on the multiple boundary model files and the description file corresponding to the top-level design.

[0029] In the signal line electromigration check method provided in the embodiments of the present disclosure, signal line electromigration check can be performed on the top-level design based on the boundary model of the sub-design and the description file of the top-level design, thereby realizing hierarchical signal line electromigration check, thereby solving the problem of the bottleneck of the tool capacity upper limit, avoiding the read-in data exceeding the tool capacity upper limit, preventing the tool process from crashing, realizing signal line electromigration check on large-scale designs, reducing the iterative running time of the signal line electromigration check, and reducing the demand for server storage capacity.

[0030] At least one embodiment of the present disclosure further provides a signal line electromigration inspection device, an electronic device, and a non-transitory computer-readable storage medium applied to the above-mentioned signal line electromigration inspection method.

[0031] The embodiments of the present disclosure are described in detail below with reference to the accompanying drawings, but the present disclosure is not limited to these specific embodiments.

[0032] Figure 1 A schematic flowchart of a signal line electromigration inspection method provided in at least one embodiment of the present disclosure.

[0033] The signal line electromigration inspection method provided by the embodiments of the present disclosure can be applied to integrated circuit design (i.e., integrated circuit), for example, the integrated circuit design can be a large-scale integrated circuit design. For example, based on the design scale and design strategy, the integrated circuit design can be divided into multiple levels. For example, in some embodiments, the integrated circuit design can include a top-level design and multiple sub-designs, the top-level design including one or more of logic units (driving units and receiving units), non-logic units, connection nets, pins, etc., and each sub-design also includes one or more of logic units, non-logic units, connection nets, pins, etc.

[0034] like Figure 1 As shown, the signal line electromigration inspection method may include the following steps S10 to S12 .

[0035] Step S10: generating a plurality of boundary model files corresponding one-to-one to the plurality of sub-designs;

[0036] Step S11: Obtain a description file corresponding to the top-level design;

[0037] Step S12: performing signal line electromigration check on the top-level design based on the multiple boundary model files and the description file corresponding to the top-level design.

[0038] For example, in step S10, each boundary model file includes description information of multiple interactive elements in the sub-design corresponding to the boundary model file. Each sub-design can interact only with the top-level design, or can interact only with other sub-designs, or can interact with both the top-level design and other sub-designs. The multiple interactive elements in the sub-design are used to realize the interaction between the sub-design and the top-level design and / or sub-designs other than the sub-design in multiple sub-designs.

[0039] For example, the description of each interactive element may include the name of the interactive element, the name of the element / pin to which it is connected, and the direction, attributes, position, shape, and other information corresponding to the interactive element. The direction of the interactive element is logical. For example, if the interactive element is a pin, the direction of the interactive element indicates whether the pin is an output pin or an input pin. The attributes of the interactive element are used to indicate whether the pin is a power pin, a ground pin, a signal pin, or a clock pin.

[0040] For example, in an integrated circuit design, each sub-design may include multiple logic units, multiple connection nets, and multiple pins. The multiple connection nets may include a clock net (clock net), a power net (power net), a ground net (ground net), a signal connection net (signal net), etc. Signal connection nets may include boundary signal connection nets, internal signal connection nets, feedthrough connection nets, etc. Each connection net is used to implement a connection function. For example, each connection net may include wires (metal wires, etc.) and may also include structures such as vias.

[0041] For example, in step S10 , the boundary model file corresponding to each sub-design is a file based on a design exchange format.

[0042] For example, in some embodiments, for the i-th sub-design among multiple sub-designs, the i-th sub-design includes multiple logic cells, multiple boundary signal connection nets, and multiple pins, where i is a positive integer, the multiple logic cells include at least one boundary driver cell and at least one boundary receiver cell, the multiple pins include at least one boundary input pin and at least one boundary output pin, each boundary signal connection net is used to connect a boundary input pin to a boundary receiver cell or a boundary output pin to a boundary driver cell, and the multiple interactive elements in the i-th sub-design include at least one boundary driver cell, at least one boundary receiver cell, at least one boundary input pin, at least one boundary output pin, and multiple boundary signal connection nets. In this case, the boundary model file corresponding to the i-th sub-design includes description information of at least one boundary driver cell, description information of at least one boundary receiver cell, description information of at least one boundary input pin, description information of at least one boundary output pin, description information of the multiple boundary signal connection nets, description information of the physical and logical connections between each boundary driver cell and the corresponding boundary output pin, and description information of the physical and logical connections between each boundary receiver cell and the corresponding boundary input pin.

[0043] It should be noted that the i-th sub-design may be any sub-design among the multiple sub-designs.

[0044] For example, for each boundary signal connection net in a sub-design, if the boundary signal connection net is connected to a boundary receiving unit in the sub-design, the driving unit corresponding to the boundary signal connection net is located in another sub-design other than the sub-design in the top-level design or multiple sub-designs; if the boundary signal connection net is connected to a boundary driving unit in the sub-design, the receiving unit corresponding to the boundary signal connection net is located in another sub-design other than the sub-design in the top-level design or multiple sub-designs. For example, in some examples, a boundary receiving unit in a sub-design is connected to a boundary input pin in the sub-design through a boundary signal connection net in the sub-design, then the boundary input pin in the sub-design can be connected to a driving unit in the top-level design through a connection net, or the boundary input pin in the sub-design can be connected to a boundary output pin in another sub-design through a connection net, and the boundary output pin in the other sub-design is connected to a driving unit in the other sub-design through a boundary signal connection net in the other sub-design.

[0045] It should be noted that, for example, a sub-design may include a boundary driving unit, a boundary output pin, and a boundary signal connection network, but does not include a boundary receiving unit and a boundary input pin. In this case, the multiple interactive elements in the sub-design include a boundary driving unit, a boundary output pin, and a boundary signal connection network. For another example, a sub-design may include a boundary receiving unit, a boundary input pin, and a boundary signal connection network, but does not include a boundary driving unit and a boundary output pin. In this case, the multiple interactive elements in the sub-design include a boundary receiving unit, a boundary input pin, and a boundary signal connection network. The embodiments of the present disclosure do not specifically limit the number and type of interactive elements in each sub-design. The specific type and number of interactive elements in each sub-design are determined according to the sub-design.

[0046] It should be noted that, in the embodiments of the present disclosure, each signal connection network can be used to connect one driving unit and at least one receiving unit, that is, each signal connection network can connect one driving unit to one receiving unit or to multiple receiving units.

[0047] For example, in some embodiments, the i-th sub-design further includes at least one feedthrough connection net, the plurality of pins further include at least one feedthrough input pin and at least one feedthrough output pin, and each feedthrough connection net represents a connection net that directly connects a feedthrough input pin of the i-th sub-design to a feedthrough output pin. The plurality of interactive elements in the i-th sub-design further include at least one feedthrough connection net, at least one feedthrough input pin, and at least one feedthrough output pin. In this case, the boundary model file corresponding to the i-th sub-design further includes description information of the at least one feedthrough connection net, description information of the at least one feedthrough input pin, description information of the at least one feedthrough output pin, and description information of the physical and logical connections between each feedthrough connection net and the feedthrough input pin and feedthrough output pin to which the feedthrough connection net is connected.

[0048] For example, in some embodiments, step S10 may include: acquiring a plurality of description files corresponding one-to-one to the plurality of sub-designs; and generating a plurality of boundary model files based on the plurality of description files corresponding one-to-one to the plurality of sub-designs.

[0049] For example, in step S10, based on multiple description files corresponding one-to-one to multiple sub-designs, generating multiple boundary model files includes: for each sub-design: deleting the description information corresponding to the elements in each sub-design except for the multiple interactive elements in each sub-design from the description file corresponding to each sub-design, so as to obtain the boundary model file corresponding to each sub-design.

[0050] For example, in some embodiments, the elements in each sub-design other than the multiple interactive elements in each sub-design may include at least one non-logical unit. In this case, deleting the description information corresponding to the elements in each sub-design other than the multiple interactive elements in each sub-design from the description file corresponding to each sub-design may include: deleting the description information corresponding to at least one non-logical unit in the sub-design from the description file corresponding to each sub-design.

[0051] For example, in some other embodiments, each sub-design further includes at least one internal signal connection network, the multiple logic units in each sub-design include at least one internal driver unit and at least one internal receiving unit, each internal signal connection network is used to connect an internal driver unit and an internal receiving unit, and the elements in each sub-design other than the multiple interactive elements in each sub-design may include at least one non-logical unit, at least one internal signal connection network, at least one internal driver unit, and at least one internal receiving unit. In this case, deleting the description information corresponding to the elements in each sub-design other than the multiple interactive elements in each sub-design from the description file corresponding to each sub-design may include: deleting the description information corresponding to the at least one non-logical unit in the sub-design, deleting the description information corresponding to the internal signal network in the sub-design, and deleting the description information corresponding to the internal driver unit and the internal receiving unit in the sub-design (including the description information of the internal driver unit and the internal receiving unit, and the description information of the logical connections and physical connections corresponding to the internal driver unit and the internal receiving unit).

[0052] For example, the non-logical cell may include a physical filler, etc. The non-logical cell does not have a logical function. The physical filler may be a metal filler, a decoupling capacitor filler, etc.

[0053] For example, in some other embodiments, step S10 may include: for each sub-design: obtaining description information of multiple interactive elements in each sub-design to obtain a boundary model file corresponding to each sub-design.

[0054] For example, in some embodiments, in step S10 , obtaining description information of the multiple interactive elements in each sub-design may include: obtaining description information of the multiple interactive elements in each sub-design from a description file corresponding to the sub-design.

[0055] For example, in other embodiments, in step S10, obtaining description information of multiple interactive elements in each sub-design may include: obtaining description information of multiple interactive elements in the sub-design from a design library file corresponding to a tool that performs layout and routing of the sub-design.

[0056] For example, if the multiple interactive elements in each sub-design include at least one boundary driving unit, at least one boundary receiving unit, at least one boundary input pin, at least one boundary output pin and multiple boundary signal connection nets, then obtaining the description information of the multiple interactive elements in each sub-design includes: obtaining the description information of at least one boundary driving unit, the description information of at least one boundary receiving unit, the description information of at least one boundary input pin, the description information of at least one boundary output pin, the description information of multiple boundary signal connection nets, the description information of the physical connection and the logical connection between each boundary driving unit and the corresponding boundary output pin (the corresponding boundary output pin represents the output pin connected to the boundary driving unit), and the description information of the physical connection and the logical connection between each boundary receiving unit and the corresponding boundary input pin (the corresponding boundary input pin represents the input pin connected to the boundary receiving unit).

[0057] For example, if the multiple interactive elements in each sub-design also include at least one feedthrough connection net, at least one feedthrough input pin and at least one feedthrough output pin, then obtaining the description information of the multiple interactive elements in each sub-design also includes: obtaining the description information of at least one feedthrough connection net, the description information of at least one feedthrough input pin, the description information of at least one feedthrough output pin, and the description information of the physical connection and logical connection between each feedthrough connection net and the feedthrough input pin and feedthrough output pin to which the feedthrough connection net is connected.

[0058] For example, the description file corresponding to the top-level design is a design exchange format file, and the description file corresponding to each sub-design can also be a design exchange format file. The description file corresponding to the top-level design and the description file corresponding to each sub-design can also be other suitable files, and the embodiments of the present disclosure do not specifically limit this.

[0059] For example, the description file corresponding to the top-level design is configured to be able to call multiple description files corresponding to multiple sub-designs. The description file corresponding to the top-level design may include description information of the physical connections and logical connections of the connection network that interacts between all sub-designs, and may also include description information of the internal components of the top-level design and description information of the physical connections and logical connections between the internal components. The description file corresponding to the sub-design may include description information of all components included in the sub-design and description information of the physical connections and logical connections between all components. The description file corresponding to the top-level design does not include description information of the physical connections and logical connections between the components included in the sub-design.

[0060] It should be noted that an integrated circuit design can be divided into more than two layers. In other embodiments, the integrated circuit design includes a top-level design, multiple first-level sub-designs, and multiple second-level sub-designs. The description file corresponding to each second-level sub-design includes at least one component included in the second-level sub-design and its connection relationship. The description file corresponding to each first-level sub-design may include the connection relationship (including physical and logical connections) between some of the second-level sub-designs in the multiple second-level sub-designs and the connection relationship between the part of the second-level sub-design and the first-level sub-design. For example, the description file corresponding to each first-level sub-design may also include at least one component within the first-level sub-design and its connection relationship. The top-level design includes the connection relationship (including physical and logical connections) between some of the first-level sub-designs in the multiple first-level sub-designs and the connection relationship between the part of the first-level sub-design and the top-level design. For example, the description file corresponding to the top-level design may also include at least one component within the top-level design and its connection relationship. The description file corresponding to the top-level design may call the description file corresponding to the first-level sub-design, and the description file corresponding to the first-level sub-design may call the description file corresponding to its corresponding second-level sub-design.

[0061] For example, the description information of the logical connection includes the logical connection relationship (represented by the netlist), physical constraints, etc. The description information of the physical connection includes layout planning, layout position and direction, and routing rules (eg, routing geometry data, etc.).

[0062] For example, when designing an integrated circuit, a corresponding description file may be set for the top-level design and a corresponding description file may be set for each sub-design, so that in step S11 , the description file corresponding to the top-level design setting may be directly obtained.

[0063] For example, in step S12 , signal line electromigration check may be performed on the signal lines in the top-level design based on the multiple boundary model files and the description file corresponding to the top-level design.

[0064] Figure 2 A schematic diagram of a sub-design provided for at least one embodiment of the present disclosure. Figure 2 The sub-design provided by the embodiments of the present disclosure is described in detail.

[0065] like Figure 2As shown, in some embodiments, sub-design 100 may include a boundary driver unit S1, a boundary receiver unit S2, a first connection net L1, a second connection net L2, a third connection net L3, a fourth connection net L4, an internal driver unit S5, an internal receiver unit S6, a feedthrough input pin S31, a feedthrough output pin S32, a boundary output pin S41, and a boundary input pin S42. It should be noted that feedthrough input pin S31 and boundary input pin S42 are both input pins, with the difference that feedthrough input pin S31 is directly connected to feedthrough output pin S32 via a connection net (e.g., second connection net L2), while boundary input pin S42 is connected to a boundary receiver unit S2 via a connection net (e.g., third connection net L3). Similarly, the feedthrough output pin S32 and the boundary output pin S41 are both output pins. The feedthrough output pin S32 is directly connected to the feedthrough input pin S31 through a connection net (for example, the second connection net L2), while the boundary output pin S41 is connected to a boundary driving unit S1 through a connection net (for example, the fourth connection net L4).

[0066] The first connection network L1 is an internal signal connection network, and the first connection network L1 is used to connect the internal driving unit S5 and the internal receiving unit S6.

[0067] The second connection net L2 is a feedthrough connection net, which is directly connected from the feedthrough input pin S31 of the sub-design 100 to the feedthrough output pin S32 .

[0068] The third connection net L3 and the fourth connection net L4 are both boundary signal connection nets. The third connection net L3 is used to connect the boundary input pin S42 to the boundary receiving unit S2, and the fourth connection net L4 is used to connect the boundary output pin S41 to the boundary driving unit S1.

[0069] It should be noted that the sub-design 100 may also include at least one non-logical unit ( Figure 2 not shown).

[0070] Below is Figure 2 The sub-design 100 shown is used as an example to describe the process of generating the boundary model file corresponding to each sub-design.

[0071] For example, in one embodiment, in step S10, first, a description file (e.g., a design exchange format file) corresponding to the sub-design 100 may be obtained, and then description information corresponding to at least one non-logic unit in the sub-design 100, description information corresponding to the internal signal connection network (i.e., the first connection network L1) in the sub-design 100, and logic units (e.g., the first connection network L2) other than the boundary driver unit S1 and the boundary receiver unit S2 in the sub-design 100 are deleted from the description file corresponding to the sub-design 100. Figure 2The description information corresponding to the internal driving unit S5 and the internal receiving unit S6 in the sub-design 100 is obtained to obtain the boundary model file corresponding to the sub-design 100. At this time, the boundary model file corresponding to the sub-design 100 includes the description information of the boundary output pin S41, the description information of the boundary input pin S42, the description information of the boundary signal connection nets L3 and L4, the description information of the boundary driving unit S1, the description information of the boundary receiving unit S2, the description information of the physical connection and logical connection between the boundary driving unit S1 and the boundary output pin S41, the description information of the physical connection and logical connection between the boundary receiving unit S2 and the boundary input pin S42, the description information of the feedthrough connection net L2, the description information of the feedthrough input pin S31, the description information of the feedthrough output pin S32, and the description information of the physical connection and logical connection between the feedthrough connection net L2 and the feedthrough input pin S31 and the feedthrough output pin S32.

[0072] For example, in another embodiment, in step S10, first, a description file corresponding to the sub-design 100 can be obtained, and then the description information of the boundary output pin S41, the description information of the boundary input pin S42, the description information of the boundary signal connection network L3 and L4, the description information of the boundary driving unit S1, the description information of the boundary receiving unit S2, the description information of the physical connection and logical connection between the boundary driving unit S1 and the boundary output pin S41, the description information of the physical connection and logical connection between the boundary receiving unit S2 and the boundary input pin S42, the description information of the feedthrough connection network L2, the description information of the feedthrough input pin S31, the description information of the feedthrough output pin S32, and the description information of the physical connection and logical connection between the feedthrough connection network L2 and the feedthrough input pin S31 and the feedthrough output pin S32 are extracted from the description file corresponding to the sub-design 100 to obtain the boundary model file corresponding to the sub-design 100.

[0073] Figure 3 A schematic diagram of a top-level design structure provided for at least one embodiment of the present disclosure.

[0074] like Figure 3 As shown, the integrated circuit design may include a top-level design 200 and a plurality of sub-designs, including a first sub-design 210 and a second sub-design 220 .

[0075] For example, Figure 3As shown, top-level design 200 may include internal receiving cell TS21, boundary receiving cell TS22, boundary receiving cell TS23, internal driving cell TS11, boundary driving cell TS12, boundary driving cell TS13, and boundary driving cell TS14. Boundary receiving cell TS22, boundary receiving cell TS23, boundary driving cell TS12, boundary driving cell TS13, and boundary driving cell TS14 are used to connect with sub-designs.

[0076] For example, Figure 3 As shown, the first sub-design 210 may include a boundary driving unit SS11, a boundary driving unit SS12, a boundary receiving unit SS21, a feedthrough connection network SL1, a boundary signal connection network SL2, a boundary signal connection network SL3, a boundary signal connection network SL4, a feedthrough input pin SP11, a feedthrough output pin SP21, a boundary input pin SP12, a boundary output pin SP22 and a boundary output pin SP23.

[0077] Inside the first sub-design 210, the feedthrough connection network SL1 is used to connect the feedthrough input pin SP11 and the feedthrough output pin SP21, the boundary signal connection network SL2 is used to connect the boundary output pin SP22 and the boundary driving unit SS11, the boundary signal connection network SL3 is used to connect the boundary input pin SP12 and the boundary receiving unit SS21, and the boundary signal connection network SL4 is used to connect the boundary output pin SP23 and the boundary driving unit SS12.

[0078] For example, Figure 3 As shown, the second sub-design 220 may include a boundary receiving unit SS22, a boundary receiving unit SS23, a boundary receiving unit SS24, a boundary driving unit SS13, a boundary signal connection network SL5 to a boundary signal connection network SL8, a boundary input pin SP13, a boundary input pin SP14, a boundary input pin SP15 and a boundary output pin SP24.

[0079] Inside the second sub-design 220, the boundary signal connection network SL5 is used to connect the boundary input pin SP13 and the boundary receiving unit SS22, the boundary signal connection network SL6 is used to connect the boundary input pin SP14 and the boundary receiving unit SS23, the boundary signal connection network SL7 is used to connect the boundary input pin SP15 and the boundary receiving unit SS24, and the boundary signal connection network SL8 is used to connect the boundary output pin SP24 and the boundary driving unit SS13.

[0080] For example, Figure 3As shown, the top-level design 200 may also include an internal connection network TL1 and boundary signal connection networks TL2 to TL8. The boundary signal connection networks TL2 to TL8 are used to connect the various sub-designs and to connect the various sub-designs with the boundary driving units and boundary receiving units in the top-level design. For example, in the top-level design 200, the internal signal connection network TL1 is used to connect the internal receiving unit TS21 and the internal driving unit TS11, the boundary signal connection network TL2 is used to connect the boundary driving unit TS12 and the feedthrough input pin SP11 of the first sub-design 210, the boundary signal connection network TL3 is used to connect the boundary driving unit TS13 and the boundary input pin SP12 of the first sub-design 210, the boundary signal connection network TL4 is used to connect the boundary receiving unit TS22 and the boundary output pin SP22 of the first sub-design 210, and the boundary signal connection network TL5 is used to connect the feedthrough output pin SP21 of the first sub-design 210 and the boundary input pin SP13 of the second sub-design 220, the boundary signal connection network TL6 is used to connect the boundary output pin SP23 of the first sub-design 210 and the boundary input pin SP14 of the second sub-design 220, the boundary signal connection network TL7 is used to connect the boundary output pin SP24 of the second sub-design 220 and the boundary receiving unit TS23, and the boundary signal connection network TL8 is used to connect the boundary input pin SP15 of the second sub-design 220 and the boundary driving unit TS14.

[0081] It should be noted that for each pin in a sub-design, the pin is an input pin relative to the sub-design, and is an output pin relative to the top-level design.

[0082] exist Figure 3 In the example shown, the boundary model file corresponding to the first sub-design 210 includes Figure 3 The first sub-design 210 includes description information of each component, connection network and pin as well as description information of their physical and logical connections. The boundary model file corresponding to the second sub-design 220 includes Figure 3 The description information of each component, connection network and pin included in the second sub-design 220 as shown, as well as the description information of the physical connection and logical connection between them, the description file corresponding to the top-level design 200 includes Figure 3 The description information of each component and connection network in the top-level design 200, the description information of the physical connection and logical connection between the top-level design 200 and the first sub-design 210 and the second sub-design 220, and the description information of the physical connection and logical connection between the first sub-design 210 and the second sub-design 220 are shown.

[0083] It should be noted that each of the first sub-design 210, the second sub-design 220 and the top-level design 200 may further include at least one non-logical unit ( Figure 3not shown).

[0084] For example, in some embodiments, the signal line electromigration check method may further include: acquiring a plurality of description files corresponding to a plurality of sub-designs; and performing a signal line electromigration check on each sub-design based on the description file corresponding to each sub-design.

[0085] The signal line electromigration inspection method provided by the embodiments of the present disclosure effectively solves the problem of large storage capacity requirements for the server, effectively solves the bottleneck problem of the upper limit of tool capacity, and effectively solves the problem of long iterative running time, avoids the read-in data exceeding the upper limit of tool capacity, thereby preventing the tool process from crashing, and realizes signal line electromigration inspection for large-scale designs, reduces the iterative running time of signal line electromigration inspection, and reduces the storage capacity of the server.

[0086] Figure 4 A schematic diagram of a signal line electromigration inspection device provided in at least one embodiment of the present disclosure.

[0087] At least one embodiment of the present disclosure further provides a signal line electromigration inspection device, which is applied to integrated circuit design. An integrated circuit design includes a top-level design and multiple sub-designs. For details regarding the top-level design and multiple sub-designs, refer to the description of the signal line electromigration inspection method described above, and any repetitions will not be repeated.

[0088] like Figure 4 As shown, the signal line electromigration inspection device 400 may include a generating unit 401 , an acquiring unit 402 and an inspecting unit 403 .

[0089] The generation unit 401 is configured to generate a plurality of boundary model files corresponding to a plurality of sub-designs. Each boundary model file includes description information of a plurality of interactive elements in the sub-design corresponding to the boundary model file, and the plurality of interactive elements are used to implement the interaction between the sub-design and the top-level design and / or the sub-designs other than the sub-design corresponding to the boundary model file in the plurality of sub-designs. The generation unit 401 is used to implement Figure 1 As shown in step S10, the specific operations performed by the generating unit 401 can be found in the above description of step S10, which will not be repeated here.

[0090] The acquisition unit 402 is configured to acquire a description file corresponding to the top-level design. Figure 1 As shown in step S11, the specific operations performed by the obtaining unit 402 can be found in the above description of step S11, which will not be repeated here.

[0091] The checking unit 403 is configured to perform a signal line electromigration check on the top-level design based on a plurality of boundary model files and a description file corresponding to the top-level design. Figure 1 As shown in step S12, the specific operations performed by the checking unit 403 can be found in the above description of step S12, which will not be repeated here.

[0092] For example, in some embodiments, the generating unit 401 , the acquiring unit 402 and / or the checking unit 403 may be implemented by hardware, software, firmware, or a combination thereof.

[0093] For example, in some embodiments, the generation unit 401, the acquisition unit 402, and / or the inspection unit 403 may include codes and programs stored in a memory; a processor may execute the codes and programs to implement some or all of the functions of the generation unit 401, the acquisition unit 402, and / or the inspection unit 403 described above. For example, the generation unit 401, the acquisition unit 402, and / or the inspection unit 403 may be dedicated hardware devices used to implement some or all of the functions of the generation unit 401, the acquisition unit 402, and / or the inspection unit 403 described above. For example, the generation unit 401, the acquisition unit 402, and / or the inspection unit 403 may be a circuit board or a combination of multiple circuit boards used to implement the functions described above. In an embodiment of the present disclosure, the circuit board or the combination of multiple circuit boards may include: (1) one or more processors; (2) one or more non-transitory memories connected to the processors; and (3) firmware stored in the memory that is executable by the processor.

[0094] For example, in some embodiments, for the i-th sub-design among multiple sub-designs, the i-th sub-design includes multiple logic units, multiple boundary signal connection nets and multiple pins, i is a positive integer, the multiple logic units include at least one boundary driving unit and at least one boundary receiving unit, the multiple pins include at least one boundary input pin and at least one boundary output pin, each boundary signal connection net is used to connect a boundary input pin and a boundary receiving unit or to connect a boundary output pin and a boundary driving unit, and the multiple interactive elements in the i-th sub-design include at least one boundary driving unit, at least one boundary receiving unit, at least one boundary input pin, at least one boundary output pin and multiple boundary signal connection nets.

[0095] For example, in some embodiments, the i-th sub-design further includes at least one feedthrough connection net, the multiple pins further include at least one feedthrough input pin and at least one feedthrough output pin, each feedthrough connection net represents a connection net directly connected from a feedthrough input pin to a feedthrough output pin of the i-th sub-design, and the multiple interactive elements in the i-th sub-design further include at least one feedthrough connection net, at least one feedthrough input pin, and at least one feedthrough output pin.

[0096] For example, in some embodiments, when performing an operation of generating multiple boundary model files corresponding one-to-one to multiple sub-designs, the generation unit 401 is configured to: obtain multiple description files corresponding one-to-one to the multiple sub-designs; and generate multiple boundary model files based on the multiple description files corresponding one-to-one to the multiple sub-designs.

[0097] For example, in some embodiments, when performing an operation of generating multiple boundary model files based on multiple description files corresponding one-to-one to multiple sub-designs, the generation unit 401 is configured to: for each sub-design: delete the description information corresponding to the elements in each sub-design except for the multiple interactive elements in each sub-design from the description file corresponding to each sub-design, so as to obtain the boundary model file corresponding to each sub-design.

[0098] For example, in other embodiments, when performing the operation of generating multiple boundary model files corresponding one-to-one to multiple sub-designs, the generation unit 401 is configured to: for each sub-design: obtain description information of multiple interactive elements in each sub-design to obtain the boundary model file corresponding to each sub-design.

[0099] For example, in some embodiments, the acquisition unit 402 is further configured to acquire multiple description files corresponding to multiple sub-designs respectively; the inspection unit 403 is further configured to perform signal line electromigration inspection on each sub-design based on the description file corresponding to each sub-design.

[0100] For example, in some embodiments, the description file corresponding to the top-level design is configured to be able to call multiple description files corresponding to multiple sub-designs.

[0101] For example, in some embodiments, the description file corresponding to the top-level design is a design exchange format file.

[0102] It should be noted that the signal line electromigration inspection device can achieve similar technical effects as the aforementioned signal line electromigration inspection method, which will not be described in detail here.

[0103] At least one embodiment of the present disclosure further provides an electronic device, Figure 5 A schematic diagram of an electronic device provided according to at least one embodiment of the present disclosure.

[0104] For example, Figure 5 As shown, the electronic device 500 includes a processor 501 and a memory 502. It should be noted that Figure 5 The components of the electronic device 500 shown are merely exemplary and non-limiting. The electronic device 500 may also have other components according to actual application requirements.

[0105] For example, the processor 501 and the memory 502 can communicate with each other. In some examples, the processor 501 and the memory 502 can communicate via a communication bus 503 or a network. For example, the communication bus 503 can be a peripheral component interconnect (PCI) bus or an extended industrial standard architecture (EISA) bus, etc. The communication bus 503 can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 5 The use of only one bold line to represent the communication bus 503 does not necessarily mean that there is only one bus or only one type of bus. The network may include a wireless network, a wired network, and / or any combination of wireless and wired networks. The embodiments of the present disclosure do not limit the type and function of the network and communication bus 503.

[0106] For example, the memory 502 is configured to non-transiently store computer-executable instructions. The processor 501 is configured to execute the computer-executable instructions. When the computer-executable instructions are executed by the processor 501, the signal line electromigration inspection method according to any of the above-described embodiments is implemented. The specific implementation and related explanations of each step of the signal line electromigration inspection method can be found in the above-described embodiments of the signal line electromigration inspection method and are not further described here.

[0107] For example, other implementations of the signal line electromigration inspection method implemented by the processor 501 executing computer-readable instructions stored in the memory 502 are the same as the implementations mentioned in the aforementioned method embodiment part and will not be repeated here.

[0108] For example, the electronic device 500 may further include a communication interface 504 , which is used to implement communication between the electronic device 500 and other devices.

[0109] For example, the processor 501 and the memory 502 may be provided on a server side (or a cloud side).

[0110] For example, the processor 501 can control other components in the electronic device 500 to perform desired functions. The processor 501 can be a device with data processing capabilities and / or program execution capabilities, such as a central processing unit (CPU), a network processor (NP), a tensor processing unit (TPU), or a graphics processing unit (GPU). It can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The central processing unit (CPU) can be an X86 or ARM architecture, etc.

[0111] For example, the memory 502 may include any combination of one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), a hard disk, an erasable programmable read-only memory (EPROM), a portable compact disk read-only memory (CD-ROM), a USB memory, a flash memory, etc. One or more computer-readable instructions may be stored on the computer-readable storage medium, and the processor 501 may execute the computer-readable instructions to implement various functions of the electronic device 500. Various applications and various data may also be stored in the storage medium.

[0112] For example, for a detailed description of the process of the electronic device 500 performing the signal line electromigration inspection, reference may be made to the relevant description in the embodiment of the signal line electromigration inspection method, and repeated parts will be omitted.

[0113] Figure 6 A schematic diagram of a non-transitory computer-readable storage medium provided for at least one embodiment of the present disclosure. Figure 6 As shown, one or more computer-executable instructions 601 may be non-transitory stored on a non-transitory computer-readable storage medium 600. For example, when the computer-executable instructions 601 are executed by a processor, one or more steps of the signal line electromigration inspection method according to any of the above embodiments may be performed.

[0114] For example, the non-transitory computer-readable storage medium 600 may be applied to the above-mentioned electronic device 500 . For example, the non-transitory computer-readable storage medium 600 may include the memory 502 in the electronic device 500 .

[0115] For example, the description of the non-transitory computer-readable storage medium 600 may refer to the description of the memory 502 in the embodiment of the electronic device 500, and the repeated parts will be omitted.

[0116] Regarding this disclosure, the following points need to be explained:

[0117] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure. Other structures may refer to conventional designs.

[0118] (2) For the sake of clarity, the thickness and size of layers or structures in the drawings used to describe the embodiments of the present invention are exaggerated. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element can be "directly on" or "under" the other element, or intervening elements may be present.

[0119] (3) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to form new embodiments.

[0120] The above description is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure shall be based on the protection scope of the claims.

Claims

1. A signal line electromigration inspection method, applied to integrated circuit design, wherein: The integrated circuit design includes a top-level design and multiple sub-designs, The signal line electromigration inspection method comprises: generating a plurality of boundary model files corresponding one-to-one to the plurality of sub-designs, wherein each boundary model file includes description information of a plurality of interactive elements in the sub-design corresponding to the boundary model file, the plurality of interactive elements being used to enable the sub-design to interact with the top-level design and / or sub-designs in the plurality of sub-designs other than the sub-design corresponding to the boundary model file; Obtaining a description file corresponding to the top-level design; Performing a signal line electromigration check on the top-level design based on the multiple boundary model files and a description file corresponding to the top-level design; The step of generating a plurality of boundary model files corresponding one-to-one to the plurality of sub-designs includes: Acquire a plurality of description files corresponding one-to-one to the plurality of sub-designs; generating the plurality of boundary model files based on a plurality of description files corresponding one-to-one to the plurality of sub-designs; The step of generating the plurality of boundary model files based on the plurality of description files corresponding one-to-one to the plurality of sub-designs includes: For each sub-design: Deleting description information corresponding to the elements in each sub-design other than the multiple interactive elements in each sub-design from the description file corresponding to each sub-design to obtain a boundary model file corresponding to each sub-design, wherein the elements in each sub-design other than the multiple interactive elements in each sub-design include at least one of at least one non-logical unit, at least one internal signal connection network, at least one internal driving unit, and at least one internal receiving unit.

2. The signal line electromigration inspection method according to claim 1, wherein: For the i-th sub-design among the multiple sub-designs, the i-th sub-design includes multiple logic units, multiple boundary signal connection nets and multiple pins, where i is a positive integer. The plurality of logic units include at least one boundary driving unit and at least one boundary receiving unit, the plurality of pins include at least one boundary input pin and at least one boundary output pin, and each boundary signal connection network is used to connect a boundary input pin and a boundary receiving unit or to connect a boundary output pin and a boundary driving unit. The plurality of interactive elements in the i-th sub-design include the at least one boundary driving unit, the at least one boundary receiving unit, the at least one boundary input pin, the at least one boundary output pin, and the plurality of boundary signal connection nets.

3. The signal line electromigration inspection method according to claim 2, wherein: The i-th sub-design further includes at least one feedthrough connection net, the plurality of pins further include at least one feedthrough input pin and at least one feedthrough output pin, each feedthrough connection net represents a connection net directly connected from a feedthrough input pin to a feedthrough output pin of the i-th sub-design, The plurality of interactive elements in the i-th sub-design further include the at least one feedthrough connection net, the at least one feedthrough input pin, and the at least one feedthrough output pin.

4. The signal line electromigration inspection method according to any one of claims 1 to 3, further comprising: Obtaining a plurality of description files corresponding to the plurality of sub-designs respectively; Based on the description file corresponding to each sub-design, a signal line electromigration check is performed on each sub-design.

5. The signal line electromigration inspection method according to claim 4, wherein: The description file corresponding to the top-level design is configured to be able to call multiple description files corresponding to the multiple sub-designs respectively.

6. The signal line electromigration inspection method according to any one of claims 1 to 3, wherein: The description file corresponding to the top-level design is a design exchange format file.

7. A signal line electromigration inspection device, used in integrated circuit design, wherein: The integrated circuit design includes a top-level design and multiple sub-designs, The signal line electromigration inspection device comprises: an acquiring unit, configured to acquire a description file corresponding to the top-level design; a generating unit configured to generate a plurality of boundary model files corresponding one-to-one to the plurality of sub-designs, wherein each boundary model file includes description information of a plurality of interactive elements in the sub-design corresponding to the boundary model file, the plurality of interactive elements being used to enable the sub-design to interact with the top-level design and / or sub-designs in the plurality of sub-designs other than the sub-design corresponding to the boundary model file; an inspection unit configured to perform a signal line electromigration inspection on the top-level design based on the plurality of boundary model files and a description file corresponding to the top-level design; Wherein, when executing the generation of the plurality of boundary model files corresponding one-to-one to the plurality of sub-designs, the generation unit is configured to: Acquire a plurality of description files corresponding one-to-one to the plurality of sub-designs; generating the plurality of boundary model files based on a plurality of description files corresponding one-to-one to the plurality of sub-designs; Wherein, when the generating unit generates the plurality of boundary model files based on the plurality of description files corresponding one-to-one to the plurality of sub-designs, the generating unit is configured to: For each sub-design: Deleting description information corresponding to the elements in each sub-design other than the multiple interactive elements in each sub-design from the description file corresponding to each sub-design to obtain a boundary model file corresponding to each sub-design, wherein the elements in each sub-design other than the multiple interactive elements in each sub-design include at least one of at least one non-logical unit, at least one internal signal connection network, at least one internal driving unit, and at least one internal receiving unit.

8. An electronic device comprising: a memory that non-transitorily stores computer-executable instructions; a processor configured to execute the computer-executable instructions, Wherein, when the computer executable instructions are executed by the processor, the signal line electromigration inspection method according to any one of claims 1 to 6 is implemented.

9. A non-transitory computer-readable storage medium, wherein: The non-transitory computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are executed by a processor, the signal line electromigration inspection method according to any one of claims 1 to 6 is implemented.

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