Interface circuit, source driver, and display device

Abstract

The present application relates to an interface circuit, a source driver, and a display device. Even when multiple drivers are connected in cascade, it is possible to sense whether a data supply line is disconnected. The device comprises: a timing signal generating circuit that generates a timing signal indicating the switching timing between the data input period and the non-input period; multiple driver abnormality detection circuits that detect abnormalities generated in the source driver; a selection circuit that selects one of the driver abnormality detection circuits during the non-input period and outputs a driver abnormality detection signal indicating the abnormality detection result; an input abnormality detection circuit that detects an input abnormality of a data signal and outputs an input abnormality detection signal indicating the result; a logic sum circuit that outputs a logical sum of the driver abnormality detection signal and the input abnormality detection signal; and a signal output section comprising a MOS transistor having a gate terminal connected to an output section of the logic sum circuit and a source terminal connected to a specified potential and a signal output line connected to the drain terminal thereof.

Description

Technical Field

[0001] The present invention relates to an interface circuit, a source driver and a display device. Background Art

[0002] In liquid crystal display devices, image signals are transmitted from a display control device such as a timing controller to the source driver that drives the liquid crystal panel. For example, mini-LVDS (mini-Low Voltage Differential Signaling) is used as a transmission method for image signals. Mini-LVDS is a differential signaling method that transmits image signals as differential signals. It can transmit an 8-bit image signal using a pair of signal lines (two lines forming a set).

[0003] However, in order to detect abnormalities occurring in the source driver, etc., an abnormality detection circuit is provided in the liquid crystal display device. For example, in order to detect various abnormalities such as temperature abnormalities, voltage value abnormalities, polarity reversal abnormalities, etc., multiple abnormality detection circuits are sometimes provided in the source driver. In order to output the detection results of these multiple abnormality detection circuits, each of the abnormality detection circuits is selected at different timings and the detection results of the selected circuits are output using time division. At this time, the interface circuit in the source driver receives a selection signal from a display control device such as a timing controller, and selects the abnormality detection circuit accordingly. As such an interface circuit, for example, an interface circuit that can transmit the detection results of the abnormal state of each abnormality detection circuit from the source driver to the TCON (Timing Controller) using mini-LVDS communication has been proposed (for example, Patent Document 1).

[0004] Such an interface circuit includes, for example, an input data control circuit that receives a clock signal and multiple input data signals supplied from TCON, and a control mode signal input sensing circuit that generates a control signal input mode signal that measures the timing of the start of data input in response to an LS signal that serves as an interval between display data. Furthermore, the interface circuit includes a signal line for transmitting a start pulse signal that is input and output between source drivers when multiple source drivers are cascaded. Furthermore, in addition to these circuits, multiple abnormality detection circuits and an abnormality detection selection circuit are provided that uses the NAND output of the differential input signal of the mini-LVDS interface as a selection signal and selectively outputs the detection results of multiple abnormality detection circuits. The output of the abnormality detection selection circuit has an open drain terminal structure as the FD_OUT signal, which is pulled up by a power supply on the outside of the chip. For example, in the control signal input mode, an H-level control mode signal is supplied, and the detection results of multiple abnormality detection circuits are sequentially output as the FD_OUT signal.

[0005] Prior art literature

[0006] Patent Literature

[0007] Patent Document 1: Japanese Patent Application Laid-Open No. 2018-54830. Summary of the Invention

[0008] Problems to be solved by the invention

[0009] In the interface circuit described above, for example, control is performed to output the L-level FD_OUT signal when all input data signals from TCON are at H level, thereby detecting whether a disconnection (ie, open circuit fault) of the data supply line to TCON has occurred.

[0010] However, the interface circuit having the above-described structure has a problem in that, when all the data supply lines of a plurality of data input signals are fixed at "H" due to a disconnection, an open-circuit fault cannot be detected.

[0011] Another issue is the inability to detect open-circuit faults in cases where multiple source drivers are cascaded. For example, if the first and second drivers of the first to third cascaded drivers are operating normally and only the third driver is disconnected (open), and all input data signals are set to an H level for disconnection detection, the first and second drivers will output L-level signals. Therefore, the TCON will detect the L-level signals and determine that no disconnection has occurred. Consequently, even if a disconnection occurs in one of the multiple source drivers, the TCON will not be able to detect it.

[0012] In order to solve the above-mentioned problems, an object of the present invention is to provide an interface circuit capable of detecting a disconnection of a data supply line even when a plurality of source drivers are connected in cascade.

[0013] Solutions to Problems

[0014] The present invention provides an interface circuit, which is provided in a source driver driving a display device, receives input of multiple data signals, and supplies the multiple data signals to a data latch unit provided in the one source driver, and is characterized in that it has: a timing signal generating circuit, which receives input of a clock signal, and generates a timing signal showing the timing of switching between a data input period for supplying the multiple data signals to the data latch unit and a non-input period for stopping the supply of the multiple data signals based on at least one of the multiple data signals and the clock signal; a data control circuit, which controls the supply of the multiple data signals to the data latch unit based on the timing signal; multiple driver abnormality detection circuits, which detect abnormalities generated in the one source driver; and a selection circuit. During the non-input period, one of the multiple driver abnormality detection circuits is selected based on the multiple data signals, and a driver abnormality detection signal showing the detection result of the selected driver abnormality detection circuit is output at a timing corresponding to the timing signal and the clock signal; an input abnormality detection circuit detects the abnormality of the data input of the multiple data signals and outputs an input abnormality detection signal showing the detection result; a logic and circuit outputs a logic and signal showing the logical sum of the driver abnormality detection signal and the input abnormality detection signal; and a signal output unit, comprising a first conductive type MOS transistor whose gate terminal is connected to the output unit of the logic and circuit and whose source terminal is connected to a specified potential, and a signal output line connected to the drain terminal of the MOS transistor.

[0015] The present invention provides a source driver that drives a display device based on multiple data signals, characterized in that it includes: an interface circuit that receives a clock signal and the multiple data signals and outputs the multiple data signals according to the clock timing of the clock signal; a latch circuit that takes in the multiple data signals output from the interface circuit and outputs them according to each of the data signals corresponding to the pixel columns in the scanning line direction of the display device; a grayscale voltage generating unit that generates multiple grayscale voltages based on the data signal output from the latch circuit; and an output unit that selects a grayscale voltage corresponding to the luminance level indicated by the data signal from the multiple grayscale voltages and outputs the signal having the one grayscale voltage as a driving signal for the display device, wherein the interface circuit has: a timing signal generating circuit that receives the input of the clock signal and generates a data input period indicating the supply of the multiple data signals to the data latch unit and the stop of the supply of the multiple data signals based on at least one of the multiple data signals and the clock signal. a timing signal for switching the timing of the non-input period; a data control circuit, which controls the supply of the multiple data signals to the data latch unit based on the timing signal; multiple driver abnormality detection circuits, which detect abnormalities generated in the one source driver; a selection circuit, which selects one of the multiple driver abnormality detection circuits based on the multiple data signals during the non-input period, and outputs a driver abnormality detection signal showing the detection result of the selected driver abnormality detection circuit at a timing corresponding to the timing signal and the clock signal; an input abnormality detection circuit, which detects the abnormality of the data input of the multiple data signals and outputs an input abnormality detection signal showing the detection result; a logic and circuit, which outputs a logic and signal showing the logical sum of the driver abnormality detection signal and the input abnormality detection signal; and a signal output unit, comprising a first conductive type MOS transistor having a gate terminal connected to the output unit of the logic and circuit and a source terminal connected to a specified potential, and a signal output line connected to the drain terminal of the MOS transistor.

[0016] The present invention provides a display device comprising: a display panel having a plurality of data lines and a plurality of scan lines, a pixel switch and a pixel portion provided at each intersection of the plurality of data lines and the plurality of scan lines; a display control portion outputting a clock signal and a plurality of data signals; and a plurality of source drivers, a plurality of which are arranged along the extending direction of the scan lines and respectively driving the display device based on the plurality of data signals. The display device is characterized in that each of the plurality of source drivers includes: an interface circuit receiving the clock signal and the plurality of data signals and outputting the plurality of data signals according to the clock timing of the clock signal; a latch circuit taking in the plurality of data signals output from the interface circuit and outputting them according to each of the data signals corresponding to the pixel columns in the scan line direction of the display device; a grayscale voltage generating portion generating a plurality of grayscale voltages based on the data signal output from the latch circuit; and an output portion selecting a grayscale voltage corresponding to the luminance level indicated by the data signal from the plurality of grayscale voltages and outputting the signal having the one grayscale voltage as a driving signal for the display device. The interface circuit includes: a timing signal generating circuit receiving an input of the clock signal and outputting the plurality of data signals based on the clock timing of the plurality of data signals. at least one of the data signals and the clock signal, generating a timing signal indicating the timing of switching between a data input period for supplying the multiple data signals to the data latch unit and a non-input period for stopping the supply of the multiple data signals; a data control circuit for controlling the supply of the multiple data signals to the data latch unit based on the timing signal; multiple driver abnormality detection circuits for detecting an abnormality generated in the one source driver; a selection circuit for selecting one of the multiple driver abnormality detection circuits based on the multiple data signals during the non-input period, and outputting a driver abnormality detection signal indicating the detection result of the selected driver abnormality detection circuit at a timing corresponding to the timing signal and the clock signal; an input abnormality detection circuit for detecting an abnormality in the data input of the multiple data signals and outputting an input abnormality detection signal indicating the detection result; a logic and circuit for outputting a logic and signal indicating the logical sum of the driver abnormality detection signal and the input abnormality detection signal; and a signal output unit comprising a first conductive type MOS transistor having a gate terminal connected to an output unit of the logic and circuit and a source terminal connected to a specified potential, and a signal output line connected to a drain terminal of the MOS transistor.

[0017] Effects of the Invention

[0018] According to the interface circuit of the present invention, even when a plurality of source drivers are connected in cascade, it is possible to sense whether a data supply line is disconnected. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1: is a block diagram showing the structure of the display device 100 of the present invention.

[0020] Figure 2 1 is a block diagram showing the internal structure of the source driver 13 .

[0021] Figure 3 : is a block diagram showing the structure of the interface circuit 14 of this embodiment.

[0022] Figure 4 This is a block diagram showing the connection relationship between a plurality of source drivers and a display control unit.

[0023] Figure 5 is a block diagram showing the structure of the input abnormality sensing circuit 17 .

[0024] Figure 6 It is a timing chart showing signal changes of each signal when there is no data input abnormality.

[0025] Figure 7 It is a timing chart showing signal changes of each signal when there is a data input abnormality.

[0026] Figure 8 It is a timing chart showing signal changes of each signal when there is a data input abnormality.

[0027] Figure 9 is a block diagram showing the configuration of an interface circuit of a comparative example.

[0028] Figure 10 3 is a timing chart showing signal changes of each signal in a comparative example. DETAILED DESCRIPTION

[0029] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the following description of the embodiments and the accompanying drawings, substantially the same or equivalent parts are denoted by the same reference numerals.

[0030] Figure 1 This is a block diagram showing the structure of a display device 100 including the interface circuit of the present invention. Display device 100 is an active matrix liquid crystal display device. Display device 100 includes a display control unit 11, gate drivers 12A and 12B, source drivers 13-1 to 13-p, and a display device 20.

[0031] The display control unit 11 is a display control device comprised of, for example, a timing controller (TCON). It supplies a video data signal VD, a clock signal CLK, and a line start signal LS to the source drivers 13 - 1 to 13 - p , thereby controlling the display timing of images on the liquid crystal display panel. The display control unit 11 transmits the video data signal VD using a differential signaling method such as mini-LVDS (mini-Low Voltage Differential Signaling).

[0032] Based on the input video signal VS, the display control unit 11 generates a sequence of pixel data pieces PD representing the brightness level of each pixel using, for example, a 6-bit luminance grayscale. The display control unit 11 supplies the video data signal VD containing this sequence of pixel data pieces PD to the source driver 13. In the following description, an example is described in which the video data signal VD is composed of input data signals LV0, LV1, and LV2. Furthermore, the input data signals LV0, LV1, and LV2 are differential signals whose signal levels change between logic level 1 and logic level 0 depending on the clock cycle of the clock signal CLK. These signals are transmitted using the mini-LVDS format. In the following description, logic level 1 is referred to as H (high level), and logic level 0 is referred to as L (low level).

[0033] The display control unit 11 also supplies the clock signal CLK and a line start signal LS indicating the position (e.g., the beginning position) of the interval between the sequence of n pixel data pieces PD corresponding to each horizontal scan line to the source drivers 13-1 to 13-p. Furthermore, the display control unit 11 detects a horizontal synchronization signal HS based on the input video signal VS and supplies it to the gate drivers 12A and 12B.

[0034] Furthermore, the display control unit 11 changes the signal levels of the input data signals LV0, LV1, and LV2 into a predetermined pattern in order to check whether a fault such as a disconnection has occurred in the data supply line between the display control unit 11 and the source driver 13. In this embodiment, for example, the display control unit 11 changes the signal levels of the input data signals LV0, LV1, and LV2 from "H" to "H" to "L" at a predetermined timing different from the data input period.

[0035] The display device 20 is an image display device composed of, for example, a liquid crystal display panel or an organic EL (electroluminescence) panel. The display device 20 includes n horizontal scan lines GL1 to GLn (n is a natural number greater than or equal to 2) extending horizontally along a two-dimensional screen, and m source lines SL1 to SLm (m is a natural number greater than or equal to 2) extending vertically along the two-dimensional screen. Pixel portions P are provided at the intersections of the horizontal scan lines and the source lines.11 ~P nm and pixel switch M 11 ~M nm , forming a display unit that acts as a pixel.

[0036] The gate drivers 12A and 12B supply gate signals Vg1 to Vgn to the gate lines GL1 to GLn based on the synchronization timing of the horizontal synchronization signal HS supplied from the display control unit 11. The supply of the gate signals Vg1 to Vgn selects the pixel portion P for each pixel row. 11 ~P nm Then, the grayscale voltage signals Vd1 to Vdm are supplied from the source drivers 13 - 1 to 13 - p to the selected pixel portions, thereby writing the grayscale voltage signals Vd1 to Vdm to the pixel electrodes.

[0037] Source drivers 13-1 to 13-p are provided for every predetermined number of source lines that are divided into source lines SL1 to SLm. The number of source lines driven by each source driver corresponds to the number of output channels of that source driver. For example, if each source driver has 960 output channels and the display panel has one source line per pixel column, a 4K panel would have 12 source drivers driving the source lines, and an 8K panel would have 24 source drivers driving the source lines. Each source driver 13-1 to 13-p is implemented on a semiconductor integrated circuit (IC) chip.

[0038] Source drivers 13-1 through 13-p generate grayscale voltage signals Vd1 through Vdm based on the video data signal VD, the line start signal LS, and the clock signal CLK, and apply them to source lines SL1 through SLm. Furthermore, each source driver 13-1 through 13-p has the function of detecting internal abnormalities, generating an abnormality detection signal ERR indicating the detection result, and supplying it to the display control unit 11.

[0039] Figure 2 This is a block diagram showing the internal structure of source driver 13-1, one of the source drivers 13-1 to 13-p. Source driver 13-1 includes a latch unit 131, a grayscale voltage converter 132, an output unit 133, and an interface circuit 14. The other source drivers 13-2 to 13-p also have the same structure.

[0040] The latch unit 131 sequentially receives a sequence of pixel data pieces PD included in the video data signal VD supplied from the display control unit 11 via the interface circuit 14. Each time the latch unit 131 receives a number of pixel data pieces PD corresponding to the number of output channels of the source driver 13-1 (i.e., the number of pixel data pieces corresponding to one horizontal scan line divided by the number of source drivers) in response to the latch start signal LS, it supplies k pixel data pieces PD as pixel data Q1 to Qk to the grayscale voltage conversion unit 132.

[0041] The grayscale voltage conversion section 132 converts each of the pixel data Q1 to Qk into grayscale voltages A1 to Ak having positive and negative polarities corresponding to the luminance grayscale indicated by the pixel data Q.

[0042] The output unit 133 generates voltages obtained by amplifying the grayscale voltages A1 to Ak individually with a gain of 1, and supplies the voltages as pixel drive voltages G1 to Gk to the source lines D1 to Dk of the display device 20 .

[0043] The interface circuit 14 receives the video data signal VD, the clock signal CLK, and the line start signal LS from the display control unit 11, and supplies the video data signal VD to the latch unit 131 at the timing indicated by these signals. Furthermore, the interface circuit 14 detects an abnormality in the source driver 13 and outputs an abnormality detection signal ERR indicating the detection result to the display control unit 11.

[0044] Figure 3 1 is a block diagram showing the configuration of the interface circuit 14. The interface circuit 14 is composed of a data control block 15 and an abnormality detection block 16.

[0045] The data control block 15 includes a control signal input pattern sensing circuit 151 and an input data control circuit 152. The data control block 15 also includes input terminals T1, T2, T3, and T4, which receive clock signal CLK and input data signals LV0-LV2. Input terminals T1, T2, T3, and T4 are connected to the display control unit 11 via data signal lines (not shown).

[0046] The clock signal CLK input to the input terminal T1 is supplied to the control signal input pattern sensing circuit 151 and the input data control circuit 152. The input data signal LV0 input to the input terminal T2 is supplied to the control signal input pattern sensing circuit 151, the input data control circuit 152, and the abnormality detection selection circuit 164 of the abnormality detection block 16. The input data signals LV1 and LV2 input to the input terminals T3 and T4 are supplied to the input data control circuit 152 and the abnormality detection selection circuit 164.

[0047] The control signal input mode sensing circuit 151 receives a line start signal LS from the display control unit 11, as well as a clock signal CLK and an input data signal LV0 via input terminals T1 and T2. Based on the line start signal LS, the clock signal CLK, and the input data signal LV0, the control signal input mode sensing circuit 151 senses periods in the data input mode (data input period) in which input data LV0, LV1, and LV2 are supplied to the latch unit 131, and periods in the control signal input mode (data non-input period) in which input data LV0, LV1, and LV2 are not supplied to the latch unit 131 and control signals (control signals) other than input data signals are input. For example, the control signal input mode sensing circuit 151 senses a switch from the control signal input mode to the data input mode if the signal level of the input data signal LV0 reaches a logic level 1 for two clock periods and then reaches a logic level 0 for the next clock period (i.e., if the signal level of the input data signal LV0 changes from H to H to L over three clock periods).

[0048] The control signal input mode sensing circuit 151 generates a control mode signal CTM, whose signal level indicates whether the control signal input mode is in effect, and supplies the signal to the input data control circuit 152 and the abnormality detection selection circuit 164. The control mode signal CTM is a timing signal that indicates the timing of switching between the control signal input mode period and the data input mode period by changes in the signal level.

[0049] The input data control circuit 152 supplies the input data signals LV0 , LV1 , and LV2 to the latch unit 131 during the data input mode.

[0050] Furthermore, the input data control circuit 152 is connected to the interface circuits of other adjacent source drivers (i.e., cascade-connected source drivers) via signal lines (not shown). The input data control circuit 152 transmits and receives start pulse signals to and from the interface circuits of the other adjacent source drivers. The start pulse signal indicates the start of data input and is used to identify the timing of mini-LVDS image data input in each source driver when the source drivers are cascade-connected.

[0051] Figure 4 1 is a block diagram schematically showing the connection relationship between a plurality of source drivers connected in cascade and the display control unit 11. Here, the number of source drivers is 3 (ie, Figure 1 The case of p=3 in the block diagram is shown as an example.

[0052] The display control unit 11 supplies a line start signal LS, a clock signal CLK, and input data signals LV0 to LV2 to each of the source drivers 13-1, 13-2, and 13-3. Furthermore, a start pulse signal SP output from the display control unit 11 is supplied to the source driver 13-3 and then to the source driver 13-2 and then to the source driver 13-1.

[0053] Furthermore, each of the source drivers 13 - 1 to 13 - 3 includes an FD_OUT terminal for outputting the abnormality detection signal ERR and supplying the signal to the display control unit 11 .

[0054] Refer again Figure 3 The abnormality detection block 16 includes a first abnormality detection circuit 161 , a second abnormality detection circuit 162 , and a third abnormality detection circuit 163 (hereinafter collectively referred to as the first to third abnormality detection circuits 161 to 163 ) and an abnormality detection selection circuit 164 .

[0055] The first to third abnormality detection circuits 161 to 163 detect abnormal conditions within the source driver 13, such as temperature abnormalities, voltage abnormalities, and polarity reversal abnormalities. Furthermore, the first to third abnormality detection circuits 161 to 163 each detect a different type of abnormality. The first to third abnormality detection circuits 161 to 163 supply detection result signals ER1 to ER3 indicating the results of their respective abnormality detections to the abnormality detection selection circuit 164.

[0056] The abnormality detection selection circuit 164 selects one of the first to third abnormality detection circuits 161 to 163 at different clock timings based on the control mode signal CTM supplied from the data control block 15 and the input data signals LV0, LV1 and LV2, and outputs the detection result signal of the selected abnormality detection circuit as the abnormality detection signal ERR.

[0057] Furthermore, the abnormality detection block 16 includes an input abnormality sensing circuit 17 , an OR gate 18 , and a signal output unit 19 .

[0058] Input abnormality sensing circuit 17 is a circuit that detects input abnormalities in input data signals LV0, LV1, and LV2, thereby detecting whether a fault such as a disconnection has occurred in these data supply lines. Input abnormality sensing circuit 17 detects the presence of a data input abnormality (i.e., whether a disconnection has occurred in a data supply line, etc.) based on whether the signal levels of input data signals LV0, LV1, and LV2 change in a predetermined pattern during the period from when line start signal LS rises until the next line start signal LS rises, and while control mode signal CTM is at an H level.

[0059] In this embodiment, when the input abnormality sensing circuit 17 senses a change in the signal level of each of the input data signals LV0, LV1, and LV2 from "H" to "H" to "L", it determines that there is no abnormality in the data input of the input data signals LV0, LV1, and LV2. On the other hand, if the input abnormality sensing circuit 17 fails to sense a change in the signal level of each of the input data signals LV0, LV1, and LV2 from "H" to "H" to "L", it determines that there is an abnormality in the data input of the input data signals LV0, LV1, and LV2.

[0060] Figure 5 17 is a block diagram showing the configuration of the input abnormality sensing circuit 17. The input abnormality sensing circuit 17 includes an HHL identification circuit 170, FFs 171, 172, 173, and an AND gate 174.

[0061] When HHL identification circuit 170 senses a change in the signal level of each of input data signals LV0, LV1, and LV2 from "H" to "H" to "L" while control mode signal CTM is at the H level, it outputs input abnormality detection signal ES1 at the L level. On the other hand, if such a change is not sensed, HHL identification circuit 170 outputs input abnormality detection signal ES1 at the H level.

[0062] FF171, 172, and 173 are flip-flop circuits. FF171 receives input abnormality detection signal ES1, holds it for the duration of one line's data period, and outputs it as input abnormality detection signal ES2. FF172 receives input abnormality detection signal ES2, holds it for the duration of one line's data period, and outputs it as input abnormality detection signal ES3. FF173 receives input abnormality detection signal ES3, holds it for the duration of one line's data period, and outputs it as input abnormality detection signal ES4.

[0063] AND gate 174 receives input abnormality detection signals ES1, ES2, ES3, and ES4 and outputs the logical product of these signals as data abnormality detection signal DES. This determines whether the signal levels of input data signals LV0, LV1, and LV2 change from "H" to "H" to "L" for four lines of data input. If the input abnormality detection signal remains H for four or more lines, it is determined that an abnormality exists in the data input.

[0064] Refer again Figure 3 The OR gate 18 receives the data abnormality sensing signal DES output from the input abnormality sensing circuit 17 and the abnormality detection signal ERR output from the abnormality detection selection circuit 164, and outputs a logical sum of them as a logical sum signal ORS.

[0065] The signal output unit 19 includes a transistor TR1 formed of an N-channel MOS transistor of the first conductivity type and a signal output line L3 connected to a drain terminal of the transistor TR1 .

[0066] The source terminal of transistor TR1 is grounded and connected to a predetermined potential (i.e., ground potential in this embodiment). The gate terminal of transistor TR1 is connected to the output of OR gate 18. The drain terminal of transistor TR1 is connected to signal output line L3, which outputs the FD_OUT signal. In other words, the drain terminal of transistor TR1 constitutes an open-drain terminal (also referred to as the FD_OUT terminal in the following description) that outputs the FD_OUT signal.

[0067] When an H-level signal is applied to the gate terminal of transistor TR1, transistor TR1 is controlled to be in the on state and outputs an L-level FD_OUT signal from the open drain terminal. On the other hand, when an L-level signal is applied to the gate terminal of transistor TR1, transistor TR1 is controlled to be in the off state and outputs an H-level FD_OUT signal from the open drain terminal.

[0068] Next, the operations of the data control block 15 and the abnormality detection block 16 will be described. First, the operations will be described when there is no abnormality in data input (ie, when there is no failure such as a disconnection in the data supply line).

[0069] Figure 6 1 is a timing chart showing changes in the signal levels of respective signals when there is no abnormality in data input.

[0070] When line start signal LS goes H, control signal input mode sensing circuit 151 senses the control mode state and generates control mode signal CTM at H. Abnormality detection selection circuit 164 sequentially selects first to third abnormality detection circuits 161 to 163 based on the combination of the signal levels of input data signals LV0, LV1, and LV2.

[0071] After all monitoring of the first to third abnormality detection circuits 161 to 163 is completed, the display control unit 11 changes the signal levels of the input data signals LV0 , LV1 , and LV2 from “H” to “H” to “L”.

[0072] If there are no abnormalities in the input data, HHL identification circuit 170 of input abnormality sensing circuit 17 identifies the transition from "H" to "H" to "L" in input data signals LV0, LV1, and LV2, and outputs an L-level input abnormality sensing signal ES1, indicating that there are no abnormalities in the input data. FF171, FF172, and FF173 output L-level input abnormality sensing signals ES2, ES3, and ES4, respectively. Based on this, input abnormality sensing circuit 17 outputs an L-level data abnormality sensing signal DES.

[0073] An L-level data abnormality detection signal DES is supplied to the gate of transistor TR1 of signal output unit 19, maintaining transistor TR1 in the OFF state. Consequently, an H-level FD_OUT signal is output from signal output unit 19. Display control unit 11, receiving the H-level FD_OUT signal, determines that there is no abnormality in the data supply lines that input data signals LV0 to LV2.

[0074] Next, refer to Figure 7 and Figure 8 The timing diagram of FIG. 1 illustrates the operation in a state where an abnormality occurs in data input (ie, a state where a failure such as a disconnection occurs in the data supply line).

[0075] In the control signal input mode, when all the monitoring of the first to third abnormality detection circuits 161 to 163 is completed, the display control unit 11 changes the signal levels of the input data signals LV0 , LV1 , and LV2 from “H” to “H” to “L”.

[0076] At this time, if a fault such as a disconnection occurs in the data supply line of input data signal LV2, input data signal LV2 is fixed at the L level. Consequently, HHL identification circuit 170 of input abnormality sensing circuit 17 cannot recognize the change from "H" to "H" to "L" in input data signal LV2. Therefore, HHL identification circuit 170 outputs input abnormality sensing signal ES1 at the H level.

[0077] like Figure 7 As shown, the input abnormality detection signal ES1 changes to H level, while the input abnormality detection signals ES2, ES3 and ES4 maintain L level during the same data input mode. The input abnormality detection signal ES2 becomes H level when the control mode signal CTM rises next.

[0078] The signal level determination of input data signals LV0, LV1, and LV2 by HHL identification circuit 170 is also performed on the data of the subsequent lines. Since HHL identification circuit 170 of input abnormality sensing circuit 17 cannot recognize the change from "H" to "H" to "L" of input data signal LV2, the signal level of input abnormality sensing signal ES1 remains at H level. The signal level of input abnormality sensing signal ES2 becomes H level.

[0079] Next, the HHL identification circuit 170 also performs the signal level determination of the input data signals LV0, LV1, and LV2 on the data of the third and fourth lines, and outputs the H level input abnormality detection signal ES1. Figure 8 As shown, the input abnormality sensing signals ES3 and ES4 sequentially become H level in response to the rise of the control mode signal CTM.

[0080] Since an abnormality in the data input is sensed for data corresponding to four lines, the input abnormality sensing circuit 17 outputs the data abnormality sensing signal DES at an H level.

[0081] An H-level data abnormality detection signal DES is supplied to the gate of transistor TR1 of signal output unit 19, turning on transistor TR1. Consequently, an L-level FD_OUT signal is output from the drain terminal of transistor TR1. Display control unit 11, upon receiving the L-level FD_OUT signal, determines that an abnormality exists in any of the data supply lines receiving data signals LV0 to LV2.

[0082] As described above, in the interface circuit 14 of this embodiment, when an abnormality in the data input of the input data signals LV0 to LV2 is detected, the signal level of the FD_OUT signal, which is the output signal of the signal output unit 19, is changed to an L level. The display control unit 11 detects the presence of an abnormality in the data supply line by sensing the L level of the forcibly dropped FD_OUT signal.

[0083] Therefore, according to the interface circuit 14 of this embodiment, when a plurality of source drivers are cascade-connected, if a failure such as a disconnection occurs in any of the data supply lines between the display control unit 11 and each source driver, the failure can be sensed.

[0084] Figure 9 This is a block diagram showing the structure of an interface circuit 24 of a comparative example that differs from the interface circuit 14 of the present embodiment and does not have a structure corresponding to the input abnormality sensing circuit 17. The interface circuit 24 of the comparative example includes an AND gate 25 that outputs the logical product of the input data signals LV0, LV1, and LV2.

[0085] Figure 10 This is a timing diagram illustrating changes in the signal levels of various signals in the interface circuit 24 of the comparative example. In the comparative example configuration, the display control unit 11 sets the signal levels of all input data signals LV0, LV1, and LV2 to an H level in order to detect, for example, a disconnection in the data supply lines of the input data signals LV0, LV1, and LV2. If there are no data input anomalies in the input data signals LV0, LV1, and LV2, the display control unit 11 outputs an L-level FD_OUT signal. If the signal level of the FD_OUT signal is L-level, the display control unit 11 determines that there are no data input anomalies. If it is not L-level, the display control unit 11 determines that there are data input anomalies.

[0086] However, in the structure of the comparative example, when a plurality of source drivers are connected in cascade, even if one of the source drivers (for example, Figure 4 A fault such as a disconnection occurs in the data supply line of the source driver 13-3 in the source driver 13-3, and other source drivers (eg Figure 4 The source drivers 13 - 1 and 13 - 2 in FIG1 also output the FD_OUT signal of the L level. Therefore, the display control unit 11 determines that no disconnection or the like has occurred in the data supply line of any source driver.

[0087] In contrast, the interface circuit 14 of this embodiment includes an input abnormality detection circuit 17 in each of the multiple source drivers. Upon detecting an abnormality in the data input, the circuit forcibly sets the signal level of the FD_OUT signal to an L level. Therefore, the display control unit 11 can determine whether a data supply line breakage, etc., has occurred in any of the source drivers 13-1 to 13-3 by determining the signal level of the FD_OUT signal.

[0088] Furthermore, the present invention is not limited to the above-described embodiments. For example, while the above-described embodiments illustrate a case where there are three source drivers, the number of source drivers is not limited to this. Furthermore, the number of abnormality detection circuits is not limited to the number shown in the above-described embodiments.

[0089] Furthermore, the combination of signal levels (H and L) of each signal can be varied as appropriate. For example, while the above embodiment illustrates the case where the signal levels of input data signals LV0, LV1, and LV2 are changed from "H" to "H" to "L," a configuration may also be employed where the signal levels are changed in a different pattern and a data input abnormality is detected based on whether or not a change in the signal levels is detected.

[0090] Description of Reference Signs

[0091] 11 Display control unit

[0092] 12 Gate Driver

[0093] 13 Source Driver

[0094] 14 Interface Circuit

[0095] 15 Data Control Block

[0096] 16 Anomaly Detection Block

[0097] 17 Input abnormality detection circuit

[0098] 18 OR gate

[0099] 19 Signal output unit

[0100] 20 Display devices

[0101] 100 Display device

[0102] 131 Latch Unit

[0103] 132 Grayscale voltage conversion unit

[0104] 133 Output

[0105] 151 Control signal input mode sensing circuit

[0106] 152 Input data control circuit

[0107] 161~163 Abnormal detection circuit

[0108] 164 Abnormal detection selection circuit.

Claims

1. An interface circuit provided in a source driver for driving a display device, receiving input of a plurality of data signals and supplying the plurality of data signals to a data latch provided in the source driver, characterized in that: have: a timing signal generating circuit that receives an input of a clock signal and generates, based on at least one of the plurality of data signals and the clock signal, a timing signal indicating timing for switching between a data input period for supplying the plurality of data signals to the data latch unit and a non-input period for stopping the supply of the plurality of data signals; a data control circuit for controlling supply of the plurality of data signals to the data latch portion based on the timing signal; a plurality of driver abnormality detection circuits for detecting abnormalities occurring in the one source driver; a selection circuit that selects one of the plurality of driver abnormality detection circuits based on the plurality of data signals during the non-input period and outputs a driver abnormality detection signal indicating a detection result of the selected driver abnormality detection circuit at a timing corresponding to the timing signal and the clock signal; an input abnormality detection circuit that detects abnormality in data input of the plurality of data signals and outputs an input abnormality detection signal indicating a detection result; a logic sum circuit that outputs a logic sum signal indicating a logic sum of the driver abnormality detection signal and the input abnormality detection signal; as well as The signal output unit includes a first conductivity type MOS transistor having a gate terminal connected to the output unit of the logic sum circuit and a source terminal connected to a predetermined potential, and a signal output line connected to a drain terminal of the MOS transistor.

2. The interface circuit according to claim 1, wherein: The plurality of data signals include first to nth data signals whose signal levels change between logic level 0 and logic level 1 at a timing corresponding to a clock cycle of the clock signal, where n is an integer greater than or equal to 2. The input abnormality detection circuit senses whether or not there is an abnormality in data input based on whether or not the signal levels of each of the first to nth data signals change in a predetermined pattern.

3. The interface circuit according to claim 2, wherein: The input abnormality detection circuit determines that an abnormality exists in the data input when it determines that the signal levels of each of the first to nth data signals do not change in the predetermined pattern over a data period corresponding to a predetermined number of lines.

4. A source driver for driving a display device based on a plurality of data signals, characterized in that: Include: an interface circuit, receiving a clock signal and the plurality of data signals, and outputting the plurality of data signals according to clock timing of the clock signal; a latch circuit that receives the plurality of data signals output from the interface circuit and outputs each data signal corresponding to a pixel column in a scanning line direction of the display device; a grayscale voltage generating unit that generates a plurality of grayscale voltages based on the data signal output from the latch circuit; as well as an output unit that selects one grayscale voltage corresponding to the luminance level indicated by the data signal from the plurality of grayscale voltages and outputs a signal having the one grayscale voltage as a driving signal for the display device; The interface circuit has: a timing signal generating circuit that receives input of the clock signal and generates, based on at least one of the plurality of data signals and the clock signal, a timing signal indicating timing for switching between a data input period for supplying the plurality of data signals to a data latch unit and a non-input period for stopping supply of the plurality of data signals; a data control circuit for controlling supply of the plurality of data signals to the data latch portion based on the timing signal; a plurality of driver abnormality detection circuits for detecting abnormalities occurring in a source driver; a selection circuit that selects one of the plurality of driver abnormality detection circuits based on the plurality of data signals during the non-input period and outputs a driver abnormality detection signal indicating a detection result of the selected driver abnormality detection circuit at a timing corresponding to the timing signal and the clock signal; an input abnormality detection circuit that detects abnormality in data input of the plurality of data signals and outputs an input abnormality detection signal indicating a detection result; a logic sum circuit that outputs a logic sum signal indicating a logic sum of the driver abnormality detection signal and the input abnormality detection signal; as well as The signal output unit includes a first conductivity type MOS transistor having a gate terminal connected to the output unit of the logic sum circuit and a source terminal connected to a predetermined potential, and a signal output line connected to a drain terminal of the MOS transistor.

5. A display device comprising: A display panel having a plurality of data lines and a plurality of scan lines, and a pixel switch and a pixel portion provided at each intersection of the plurality of data lines and the plurality of scan lines; A display control unit outputs a clock signal and a plurality of data signals; as well as A plurality of source drivers are arranged along the extending direction of the scan lines, and drive the display device based on the plurality of data signals respectively. The display device is characterized in that Each of the plurality of source drivers comprises: an interface circuit, receiving the clock signal and the plurality of data signals, and outputting the plurality of data signals according to clock timing of the clock signal; a latch circuit that receives the plurality of data signals output from the interface circuit and outputs each data signal corresponding to a pixel column in a scanning line direction of the display device; a grayscale voltage generating unit that generates a plurality of grayscale voltages based on the data signal output from the latch circuit; as well as an output unit that selects one grayscale voltage corresponding to the luminance level indicated by the data signal from the plurality of grayscale voltages and outputs a signal having the one grayscale voltage as a driving signal for the display device; The interface circuit has: a timing signal generating circuit that receives input of the clock signal and generates, based on at least one of the plurality of data signals and the clock signal, a timing signal indicating timing for switching between a data input period for supplying the plurality of data signals to a data latch unit and a non-input period for stopping supply of the plurality of data signals; a data control circuit for controlling supply of the plurality of data signals to the data latch portion based on the timing signal; a plurality of driver abnormality detection circuits for detecting abnormalities occurring in a source driver; a selection circuit that selects one of the plurality of driver abnormality detection circuits based on the plurality of data signals during the non-input period and outputs a driver abnormality detection signal indicating a detection result of the selected driver abnormality detection circuit at a timing corresponding to the timing signal and the clock signal; an input abnormality detection circuit that detects abnormality in data input of the plurality of data signals and outputs an input abnormality detection signal indicating a detection result; a logic sum circuit that outputs a logic sum signal indicating a logic sum of the driver abnormality detection signal and the input abnormality detection signal; as well as The signal output unit includes a first conductivity type MOS transistor having a gate terminal connected to the output unit of the logic sum circuit and a source terminal connected to a predetermined potential, and a signal output line connected to a drain terminal of the MOS transistor.

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