Multi-cycle path circuit, on-chip controller, and control system

Abstract

A multi-cycle path circuit includes a logic circuit, a memory, and an on-chip clock controller. The multi-cycle path circuit is configured to operate in a functional mode in which the logic circuit controls reading and / or writing of the memory, and in a full-speed test mode in which the logic circuit controls reading and / or writing of the memory. The invention uses a clock pulse shaping circuit to control a functional mode clock gating element and a clock divider to establish a multi-cycle phase relationship between a clock into the logic and a secondary cache DRAM memory timing path. It also ensures that the clock path into and out of the secondary cache DRAM is the same in the functional mode and the full-speed test mode to avoid hold and set timing conflicts between these modes.

Description

Technical Field

[0001] This invention relates to the field of circuit technology, and in particular to a multi-cycle path circuit, an on-chip controller, and a control system. Background Technology

[0002] The industry can verify the function of semiconductor chips by testing them. Testing semiconductor chips requires applying various combinations of signal patterns using testing equipment. Given the complexity of modern integrated circuits, the number of patterns or templates that need to be tested can be in the thousands, hundreds of thousands, or even more. Automatic test pattern generation (ATPG) refers to generating various permutations of test patterns to thoroughly test the chip.

[0003] Currently, traditional ATPG tools available in the EDA (Electronic Design Automation) industry cannot generate patterns to test these critical MCP (Multi-cycle Path) timing paths, resulting in lost test coverage on these interfaces. Therefore, in previous solutions, these multi-cycle timing paths would exhibit DPPM (defective parts per million) issues on the silicon wafer (or chip). Summary of the Invention

[0004] In view of this, the present invention provides a multi-cycle path circuit, on-chip controller and control system to solve the above problems. The multi-cycle path circuit, on-chip controller and control system of the present invention are designed to create multi-cycle phase relationships in test mode to achieve high-speed testing of these multi-cycle paths.

[0005] According to a first aspect of the present invention, a multi-cycle path circuit is disclosed, comprising:

[0006] The logic circuit is configured to operate with a first clock signal of a first time period.

[0007] A memory, coupled to the logic circuit and configured to operate with a second clock signal of a second time period, the second time period being a multiple of the first time period; and

[0008] An on-chip clock controller, coupled to the logic circuit and the memory, is configured to provide the first clock signal to the logic circuit and the second clock signal to the memory.

[0009] The multi-cycle path circuit is configured to operate in a functional mode, in which the logic circuit controls the reading and / or writing of the memory, and

[0010] The multi-cycle path circuit is configured to operate in full-speed test mode, in which the logic circuit controls the reading and / or writing of the memory to test the transformation of the value output from the memory within multiple clock cycles of the first clock signal.

[0011] According to a second aspect of the invention, an on-chip controller is disclosed, configured to provide clock signals to a first circuit and a second circuit coupled to each other, and to operate using the first clock signal and the second clock signal respectively in a multi-cycle phase relationship, the on-chip controller comprising:

[0012] A first pulse shaper receives the clock signal from the chip and outputs a first test clock enable signal; and

[0013] The second pulse shaper receives the clock signal on the chip and outputs a second test clock enable signal, so that the controller on the chip provides the first clock signal and the second clock signal to the first circuit and the second circuit respectively, based at least in part on the first test clock enable signal and the second test clock enable signal.

[0014] According to a third aspect of the present invention, an on-chip control system is disclosed, comprising:

[0015] The first circuit and the second circuit are coupled to each other and operate with the first clock signal and the second clock signal respectively in a multi-cycle phase relationship.

[0016] A first on-chip clock controller is configured to modulate an on-chip clock signal to provide the first clock signal and the second clock signal to the first circuit and the second circuit, respectively; and

[0017] The second on-chip clock controller is configured to provide the on-chip clock signal to the first on-chip clock controller based on the scan clock signal.

[0018] The multi-cycle path circuit of the present invention comprises: a logic circuit configured to operate with a first clock signal of a first time period; a memory coupled to the logic circuit and configured to operate with a second clock signal of a second time period, the second time period being a multiple of the first time period; and an on-chip clock controller coupled to the logic circuit and the memory and configured to provide the first clock signal to the logic circuit and the second clock signal to the memory. The multi-cycle path circuit is configured to operate in a functional mode in which the logic circuit controls reads and / or writes to the memory, and wherein the multi-cycle path circuit is configured to operate in a full-speed test mode in which the logic circuit controls reads and / or writes to the memory to test the transitions of values ​​output from the memory over multiple clock cycles of the first clock signal. The customized on-chip clock controller of the present invention utilizes a clock pulse shaping circuit to control a functional mode clock gating element and a clock divider to establish a multi-cycle phase relationship between the clock entering the logic and the timing path of random access to memory for L2 cache data. The design of this invention also ensures that the clock paths for random access to the L2 cache data in the functional mode and the full-speed test mode are the same, in order to avoid timing conflicts between these modes in terms of maintenance and setup. Attached Figure Description

[0019] Figure 1 This is a block diagram of a multi-cycle path circuit according to some embodiments.

[0020] Figure 2 According to some embodiments Figure 1 Block diagram of a pulse shaper for a multi-cycle path circuit.

[0021] Figure 3 According to some embodiments Figure 1 Timing diagram of multi-cycle path circuits in functional modes.

[0022] Figure 4 According to some embodiments Figure 1 Timing diagram of a multi-cycle path circuit in test mode.

[0023] Figure 5 According to some embodiments Figure 1 Timing diagram of a multi-cycle path circuit in test mode.

[0024] Figure 6 According to some embodiments Figure 1 Timing diagram of a multi-cycle path circuit in test mode. Detailed Implementation

[0025] In the following detailed description of embodiments of the invention, reference is made to the accompanying drawings, which form part of the invention, and which illustrate specific preferred embodiments in which the invention can be practiced. These embodiments have been described in sufficient detail to enable those skilled in the art to practice them, and it should be understood that other embodiments may be utilized, and mechanical, structural, and procedural changes may be made, without departing from the spirit and scope of the invention. Therefore, the following detailed description should not be construed as limiting, and the scope of the embodiments of the invention is defined only by the appended claims.

[0026] It will be understood that although the terms “first,” “second,” “third,” “primary,” “secondary,” etc., may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or portion from another. Therefore, without departing from the teachings of the inventive concept, the first or primary element, component, region, layer, or portion discussed below may be referred to as a second or secondary element, component, region, layer, or portion.

[0027] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “under,” “above,” and “above” may be used herein to describe the relationship of an element or feature to it. Another element or feature is shown in the figure. In addition to the orientation described in the figure, the spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptive terms used herein may be interpreted accordingly. Additionally, it will be understood that when a “layer” is referred to as being “between” two layers, it can be the only layer between the two layers, or there may be one or more intermediate layers.

[0028] The terms “about,” “roughly,” and “about” generally mean a range of ±20%, ±10%, ±5%, ±3%, ±2%, ±1%, or ±0.5% of a specified value. The specified values ​​in this invention are approximate. Unless otherwise specified, the specified values ​​include the meanings of “about,” “roughly,” and “about.” The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, the singular terms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise.

[0029] It will be understood that when an “element” or “layer” is referred to as being “on,” “connected to,” “coupled to,” or “adjacent to” another element or layer, it can be directly on, connected to, coupled to, or adjacent to the other element or layer, or there may be intermediate elements or layers. Conversely, when an element is referred to as being “directly on,” “directly connected to,” “directly coupled to,” or “immediately adjacent to” another element or layer, there are no intermediate elements or layers.

[0030] Note: (i) the same features will be represented by the same reference numerals throughout the figures and will not necessarily be described in detail in every figure in which they appear, and (ii) a series of figures may show different aspects of a single item, each of which is associated with various reference labels that may appear throughout the series or only in selected figures of the series.

[0031] ARM (Advanced RISC Machines, RISC microprocessors designed by Acorn Ltd., UK) CPU (central processing unit) designs have multi-cycle timing paths (MCPs) to and from L2 (Level 2 cache) data RAM (random access memory), as L2 SRAM designs require accesses or accesses exceeding one CPU cycle. Currently available conventional ATPG tools in the EDA industry cannot generate patterns to test these critical MCP timing paths, resulting in lost test coverage on these interfaces. Therefore, these multi-cycle timing paths have appeared as DPPM (Distributed Processing Time) issues in previous solutions on the silicon or chip. To overcome these problems, the multi-cycle path circuit, on-chip controller, and control system provided in this invention are designed to create multi-cycle phase relationships in test modes to achieve high-speed testing of these multi-cycle paths. The multi-cycle path circuit described herein is capable of high-speed (or full-speed) testing. The inventors have recognized and understood that test patterns generated by the automatic test pattern generator (ATPG) tool can only support circuitry accessible within one clock cycle. Multi-cycle path circuits may not be able to complete signal propagation along one or more of their paths within one clock cycle, and therefore cannot be tested using the ATPG tool. Consequently, defective multi-cycle path circuits may not be detected. Because defective multi-cycle paths cannot be detected, chips with defective multi-cycle path circuits will appear as parts per million (DPPM), thus reducing yield.

[0032] The inventors have developed methods and circuits to perform full-speed testing of multi-cycle path circuits. In some embodiments, the multi-cycle path circuit is capable of operating in both functional mode and full-speed test mode. The multi-cycle path circuit may include an on-chip controller configured to provide a first clock signal to a first circuit (e.g., logic circuit) and a second clock signal to a second circuit (e.g., memory, or possibly another logic circuit). The first and second clock signals may be in a multi-cycle phase relationship. The period of the second clock signal may be a multiple of the period of the first clock signal (e.g., twice or any other value). The on-chip controller may be configured to ensure that the clock paths of the first and second circuits are identical for both functional mode and full-speed test mode, thereby avoiding hold and setup timing conflicts between these modes due to clock divergence.

[0033] Figure 1 An on-chip clock controller (OCC) (or custom on-chip clock controller) is used to shape the functional logic clock and SRAM clock in test mode to achieve test coverage missing in the prior art, to check setup / hold multi-cycles on SRAM input and output paths, and to solve problems existing in the prior art. In the on-chip clock controller (custom on-chip clock controller) of this invention, the clock enable of the logic integrated clock gate and SRAM divider is controlled using a pulse shaper in test mode. Since there are dedicated pulse shapers for clock enable, any desired clock relationship can be generated using the on-chip clock controller (custom on-chip clock controller) of this invention. Figure 2 The pulse shaper generates the `test_clk_enable` signal according to the test program programmed via a shift register. The shift register is linked to a general-purpose clock control scan chain. The pulse shaper's internal counter obtains a clock from, for example, an on-chip clock controller 102 to generate `test_clk_enable` at high speed. In ATPG mode, the `test_clk_enable` control logic integrates a clock gate and an SRAM divider (or may be an SRAM integrated clock gate) to ensure clock control in scan capture or OCC capture modes (which may correspond to full-speed test mode). In functional mode, `logic_clk_en` and `sram_clk_en` control the ICG (Integrated Clock Gate) and SRAM DIV (divider) logics, respectively. Figure 3As shown, in functional mode, test mode signals such as logic_clk_1hot, sram_occ_en, and div_clk_bypass are forced to be set to 0. The input of the SRAM (A / DI / CS / WE) has a hold-for-multiple-cycles-to-1, where data is expected to be held for 1 additional logic_clk cycle, as indicated by labels (1) and (2) in the figure. (1) is the start clock of the logic controlling the memory input, and (2) is the SRAM capture clock. This is a typical diagram of the SRAM write operation or read control logic. For the SRAM output path, there is a set-multiple-cycles of 2 logic_clk cycles to enable timing for slow SRAM. (3) is the start clock on the SRAM, and (4) is the location where data is typically captured based on valid data. To achieve ATPG fixed coverage on the SRAM input, the test control logic_clk_1hot is set to 0, sram_occ_en to 1, and div_clk_bypass to 1 to stop logic_clk to obtain the following results: Figure 4 The timing diagram is shown. In ATPG OCC mode, the SRAM memory input logic is overlaid at high speed, and a clock program is used to shape the custom OCC controller to provide one clock pulse, such as... Figure 5 The timing diagrams (51) and (52) are shown, with test settings of logic_clk_1hot = 1, sram_occ_en = 1, and div_clk_bypass = 0. The SRAM memory output logic of the capture flip-flop is overridden at high speed by a clock program to provide one clock pulse, as shown in the diagram. Figure 6 As shown in the timing diagrams (63) and (64), the test settings are logic_clk_1hot 1, sram_occ_en 1, and div_clk_bypass 0. The custom OCC controller shaping in this invention is controlled by programming the correct values ​​in the clock program file.

[0034] Figure 1 This is a block diagram of a multi-cycle path circuit 100 according to some embodiments. In the illustrated example, the multi-cycle path circuit 100 includes logic circuitry 106 and static random-access memory (SRAM) 108 (which may be another logic circuit in other embodiments). Logic circuitry 106 may be configured to operate (or run, work) using a clock signal logic_clk. Logic circuitry 106 may be configured to provide an output data signal to input A / DI of SRAM 108. Figure 1 The location marked 136 in the image (136 can be an output signal) and the output signal is received from the output terminal DO of the SRAM108.Figure 1 The location marked 138 (where 138 can be an output signal) controls the writing and reading of SRAM 108. SRAM 108 can be configured to operate (or work) using a clock signal sram_clk, which is a multiple (e.g., twice or other values) of the time period of the clock signal logic_clk, because writing to SRAM... Figure 1 (the location marked in 136) and read operations ( Figure 1 The data is expected to remain for two or more CPU logical clock cycles during the period indicated by position 138 (see [reference]). Figure 3 ). Figure 1 The multi-cycle path circuit 100 can be referred to as an on-chip control system in one embodiment; while Figure 1 The multi-cycle path circuit 100, excluding the logic circuit 106 and SRAM 108, can be referred to as an on-chip controller. Figure 1 The frequency divider 124 and the integrated clock gate 118 may or may not be included in the on-chip controller.

[0035] The multi-cycle path circuit 100 may include an on-chip clock controller (OCC) 102. The OCC 102 can receive a clock signal pll_clk, which may be generated by a phase-locked loop (PLL) circuit (not shown). The OCC 102 can also receive a clock signal scan_clk, which may be provided by an automated test equipment (ATE). The OCC 102 can output a clock signal occ_clk based on the clock signals pll_clk and scan_clk.

[0036] Multi-cycle path circuit 100 may include a custom or custom OCC 104 (or also referred to as OCC) that provides clock signals to logic circuit 106 and SRAM 108 based on an operating (or running) mode. In the operating (or working) functional mode, no tests are performed, and the custom OCC allows clock signals to be delivered to logic circuit 106 and SRAM 108 based on functional logic (not shown). OCC 104 modulates an on-chip clock signal (e.g., occ_clk) to provide clock signals logic_clk and sram_clk to logic circuit 106 and SRAM 108, respectively. OCC 102 may output clock signal occ_clk to OCC 104 based on clock signals pll_clk and scan_clk.

[0037] Customized OCC or OCC 104 may include a first part comprising a pulse shaper 200A, an AND gate 112, and a multiplexer 110A. In functional mode, OR gate 111 receives logic_clk disable and sram_occ_en and generates a signal that selects the 0 input of multiplexer 110A, namely logic_clk_en. The signal logic_clk_en is passed through multiplexer 110A as output signal 116 and enables the integrated clock gate (ICG) 118 based on functional logic. ICG 118 receives the clock input of occ_clk. ICG 118 then provides logic_clk to logic circuitry 106, which in functional mode is occ_clk selected by logic_clk_en. Figure 1 The ICG 118 in the chip is an integrated clock gate that provides a gated version of the on-chip clock signal.

[0038] In test mode, a custom OCC or OCC 104 provides the test signal for strobing ICG 118. Pulse shaper 200A can receive the clock signal occ_clk and generate a test clock enable signal (or clock enable signal) test_clk_enable, at least in part, based on the clock signal occ_clk. AND gate 112 can receive the test clock enable signal test_clk_enable and the test control signal logic_clk_1hot, if the custom OCC 104 is to provide ATPG (stuck-at SRAM coverage) (see...). Figure 4If the signal (test control signal logic_clk_1hot) is not found, then the signal is set to zero. AND gate 112 can provide output signal 114 to multiplexer 110A. Multiplexer 110A can also receive signal logic_clk_en, and control signal sram_occ_en that performs an OR operation with logic_clk_disable; specifically, multiplexer 110A can receive signal logic_clk_en on input marked "0", while output signal 114 of AND gate 112 is output to input of multiplexer 110A marked "1", which can be driven by an OR operation of logic_clk_disable and sram_occ_en. logic_clk_disable is set to 1, and sram_occ_en is set to 0 to obtain ATPG fixed SRAM coverage on the A / DI pin of SRAM circuit 108. Controlled by control signal 140, multiplexer 110A can generate output signal 116 based on signal logic_clk_en or output signal 114.

[0039] Customized OCC 104 may include a second part comprising a pulse shaper 200B, a multiplexer 110B-D, an AND gate 120, and an ICG (Integrated Clock Gated) 122. In functional mode, multiplexer 110B is controlled by sram_occ_en to select input 0, i.e., sram_clk_en. Pulse shaper 200B can receive the clock signal occ_clk and generate a test clock enable signal test_clk_enable based at least in part on the clock signal occ_clk. Multiplexer 110B can receive the test clock enable signal test_clk_enable and the signal sram_clk_en. Multiplexer 110B can generate an output signal 126. Multiplexer 110C can generate an output signal 128 based on the clock signal logic_clk and the clock signal occ_clk controlled by the control signal sram_occ_en. AND gate 120 can generate output signal 130 based on the test clock enable signal test_clk_enable and the control signal div_clk_bypass provided by pulse shaper 200B. ICG 122 can generate output signal 132 based on the output signal 130 output by AND gate 120 and the clock signal occ_clk. In one embodiment, OCC 102 can be referred to as the first OCC, and OCC 104 as the second OCC. The main improvement of the present invention lies in OCC 104 (the second OCC, or custom OCC). Furthermore, the integrated clock gate 118 and frequency divider 124 may or may not be included in OCC 104 (depending on design requirements).

[0040] The multi-cycle path circuit 100 may include a frequency divider 124. The frequency divider 124 may generate an output signal 134 based on the output signal 128 output from multiplexer 110C and the output signal 126 output from multiplexer 110B. The frequency divider 124 may be configured to divide the output signal 128 output from multiplexer 110C into a multiphase clock controlled by the output signal 126 output from multiplexer 110B.

[0041] Multiplexer 110D can generate an output signal based on the output signal 132 from ICG 122 and the output signal 134 from frequency divider 124 controlled by the control signal div_clk_bypass. The output signal of multiplexer 110D can be provided to SRAM 108 as a clock signal sram_clk.

[0042] Figure 2This is a block diagram of a pulse shaper 200 of a multi-cycle path circuit 100 according to some embodiments (e.g., it can be used to implement pulse shapers 200A and / or 200B). The pulse shaper 200 may include a shift register 204 configured to receive a clock signal scan_clk and a data signal scan_in, which can be provided by the ATE. The shift register 204 can generate an output signal scan_out and an output signal 208 based on the clock signal scan_clk and the data signal scan_in.

[0043] The pulse shaper 200 may include a counter 206 configured to receive a clock signal occ_clk from the OCC 102. The counter 206 may generate an output signal 210 based on the clock signal occ_clk.

[0044] The pulse shaper 200 may include a control circuit 202 configured to receive a signal 208 generated by the shifter buffer 204, a signal 210 generated by the counter 206, a signal scan_mode, a signal scan_enable, and a signal occ_mode. The control circuit 202 may generate a test clock enable signal test_clk_enable based on signals 208, 210, scan_mode, scan_enable, and occ_mode.

[0045] Figure 3 This is a timing diagram of a multi-cycle path circuit 100 in functional mode according to some embodiments. In functional mode, logic_clk_en and sram_clk_en control ICG 118 and frequency divider 124, respectively. Test mode signals such as scan_mode, scan_enable, occ_mode, logic_clk_1hot, logic_clk_disable, sram_occ_en, and div_clk_bypass are set to zero. As shown, the input of SRAM 108 (A / DI / CS / WE) can be maintained for multiple logic_clk cycles. At time (1), logic circuit 106 can start the clock for write operation. At time (2), SRAM 108 can perform write operation. At time (3), SRAM 108 can start the clock for read operation. At time (4), when the data valid signal logic.datavalid indicates valid data, logic circuit 106 can read the data output by SRAM 108, which may require multiple cycles of logic_clk.

[0046] Figure 4 This is a timing diagram of a multi-cycle path circuit 100 in a fixed test mode according to some embodiments. Scan_mode is high and occ_mode is low, indicating that the multi-cycle path circuit 100 is in a stuck-at-test mode. In the fixed test mode, the multi-cycle path circuit 100 is configured to test whether path 137 has a stuck-at fault (a fixed "0" or "1" fault). In the fixed test mode, the signal logic_clk can be set to zero, the test control signals logic_clk_1hot can be set to 0, logic_clk_disable to 1, sram_occ_en to 0, and div_clk_bypass to 1. A stuck-at fault on test path 137 can be detected by providing a signal mode to test path 137 (e.g., using a test method design) and capturing the value on the DO terminal of SRAM 108.

[0047] Figure 5 This is a timing diagram of a multi-cycle path circuit 100 in full-speed test mode according to some embodiments. Scan_mode is high and occ_mode is low, indicating that the multi-cycle path circuit 100 is in full-speed test mode. In full-speed test mode, the multi-cycle path circuit 100 can perform full-speed write operations. Test control signals logic_clk_1hot and sram_occ_en can be set to 1, and div_clk_bypass and logic_clk_disable can be set to zero. As shown, when the multi-cycle path circuit 100 is in functional mode, at times (51) and (52), simulations can be provided for logic_clk and sram_clk. Figure 3 The pulses at time (1) and time (2) are observed. Then, the DO pin of the SRAM 108 is observed to ensure that the transition is performed with the correct timing.

[0048] Figure 6 This is a timing diagram of a multi-cycle path circuit 100 in full-speed test mode according to some embodiments. In this test mode, the multi-cycle path circuit 100 can perform a full-speed read operation. The test control signals logic_clk_1hot and sram_occ_en can be set to 1, and div_clk_bypass and logic_clk_disable can be set to zero. As shown, when the multi-cycle path circuit 100 is in functional mode, at times (63) and (64), simulations can be provided for logic_clk and sram_clk. Figure 3The pulses at time (3) and time (4) are observed. Then, the DO pin of the SRAM 108 is observed to ensure that the conversion is performed with the correct timing.

[0049] The custom on-chip clock controller (COCC) of this invention utilizes clock pulse shaping circuitry to control the functional mode clock gating element and clock divider to establish a multi-cycle phase relationship between the clock entering the logic and the timing path of the L2 data RAM memory. The design of this invention also ensures that the clock paths entering and exiting (sent to and from) the L2 data RAM are the same in functional mode and full-speed capture mode (full-speed test mode) to avoid hold and set timing conflicts between these modes.

[0050] Various modifications can be made to the illustrative structures shown and described herein. For example, an on-chip clock controller is described in conjunction with a multi-cycle path circuit having logic circuitry and SRAM. The on-chip clock controller can be used in conjunction with any suitable multi-cycle path circuitry. As a specific example of a possible variation, the on-chip clock controller can be used in conjunction with a multi-cycle path circuit having two logic circuits.

[0051] The various aspects of the apparatus and techniques described herein can be used individually, in combination, or in various arrangements not specifically discussed in the embodiments described above, and are therefore not limited to the details and arrangements of their application to the group of components set forth in the foregoing description or shown in the accompanying drawings. For example, an aspect described in one embodiment can be combined in any way with aspects described in other embodiments.

[0052] Those skilled in the art will readily observe that numerous modifications and alterations can be made to the apparatus and method while maintaining the teachings of this invention. Therefore, the foregoing disclosure should be interpreted as being limited only by the scope and limits of the appended claims.

Claims

1. A multi-cycle path circuit, characterized in that, include: The logic circuit is configured to operate with a first clock signal of a first time period. A memory, coupled to the logic circuit and configured to operate with a second clock signal of a second time period, the second time period being a multiple of the first time period; as well as An on-chip clock controller, coupled to the logic circuit and the memory, is configured to provide the first clock signal to the logic circuit and the second clock signal to the memory. The multi-cycle path circuit is configured to operate in a functional mode, in which the logic circuit controls the reading and / or writing of the memory, and The multi-cycle path circuit is configured to operate in full-speed test mode, in which the logic circuit controls the reading and / or writing of the memory to test the transformation of the value output from the memory within multiple clock cycles of the first clock signal. The on-chip controller is configured to ensure that the clock path to the logic circuit and the memory is the same for the functional mode and the full-speed test mode, in order to avoid hold and setup timing conflicts between the functional mode and the test mode due to clock differences.

2. The multi-cycle path circuit as described in claim 1, characterized in that: The on-chip clock controller receives the on-chip clock signal and modulates the on-chip clock signal to generate the first clock signal and the second clock signal.

3. The multi-cycle path circuit as described in claim 2, characterized in that: The on-chip clock controller includes: The first pulse shaper receives the clock signal from the chip and outputs the first test clock enable signal, and The second pulse shaper receives the clock signal from the chip and outputs the second test clock enable signal.

4. The multi-cycle path circuit as described in claim 3, characterized in that: The on-chip clock controller includes a first multiplexer that provides the first test clock enable signal to an integrated clock selector. When the multi-cycle path circuit is running in the full-speed test mode, the integrated clock selector selects the on-chip clock signal and provides a gated version of the on-chip clock signal to the logic circuit.

5. The multi-cycle path circuit as described in claim 3, characterized in that: The first pulse shaper includes: The first control circuit generates the first test clock enable signal. The first shift register is coupled to the first control circuit, and The first counter is coupled to the first control circuit.

6. The multi-cycle path circuit as described in claim 3, characterized in that: The second pulse shaper includes: The second control circuit generates the second test clock enable signal. The second shift register is coupled to the second control circuit, and The second counter is coupled to the second control circuit.

7. The multi-cycle path circuit as described in claim 1, characterized in that: The multi-cycle path circuit includes a frequency divider configured to generate the second clock signal from the first clock signal.

8. The multi-cycle path circuit as described in claim 1, characterized in that: The multi-cycle path circuit is also configured to operate in a fixed test mode to test whether the input of the memory is fixed at a logic value.

9. An on-chip controller, characterized in that, Configured to provide clock signals to a first and a second circuit coupled to each other, and operating using the first and second clock signals respectively in a multi-cycle phase relationship, the on-chip controller is configured to ensure that the clock paths to the first and second circuits are the same for both functional mode and full-speed test mode, to avoid hold-up and setup timing conflicts between the functional mode and the test mode due to clock differences. The on-chip controller includes: A first pulse shaper receives the clock signal from the chip and outputs a first test clock enable signal; and The second pulse shaper receives the clock signal on the chip and outputs a second test clock enable signal, so that the controller on the chip provides the first clock signal and the second clock signal to the first circuit and the second circuit respectively, based at least in part on the first test clock enable signal and the second test clock enable signal.

10. A chip-based control system, characterized in that, include: The first circuit and the second circuit are coupled to each other and operate with the first clock signal and the second clock signal respectively in a multi-cycle phase relationship. The first on-chip clock controller is configured to modulate the on-chip clock signal to provide the first clock signal and the second clock signal to the first circuit and the second circuit respectively. as well as The second on-chip clock controller is configured to provide the on-chip clock signal to the first on-chip clock controller based on the scan clock signal; The on-chip control system is also configured to ensure that the clock paths to the first circuit and the second circuit are the same for both the functional mode and the full-speed test mode, in order to avoid hold-up and setup timing conflicts between the functional mode and the test mode due to clock differences.

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