A method and apparatus for detecting leakage in a transistor channel of a dram memory cell

Abstract

The present disclosure relates to the technical field of semiconductor memory testing, and particularly relates to a method and device for detecting leakage of a transistor channel of a DRAM memory cell. An active driving mechanism is constructed, which keeps a first word line active during a standby period and keeps a sense amplifier continuously in an enabled state. The physical limitation that a bit line automatically falls to a pre-charge potential after a word line is closed in mainstream DRAM architecture is broken, and the bit line is forced to be maintained at a limit target potential. The mechanism can effectively solve the problem that the test voltage difference between the source and the drain of a transistor is seriously insufficient due to the pre-charge potential in a conventional standby test. A maximum limit voltage stress environment is successfully constructed across an access transistor in a closed state, thereby effectively improving the limit detection coverage and interception capability of weak channel sub-threshold leakage defects. Without adding any additional hardware test circuit modification overhead inside the chip, the detection result accuracy and overall application efficiency in a mass production test scene are improved.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor memory testing technology, specifically to a method and apparatus for detecting leakage current in the transistor channel of a DRAM memory cell. Background Technology

[0002] When performing leakage current detection on the transistor channel of a memory cell in Dynamic Random Access Memory (DRAM), a method is often used: writing a specified level of data to the capacitor, then turning off the word line (WL) and waiting for a period of time, before reading the capacitor data to observe the leakage failure.

[0003] However, there are two main problems with current leakage detection of DRAM transistor channels: First, during the rest period when the word line is off, the bit line (BL) in mainstream memory architecture is forcibly pulled back to a precharge potential of about half the operating voltage. This results in a severe lack of drain-to-source voltage (Vds) between the source and drain of the transistor in the off state, which cannot simulate the worst leakage conditions at all, making it easy to miss edge failure particles with weak channel leakage defects. Second, some existing accelerated leakage test schemes are mostly implemented by applying unconventional word line bias voltages. The physical mechanism of these schemes is essentially aimed at gate-induced drain leakage (GIDL), which cannot truly excite and effectively screen for subthreshold channel leakage between the source and drain of the transistor.

[0004] Therefore, how to address the issues of insufficient test voltage difference and misaligned physical mechanisms in existing DRAM channel leakage detection, and how to implement a leakage detection mechanism that can break the bit line precharge limitation during the resting period and actively build an extreme voltage difference between the source and drain without adding extra hardware circuitry, thereby improving the extreme coverage and interception accuracy of weak channel leakage defects, has become an urgent problem to be solved. Summary of the Invention

[0005] In view of this, this disclosure provides a method and apparatus for detecting leakage current in the transistor channel of a DRAM memory cell, in order to solve the problem of insufficient test voltage difference and physical mechanism misalignment in existing DRAM channel leakage current detection. It aims to achieve a leakage current detection mechanism that can break the bit line precharge limitation during the resting period and actively build a limit voltage difference between the source and drain without adding additional hardware circuitry, thereby improving the limit coverage and interception accuracy of weak channel leakage current defects.

[0006] This disclosure provides a method for detecting leakage current in the transistor channel of a DRAM memory cell, the method comprising: First-level data is written to a first memory cell connected to a first word line in the target memory array, and second-level data is written to a second memory cell connected to a second word line. The first-level data and the second-level data are logically opposite, and both the first and second memory cells are connected to the same bit line of the same sense amplifier. Each of the first and second memory cells includes an access transistor and a capacitor for storing charge. Activate the first word line and enable the sense amplifier to drive the potential of the bit line on the same side to the target potential corresponding to the first level data, and simultaneously drive the complementary bit line on the other side of the sense amplifier to a reference potential opposite to the target potential. During the preset rest period, the first word line is kept in the active state, the sense amplifier is kept in the enabled state, and the second word line is kept in the inactive state, so that the access transistor of the second memory cell is kept off, and a leakage test voltage difference is continuously built between the source and drain of the access transistor of the second memory cell. After the resting time is over, the first word line is turned off, the data of the second memory cell is read, and the data read is used to determine whether there is leakage between the source and drain of the access transistor of the second memory cell.

[0007] This disclosure also provides a leakage current detection device for the transistor channel of a DRAM memory cell, the device comprising: The data writing module is used to write first-level data to a first memory cell connected to a first word line in the target memory array, and to write second-level data to a second memory cell connected to a second word line. The first-level data and the second-level data are logically opposite, and the first memory cell and the second memory cell are both connected to the same bit line of the same sense amplifier. The first memory cell and the second memory cell both include access transistors and capacitors for storing charge. The activation enable module is used to activate the first word line and enable the sense amplifier to drive the potential of the bit line on the same side to the target potential corresponding to the first level data, and simultaneously drive the complementary bit line on the other side of the sense amplifier to the reference potential opposite to the target potential. An active hold module is used to keep the first word line in an active state, the sense amplifier in an enabled state, and the second word line in an inactive state for a preset rest period of time, so as to keep the access transistor of the second memory cell off and continuously build a leakage test voltage difference between the source and drain of the access transistor of the second memory cell. The leakage current detection module is used to shut down the first word line after the resting time ends, read the data of the second memory cell, and determine whether there is leakage current between the source and drain of the access transistor of the second memory cell based on the read data.

[0008] This disclosure also provides an electronic device, including: a memory for storing a computer program; and a processor for implementing the leakage current detection method of any of the above-described DRAM memory cell transistor channels when executing the computer program.

[0009] This disclosure also provides a computer-readable storage medium storing a computer program, wherein when the computer program is executed by a processor, it implements the steps of any of the above-described DRAM memory cell transistor channel leakage detection methods.

[0010] This disclosure also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of any of the above-described DRAM memory cell transistor channel leakage detection methods.

[0011] In the DRAM memory cell transistor channel leakage detection method and apparatus of the above embodiments of this disclosure, firstly, by constructing an active driving mechanism that keeps the first word line active during the rest period and keeps the sense amplifier continuously enabled, the physical limitation of the bit line automatically falling back to the precharge potential after the word line is turned off in the mainstream DRAM architecture is broken, and the bit line is forced to be maintained at the extreme target potential. This mechanism can effectively solve the problem of insufficient test voltage difference between the source and drain of the transistor due to the precharge potential in the traditional rest test. The maximum extreme voltage stress environment is successfully constructed at both ends of the access transistor in the off state, thereby effectively improving the extreme detection coverage and interception capability of weak channel subthreshold leakage defects.

[0012] Secondly, by writing logically opposite data to memory cells connected to different word lines on the same bit line, and combining this with the asymmetric operation mode of target row activation holding voltage and background row deactivation leakage, the ultimate leakage test voltage difference is continuously applied between the source and drain of the access transistor. This mechanism not only eliminates the physical mechanism misalignment interference caused by applying unconventional word line bias for accelerated testing in existing technologies (i.e., eliminates the interference of gate-induced drain leakage GIDL), but also achieves physical attribution of the true channel leakage defect. Moreover, it does not require any additional hardware test circuit modification to the chip, thereby improving the accuracy of the DRAM channel leakage detection solution in mass production testing scenarios and the overall application efficiency. Attached Figure Description

[0013] To more clearly illustrate the embodiments of this disclosure, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0014] Figure 1 This is a schematic diagram of a typical embedded word-line DRAM memory cell in the prior art. Figure 2 A schematic flowchart illustrating a leakage current detection method for a transistor channel in a DRAM memory cell provided in this embodiment of the present disclosure; Figure 3 A schematic diagram of the memory cell structure for a leakage current detection method of a transistor channel in a DRAM memory cell provided in an embodiment of this disclosure; Figure 4 A schematic diagram of the full array data graphic configuration for a leakage current detection method for a DRAM memory cell transistor channel provided in an embodiment of this disclosure; Figure 5 A flowchart illustrating another method for detecting leakage current in the transistor channel of a DRAM memory cell provided in this embodiment of the present disclosure; Figure 6 A schematic diagram of a leakage current detection device for a DRAM memory cell transistor channel provided in an embodiment of this disclosure; Figure 7 This is a schematic diagram of the structure of an electronic device according to an embodiment of the present disclosure. Detailed Implementation

[0015] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this disclosure.

[0016] As the core data throughput hub of modern computing systems, DRAM, with its high-density physical layout and high-reliability data retention capability under advanced processes, is the core foundation for achieving high-performance computing and improving the overall system stability.

[0017] However, as DRAM process dimensions continue to shrink, the access transistors within memory cells are also gradually becoming smaller in feature size. This physical miniaturization exacerbates the channel leakage (subthreshold leakage) problem in the transistor's off state, easily leading to the loss of charge stored in the capacitor and consequently reducing data retention time. Existing channel leakage detection mechanisms typically rely on writing specified data to the capacitor, then turning off the word line for a long period of static rest, and subsequently reading the capacitor data to determine if leakage failure has occurred. In this scenario, the stress environment for leakage testing is entirely limited by the native standby potential setting within the DRAM chip. Relying solely on the conventional word line-off rest mode to apply leakage stress results in several limitations of existing technology: 1. Please refer to Figure 1 , Figure 1 This is a schematic diagram of a typical cross-sectional structure of an embedded word-line DRAM memory cell in the prior art, such as... Figure 1 As shown, the isolation structure 13 above word line 14 has a size of L1, and the source / drain 12 has a size of L2. Because L1 is smaller than L2, the source / drain 12 is easily connected to word line 14, causing leakage between word line 14 and capacitor 11, resulting in errors in the stored data "0" and "1". In mainstream DRAM architecture designs, the potential control of the bit line (BL) is strictly limited by regular operating instructions. When word line 14 is turned off and enters a silent standby state, the sense amplifier is turned off, and the bit line is forced back to half of the operating voltage (Voltage Drain, VDD) by the pre-charge mechanism. This means that regardless of whether the capacitor stores a high or low level, the voltage difference Vds between the two source / drain 12 of the transistor in the off state is only approximately equal to VDD / 2. This relatively mild test voltage difference cannot simulate the worst leakage conditions on the test bench. In extremely demanding mass production testing scenarios, insufficient test stress can easily lead to… Figure 1 Edge failure cells with weak channel leakage defects between the two source / drain electrodes 12 were missed, which led to reliability issues in the long-term use of the memory system. 2. To break through the above limitations of the pre-charge voltage to apply a greater leakage stress, some existing technologies (such as patent document CN116705103A) propose a solution of imposing a bias on the bit line during the off period of the word line 14. For example, the related patent document proposes that after the word line 14 is turned off, a first voltage (such as a high potential or a low potential) is applied to the bit line to construct a leakage potential difference. However, based on the underlying control logic of the above DRAM, in the standby state where both the word line 14 and the sense amplifier are off, conventional operation instructions simply cannot maintain the bit line potential at VDD or 0. To implement this technical solution, it is necessary to forcibly introduce an additional design for test (DFT) test circuit to change the bit line potential. However, this not only significantly increases the chip area overhead and design complexity, but it is also difficult to achieve low-cost mass production testing without damaging the native memory array structure; 3. In some existing solutions (such as patent document CN115954040A) that accelerate the leakage test without adding hardware, the industry usually adopts the method of applying an unconventional bias voltage (such as applying a deeper negative bias voltage) to the non-activated word line. However, in terms of the microscopic physical mechanism of this test mode, combined with Figure 1 it can be seen that due to the buried process of the transistors in the DRAM semiconductor, the size L2 of the source / drain 12 is larger than the size L1 of the isolation structure 13, resulting in a physical overlap region between the source / drain 12 connected to the capacitor 11 and the word line 14 of the transistor. This makes the DRAM have a larger GIDL current compared to planar transistors. The above test scheme of applying a negative bias voltage to the word line actually artificially exacerbates the voltage difference between the word line 14 and the source / drain 12, and most of the GIDL current excited and tested is exactly the above-mentioned GIDL current. Due to the interference of other leakage mechanisms, this method of regulating the word line voltage cannot purely and truly reflect the channel subthreshold leakage caused by process defects between the two source / drains 12 of the transistor. That is, the leakage measured by the existing technology cannot accurately determine that the leakage only comes from the transistor channel, resulting in the measurement result not being attributable to the degradation of the channel physical characteristics by 100%. This mixed leakage effect seriously masks the true channel failure boundary, resulting in a lack of exact data guidance for the evaluation of the process yield of advanced process transistors.

[0018] Therefore, how to achieve a leakage detection mechanism that can break the bit line pre-charge limit during the static period and actively construct a constant limit voltage difference between the source and drain without adding additional hardware circuits, so as to improve the limit coverage rate and interception accuracy of weak channel leakage defects, has become an urgent problem to be solved.

[0019] To solve the above problems, a method for detecting leakage current in the transistor channel of a DRAM memory cell provided in various embodiments of the present disclosure includes: writing first-level data to a first memory cell connected to a first word line in a target memory array, and writing second-level data to a second memory cell connected to a second word line, where the first-level data and the second-level data are logically opposite, and both the first memory cell and the second memory cell are connected to the same side bit line of the same sense amplifier; wherein, both the first memory cell and the second memory cell include an access transistor and a capacitor for storing charge; activating the first word line and enabling the sense amplifier to drive the potential of the same side bit line to the target potential corresponding to the first-level data, and synchronously driving the complementary bit line on the other side of the sense amplifier to a reference potential opposite to the target potential; within a preset static time, keeping the first word line in an activated state, the sense amplifier in an enabled state, and keeping the second word line in an unactivated state, so that the access transistor of the second memory cell remains off, and continuously building a leakage test voltage difference between the source and drain of the access transistor of the second memory cell; after the static time ends, turning off the first word line, reading the data of the second memory cell, and determining whether there is leakage between the source and drain of the access transistor of the second memory cell according to the read data.

[0020] It should be noted that in the description of the present disclosure, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in the present disclosure are used to distinguish similar objects, and are not used to describe a specific order or sequence.

[0021] In order to enable those skilled in the art of the present technology to better understand the solutions of the present disclosure, the present disclosure will be further described in detail below with reference to the drawings and specific embodiments.

[0022] Please refer to Figure 2 , Figure 2 which is a schematic flow chart of a method for detecting leakage current in the transistor channel of a DRAM memory cell provided in an embodiment of the present disclosure. The flow of the method may include the following steps: Step S201: Write first-level data to a first memory cell connected to a first word line in a target memory array, and write second-level data to a second memory cell connected to a second word line, where the first-level data and the second-level data are logically opposite, and both the first memory cell and the second memory cell are connected to the same side bit line of the same sense amplifier.

[0023] In this embodiment, both the first storage unit and the second storage unit include an access transistor and a capacitor for storing charges.

[0024] To achieve efficient concurrent detection of the entire array, the target storage array in this embodiment may adopt a differential readout architecture, which may include a first memory region and a second memory region sharing the same sense amplifier (SA). The same-side bit line and the complementary bit line specifically form a bit line pair connected to both ends of the SA. This bit line pair includes a true bit line (BLT) extending to the first memory region and a complementary bit line (BLB) extending to the second memory region.

[0025] Exemplarily, please refer to Figure 3 , Figure 3 which is a schematic diagram of the storage unit structure for a method of detecting leakage current in the transistor channel of a DRAM storage unit provided by an embodiment of the present disclosure. As Figure 3 shown, the control terminal (such as the gate of the transistor) of the access transistor is electrically coupled to the word line in the target storage array (such as the aforementioned first word line or second word line) for receiving an on or off instruction sent by the word line; one of the first conduction terminals (such as one of the source or drain of the transistor) of the access transistor is electrically connected to one plate of the capacitor, and the second conduction terminal of the access transistor (such as the other of the source or drain of the transistor) is electrically connected to the corresponding bit line (such as the same-side bit line mentioned above); in addition, the other plate of the capacitor is connected to a preset reference voltage (such as the plate voltage Vplate).

[0026] It can be understood that when a specific word line is applied with an activation voltage, the control terminal of the corresponding access transistor responds and causes the first conduction terminal and the second conduction terminal to conduct, thereby establishing a physical conduction path between the bit line and the capacitor plate; at this time, the level data carried by the bit line can be converted into a corresponding charge flow, injected through the conducting access transistor and retained in the capacitor, or the charges in the capacitor can also be released to the bit line and read.

[0027] Specifically, the target storage array may refer to a physical array block formed by the interweaving of multiple word lines and multiple bit lines in DRAM. During the execution of step S201 above, according to the above hardware connection mechanism, logically opposite data are written to the first storage unit and the second storage unit connected to the same side bit line of the same SA respectively. In the differential readout architecture, specifically, an asymmetric leakage stress environment can be constructed by writing complementary data background patterns to both sides of the bit line pair, including: in the first memory area, writing logic "1" to the selected first word line and writing logic "0" to the remaining second word lines; while in the second memory area, correspondingly writing logic "0" to its first word line and writing logic "1" to the remaining second word lines. For example, the first-level data may be high-level data representing logic "1", and the second-level data may be low-level data representing logic "0"; or vice versa.

[0028] It can be understood that through the above writing operation, opposite-polarity charges are resident in the capacitors of the first storage unit and the second storage unit on the same side bit line, which provides an initial state preparation for subsequently exciting the source-drain extreme voltage difference of the access transistor at the microscopic physical level.

[0029] Step S202, activate the first word line and enable the sense amplifier to drive the potential of the same side bit line to the target potential corresponding to the first-level data, and synchronously drive the complementary bit line on the other side of the sense amplifier to a reference potential opposite to the target potential.

[0030] In this embodiment, activating the first word line may refer to making the access transistor of the first storage unit in a conducting state by applying an enabling level to the first word line.

[0031] Specifically, when the first word line is opened, the charge (i.e., the first-level data) inside the capacitor of the first storage unit will share charges with the bit line. Subsequently, enable the SA corresponding to this bit line. After the SA senses the tiny potential signal on this side bit line, it can drive the potential of this same side bit line to the corresponding target potential, and synchronously drive the complementary bit line on the other side of the SA to a reference potential opposite to the target potential.

[0032] Combined with the data written in step S201, if the first-level data is logic "1", SA will forcibly pull up the bit line potential on the side where the first storage cell is located and anchor it at the highest operating potential (such as VDD), and simultaneously drive the complementary bit line on the other side of the SA to the lowest operating potential (such as the source voltage VSS, i.e., the reference potential); if the first-level data is logic "0", SA will forcibly pull down the bit line potential on this side and anchor it at the lowest operating potential it can output (such as VSS), and simultaneously drive the complementary bit line on the other side to the highest operating potential (such as VDD). This step breaks the limitation that the bit line is at the pre-charge potential (VDD / 2) in the conventional standby state, and endows the entire bit line with an extreme physical bias environment.

[0033] It should be noted that in the conventional DRAM access logic, logic "1" or logic "0" only represents a potential range, and as long as the bit line potential exceeds the decision threshold, it can be recognized as the corresponding logic state. In this embodiment, by continuously enabling SA to forcibly anchor the bit line at the highest operating potential VDD or the lowest operating potential VSS, the purpose is not simple data representation, but to break the physical tendency of the bit line potential to fall back to VDD / 2 during the conventional read / write or static cycle, so as to construct the maximum source-drain voltage difference that the access transistor in the off state can withstand within its physical characteristics range.

[0034] Step S203, within the preset static time, keep the first word line in the active state, the sense amplifier in the enabled state, and keep the second word line in the non-active state, so that the access transistor of the second storage cell remains off, and continuously construct a leakage test voltage difference between the source and drain of the access transistor of the second storage cell.

[0035] In this embodiment, the preset static time can refer to a waiting period artificially set according to the chip physical characteristics or test coverage requirements for fully stimulating and accumulating the subthreshold channel leakage effect.

[0036] Specifically, within the above-mentioned static time, since the first word line is continuously activated and SA is continuously enabled, SA, as an active driving circuit, continuously provides charge compensation to the bit line, making the bit line always rigidly maintained at the above-mentioned target potential (such as VDD). In the differential readout architecture, SA, as a bidirectional active driving source, simultaneously maintains the extreme bias environment of BLT at VDD and BLB at VSS.

[0037] Meanwhile, the second word line remains strictly inactive during this period, causing the access transistor of the second memory cell to be physically turned off. Since the capacitor of the second memory cell has pre-stored second-level data (such as VSS) that is logically opposite to the first-level data, at this time, at both ends of the access transistor of the second memory cell in the off state: the end (drain) connected to the bit line is forced by the SA to VDD, while the end (source) connected to the capacitor is at VSS. At the same time, in the second memory area, since the BLB is automatically pulled down to VSS and the capacitor in this area has pre-resided the logic "1" (VDD), the transistors in the off state in the second memory area synchronously withstand the reverse full voltage drop limit.

[0038] It can be understood that the above mechanism effectively utilizes the SA driving force of another open cell on the bit line to construct a limit voltage difference Vds equal to the full voltage drop (such as VDD - VSS) between the source and drain of the access transistor of the second memory cell in the off state. This limit and constant voltage difference that does not decay with time effectively overcomes the mild environment where the limit voltage difference Vds in traditional tests is only VDD / 2, and can effectively force the transistor channel with a weak turn-off defect to expose subthreshold leakage. This mechanism further utilizes the physical isolation and differential linkage characteristics of the SA to achieve two-way limit stress application to a large number of background cells in the memory areas on both sides of the SA through the activation of a single row.

[0039] Step S204, after the static time ends, turn off the first word line, read the data of the second memory cell, and determine whether there is leakage between the source and drain of the access transistor of the second memory cell according to the read data.

[0040] In this embodiment, the end of the static time means that the limit physical stress application stage is completed, and the test process enters the data verification and failure determination stage.

[0041] Turning off the first word line can refer to issuing a pre-charge command (PRE), disconnecting the connection between the first memory cell and the bit line, and restoring the potential on the bit line to the initial balanced state (VDD / 2) for the next independent read. Subsequently, activate the second word line and enable the SA again to sense and extract the current true charge residence state of the capacitor of the second memory cell. In a differential readout architecture, the second word lines of the first memory area and the second memory area can be activated in sequence, and the capacitors storing logic "0" in the first memory area and the capacitors storing logic "1" in the second memory area can be read respectively.

[0042] Specifically, determining whether there is channel leakage may mean comparing the currently read logical state of the second storage unit with the second-level data initially written in step S201. If channel leakage occurs in the access transistor due to the aforementioned extreme voltage difference Vds, the charge on the bit line will penetrate into the capacitor through the poorly turned-off channel, resulting in an abnormal inversion of the read data (for example, an abnormal inversion from the initially written logical "0" to logical "1", or from logical "1" to logical "0"). Capturing this inversion phenomenon can determine that there is a physical leakage failure between the source and drain of the transistor.

[0043] In the method and device for detecting leakage of the DRAM memory cell transistor channel in the above embodiments of the present disclosure, first, by constructing an active driving mechanism that keeps the first word line activated and the SA continuously enabled during static periods, the physical limitation that the bit line automatically returns to the pre-charge potential after the word line is turned off in the mainstream DRAM architecture is broken, and the bit line is forced to maintain at the extreme target potential. This mechanism can effectively solve the problem of serious insufficient test voltage difference between the source and drain of the transistor caused by the pre-charge potential in traditional static tests, and successfully construct a maximized extreme voltage stress environment at both ends of the access transistor in the off state, thereby effectively improving the extreme detection coverage rate and interception ability for weak channel sub-threshold leakage defects. Secondly, by writing logically opposite data to the memory cells connected to different word lines on the same bit line, and combining the asymmetric operation mode of target row activation and voltage holding, and background row shutdown and leakage reception, the extreme leakage test voltage difference is continuously applied between the source and drain of the access transistor. This mechanism not only eliminates the physical mechanism misalignment interference caused by accelerating the test by applying unconventional word line biasing in the prior art (that is, eliminates the interference of gate-induced drain leakage GIDL), and realizes the physical attribution of true channel leakage defects; moreover, it does not require any additional hardware test circuit modification cost inside the chip, thereby improving the detection result accuracy and overall application efficiency of the DRAM channel leakage detection scheme in the mass production test scenario. Finally, by utilizing the differential amplification instinct of the SA and cooperating with the cross-region complementary data background pattern, a double-effect test mode of single-row activation and two-region concurrent pressure application is realized, which compresses the test time required for full-chip scanning.

[0044] In a possible implementation manner of the above embodiment, the first-level data is a high level, the second-level data is a low level, the target potential is the highest working potential of the sense amplifier, and the reference potential is the lowest working potential of the sense amplifier; or, The first-level data is a low level, the second-level data is a high level, the target potential is the lowest working potential of the sense amplifier, and the reference potential is the highest working potential of the sense amplifier.

[0045] In this embodiment, the high-level data can correspond to "1" in digital logic, and the low-level data can correspond to "0" in digital logic. In the actual physical circuit of DRAM, the highest working potential of the SA is usually equal to the core supply high rail voltage of the array (e.g., VDD), and the lowest working potential is usually equal to the ground low rail voltage (e.g., VSS).

[0046] In the first implementation scenario (i.e., the first level is high and the second level is low), when the first word line is activated and the SA is enabled, the SA senses logic "1" and, as an active drive circuit, pulls up and locks the potential of the same-side bit line to VDD and synchronously drives the complementary bit line on the other side to VSS. At this time, for the second storage unit capacitor on the same-side bit line that is in the off state, its capacitance is at the VSS potential because it stores logic "0". The drain of the transistor (connected to the same-side bit line) is VDD, and the source (connected to the capacitor) is VSS, creating a full voltage drop (Vds = VDD - VSS) between them.

[0047] In the second implementation scenario (i.e., the first level is low and the second level is high), the polarity is reversed. After the SA senses the logic "0" of the first storage unit, it pulls down and locks the potential of the same-side bit line to VSS and synchronously drives the complementary bit line on the other side to VDD; at this time, for the second storage unit on the same-side bit line that is in the off state, the VDD corresponding to logic "1" resides in its capacitance. The drain of this access transistor is VSS, and the source is VDD, creating an inverse full voltage drop across the two ends of the transistor channel.

[0048] It can be understood that regardless of which of the above polarity configurations is adopted, the core physical essence is to utilize the differential amplification characteristic of the SA to push and lock the potential of the same-side bit line to the physical system limit (VDD or VSS), preventing the bit line from falling back to VDD / 2 after the word line is turned off.

[0049] In the method and device for detecting leakage in the transistor channel of the DRAM storage unit in the above embodiments of the present disclosure, by clearly defining the target potential as the physical limit that the sense amplifier can output (i.e., the highest working potential or the lowest working potential), and writing the leakage-affected end unit (i.e., the second storage unit) with its complementary inverted level, it is ensured that the maximum absolute value of the limit voltage difference Vds applied between the source and drain of the access transistor in the off state can reach the maximum allowed by the physical design of the chip. This mechanism can utilize the limit voltage difference Vds at the full voltage drop level to excite a weak channel subthreshold leakage current, thereby improving the screening and recognition rate and interception rate of particles in the leakage-edge failure state, and thus enhancing the reliability of the chip.

[0050] In a possible implementation of the above step S201, the first word line is a single target test row in the target memory array, and the second word line includes multiple background test rows, other than the first word line, that are connected to the same side bit line; Writing first-level data to the first memory cell connected to the first word line in the target memory array, and writing second-level data to the second memory cell connected to the second word line, includes: Globally writing first-level data to the memory cells connected to the target test row, and globally writing second-level data to the memory cells connected to each background test row, to construct an asymmetric data background pattern for leakage testing in the target memory array.

[0051] In this embodiment, in the high-density physical array of DRAM, a single bit line can usually mount multiple memory cells (for example, hundreds or thousands can be mounted), and these memory cells are independently controlled by different word lines. Through data configuration in this embodiment, an asymmetric data distribution rule of 1 to N can be constructed on the same side bit line. Specifically, logic "1" is uniformly written to a single target test row (the first word line), and logic "0" is uniformly written to all the remaining background test rows (the second word line).

[0052] On this basis, in order to more intuitively display the final distribution state formed by the above data configuration in the macroscopic physical array,示例性地, please refer to Figure 4 , Figure 4 which is a schematic diagram of the full-array data graphic configuration of a method for detecting leakage of the channel of a DRAM memory cell transistor provided by an embodiment of the present disclosure. As Figure 4 shown, in the target memory array (such as Figure 4 the area 1 to area N in), multiple rows (word lines WL, Figure 4 arranged vertically in) are intertwined with multiple columns (bit lines BL, Figure 4 arranged horizontally in) to connect the memory cells shown as circles. The adjacent memory areas are electrically connected and signal-controlled through a shared SA module.

[0053] On the basis of this physical architecture, in order to locate and stimulate the channel leakage between the source and drain of the access transistor, this embodiment constructs an extremely asymmetric data graphic background in the macroscopic physical array. Combining with the aforementioned differential readout architecture, Figure 4 further shows the data configuration of the first memory area and the second memory area.

[0054] Specifically, referring to Figure 4From the internal details of each region, it can be seen that in the first memory region (such as region 1), only a specific word line is selected as a single target test line (i.e., the aforementioned first word line), and the first level data representing logic "1" is globally and uniformly written to all the memory cells connected to this target test line; at the same time, all the other word lines connected to the same side bit line are designated as background test lines (i.e., the aforementioned second word lines), and the second level data representing logic "0" is globally and uniformly written to all the memory cells on these background lines. Correspondingly, in the second memory region (such as region 2) connected to the complementary bit line on the other side of the SA, only one word line is written with logic "0", and all the other background word lines are written with logic "1".

[0055] It can be understood that through the above full-array graphic configuration, an asymmetric topological state of 1 logic "1" versus N logic "0s" (or vice versa) is constructed on each bit line of the target array. In the subsequent single-sided continuous pressure-holding stage, when the aforementioned first word line in region 1 is activated and the corresponding SA is enabled, the SA will read logic "1" and drive and lock the potential of the same side bit line at VDD. According to the differential driving principle of the SA, the complementary bit line in the other region 2 is synchronously driven and locked at VSS.

[0056] Meanwhile, the internal capacitances of hundreds of background test lines in the physical off state connected to the bit lines on both sides of the SA are all at VSS (region 1) or VDD (region 2). Therefore, as Figure 4 shown in the data arrangement, it is ensured that on any bit line, except for the activated target test line, the drain (the end connected to the bit line) of the access transistors on all the other background test lines is at VDD, and the source (the end connected to the capacitor) is at VSS, so as to concurrently withstand the full voltage drop limit leakage test stress with the potential polarity controlled and the amplitude constant at the same moment.

[0057] In the above embodiments of the present disclosure, by constructing an asymmetric data background pattern, the coverage of a single test is extended from a single transistor to the entire column of background transistors. This mechanism effectively utilizes the global sharing property of the bit line and the active driving ability of the SA, enabling the concurrent extreme pressure application to multiple off-state transistors to be achieved by simply activating the SA once. This not only avoids the long test timing overhead caused by constructing the voltage difference row by row, improves the concurrency of the test machine, but also ensures the efficient and full coverage screening of all transistor channel subthreshold leakage defects in a high-density array within a limited time window.

[0058] In a possible implementation manner of the above step S204, after the static time ends, the first word line is turned off, and the data of the second memory cell is read, including: Send a precharge command to turn off the first word line and restore the balanced potential of the same-side bit line and its complementary bit line; Perform a refresh operation on the target memory array; Send a row activation command for the second word line to turn on the access transistor of the second memory cell; Send a read command to extract and output the data of the second memory cell through a sense amplifier.

[0059] In this embodiment, after the voltage difference Vds holds, since the same-side bit line is at the target potential (i.e., VDD or VSS), it is impossible to directly read other memory cells accurately. [[ID=Ten]]

[0060] Therefore, the precharge command PRE can be issued first to disconnect the first word line, cut off the connection between the first memory cell and the same-side bit line, and end the pressure application process; at the same time, the PRE command can trigger the precharge circuit to discharge or supplement the residual charges on the same-side bit line and its complementary bit line, restoring them to the balanced potential (VDD / 2), providing a reference potential environment for the next independent and interference-free read operation...

[0061] Furthermore, after the potentials of the same-side bit line and its complementary bit line are restored to balance, a refresh operation is performed on the target memory array. Since the static time for leakage testing is usually long, performing a full-chip or local array refresh operation can effectively prevent data loss of the background memory cells that did not participate in this read operation in the target memory array due to natural charge loss, thus avoiding test misjudgment and ensuring the integrity of the background data of the entire array in the long-term test scenario.

[0062] After the refresh operation is completed, the activation command ACT can be issued for the second word line to turn on the second word line in the off state, and the access transistor of the second memory cell is then turned on, and the charge resident in its internal capacitor shares charge with the same-side bit line at VDD / 2.

[0063] Furthermore, the read command READ can be issued to trigger the SA, differentially amplify the potential offset on the same-side bit line, and convert it into a standard digital logic level (logic "1" or logic "0") and output it to an external test machine, thus completing the extraction of the data of the second memory cell.

[0064] In the method and device for detecting leakage of the DRAM memory cell transistor channel in the above embodiments of the present disclosure, by strictly following the standard underlying control timing of sending a precharge command - performing a refresh operation - sending a row activation command - sending a read command, the complex extreme pressure holding and leakage verification operations are effectively decoupled. The core advantage of this mechanism lies in: on the one hand, through the forced clearing effect of the precharge command, the crosstalk of the residual extreme test potential on the bit line to the subsequent reading process is excluded, ensuring the accuracy of leakage data extraction; on the other hand, by introducing a refresh operation step, the data state after long-term static placement of the entire chip is stabilized, enabling the long-cycle extreme pressure test to be completed in this embodiment without losing the data of the remaining untested cells, and enabling this embodiment to directly adapt to existing automated test equipment without any non-standard modifications to the underlying timing control logic of mainstream memories, thereby enhancing the generality and executability of this test method when it is introduced in large-scale industrial mass production.

[0065] In a possible implementation manner of the above step S204, determining whether there is leakage between the source and drain of the access transistor of the second memory cell according to the read data includes: Logically comparing the data of the second memory cell read with the second-level data initially written; If the read data flips from the second-level data to the first-level data, it is determined that there is a leakage failure between the source and drain of the access transistor of the second memory cell.

[0066] In this embodiment, taking the example of writing logic "1" (first-level data) to the first memory cell and logic "0" (second-level data) to the second memory cell in the initial state for illustration.

[0067] During the static pressure holding period, for the second memory cell in the unactivated state, its capacitance should theoretically always maintain the low potential corresponding to logic "0".

[0068] Specifically, if there is a weak turn-off defect (i.e., channel subthreshold leakage) in the access transistor of this second memory cell, since the same-side bit line is forced to maintain at VDD corresponding to logic "1" by SA, the charge on the bit line, driven by the voltage difference Vds, continuously penetrates and leaks into the capacitor with a lower potential through the not-fully-closed transistor channel. As the static time passes, the above charge leakage will gradually and abnormally raise the actual potential inside the second memory cell.

[0069] When the static time ends and the read operation is performed, if the potential in the capacitor has been raised by leakage and exceeds the decision flip threshold for differential amplification by the SA, the SA will amplify it incorrectly and output it as logic "1". At this time, through a simple logic gate comparison, it is found that the data read from this cell (logic "1") is completely opposite to the data initially written (logic "0"). By capturing this clear logical flip phenomenon from the second-level data to the first-level data, it is possible to directly determine that channel leakage failure has occurred between the source and drain of the transistor without the aid of any analog measurement instruments.

[0070] In the method and device for detecting leakage of the transistor channel of the DRAM memory cell in the above embodiments of the present disclosure, by converting the channel charge leakage phenomenon at the microscopic physical level into a unidirectional state flip of data in macroscopic digital logic, a clear failure determination basis is provided for the test equipment. This mechanism can eliminate the hardware overhead and time cost of high-precision measurement of weak analog leakage current in mass production testing, enabling ordinary digital automated test equipment to quickly locate defective particles only through standard logic data comparison, thereby effectively improving the automatic recognition speed and accuracy of weak channel leakage defects.

[0071] In a possible implementation manner of the above embodiment, the method further includes a reverse test step, and the reverse test step includes: Writing second-level data to the first memory cell and writing first-level data to the second memory cell; Activating the first word line and enabling the sense amplifier to drive the potential of the same-side bit line to the reverse target potential corresponding to the second-level data, and synchronously driving the complementary bit line on the other side of the sense amplifier to the reverse reference potential opposite to the reverse target potential; During the preset static time, keep the first word line in the activated state, the sense amplifier in the enabled state, and keep the second word line in the unactivated state; After the static time ends, turn off the first word line and read the data of the second memory cell to determine whether there is leakage between the source and drain of the access transistor of the second memory cell under the reverse voltage difference.

[0072] In this embodiment, considering that in the actual semiconductor manufacturing process of DRAM, due to lithography alignment deviation, uneven doping concentration gradient or asymmetry of the microscopic topography, the physical defects formed inside the access transistor often exhibit electrical directionality. This means that there may be a significant difference in the ease of leakage between the direction from the drain to the source and the direction from the source to the drain of the transistor channel. If only the forward leakage detection with a single-polarity voltage difference is performed in mass production testing, it is very easy to miss weak leakage defects with the characteristic of unidirectional conduction.

[0073] Therefore, in this embodiment, a reverse test step is introduced. Physically, data is rewritten to the target storage array, and the electric field polarities borne by the first storage unit and the second storage unit are interchanged.

[0074] Specifically, if the first-level data is logic "1" and the second-level data is logic "0" during the forward test; in the reverse test, logic "0" is written to the first storage unit, and logic "1" is written to the second storage unit.

[0075] Activate the first word line and enable the sense amplifier. The sense amplifier senses logic "0", drives and locks the potential of the same-side bit line at the reverse target potential (such as VSS), and synchronously drives the complementary bit line on the other side to the reverse reference potential (such as VDD).

[0076] During the reverse static period, in the second storage unit in the unactivated state, its drain (connected to the same-side bit line) is driven to VSS by the sense amplifier, and its source (connected to the capacitor) is at VDD because it stores the rewritten logic "1". A full voltage drop opposite to the electric field direction in the forward test is built across the access transistor of the second storage unit.

[0077] After the static time ends, turn off the first word line, read the data of the second storage unit, and observe whether the data is driven by the reverse voltage difference Vds to flip from the rewritten logic "1" to logic "0", so as to determine whether there is a reverse channel leakage failure.

[0078] In the method and device for detecting leakage of the DRAM storage unit transistor channel in the above embodiment of the present disclosure, by introducing a reverse test step of data rewriting and polarity interchange based on forward leakage detection, two-way full coverage screening of the forward and reverse electric field stresses at both ends of the access transistor source and drain is achieved. This mechanism effectively compensates for the physical detection blind spot of the single-direction constant voltage test in the face of asymmetric semiconductor manufacturing defects, ensuring that no matter which physical direction the channel leakage biases, it can be excited by the voltage difference, and improving the leakage defect screening process of the memory chip.

[0079] In a possible implementation manner of the above embodiment, the target storage array includes multiple memory regions sharing a sense amplifier, and the method further includes a full-array scanning step: according to a preset address order, cyclically update the physical addresses of the first word line and the second word line, and perform step-by-step switching in multiple memory regions until full-coverage leakage detection of the target storage array is completed.

[0080] In this embodiment, in an array architecture with multiple memory regions, effective coverage of the chip can be achieved by translating and stepping the test window along the physical layout direction.

[0081] Specifically, after completing the forward and reverse tests on the currently selected memory area, the physical addresses of the first word line and the second word line can be automatically cyclically updated according to the preset address order, the test target can be translated and switched to the next memory area, and step-by-step scanning can be performed along the arrangement rule of the SA.

[0082] It can be understood that this area step-by-step cyclic traversal mechanism ensures that no matter how large the physical scale of the DRAM array is, the test stress can cover all storage units of the entire chip without dead ends in the form of block concurrency.

[0083] In the method and device for detecting leakage current of the transistor channel of the DRAM storage unit in the above embodiments of the present disclosure, by introducing the full-array address cycle and area step-by-step scanning mechanism, the local differential concurrent pressure application technology is seamlessly extended to the macroscopic chip-level mass production test process. This mechanism not only provides specific excitation means for a single weak leakage current defect, but also provides a complete, structured, and directly dockable full-chip coverage scanning logic for automated test equipment. While maximizing the interception rate of edge leakage current defects, through the coordinated cooperation of high concurrency and non-rewriting, the overall screening test time of the full chip is significantly shortened.

[0084] In one embodiment, please refer to Figure 5 , Figure 5 which is a schematic flowchart of another method for detecting leakage current of the transistor channel of the DRAM storage unit provided by the embodiment of the present disclosure. As Figure 5 shown, this process includes the following steps: Step S501, in two memory areas sharing the SA, write logic 1 to the target test row (i.e., the first word line) in the first memory area, and write logic 0 to the remaining background test rows (i.e., the second word line); write logic 0 to the target test row in the second memory area, and write logic 1 to the remaining background test rows.

[0085] Specifically, the first memory area is connected to the same-side bit lines of the SA, and the second memory area is connected to the complementary bit lines on the other side of the SA. Through the write operation, a data pattern with logic 1 stored in the target row and logic 0 stored in the background row is constructed in the first memory area; a data pattern with logic 0 stored in the target row and logic 1 stored in the background row is constructed in the second memory area.

[0086] Step S502, activate the target test row storing logic 1 in the first memory area.

[0087] Specifically, activate this target test row and enable the SA. After the SA senses the logic 1 signal on the same-side bit lines, drive the same-side bit lines to the highest working potential VDD, and synchronously drive the complementary bit lines to the lowest working potential VSS.

[0088] Step S503: Keep the target test row in the first memory area activated within the preset static time T.

[0089] Specifically, within the static time T, the sense amplifier maintains a bias environment where the same side bit line is at VDD and the complementary bit line is at VSS. At this time, for the background test rows with logic 0 stored in the first memory area, the drain of the access transistor is at VDD and the source is at VSS, bearing the full voltage drop Vds; for the background test rows with logic 1 stored in the second memory area, the drain of the access transistor is at VSS and the source is at VDD, bearing the reverse full voltage drop Vds, and two-way stress is applied to the background cells in the memory areas on both sides of the sense amplifier concurrently.

[0090] Step S504: After the static time T ends, turn off the target test row with logic 1 stored in the first memory area.

[0091] Specifically, issue a precharge command PRE to disconnect the target test row in the first memory area, end the stress application process in the first stage, and restore the potentials of the same side bit line and the complementary bit line to the balanced reference potential VDD / 2, excluding the interference of the remaining extreme test potentials on the subsequent processes.

[0092] Step S505: Perform a full-chip refresh operation on the target memory array.

[0093] Specifically, due to the relatively long static time T, by performing a full-chip refresh operation, it is possible to effectively prevent data loss of the storage cells on the background test rows that did not participate in this active excitation and the target test rows in the second memory area due to natural charge leakage, and maintain the integrity of the test pattern.

[0094] Step S506: Activate the target test row with logic 0 stored in the second memory area.

[0095] Specifically, activate this target test row and enable the SA again. After the SA senses the logic 0 signal on the complementary bit line, drive the complementary bit line to VSS and synchronously drive the same side bit line to VDD.

[0096] Step S507: Keep the target test row in the second memory area activated within the preset static time T.

[0097] Specifically, within the static time T, the SA maintains a bias environment where the complementary bit line is at VSS and the same side bit line is at VDD. The access transistor at both ends of the background test row with logic 0 stored in the first memory area bears the reverse full voltage drop Vds; the access transistor at both ends of the background test row with logic 1 stored in the second memory area bears the forward full voltage drop Vds, and stress is applied to the background cells in the memory areas on both sides again.

[0098] Step S508, after the static time T ends, close the target test line storing logic 0 in the second memory area.

[0099] Specifically, issue a precharge command PRE to disconnect the target test line of the second memory area, end the pressure application process of the second stage, and restore the same side bit line and complementary bit line to the balanced potential VDD / 2.

[0100] Step S509, perform a full-chip refresh operation on the target storage array again.

[0101] Specifically, through the full-chip refresh operation, maintain the data state in the background test line to provide an accurate basis for subsequent read verification.

[0102] Step S510, read the data of the background test line storing logic 0 in the first memory area and the background test line storing logic 1 in the second memory area to determine whether there is a leakage failure.

[0103] Specifically, sequentially activate the background test lines of the first memory area and the second memory area, and read the data of the capacitors storing logic 0 in the first memory area and the capacitors storing logic 1 in the second memory area. Logically compare the read data with the initially written data. If the read data is flipped, it is determined that there is a leakage failure in the corresponding transistor channel.

[0104] Step S511, determine whether all memory areas in the target storage array have completed testing; if so, end the process; if not, go to step S512 for test area stepping switching and then return to execute step S501.

[0105] Specifically, in an array architecture with multiple memory areas, translate and step the test window along the physical layout direction. Update the original second memory area as the first memory area in the next test cycle, and use the adjacent memory area sharing the next SA with this area as the second memory area in the next test cycle. Enter the next test cycle through stepping switching until all memory areas in the target storage array are covered.

[0106] Step S512, perform test area stepping switching.

[0107] Specifically, perform test area stepping switching and circularly update the physical addresses corresponding to the first word line and the second word line.

[0108] In one embodiment, please refer to Figure 6 , Figure 6 is a schematic structural diagram of a leakage detection device for a DRAM memory cell transistor channel provided by an embodiment of the present disclosure. As Figure 6 所示,装置可以包括: shown, the device may include: A data writing module 61 is configured to write first-level data to a first storage cell connected to a first word line in a target storage array, and write second-level data to a second storage cell connected to a second word line. The first-level data and the second-level data are logically opposite, and both the first storage cell and the second storage cell are connected to the same side bit line of the same sense amplifier. Wherein, both the first storage cell and the second storage cell include an access transistor and a capacitor for storing charge; An activation enabling module 62 is configured to activate the first word line and enable the sense amplifier to drive the potential of the same side bit line to a target potential corresponding to the first-level data, and synchronously drive the complementary bit line on the other side of the sense amplifier to a reference potential opposite to the target potential; An active holding module 63 is configured to keep the first word line in an active state, the sense amplifier in an enabled state, and keep the second word line in an inactive state within a preset static time, so as to keep the access transistor of the second storage cell closed, and continuously build a leakage test voltage difference between the source and drain of the access transistor of the second storage cell; A leakage detection module 64 is configured to, after the static time ends, turn off the first word line, read the data of the second storage cell, and determine whether there is leakage between the source and drain of the access transistor of the second storage cell according to the read data.

[0109] In one embodiment, the first-level data is a high level, the second-level data is a low level, the target potential is the highest operating potential of the sense amplifier, and the reference potential is the lowest operating potential of the sense amplifier; or, The first-level data is a low level, the second-level data is a high level, the target potential is the lowest operating potential of the sense amplifier, and the reference potential is the highest operating potential of the sense amplifier.

[0110] In one embodiment, the first word line is a single target test row in the target storage array, and the second word line includes multiple background test rows other than the first word line that are connected to the same side bit line; The data writing module 61 is specifically configured to globally write the first-level data to the storage cells connected to the target test row, and globally write the second-level data to the storage cells connected to each background test row, so as to construct an asymmetric data background pattern for leakage testing in the target storage array.

[0111] In one embodiment, the leakage detection module 64 is specifically configured to send a precharge command to turn off the first word line and restore the balance potential of the same side bit line and its complementary bit line; Perform a refresh operation on the target storage array; Send a row activation command for the second word line to turn on the access transistor of the second storage cell; Send a read instruction to extract and output the data of the second storage unit through a sense amplifier.

[0112] In one embodiment, the leakage detection module 64 is further configured to logically compare the data of the second storage unit read with the second-level data initially written. If the read data flips from the second-level data to the first-level data, it is determined that there is a leakage failure between the source and drain of the access transistor of the second storage unit.

[0113] In one embodiment, the device further includes a reverse test module, configured to write the second-level data to the first storage unit and write the first-level data to the second storage unit. Activate the first word line and enable the sense amplifier to drive the potential of the same-side bit line to the reverse target potential corresponding to the second-level data, and synchronously drive the complementary bit line on the other side of the sense amplifier to the reverse reference potential opposite to the reverse target potential. During a preset static time, keep the first word line in the activated state, the sense amplifier in the enabled state, and keep the second word line in the non-activated state. After the static time ends, turn off the first word line and read the data of the second storage unit to determine whether there is a leakage between the source and drain of the access transistor of the second storage unit under the reverse voltage difference.

[0114] In one embodiment, the device further includes a full array scan module, configured to cyclically update the physical addresses of the first word line and the second word line in a preset address order and perform step-by-step switching in multiple memory regions until full-coverage leakage detection of the target storage array is completed.

[0115] It should be noted that when the above-described leakage detection device for the DRAM storage unit transistor channel implements the corresponding leakage detection method for the DRAM storage unit transistor channel, only the above division of each program module is used as an example. In actual applications, the above processing can be allocated to different program modules according to needs, that is, the internal structure of the above device is divided into different program modules to complete all or part of the above-described processing. In addition, the device provided in the above embodiment and the corresponding Figure 2 or Figure 5 The embodiments of the method shown belong to the same concept, and the specific implementation process is detailed in the method embodiments, which will not be repeated here.

[0116] [[ID=2二十七]]This disclosure embodiment also provides an electronic device having the above-mentioned Figure 6 leakage detection device for the DRAM storage unit transistor channel shown [[ID=3三十一]]

[0117] Figure 7 is a schematic structural diagram of an electronic device according to an embodiment of the present disclosure.

[0118] Specifically referring to Figure 7 , which shows a schematic structural diagram of an electronic device suitable for implementing the electronic device in the embodiments of the present disclosure. The electronic device may include a processor (such as a central processing unit, a graphics processing unit, etc.) 701, which can perform various appropriate actions and processes according to the program stored in the read-only memory (ROM) 702 or the program loaded from the memory 708 into the random access memory (RAM) 703. In the RAM 703, various programs and data required for the operation of the electronic device are also stored. The processor 701, the ROM 702, and the RAM 703 are connected to each other through a bus 704. The input / output (I / O) interface 705 is also connected to the bus 704.

[0119] Generally, the following devices may be connected to the I / O interface 705: an input device 706 including, for example, a touch screen, a touchpad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 707 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a memory 708 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 709. The communication device 709 can allow the electronic device to communicate with other devices wirelessly or wiredly to exchange data. Although Figure 7 shows an electronic device having various devices, it should be understood that it is not required to implement or have all the shown devices, and alternatively, more or fewer devices may be implemented or had. <00003​​​​​​​​Embodiments of the present disclosure also provide a computer-readable storage medium. The methods according to the embodiments of the present disclosure can be implemented in hardware, firmware, or be implemented as computer code that can be recorded on a storage medium, or be implemented as computer code that is originally stored in a remote storage medium or a non-transitory machine-readable storage medium and downloaded through a network and will be stored in a local storage medium, so that the methods described herein can be processed by such software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only memory, a random access memory, a flash memory, a hard disk, or a solid-state drive, etc.; further, the storage medium can also include a combination of the above-mentioned types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by the computer, the processor, or the hardware, the leakage detection method of the DRAM memory cell transistor channel shown in the above embodiments is implemented.

[0123] A part of the present disclosure can be applied as a computer program product, for example, computer program instructions. When executed by a computer, through the operation of the computer, the methods and / or technical solutions according to the present disclosure can be invoked or provided. Those skilled in the art should understand that the forms of existence of computer program instructions in a computer-readable medium include, but are not limited to, source files, executable files, installation package files, etc. Correspondingly, the ways in which computer program instructions are executed by a computer include, but are not limited to: the computer directly executes the instructions, or the computer compiles the instructions and then executes the corresponding compiled program, or the computer reads and executes the instructions, or the computer reads and installs the instructions and then executes the corresponding installed program. Here, the computer-readable medium can be any available computer-readable storage medium or communication medium accessible to the computer.

[0124] Although the embodiments of the present disclosure have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the present disclosure, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A method for detecting leakage current in the transistor channel of a DRAM memory cell, characterized in that, The method includes: A first-level data is written to a first memory cell connected to a first word line in the target memory array, and a second-level data is written to a second memory cell connected to a second word line. The first-level data and the second-level data are logically opposite, and both the first and second memory cells are connected to the same bit line on the same side of the same sense amplifier. Both the first and second memory cells include access transistors and capacitors for storing charge. The first word line is a single target test line in the target memory array, and the second word line includes multiple background test lines (excluding the first word line) connected to the same bit line on the same side. The first word line is activated and the sense amplifier is enabled to drive the potential of the bit line on the same side to the target potential corresponding to the first level data, and simultaneously drive the complementary bit line on the other side of the sense amplifier to a reference potential opposite to the target potential. During a preset rest period, the first word line is kept in an active state, the readout amplifier is kept in an enabled state, and the second word line is kept in an inactive state, so that the access transistor of the second memory cell remains off, and a leakage test voltage difference is continuously built between the source and drain of the access transistor of the second memory cell. After the resting time ends, the first word line is turned off, the data of the second memory cell is read, and it is determined whether there is leakage between the source and drain of the access transistor of the second memory cell based on the read data.

2. The method according to claim 1, characterized in that, The first level data is high, the second level data is low, the target potential is the highest operating potential of the sense amplifier, and the reference potential is the lowest operating potential of the sense amplifier; or, The first level data is low, the second level data is high, the target potential is the lowest operating potential of the sense amplifier, and the reference potential is the highest operating potential of the sense amplifier.

3. The method according to claim 1, characterized in that, After the settling time ends, closing the first word line and reading the data from the second storage unit includes: Send a precharge command to shut down the first word line and restore the same-side bit line and its complementary bit line to a balanced potential; Perform a refresh operation on the target storage array; Send a row activation instruction to the second word line to turn on the access transistor of the second memory cell; A read command is sent to extract and output the data of the second storage unit through the read amplifier.

4. The method according to claim 1, characterized in that, The step of determining whether there is leakage between the source and drain of the access transistor of the second memory cell based on the read data includes: The data read from the second storage unit is logically compared with the initially written second level data; If the read data is flipped from the second level data to the first level data, it is determined that there is a leakage failure between the source and drain of the access transistor of the second memory cell.

5. The method according to any one of claims 1-4, characterized in that, The method further includes a reverse testing step that interchanges the polarity of the test pressure difference, the reverse testing step including: Write the second level data to the first storage unit, and write the first level data to the second storage unit; The first word line is activated and the sense amplifier is enabled to drive the potential of the bit line on the same side to the inverse target potential corresponding to the second level data, and simultaneously drive the complementary bit line on the other side of the sense amplifier to the inverse reference potential opposite to the inverse target potential. During the preset rest period, the first word line is kept in the active state, the readout amplifier is kept in the enabled state, and the second word line is kept in the inactive state. After the settling time ends, the first word line is turned off, and the data of the second memory cell is read to determine whether there is leakage between the source and drain of the access transistor of the second memory cell under reverse voltage difference.

6. The method according to claim 5, characterized in that, The target memory array includes multiple memory regions sharing a sense amplifier, and the method further includes a full array scan step: The physical addresses of the first word line and the second word line are updated cyclically according to a preset address order, and step switching is performed in multiple memory regions until the full coverage leakage detection of the target storage array is completed.

7. A leakage current detection device for a transistor channel of a DRAM memory cell, characterized in that, The device includes: A data writing module is used to write first-level data to a first memory cell connected to a first word line in a target memory array, and to write second-level data to a second memory cell connected to a second word line. The first-level data and the second-level data are logically opposite, and the first memory cell and the second memory cell are both connected to the same bit line on the same side of the same sense amplifier. Both the first memory cell and the second memory cell include access transistors and capacitors for storing charge. The first word line is a single target test line in the target memory array, and the second word line includes multiple background test lines other than the first word line connected to the same bit line on the same side. The activation enable module is used to activate the first word line and enable the sense amplifier to drive the potential of the bit line on the same side to the target potential corresponding to the first level data, and simultaneously drive the complementary bit line on the other side of the sense amplifier to a reference potential opposite to the target potential. An active hold module is used to keep the first word line in an active state, the sense amplifier in an enabled state, and the second word line in an inactive state for a preset rest period of time, so as to keep the access transistor of the second memory cell off and continuously build a leakage test voltage difference between the source and drain of the access transistor of the second memory cell. The leakage current detection module is used to shut down the first word line after the resting time ends, read the data of the second memory cell, and determine whether there is leakage current between the source and drain of the access transistor of the second memory cell based on the read data.

8. An electronic device, characterized in that, include: A memory and a processor are communicatively connected, the memory stores computer instructions, and the processor executes the computer instructions to perform the leakage current detection method for the transistor channel of a DRAM memory cell according to any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions for causing a computer to execute the leakage current detection method for the DRAM memory cell transistor channel according to any one of claims 1-6.

10. A computer program product, characterized in that, Includes computer instructions for causing a computer to execute the leakage current detection method for the transistor channel of a DRAM memory cell according to any one of claims 1-6.

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