Semiconductor device and its corresponding method

Abstract

Embodiments of the present disclosure relate to a semiconductor device and its corresponding method. A semiconductor die is mounted in a die area of a ball grid array package comprising an array of electrically conductive solder balls. A power supply channel conveys a power supply current to the semiconductor die. The power supply channel is formed by an electrically conductive connection plane layer extending in a longitudinal direction between a distal end at a package periphery and a proximal end at the die area. The electrically conductive solder balls are distributed along the longitudinal direction. The electrically conductive connection plane layer comprises successive portions between adjacent distributed electrically conductive solder balls in the longitudinal direction. The respective electrical resistance values of the successive portions monotonically decrease from the distal end to the proximal end. This contributes to a uniform distribution of the power supply current over the length of the power supply channel.

Description

[0001] Priority Claim

[0002] This application claims the priority benefit of Italian Patent Application No. 102020000029210, filed on December 1, 2020, the contents of which are incorporated herein in their entirety to the maximum extent permitted by law. TECHNICAL FIELD

[0003] The present description relates to semiconductor devices.

[0004] One or more embodiments can apply to semiconductor devices comprising a ball grid array (BGA) package.

[0005] One or more embodiments can apply to high power BGA package designs in wire bonding and flip chip configurations. BACKGROUND

[0006] Increasingly stringent current regulatory specifications apply to high-end digital products, which can lead to various problems at the package and printed circuit board (PCB) level.

[0007] In order to facilitate the distribution of power (current) from external peripheral devices to internal power balls located directly below the semiconductor chip or die in the center of the ball grid array (BGA) substrate, so-called power channel structures can be employed.

[0008] It is noted that at the package level, certain balls in the array can be traversed by excessive current, which can lead to electromigration problems. That is, the current tends to flow through the outermost balls, which are close to the voltage regulator, thus creating a serious bottleneck. The uniform connection plane layer reduces the maximum acceptable current, since the current is not uniformly distributed over the ball surface.

[0009] There is a need in the art to help overcome the above-mentioned drawbacks. SUMMARY

[0010] One or more embodiments can relate to semiconductor devices.

[0011] One or more embodiments can relate to corresponding methods.

[0012] One or more embodiments can provide an improved solution at the package level, which helps to obtain a uniform current distribution.

[0013] One or more embodiments provide a power channel connection plane layer, which results in a more uniform current distribution over the ball grid array (BGA) power channel balls.

[0014] One or more embodiments can relate to a controlled variation of the electrical resistance from different balls to the die.

[0015] In one or more embodiments, the current can be modulated, thereby creating a specific incremental aperture (void) on the power channel connection plane.

[0016] In one or more embodiments, this can involve creating a void in the plane layer by gradually reducing the size from the edge of the package to the center. The position of the void relative to each solder ball column can be designed to make the structure replicable for multiple solder ball rows (more than two).

[0017] In one or more embodiments, such a structure can be replicated on each power connection plane layer by adhering to regular substrate design rules (e.g., avoiding overlapping voids in vertically adjacent layers).

[0018] Accordingly, one or more embodiments can adjust according to the optimal number of rows of solder balls to include in the power channel of the package (which can depend on factors such as the current consumption of the die, the power solder ball budget of the package, and the substrate stack).

[0019] In one or more embodiments, the local current density can be reduced.

[0020] In one or more embodiments, the more uniform current distribution between the solder balls helps to reduce the number of solder balls involved in providing a certain amount of power. This in turn helps to reduce the package size as well as the substrate stack, which is beneficial in terms of overall package cost.

[0021] One or more embodiments can be implemented at the device level, for example as a BGA package including power channel connection planes for connecting rows of power channel balls, providing a decreasing value of resistance path from the periphery to the center between adjacent power channel solder ball rows, having different cross sections along the current propagation path.

[0022] One or more embodiments can provide one or more of the following advantages: uniform current distribution over the BGA power channel solder balls; embodiments can be applied to single and multi-layer connection plane layer configurations as well as any standard substrate stack and material; no additional manufacturing and assembly processes are involved; and various different available implementations. BRIEF DESCRIPTION OF DRAWINGS

[0023] One or more embodiments will now be described, by way of example only, with reference to the accompanying drawings:

[0024] Figure 1 is a plan view of an exemplary ball grid array (BGA) package according to possible use contexts of embodiments of the present description;

[0025] Figure 2 is a plan view of a conventional power channel as can be included in a BGA package; Figure 1 is a plan view of a conventional power channel as can be included in a BGA package;

[0026] Figure 3 is a circuit diagram illustrating the operation of a power channel as Figure 2

[0027] Figure 4 is a plan view of a power channel according to embodiments herein, which can be included in a BGA package as Figure 1

[0028] Figure 5 is a circuit diagram illustrating the operation of a power channel as Figure 4

[0029] Figure 6 is a detailed view of a part of a possible implementation of a power channel as Figure 4

[0030] Figures 7 to 9 is a plan view of a power channel according to the present description;

[0031] Figure 10 is a plan view of a power channel according to the present description, which can be included in a BGA package as Figure 1

[0032] Figures 11 to 13 is a plan view of a power channel according to the present description;

[0033] Figures 14 to 17 is a detailed view of a part of a power channel according to the present description. DETAILED DESCRIPTION

[0034] In the following description, one or more specific details are described to provide an example embodiment of the description. One or more of the embodiments can also be used in other implementations not specifically described herein. In other instances, well-known structures, materials, or operations are not shown or described in detail in order to avoid obscuring aspects of the embodiments.

[0035] Reference throughout this description to "embodiment" or "one embodiment" is intended to indicate that a particular configuration, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. The appearances of the phrases "in one embodiment" or "in an embodiment" in various places in the specification are not necessarily all referring to one and the same embodiment.

[0036] Furthermore, the particular configurations, structures, or characteristics can be combined in any suitable manner in one or more embodiments.

[0037] The headings / reference used herein are provided for convenience only and therefore do not define the scope of protection or the scope of the embodiments. ​​​​​

[0038] Throughout the drawings, like reference numerals will be used to refer to like or similar items or elements throughout the drawing(s) and the detailed description, making connections between drawings and detailed description self-evident, wherein the similar elements will not be described again in great detail in order to avoid obscuring the present described embodiments.

[0039] Figure 1 is an exemplary plan view from the rear or bottom surface of a conventional ball grid array (BGA) of a semiconductor device package 10, which includes an array of ball contacts or "solder balls" 12. The solder balls provide electrical connections for a semiconductor chip or die 14 (whose outline is shown in dashed lines in Figure 1 ) that is attached in a die area facing the top or front side of the semiconductor device package 10.

[0040] The array of solder balls is intended to facilitate mounting of the semiconductor device package 10 onto a substrate (e.g. Figure 3 and Figure 5 a printed circuit board (PCB), discussed below). A power supply for the semiconductor chip or die in the semiconductor device package 10 can be provided via a voltage regulator VR (possibly located on the PCB) with current CF flowing from the periphery of the semiconductor device package 10 to a subset of the BGA solder balls located underneath the die area (i.e., the area where the semiconductor chip or die 14 is mounted).

[0041] A so-called power channel 16 can be employed to facilitate current flow from the periphery of the semiconductor device package 10 to the "power" solder balls 122. As shown in Figure 2 , the power channel 16 includes a subset of the solder balls 12 that are coupled to a common conductive structure or "power channel connection plane" 12A on the package side, and to a conductive structure on the substrate (PCB) side, which in turn is coupled to a power supply (voltage regulator) VR that provides the current CF.

[0042] This arrangement is otherwise conventional in the art, and thus need not be described in greater detail herein.

[0043] It is noted that the current CF tends to flow (mostly) through the "outermost" solder balls in the power channel 16, as shown in 162 in Figure 1 , which are closer to the voltage regulator VR, thus creating a severe bottleneck.

[0044] By referring to Figure 2 and Figure 3 , the mechanism behind this (undesirable) phenomenon can be understood.

[0045] Figure 2Basically an enlarged view of the power channel 16, which, by way of example, comprises two parallel rows or columns, each row or column consisting of 8 solder balls (arranged in 8 pairs, numbered from 1 to 8), electrically coupled with the power channel connection plane 12A of uniform width.

[0046] Figure 3 is a representation of the respective circuit of the power channel 16 for coupling the die area (more precisely, the semiconductor chip or die 14 mounted thereon) to the voltage regulator VR.

[0047] In Figure 3 : the resistance Rpcb_layer is an example of the resistance of the conductive structure or track extending between adjacent pairs of solder balls 12 of the top or front surface of the substrate S (on which the semiconductor device package 10 is mounted by means of the solder balls 12 (RGB solder balls)); the resistance Rball is an example of the resistance of the solder balls 12 (RGB solder balls) of the power channel 16, which are located between the top or front surface of the PCB and the bottom (Z axis) of the back surface of the semiconductor device package 10; and the resistance Rshape is an example of the resistance of the portion of the power channel connection plane 12A between adjacent pairs of solder balls 12 of the power channel 16.

[0048] Even without specific calculations, it can be noted that, in the case where all Rshape (and Rpcb_layer) values are equal, the current CF will tend to follow the shortest path (with the lowest resistance value), which is basically through the "outermost" solder balls 162, i.e. the solder balls 12 closest to the voltage regulator VR (on the right of the circuit diagram of Figure 2 and Figure 3 ).

[0049] One or more embodiments basically rely on the concept of making this shortest path (or, more generally, the shorter paths close to the voltage regulator VR) more resistive, in order to redistribute the current CF more evenly over all the solder balls 182 of the power channel 16.

[0050] As will be described below, this can be done without any changes at the PCB level (i.e. keeping the value of Rpcb_layer unchanged).

[0051] Figure 4 (more importantly, compared to the circuit diagram of Figure 3 , Figure 5The circuit diagram) shows that the current CF can be more evenly (uniformly) distributed across the various paths through the solder balls 12 in the power channel 16, avoiding undesirable congestion of the "peripheral" solder balls 12, by selecting Rshape_8 < Rshape_7 < Rshape_6 < Rshape_5 < Rshape_4 < Rshape_3 < Rshape_2 < Rshape_1 as indicated 162, where Rshape_j (in the example shown j = 1 to 8) represents the resistance value of the portion of the power channel connection plane 12A between two adjacent pairs of solder balls 12 in the power channel 16.

[0052] In this way, the current CF will be distributed in a more uniform manner rather than flowing mainly (if not exclusively) through the solder balls 162 (the solder balls 12 closest to the package periphery in the power channel 16), so that each pair of solder balls 12 in the power channel 16, including the pairs closest to the power solder balls 122 and the semiconductor chip or die 14 area, will carry a more evenly distributed portion of the current CF (some exemplary percentage values will be discussed below).

[0053] By direct comparison with Figure 2 it is shown that such a result can be obtained, for example, by varying the width of the power channel connection plane 12A such that the width is narrowest at the "peripheral" solder balls 12 and gradually increases towards the "inner" solder balls in the power channel 16, i.e., the solder balls closest to the power solder balls 122 and the semiconductor chip or die 14 area.

[0054] Additionally, as Figure 4 shown, the power channel connection plane 12A呈现出从半导体器件封装10的外围到中心部分的扩口形状(从右到左),以及从半导体器件封装10的中心部分到外围的锥形形状(从左到右)。呈现出从半导体器件封装10的外围到中心部分的扩口形状(从右到左),以及从半导体器件封装10的中心部分到外围的锥形形状(从左到右)。The power channel connection plane 12A呈现出从半导体器件封装10的外围到中心部分的扩口形状(从右到左),以及从半导体器件封装10的中心部分到外围的锥形形状(从左到右)。The power channel connection plane 12A呈现出从半导体器件封装10的外围到中心部分的扩口形状(从右到左),以及从半导体器件封装10的中心部分到外围的锥形形状(从左到右)。The power channel connection plane 12A呈现出从半导体器件封装10的外围到中心部分的扩口形状(从右到左),以及从半导体器件封装10的中心部分到外围的锥形形状(从左到右)。The power channel connection plane 12A呈现出从半导体器件封装10的外围到中心部分的扩口形状(从右到左),以及从半导体器件封装10的中心部分到外围的锥形形状(从左到右)。The power channel connection plane 12A呈现出从半导体器件封装10的外围到中心部分的扩口形状(从右到左),以及从半导体器件封装10的中心部分到外围的锥形形状(从左到右)。The power channel connection plane 12A呈现出从半导体器件封装10的外围到中心部分的扩口形状(从右到左),以及从半导体器件封装10的中心部分到外围的锥形形状(从左到右)。The power channel connection plane 12A呈现出从半导体器件封装10的外围到中心部分的扩口形状(从右到左),以及从半导体器件封装10的中心部分到外围的锥形形状(从左到右)。The power channel connection plane 12A呈现出从半导体器件封装10的外围到中心部分的扩口形状(从右到左),以及从半导体器件封装10的中心部分到外围的锥形形状(从左到右)。The power channel connection plane 12A呈现出从半导体器件封装10的外围到中心部分的扩口形状(从右到左),以及从半导体器件封装10的中心部分到外围的锥形形状(从左到右)。The power channel connection plane 12A呈现出从半导体器件封装10的外围到中心部分的扩口形状(从右到左),以及从半导体器件封装10的中心部分到外围的锥形形状(从左到右)。The power channel connection plane 12A呈现出从半导体器件封装10的外围到中心部分的扩口形状(从右到左),以及从半导体器件封装10的中心部分到外围의锥形形状(从左到右)。The power channel connection plane 12A呈现出从半导体器件封装10的外围到中心部分的扩口形状(从右到左),以及从半导体器件封装10的中心部分到外围의锥形形状(从左到右)。The power channel connection plane is shown to have a flared shape (from right to left) from the periphery to the central portion of the semiconductor device package 10 and a tapered shape (from left to right) from the central portion to the periphery of the semiconductor device package 10.

[0055] Those skilled in the art will note that the resistance of a conductor is inversely proportional to its cross-sectional area and directly proportional to its length.

[0056] Figure 6 shows two adjacent pairs of solder balls 12 in the power channel 16 and illustrates the possibility of obtaining Rshape_j < Rshape_j - 1 by simultaneously inserting these two solder balls in terms of the width W (and cross-sectional area) and the length L of the portion of the power channel connection plane 12A between the jth pair of solder balls 12 in the power channel 16, where in the example shown, j = 1 to 8.

[0057] It seems there is some repeated and incorrect text in the original for item . I've translated it as best as possible with the correct content I could extract. Please check and correct if needed.​That is, the desired resistance value (“modulation”) can be obtained by changing (narrowing or widening) the width W of a portion of the power channel 16 and changing the length L of the narrowed / widened portion.

[0058] Please also note that, for ease of explanation and understanding, Figures 2 to 6 The representation in

[0059] In fact, while these representations involve a single conductive connection plane layer on the PCB and a single conductive connection plane layer on the package, one or more embodiments can envision a plurality of connection plane layers connected together in the Z direction by, for example, vias, as shown in Figures 7 to 17 “dot” shown.

[0060] In this case, the various connection plane layers involved can be modified as described below to obtain a gradually changing resistance between the solder balls, as described below.

[0061] As mentioned previously, the exemplary embodiments presented herein contemplate modifications in the semiconductor device package 10 (power channel connection plane 12A; resistance value Rshape_j). As described below, this can be done without changing the substrate S (e.g., PCB) level, i.e., keeping Rpcb_layer constant.

[0062] Figure 7 , Figure 8 and Figure 9 illustrate how the concept of providing voids on a power channel connection plane 12A of a power channel such as 16 (known per se) can be applied to embodiments as shown herein.

[0063] As a standard substrate manufacturing process, a portion of metal can be removed from the conductor layer in the power channel connection plane 12A, thereby creating a void on such connection plane layer.

[0064] Such voids help to avoid delamination issues. For example, every 25 mm 2 At least one void helps with adhesion of the base layer. Typically, voids on adjacent layers are avoided from overlapping.

[0065] On a power channel 16 as shown herein, such voids designated 18 in Figure 7 , 8 and 9 can have different shapes, be located at different positions, and have different numbers.

[0066] For example, as shown in Figure 7 , 8 and 9, the voids 18 can be elongated in shape and can also be located at the side of the power channel connection plane 12A (i.e., form a notch or indentation at the side of the power channel connection plane 12A).

[0067] As highlighted (for simplicity, only in Figure 7 ), the length L, L' of the void 18 can be varied as needed to change the width W of the power channel 16 (see Figure 6 ).

[0068] The above is in other respects in line with the standard criteria for providing a void 18.

[0069] For example, for low-medium currents, a simple design and medium void width is compatible with open / complete voids, i.e. voids completely surrounded by conductive material of the metal connection plane layer (so-called “complete” voids: see upper voids in Figure 7 , 8 and 9) and voids extending to the border of the connection plane layer (so-called “open” voids: see lower voids in Figure 7 , 8 and 9).

[0070] With regard to positioning, the voids envisaged herein can be formed so that the voids on adjacent layers have an offset.

[0071] Standard processes, such as (copper) etching, full subtractive or semi-additive and full additive methods, can be used to produce voids (in the shape of slots) 18 of controlled length L, L',... as needed.

[0072] In this regard, Figure 7 exemplary plan views are provided of “complete” power channels 16 (bottom metal layer plus top layer), Figure 8 and Figure 9 illustrating the upper (internal) layer and the bottom metal layer, respectively.

[0073] As mentioned previously, one or more embodiments can also be applied to multiple connection plane layers, possibly including more than two layers.

[0074] Figure 7 , 8 and 9 are merely examples of such multi-layer structures, the aim being to illustrate how the voids can be moved when the layers are adjacent to avoid overlapping.

[0075] Figure 4 Embodiments in which the power channel 16 comprises two rows of solder balls 12 can advantageously (only) use the “open void” option (see again lower voids in Figure 7 , 8 and 9), since this helps to avoid bottlenecks at the power plane border.

[0076] Figure 10 is an example of the extension of the above concept to the possibility of including multiple rows of power channels 16 comprising two rows or more than two rows of solder balls 12.

[0077] For simplicity, in Figure 10 the figures, only the solder ball locations (not the solder balls themselves) are indicated by dashed lines and are indicated by reference numeral 12'.

[0078] Figure 10 The illustrated power via 16 includes four rows or columns of solder balls 12 with voids 18 defining three (substantially parallel) conductive branches that (all) exhibit a flared shape (from right to left) from the periphery to the center portion of the semiconductor device package 10 and a tapered shape (from left to right) from the center portion to the periphery of the semiconductor device package 10.

[0079] As Figure 10 illustrated, the power via structure can be replicated (in a manner known to those skilled in the art) by void offsets on multiple power layers.

[0080] Due to the void locations in the inner via rows, the structure can also be replicated in the XY plane. In the presence of voids centered on the solder balls, the complete layout of one via row can be replicated on a number n of rows, which facilitates regular structures and design processes.

[0081] As Figure 10 illustrated, the three conductive branches in the power via 16 can be defined by four rows of voids 18 having different lengths to provide a desired variation in branch width, i.e. Figure 10 the power via connection plane 12A in has a "higher resistance" on the right side of the figure (the periphery of the semiconductor device package 10) and a "lower resistance" on the left side of the figure (towards the center of the semiconductor device package 10).

[0082] As Figure 10 illustrated, the four rows of voids 18 can be arranged in three groups, including: a first group, as indicated by reference numeral I, including a row of "open" voids 18 between the upper side of the power via connection plane 12A and the first (uppermost) conductive branch of the power via 16; a second group, as indicated by reference numeral II, including two rows of "full" voids 18, the first row between the first (uppermost) conductive branch of the power via 16 and the second (central) conductive branch of the power via 16, and the second row between the second (central) conductive branch of the power via 16 and the third (lowermost) conductive branch of the power via 16; and a third group, as indicated by reference numeral III, again including a row of "open" voids 18 between the third (lowermost) conductive branch of the power via 16 and the lower side of the power via connection plane 12A.

[0083] Figures 11 to 13As an example of how a larger gap 18 contributes to achieving higher planar (electrical) resistance, the shape of the ground GND overlap on the adjacent layer avoids direct gap overlap.

[0084] in this regard, Figure 11 Again, an exemplary plan view of a "complete" power channel 16 (bottom metal layer plus top layer) is provided. Figure 12 and Figure 13 The top (inner) and bottom metal layers are shown separately. The image shows GND filled void 18 in the “Open void” option.

[0085] Note again here that one or more embodiments may also be applied to multiple planar layers, possibly including more than two layers.

[0086] Figure 7 、 8 The case of two connected planar layers shown in and 9 is merely an example of such a multilayer structure, and its purpose is to illustrate how the gaps can be moved to avoid overlap when the layers are adjacent.

[0087] Figure 14 and Figure 15 (where the solder ball locations are again shown in dashed lines and designated 12') is an example of a larger void 18 that helps increase the (electrical) resistance of the power path connection plane 12A according to current specifications.

[0088] Also note that larger voids 18 may affect the proper copper balance between layers. Figure 15 ) replaces a single larger gap 18 ( Figure 14 ) may help resolve the issue.

[0089] Figure 16 and Figure 17 (where the location of the solder balls is again indicated by dashed lines and 12') is achieved by using a "T" shape ( Figure 16 , center) or "L" shaped ( Figure 16 , center) (possibly at least partially filled with GND material) to avoid large voids 18, thereby not occupying most of the surface of the power channel connection plane 12A and also being able to provide high resistance values.

[0090] Figure 17 (Right side) illustrates the possibility of increasing (e.g., by defining gaps 18 between the S-shaped portions of the power path connection plane 12A) the total length L of the narrow portion of the power path connection plane 12A between two adjacent solder balls 12 without affecting the width W. This may contribute to higher resistance without creating a significant bottleneck on the power path connection plane 12A.

[0091] Figure 2 and Figure 3 the arrangement of FIG. 1 1 (power channel connection plane 12A of uniform width / resistance) compared to the arrangement of FIG. 10 (power channel connection plane 12A of varying width) indicates the following: Figure 4 Figure 5 the arrangement of FIG. 1 1 (power channel connection plane 12A of uniform width / resistance) compared to the arrangement of FIG. 10 (power channel connection plane 12A of varying width) indicates the following:

[0092] In the arrangement as shown in FIG. 1 1, the current through the "first" pair of solder balls 162, closest to the package periphery, is approximately 8.7% of the total current (e.g. 6A), and the current through the other pairs of solder balls (power balls 122 and area of semiconductor chip or die 14) closer to the package center can be as low as 0.3% of the total current; this indicates a significantly non-uniform distribution of current CF, with the majority of current flow through the solder balls closest to the package periphery; and Figure 2 Figure 3 In the arrangement as shown in FIG. 1 1, the current through the "first" pair of solder balls 162, closest to the package periphery, is approximately 8.7% of the total current (e.g. 6A), and the current through the other pairs of solder balls (power balls 122 and area of semiconductor chip or die 14) closer to the package center can be as low as 0.3% of the total current; this indicates a significantly non-uniform distribution of current CF, with the majority of current flow through the solder balls closest to the package periphery; and

[0093] In the arrangement as shown in FIG. 1 1, the current through the "first" pair of solder balls 162, closest to the package periphery, is approximately 8.7% of the total current (e.g. 6A), and the current through the other pairs of solder balls (power balls 122 and area of semiconductor chip or die 14) closer to the package center can be as low as 0.3% of the total current; this indicates a significantly non-uniform distribution of current CF, with the majority of current flow through the solder balls closest to the package periphery; and Figure 4 Figure 5 In the arrangement as shown in FIG. 1 1, the current through the "first" pair of solder balls 162, closest to the package periphery, is approximately 8.7% of the total current (e.g. 6A), and the current through the other pairs of solder balls (power balls 122 and area of semiconductor chip or die 14) closer to the package center can be as low as 0.3% of the total current; this indicates a significantly non-uniform distribution of current CF, with the majority of current flow through the solder balls closest to the package periphery; and

[0094] ​​​As exemplified herein, a semiconductor device may include: a semiconductor die (e.g., 14) mounted in a die area of ​​a package (e.g., 10), the semiconductor die having an array of conductive solder balls (e.g., 12) providing electrical contacts for the semiconductor die; a power channel (e.g., 16) for delivering a power current (e.g., CF) to the semiconductor die (e.g., 14), wherein the power channel includes at least one conductive connection plane layer (e.g., 12A) extending in a longitudinal direction of the conductive connection plane layer between a distal end of the package periphery and a proximal end of the package die area (e.g., at power solder balls 122), and a distribution of the conductive solder balls (e.g., 12), the conductive solder balls being distributed along the longitudinal direction of the conductive connection plane layer (e.g., 12A), the (at least one) conductive connection plane layer (e.g., 12A) including a subsequent portion in the distribution between adjacent conductive solder balls in the longitudinal direction, the subsequent portion having a corresponding resistance value, wherein the resistance value decreases monotonically from the distal end to the proximal end of the conductive connection plane layer (e.g., Rshape_8). <Rshape_7<Rshape_6<Rshape_5<Rshape_4<Rshape_3<Rshape_2<Rshape_1)。

[0095] In the semiconductor devices exemplified herein, subsequent portions of the (at least one) electrically conductive connection plane layer have respective widths that increase from the distal end to the proximal end of the (at least one) connection plane layer (see, for example, Figure 6 W in ), and / or a corresponding length decreasing from the distal end to the proximal end of the conductive connection plane layer (for example, see Figure 6 L in ).

[0096] In the semiconductor device as exemplified herein, the distribution of the conductive solder balls in the power channel may include a plurality of rows of conductive solder balls distributed along the longitudinal direction of (at least one) conductive connection plane layer, with the conductive solder balls in adjacent rows (e.g., see Figure 4 or Figure 6 Two rows or two columns of solder balls 12, or Figure 10 The four rows or four columns of solder balls 12) define that (at least one) subsequent portion of the conductive connection plane layer extending in the longitudinal direction therebetween has a corresponding resistance value, wherein the corresponding resistance value decreases (monotonically) from the distal end to the proximal end of the conductive connection plane layer (e.g., 12A).

[0097] In the semiconductor device exemplified herein, the (at least one) conductive connection plane layer may include gaps (e.g., 18) formed between the distributed adjacent conductive solder balls, wherein the gaps define the subsequent portion of the (at least one) conductive connection plane therebetween to have a corresponding resistance value.

[0098] In the semiconductor devices illustrated herein, such voids can include: complete voids contained entirely within (at least one) conductive connection plane layer (i.e., "internal" voids), completely surrounded by power via connection plane 12A: see, e.g., upper void 18 in Figures 7 to 9 , Figure 10 middle-high void 18 in Figure 14 , and Figure 15 voids in Figures 7 to 9 , and / or open voids extending to a side of (at least one) conductive connection plane layer (i.e., "side" voids formed on a side of power via connection plane 12A: see, e.g., lower void 18 in Figure 10 uppermost and lowermost voids 18 in Figures 11 to 13 , and Figure 16 , and Figure 17 voids 18 in .

[0099] In the semiconductor devices illustrated herein, (at least one) conductive connection plane layer can include opposing sides extending along the longitudinal direction, the opposing sides having a complementary distribution of the open voids formed therein (see, e.g., uppermost and lowermost voids 18 in Figure 10 , and Figures 11 to 13 , and Figure 16 , and 17 voids 18 in .

[0100] In the semiconductor devices as shown herein, (at least one) conductive connection plane layer can include at least one distribution of the complete voids extending along the longitudinal direction between the opposing sides having a complementary distribution of the open voids formed therein (see, e.g., two rows of middle-height voids 18 in Figure 10 extending between the uppermost and lowermost voids 18.

[0101] In the semiconductor devices illustrated herein, (at least one) conductive connection plane layer can include: T-shaped or L-shaped voids formed therein (see, e.g., right side of Figure 16 , and / or curved portions extending along the longitudinal direction (see, e.g., S-shaped or serpentine portion of right side power via connection plane 12A in Figure 17 .

[0102] Methods as exemplified herein can include providing electrical contacts for a semiconductor die mounted in a die area of a semiconductor device package in which electrical contacts are provided by an array of electrically conductive solder balls; and delivering power supply current (e.g., CF) to the semiconductor die via a power channel extending in a longitudinal direction between a distal end of a package periphery and a proximal end of a die area of the package, wherein the power channel includes a distribution of electrically conductive solder balls distributed along the longitudinal direction, the power channel includes successive portions extending between adjacent electrically conductive solder balls in the distribution along the longitudinal direction, the successive portions having respective resistance values, wherein the respective resistance values decrease from the distal end of the electrically conductive connection plane layer to the proximal end (e.g., Rshape_8 < Rshape_7 < Rshape_6 < Rshape_5 < Rshape_4 < Rshape_3 < Rshape_2 < Rshape_1).

[0103] Details and embodiments can vary even significantly from what is described by way of example without, however, departing from the basic principles, only within the scope of protection.

[0104] The claims are an integral part of the teaching provided herein about the embodiments.

[0105] The scope of protection is defined by the appended claims.

Claims

1. A semiconductor device comprising: a semiconductor die mounted at a die area of a package, the package having an array of conductive solder balls providing electrical contacts for the semiconductor die; and a power channel for conveying power supply current to the semiconductor die; wherein the power channel comprises: at least one conductive connection plane layer extending in a longitudinal direction of the conductive connection plane layer between a distal end of a periphery of the package and a proximal end of the die area of the package; and a distribution of conductive solder balls arranged to be distributed along the longitudinal direction of the conductive connection plane layer; the conductive connection plane layer comprising subsequent portions in the longitudinal direction between adjacent conductive solder balls in the distribution; wherein the subsequent portions have respective resistance values, wherein the respective resistance values decrease from the distal end to the proximal end of the conductive connection plane layer.

2. The semiconductor device of claim 1, wherein the subsequent portions of the conductive connection plane layer have respective widths that increase from the distal end to the proximal end of the conductive connection plane layer.

3. The semiconductor device of claim 1, wherein the subsequent portions of the conductive connection plane layer have respective lengths that decrease from the distal end to the proximal end of the conductive connection plane layer.

4. The semiconductor device of claim 1, wherein the distribution of conductive solder balls in the power channel comprises a plurality of rows of conductive solder balls distributed along the longitudinal direction of the conductive connection plane layer, with adjacent rows of conductive solder balls defining therebetween subsequent portions of the conductive connection plane layer extending in the longitudinal direction, the subsequent portions having respective resistance values, wherein the respective resistance values decrease from the distal end to the proximal end of the conductive connection plane layer.

5. The semiconductor device of claim 1, wherein the conductive connection plane layer comprises voids formed therein, the voids being between adjacent conductive solder balls in the distribution, wherein the voids define the subsequent portions of the conductive connection plane layer therebetween having respective resistance values.

6. The semiconductor device of claim 5, wherein the voids comprise complete voids entirely contained in the conductive connection plane layer.

7. The semiconductor device of claim 5, wherein the voids comprise open voids extending to a side of the conductive connection plane layer.

8. The semiconductor device of claim 7, wherein the conductive connection plane layer comprises opposing sides extending in the longitudinal direction, the opposing sides having complementary distributions of the open voids formed therein.

9. The semiconductor device of claim 8, wherein the conductive connection plane layer comprises at least one distribution of complete voids entirely contained in the conductive connection plane layer, the conductive connection plane layer extending in the longitudinal direction between the opposing sides in which the complementary distributions of open voids extending to a side of the conductive connection plane are formed. ​ 10. The semiconductor device of claim 5, wherein the electrically conductive land layer includes a T-shaped void formed therein.

11. The semiconductor device of claim 5, wherein the electrically conductive land layer includes an L-shaped void formed therein.

12. The semiconductor device of claim 5, wherein the electrically conductive land layer includes a curved shaped portion extending along the longitudinal direction.

13. A method comprising: providing electrical contact for a semiconductor die mounted at a die area of a semiconductor device package via an array of electrically conductive solder balls; and delivering supply current to the semiconductor die via a power channel extending in a longitudinal direction between a distal end of a periphery of the package and a proximal end of the die area of the package; wherein the power channel includes a distribution of electrically conductive solder balls distributed along the longitudinal direction and mounted to an electrically conductive land layer, the power channel includes a subsequent portion of the electrically conductive land layer extending along the longitudinal direction between adjacent electrically conductive solder balls in the distribution, the subsequent portion having a respective resistance value, wherein the respective resistance value decreases from the distal end to the proximal end of the electrically conductive land layer.

14. A semiconductor device comprising: a semiconductor die mounted at a front side of a package; an array of electrically conductive solder balls mounted at a back side of the package; and a power channel for transferring supply current to the semiconductor die; wherein the power channel includes: an electrically conductive land layer having a length in a longitudinal direction and a width extending perpendicular to the length, the length of the electrically conductive land layer extending from a distal end of a periphery of the package to a proximal end of a die area of the package; and wherein the array of electrically conductive solder balls includes a distribution of electrically conductive solder balls along the longitudinal direction of the electrically conductive land layer; wherein the electrically conductive land layer includes at least one void formed therein, the at least one void between each pair of adjacent electrically conductive solder balls in the distribution in the longitudinal direction, wherein a portion of the electrically conductive land layer between adjacent voids has a resistance value; wherein the respective resistance value of the portion of the electrically conductive land layer decreases from the distal end to the proximal end.

15. The semiconductor device of claim 14, wherein the voids include complete voids entirely contained in the electrically conductive land layer.

16. The semiconductor device of claim 14, wherein the voids include open voids extending to a side of the electrically conductive land layer.

17. The semiconductor device of claim 14, wherein the electrically conductive land layer includes opposing sides extending along the longitudinal direction, the voids including open voids located at the opposing sides.

18. The semiconductor device of claim 14, wherein the electrically conductive land layer includes opposing sides extending along the longitudinal direction, the voids including a complete void adjacent to an open void located at one of the opposing sides.

19. The semiconductor device of claim 14, wherein the voids include T-shaped voids. ​ 20. The semiconductor device of claim 14, wherein the void comprises an L-shaped void.

21. The semiconductor device of claim 14, wherein the void comprises a curved shaped portion.

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