Packaging structure

Abstract

A packaging structure includes a carrier, a redistribution layer, and a positioning layer. The redistribution layer is on the carrier and includes a dielectric layer, a conductive pattern, and a landing pad. The conductive pattern is in the dielectric layer. The landing pad is on the dielectric layer and electrically connected to the conductive pattern. The positioning layer is on the redistribution layer and has an opening. The opening overlaps a projection of the landing pad on the carrier, and a height of the positioning layer is greater than a height of the landing pad.

Description

TECHNICAL FIELD

[0001] The present application relates to a packaging structure. BACKGROUND

[0002] With the development of integrated circuits towards high performance, high density, low power consumption and small size, the development of forward-looking packaging is also accelerated. Currently, fan-out wafer level package (FOWLP) can be applied to high-level products. In order to reduce the price and improve the productivity, the relevant industry also actively develops fan-out panel level package (FOPLP) technology.

[0003] However, due to the error of mechanical pick and place (Pick&Place) and the thermal expansion and contraction of the dielectric layer material, the FOPLP technology still has the problem of die shift, which causes the chip to be unable to be accurately bonded on the redistribution layer (RDL), and when the area of the carrier board is larger, the amplitude of the die shift is larger, causing the packaging yield to be difficult to improve. SUMMARY

[0004] The purpose of the present application is to provide a packaging structure with improved packaging yield.

[0005] One embodiment of the present application provides a packaging structure, comprising: a carrier board; a redistribution layer located on the carrier board, and comprising: a dielectric layer; a conductive pattern located in the dielectric layer; and a contact pad located on the dielectric layer and electrically connected to the conductive pattern; and a positioning layer located on the redistribution layer and having an opening, wherein the opening overlaps the contact pad in the orthographic projection of the carrier board, and the height of the positioning layer is greater than the height of the contact pad.

[0006] In one embodiment of the present application, the coefficient of thermal expansion of the positioning layer is less than the coefficient of thermal expansion of the dielectric layer.

[0007] In one embodiment of the present application, the coefficient of thermal expansion of the positioning layer is less than 40ppm / ℃.

[0008] In one embodiment of the present application, the thickness of the positioning layer is greater than the thickness of the dielectric layer.

[0009] In one embodiment of the present application, the thickness of the positioning layer is between 10μm and 100μm.

[0010] In one embodiment of the present application, the top surface height of the positioning layer is higher than the top surface height of the contact pad.

[0011] In an embodiment of the present application, the material of the positioning layer is polyimide (PI), polybenzoxazole (PBO), epoxy resin or siloxane.

[0012] In an embodiment of the present application, the packaging structure further comprises a chip located in the opening of the positioning layer and electrically connected to the pads.

[0013] In an embodiment of the present application, the chip has a width Y, the pads have a width X, and the opening has a diameter between (Y+1 / 2X) and (Y+2X).

[0014] In an embodiment of the present application, the top surface of the positioning layer is lower than the top surface of the chip.

[0015] The packaging structure of the present application can adjust the offset amplitude and orientation of the chip during the subsequent chip bonding process, so that the pins of the chip can be precisely connected to the pads of the redistribution layer, thereby improving the yield of the packaging structure.

[0016] In order to make the above features and advantages of the present application more obvious and easy to understand, the following embodiments are described in detail below, and the accompanying drawings are described as follows. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 is a cross-sectional view of a packaging structure according to an embodiment of the present application.

[0018] Figure 2A is a partial top view of a packaging structure according to an embodiment of the present application.

[0019] Figure 2B is a cross-sectional view along the section line A-A' of Figure 2A .

[0020] The following are the reference signs:

[0021] 10, 20: packaging structure

[0022] 110: carrier plate

[0023] 120: redistribution layer

[0024] 130: positioning layer

[0025] 130T: top surface

[0026] 140: chip

[0027] 140T: top surface

[0028] 141: pin

[0029] A-A': section line

[0030] C1, C2, C3: conductive pattern

[0031] CL: connecting material

[0032] G: gap

[0033] H1: thickness / height

[0034] H2, H4: height

[0035] H3: thickness

[0036] HI1, HI2, HI3: thickness

[0037] I1, I2, I3: dielectric layer

[0038] OP: opening

[0039] PD: pad

[0040] PT: top surface

[0041] SW: sidewall

[0042] V1, V2, V3: via

[0043] W: aperture

[0044] X: width

[0045] Y: width DETAILED DESCRIPTION

[0046] In the drawings, the thickness of layers, films, panels, regions, etc., can be exaggerated for clarity. Like reference numerals can be used to denote like elements throughout the several figures of the drawings. It should be understood that when a layer, film, region, or substrate is referred to as being "on" or "connected to" another layer, film, region, or substrate, it can be directly on or connected to the other layer, film, region, or substrate or intervening layers can also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connected" can mean physically and / or electrically connected. Also, "electrical connection" or "coupling" between two elements can be present even though other elements can be present between the two elements.

[0047] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, including "at least one," unless the content clearly indicates otherwise. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. It will be understood by those within the art that, in some aspects of the disclosure, terms such as "including," "includes," "comprising," "comprises," "has," "contains," or "containing," when preceded by the term "at least one," are intended to mean that anything disclosed herein that might conceivably be added under the term "comprising" or "including" is specifically claimed. It will be understood by those within the art that when a phrase occurs both preceded and followed by a comma, as in "A, B, and C," it is our intent that the full list of members A, B, and C is intended to be the members of that list, and that no additional members are intended to be included.

[0048] Furthermore, relative terms such as "lower" or "bottom" and "upper" or "top" can be used herein to describe one element's or feature's relationship to another element or feature as illustrated in the Figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures. For example, if the device in one of the figures is turned over, elements described as being on the "lower" side of other elements would then be oriented on "upper" sides of the other elements. The exemplary term "lower" can therefore encompass both an orientation of "lower" and "upper," depending on the particular orientation of the figure. Similarly, if the device in one of the figures is turned over, elements described as "below" or "beneath" other elements would then be oriented "above" the other elements. The exemplary term "below" or "beneath" can, therefore, encompass both an orientation of above and below.

[0049] "about," or "substantially" as used herein include the stated value and the average value within an acceptable range of deviation for the particular quantity that is being referred to as determined by one of ordinary skill in the art. For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value. Further, "about," "approximately," or "substantially" as used herein can select a more acceptable range of deviation or standard deviation for optical properties, etching properties, or other properties, as can not apply one standard deviation to all properties.

[0050] Figure 1 FIG. 1 is a schematic cross-sectional view of a package structure 10 according to an embodiment of the present disclosure. The package structure 10 includes a carrier 110, a redistribution layer 120 on the carrier 110, and a positioning layer 130 on the redistribution layer 120. The redistribution layer 120 includes a dielectric layer I1, a conductive pattern C1 in the dielectric layer I1, and a pad PD on the dielectric layer I1 and electrically connected to the conductive pattern C1. The positioning layer 130 has an opening OP, and a height H1 of the positioning layer 130 is greater than a height H2 of the pad PD.

[0051] In the packaging structure 10 of an embodiment of the present application, by providing the positioning layer 130 with the opening OP, the magnitude of the chip offset can be reduced during the subsequent chip bonding process, thereby helping to improve the packaging yield.

[0052] Hereinafter, the embodiments of the various elements of the packaging structure 10 will be described in conjunction with Figure 1 , but the present application is not limited thereto.

[0053] In the present embodiment, the carrier plate 110 is, for example, a carrier for carrying the redistribution layer 120 and the positioning layer 130. In some embodiments, the coefficient of thermal expansion of the carrier plate 110 can be between 3 and 10 ppm / °C. The material of the carrier plate 110 can be glass, wafer, or other applicable materials. For example, in the present embodiment, the material of the carrier plate 110 is glass with a coefficient of thermal expansion of about 8.5 ppm / °C, but the present application is not limited thereto. In other embodiments, the carrier plate 110 can be a wafer, and the wafer can have a coefficient of thermal expansion of about 3 ppm / °C.

[0054] In the present embodiment, the dielectric layer I1 is located on the carrier plate 110 and covers the conductive pattern C1. The dielectric layer I1 can also have a via V1, so that the pad PD can be electrically connected to the conductive pattern C1 via the via V1. In some embodiments, in addition to the dielectric layer I1, the redistribution layer 120 can also include dielectric layers I2, I3, and the pad PD can be located on the dielectric layer I3, but the present application is not limited thereto. In other embodiments, the redistribution layer 120 can include fewer or more layers of dielectric layers as needed, such as two layers, four layers, or more layers of dielectric layers.

[0055] In the present embodiment, the dielectric layers I1, I2, I3 of the redistribution layer 120 can be sequentially stacked on the carrier plate 110, and the coefficients of thermal expansion of the dielectric layers I1, I2, I3 can be between 30 and 80 ppm / °C, respectively, but the present application is not limited thereto. The materials of the dielectric layers I1, I2, I3 can be selected from polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), and other suitable materials, respectively. In addition, the dielectric layers I1, I2, I3 can also have a single-layer structure or a multi-layer structure, respectively, such as a stack of any two or more layers of the above-mentioned materials, which can be combined and varied as needed.

[0056] In the present embodiment, the redistribution layer 120 can include conductive patterns C2, C3 in addition to the conductive pattern C1, and the conductive patterns C1, C2, C3 can be located in dielectric layers I1, I2, I3, respectively, but the present disclosure is not limited thereto. In other embodiments, the redistribution layer 120 can include fewer or more layers of conductive patterns, such as two, four, or more layers of conductive patterns, as needed or in coordination with the number of dielectric layers. The redistribution layer 120 can form desired electrical connections through the conductive patterns C1, C2, C3 in the dielectric layers I1, I2, I3, and the redistribution layer 120 can be electrically connected to external components or traces through the pads PD.

[0057] For example, in the present embodiment, the dielectric layers I1, I2, I3 can have vias V1, V2, V3, respectively, and the pad PD can connect the conductive pattern C3 through the via V3, the conductive pattern C3 can connect the conductive pattern C2 through the via V2, and the conductive pattern C2 can connect the conductive pattern C1 through the via V1, so that the pad PD can be electrically connected to the conductive pattern C1. The number of pads PD is not particularly limited, and the desired number of pads PD can be provided as needed.

[0058] The conductive patterns C1, C2, C3 and the pads PD can include metals or alloys having good electrical conductivity, such as aluminum, molybdenum, titanium, copper, nickel, gold, tin, silver, alloys thereof, or combinations thereof. For example, in an embodiment, the conductive patterns C1, C2, C3 and the pads PD can each independently be a single-layer structure or a multi-layer structure, such as a multi-layer structure including a titanium layer, an aluminum layer, and a titanium layer stacked in succession, but the present disclosure is not limited thereto.

[0059] The positioning layer 130 can expose all of the pads PD. For example, in the present embodiment, the positioning layer 130 can not cover the pads PD at all. However, in some embodiments, the positioning layer 130 can also partially cover each of the pads PD, and expose a portion of each of the pads PD.

[0060] In some embodiments, the coefficient of thermal expansion of the positioning layer 130 can be less than the coefficient of thermal expansion of any of the dielectric layers I1, I2, I3. In this way, warpage of the package structure 10 can also be inhibited or eliminated. For example, in some embodiments, the coefficient of thermal expansion of the positioning layer 130 can be between the coefficient of thermal expansion of the carrier substrate 110 and the coefficient of thermal expansion of any of the dielectric layers I1, I2, I3, and the thickness H1 of the positioning layer 130 can be greater than the thickness H3 of the carrier substrate 110, such that the stresses exerted by the positioning layer 130 and the carrier substrate 110 on the redistribution layer 120 can cancel each other out. In some embodiments, the coefficient of thermal expansion of the positioning layer 130 can be less than 40 ppm / °C, for example, the coefficient of thermal expansion of the positioning layer 130 can be about 30 ppm / °C or 15 ppm / °C. For example, the material of the positioning layer 130 can be polyimide (PI), polybenzoxazole (PBO), epoxy, or siloxane, but is not limited thereto.

[0061] In some embodiments, the thickness H1 of the positioning layer 130 can be greater than the thickness of any of the dielectric layers I1, I2, I3. For example, the thickness H1 of the positioning layer 130 can be greater than the thickness HI1 of the dielectric layer I1; or, the thickness H1 of the positioning layer 130 can be greater than the thickness HI2 of the dielectric layer I2; or, the thickness H1 of the positioning layer 130 can be greater than the thickness HI3 of the dielectric layer I3; or, the thickness H1 of the positioning layer 130 can be greater than the maximum thickness among the dielectric layers I1, I2, I3. In some embodiments, the thickness H1 of the positioning layer 130 can be between 10 μm and 100 μm, for example, about 20 μm, 50 μm, or 80 μm. In some embodiments, the height H1 of the top surface 130T of the positioning layer 130 from the redistribution layer 120 can also be greater than the height H2 of the top surface PT of the pad PD from the redistribution layer 120.

[0062] The formation of the opening OP of the positioning layer 130 is not particularly limited. For example, in some embodiments, the opening OP can be formed by a photolithography process. In other embodiments, the opening OP can be formed by laser drilling.

[0063] Hereinafter, the following Figures 2A-2B Further embodiments of the present application will be described, and the following Figure 1 embodiments of the present application will be described, and the following Figure 1 embodiments of the present application will be described, and the following

[0064] Figure 2A is a partial top view of a package structure 20 according to an embodiment of the present application. Figure 2B is a cross-sectional view taken alongFigure 2A FIG. 4 is a schematic view of a cross-section of the package structure 20 taken along the cross-section line A-A' shown in FIG. 3. The package structure 20 includes a carrier board 110, a redistribution layer 120, and a positioning layer 130. The redistribution layer 120 can include dielectric layers I1, I2, I3, conductive patterns C1, C2, C3, and a plurality of pads PD. The positioning layer 130 can have a plurality of openings OP, and the plurality of openings OP can be distributed in the positioning layer 130 in an array.

[0065] Compared with the package structure 10 shown in FIG. 1, Figure 1 the package structure 20 shown in FIG. 3 is different in that the package structure 20 further includes a plurality of chips 140, and the chips 140 are respectively located in the openings OP of the positioning layer 130 and electrically connected to the pads PD. Figures 2A-2B

[0066] For example, in the embodiment, the chips 140 can further include a plurality of pins 141, and the pins 141 can be electrically connected to the pads PD through a connecting material CL. The connecting material CL is, for example, solder, conductive glue, or other materials. In some embodiments, other conductive materials or conductive glue can be further included between the connecting material CL and the pins 141 or the pads PD.

[0067] In the embodiment, assuming that the chips 140 have a width Y and the pads PD have a width X, the caliber W of the openings OP can be between (Y+1 / 2X) and (Y+2X). That is, the gap G between the sidewall SW of the chip 140 and the positioning layer 130 can be between 1 / 4X and X, i.e., the gap G is preferably smaller than the width X of the pads PD. In this way, when the chips 140 are placed in the openings OP through mechanical pick-and-place to butt the pins 141 and the pads PD, the offset amplitude and the orientation of the chips 140 can be adjusted, which helps the pins 141 to butt the pads PD accurately, so that the chips 140 can be accurately bonded on the redistribution layer 120.

[0068] In some embodiments, the height H1 of the top surface 130T of the positioning layer 130 from the redistribution layer 120 can be lower than the height H4 of the top surface 140T of the chips 140 from the redistribution layer 120, but is not limited thereto. In some embodiments, the height H1 of the top surface 130T of the positioning layer 130 from the redistribution layer 120 can still be higher than the height H4 of the top surface 140T of the chips 140 from the redistribution layer 120.

[0069] In summary, the package structure of the present application can adjust the offset amplitude and the orientation of the chips in the subsequent chip bonding process by arranging the positioning layer with openings on the redistribution layer, so that the pins of the chips can butt the pads of the redistribution layer accurately, thereby improving the yield of the package structure.

[0070] ​Although the present application has been disclosed in the above with examples, it is not intended to limit the present application, and those skilled in the art can make some changes and modifications without departing from the spirit and scope of the present application, and the protection scope of the present application should be defined by the appended claims.

Claims

1. A package structure, comprising: a carrier; a redistribution layer on the carrier, and the redistribution layer comprises a dielectric layer, a plurality of conductive patterns, and a plurality of pads, wherein: the dielectric layer comprises a first dielectric layer, a second dielectric layer, and a third dielectric layer sequentially stacked on the carrier, and the first dielectric layer, the second dielectric layer, and the third dielectric layer each have a plurality of vias; the plurality of conductive patterns are in the first dielectric layer, the second dielectric layer, and the third dielectric layer of the dielectric layer, and the plurality of vias are on the plurality of conductive patterns, respectively; and the plurality of pads are on the third dielectric layer of the dielectric layer of the redistribution layer, and are electrically connected to the plurality of conductive patterns via the plurality of vias, respectively; and a positioning layer on the third dielectric layer of the dielectric layer of the redistribution layer, and the positioning layer has a plurality of openings, wherein the material of the positioning layer is polyimide, polybenzoxazole, epoxy, or siloxane, wherein the plurality of openings are distributed in an array, each of the openings overlaps the pads in the orthographic projection of the carrier, and the height of the positioning layer is greater than the height of the pads, wherein the top surface height of the pads is higher than the top surface height of the third dielectric layer; and a plurality of chips are received in the plurality of openings of the positioning layer, each of the chips comprises a plurality of pins, and the plurality of pins are electrically connected to corresponding pads exposed by the plurality of openings, wherein the diameter W of each of the openings is greater than the width Y of each of the chips, each of the pads has a width X, and the diameter W of each of the openings is between (Y+1 / 2X) and (Y+2X), the gap G between the sidewall of each of the chips and the sidewall of the corresponding opening of the positioning layer is 1 / 4X to X, wherein the top surface height of the positioning layer is lower than the top surface height of each of the chips, wherein the thickness of the positioning layer is greater than the thickness of any one of the first dielectric layer, the second dielectric layer, and the third dielectric layer, wherein the top surface height of the positioning layer is higher than the top surface height of the pads, wherein the coefficient of thermal expansion of the first dielectric layer, the second dielectric layer, and the third dielectric layer is between 30 and 80 ppm / °C, respectively, wherein the material of any one of the first dielectric layer, the second dielectric layer, and the third dielectric layer is polyimide, polybenzoxazole, or benzocyclobutene, wherein the coefficient of thermal expansion of the positioning layer is less than the coefficient of thermal expansion of any one of the first dielectric layer, the second dielectric layer, and the third dielectric layer, wherein the coefficient of thermal expansion of the positioning layer is between the coefficient of thermal expansion of the carrier and the coefficient of thermal expansion of any one of the first dielectric layer, the second dielectric layer, and the third dielectric layer, and the thickness of the positioning layer is greater than the thickness of the carrier.

2. The package structure of claim 1, wherein the coefficient of thermal expansion of the positioning layer is less than 40 ppm / °C, wherein the carrier is a glass with a coefficient of thermal expansion of about 8.5 ppm / °C or a wafer with a coefficient of thermal expansion of about 3 ppm / °C.

3. The package structure of claim 1, wherein the thickness of the positioning layer is between 10 μm and 100 μm.

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