A single-event-effect reinforced printed GaN / Ga2O3 cascode power device

Abstract

The present invention discloses a single-particle effect reinforced printing transfer GaN / Ga2O3Cascode power device, wherein the drain Drain2 of a low-voltage enhanced GaN HEMT is connected to the source Source1 of a high-voltage depletion Ga2O3FET, the source Source2 of the low-voltage enhanced GaN HEMT is connected to the gate Gate1 of a high-voltage depletion Ga2O3FET, and the low-voltage enhanced GaN HEMT and the high-voltage depletion Ga2O3FET are connected by printing and transferring each epitaxial wafer structure to form a monolithic integration. The present invention adopts a single-particle effect reinforced printing transfer GaN / Ga2O3Cascode power device of the above structure to realize a new type of GaN and Ga2O3 cascade enhanced device, reduce the complexity of the aerospace system, improve the radiation resistance of the device, and improve the single-particle burnout threshold voltage of the device under the application of the aerospace radiation environment.

Description

Technical Field

[0001] The invention relates to the technical field of power semiconductor devices, and in particular to a single particle effect reinforced printed transfer GaN / Ga2O3 Cascode power device. Background Art

[0002] With the development of semiconductor device technology, the third-generation wide bandgap semiconductor materials represented by GaN have attracted extensive attention from researchers due to their many material advantages such as wide bandgap width, high electron mobility, and fast electron saturation velocity. The electronic devices prepared by them have higher operating voltage and operating frequency, higher current density, and better radiation resistance and high temperature resistance. Therefore, they are very suitable for use in power electronic systems with high power density, high energy conversion, and irradiation environment in the aerospace field. The continuous development of aerospace technology requires the development of power electronic devices with higher power conversion efficiency, higher power density, and stronger reliability. In addition, due to the presence of high-energy particles in the space environment, these particles will penetrate the power electronic system and cause serious single-particle burning. Therefore, this requires that aerospace power electronic devices must have excellent single-particle irradiation resistance. The ultra-wide bandgap material Ga2O3 has a wider bandgap width, low intrinsic carrier concentration, and high electron saturation velocity. The devices prepared by it have higher voltage resistance and faster operating frequency, as well as better radiation resistance and high temperature resistance, which can be used as a solution for aerospace power electronic devices.

[0003] Enhancement-mode power electronic devices have many advantages over depletion-mode devices, such as simplified circuit design, no need for additional negative gate voltage drive circuits, and reduced energy consumption. The usual methods for achieving enhancement in Ga2O3-based power devices are: 1. Non-in-situ growth of P-type NiOX oxide to deplete the channel electrons under the gate; 2. Removing the channel electrons under the gate through a grooved MIS structure. However, processes such as non-in-situ growth of oxide layers and groove etching will introduce new interface states or defects, which may cause serious reliability problems and are obviously not suitable for use in the aerospace field. This problem can be effectively solved by an enhanced Cascode structure consisting of a low-voltage enhancement-mode device and a high-voltage depletion-mode device cascaded.

[0004] Usually, the enhanced Cascode structure is composed of low-voltage enhanced Si metal oxide semiconductor field effect transistors and high-voltage depletion-type GaN high electron mobility transistors. In order to further improve the radiation resistance of the Cascode structure, enhanced P-GaN AlGaN / GaN high electron mobility transistors and depletion-type Ga2O3 transistors are used to form the Cascode to avoid premature failure of Si devices under radiation.

[0005] At present, the Cascode structure in the world is mainly based on hybrid integration, that is, it is formed by packaging and bonding the enhancement mode device chip and the depletion mode device chip. However, the Cascode structure made by this method will introduce a large parasitic inductance into the bonding wire, thus affecting the normal operation of the system. Therefore, a new Cascode structure manufacturing method must be proposed to eliminate the influence of parasitic inductance. Summary of the invention

[0006] The purpose of the present invention is to provide a single particle effect reinforced printed transfer GaN / Ga2O3 cascode power device, to realize a new type of GaN and Ga2O3 cascade enhanced device, to reduce the complexity of the aerospace system, to enhance the device's radiation resistance, and to increase the single particle burnout threshold voltage of the device in aerospace radiation environment applications.

[0007] To achieve the above object, the present invention provides a single particle effect reinforced printed transfer GaN / Ga2O3Cascode power device, the cascade structure includes from left to right: a high voltage depletion mode Ga2O3FET source Source1, a gate Gate1, a drain Drain1, a low voltage enhancement mode GaN HEMT device source Source2, a gate Gate2 and a drain Drain2;

[0008] The drain Drain2 of the low-voltage enhancement-mode GaN HEMT is connected to the source Source1 of the high-voltage depletion-mode Ga2O3 FET, and the source Source2 of the low-voltage enhancement-mode GaN HEMT is connected to the gate Gate1 of the high-voltage depletion-mode Ga2O3FET, that is, the gate Gate2 of the low-voltage enhancement-mode GaN HEMT serves as the gate of the cascode structure enhancement power device in which the GaN and Ga2O3 devices are cascaded, the source Source2 of the low-voltage enhancement-mode GaN HEMT serves as the source of the cascode structure enhancement power device in which the GaN and Ga2O3 devices are cascaded, and the drain Drain1 of the high-voltage depletion-mode Ga2O3 FET serves as the drain of the cascode structure enhancement power device in which the GaN and Ga2O3 devices are cascaded. The low-voltage enhancement-mode GaN HEMT and the high-voltage depletion-mode Ga2O3 FET are connected by transferring the printing between each epitaxial wafer structure to form a monolithic integration.

[0009] Preferably, the device substrate is made of one of sapphire, Si, SiC, GaN, and Ga2O3 bulk materials.

[0010] Preferably, the source Source1 and the drain Drain1 of the Ga2O3 FET adopt one of the metal layer combinations of Ti / Al, Ti / Au, Ti / Al / Ni / Au, and Ti / Al / Mo / Au, and the gate metal Gate1 adopts one of the metal layer combinations of Ni / Au / Ni, Ni / Au, W / Au, and Mo / Au.

[0011] Preferably, the source Source2 and the drain Drain2 of the GaN HEMT adopt one of the metal layer combinations of Ti / Al, Ti / Al / Ni / Au, and Ti / Al / Mo / Au, and the gate Gate2 adopts one of the metal layer combinations of Ni / Au / Ni, Ni / Au or W / Au, and Mo / Au.

[0012] A method for manufacturing a single particle effect reinforced printed transfer GaN / Ga2O3 cascode power device comprises the following steps:

[0013] 1) Cleaning and pre-treating the substrate surface to eliminate surface dangling bonds, and heat treating at 900°C to 1200°C in a H2 atmosphere reaction chamber to remove surface contaminants;

[0014] 2) depositing Ga2O3 with a thickness of 100nm to 1000nm on the heat-treated substrate by MOCVD process as a buffer layer for a high-voltage depletion-mode Ga2O3 FET device;

[0015] 3) Ga2O3 with a thickness of 100nm to 1000nm is deposited on the Ga2O3 buffer layer by MOCVD process as the channel layer of the device, and the doping concentration is 1×10 15 cm -3 -1×10 20 cm -3 Si;

[0016] 4) Masking the entire cascode structure area, and forming mutual isolation between cascode structures through photolithography and etching;

[0017] 5) growing a mask layer on the Ga2O3 channel layer, performing photolithography and etching on the mask layer, and exposing a regional window of the GaN HEMT device on the substrate;

[0018] 6) removing the old mask layer from the epitaxial wafer obtained in the above steps, then growing a new mask layer on the Ga2O3 channel layer, photolithography and etching to expose the source and drain windows, and using an ion implantation process to implant Si into the source and drain regions in the source and drain windows;

[0019] 7) Another SOI substrate with a buried oxide layer thickness of 200 nm is selected, the surface of the SOI substrate is cleaned and pretreated to eliminate surface dangling bonds, and the surface contaminants are removed by heat treatment at 900° C. to 1200° C. in a H2 atmosphere reaction chamber;

[0020] 8) Depositing an AlN nucleation layer with a thickness of 50 nm to 100 nm on the SOI substrate using a MOCVD process;

[0021] 9) depositing a GaN buffer layer with a thickness of 0.1 μm to 10 μm on the AlN nucleation layer by using a MOCVD process;

[0022] 10) depositing an AlGaN barrier layer with a thickness of 10 nm to 50 nm on the GaN buffer layer by using a MOCVD process;

[0023] 11) A p-type p-GaN layer with a thickness of 50nm to 100nm is deposited on the AlGaN barrier layer using MOCVD process, and the doping concentration is 1×10 16 cm -3 -1×10 20 cm -3 Mg;

[0024] 12) Masking the enhanced GaN HEMT device region and forming mutual isolation between GaN HEMT devices by photolithography and etching;

[0025] 13) Soaking the SOI epitaxial wafer after the epitaxial layer is grown in the above steps in a 49% HF solution for 15 minutes to etch away part of the exposed SOI buried oxide layer;

[0026] 14) Using photolithography technology, anchor points are made at the edge of the AlGaN barrier layer film on the SOI substrate to prevent the epitaxial layer on the SOI from falling off after the buried oxide layer is completely corroded;

[0027] 15) The SOI substrate with the anchor point made is placed in the 49% HF solution for 2 hours to completely etch away the buried oxide layer;

[0028] 16) Using transfer printing technology, the epitaxial layer on the SOI substrate is transferred to the GaN HEMT device window described in step 5), and the specific implementation method is as follows:

[0029] a) Using solidified polydimethylsiloxane to couple with the p-GaN layer on the upper surface of the epitaxial layer on SOI, and then separating the two systems at a speed of 10 cm / s. Since the adhesion of polydimethylsiloxane is proportional to the separation rate, the faster separation speed allows the epitaxial layer on SOI and the Si film to detach from the substrate and adhere to the polydimethylsiloxane;

[0030] b) coupling the polydimethylsiloxane with the epitaxial layer film on the single crystal silicon with the exposed GaN HEMT region described in step 5), and then separating them at a speed of 1 mm / s. Since the separation speed is low, the adhesion of the polydimethylsiloxane is weak. At this time, the adhesion of the polydimethylsiloxane to the p-GaN layer on the upper surface of the epitaxial layer on Si is weaker than the adhesion of the exposed region described in step 5) to the single crystal Si on the lower surface of the epitaxial layer on Si. Therefore, the epitaxial layer on Si can be obtained by the exposed region described in step 5), thereby completing the printing transfer;

[0031] 17) Making a mask on the p-GaN, and only retaining the p-GaN layer slightly larger than the gate below the GaN HEMT gate by photolithography and etching, and exposing the AlGaN barrier layer in the rest of the area;

[0032] 18) performing photolithography on the AlGaN barrier layer, and depositing source and drain metals by metal evaporation or magnetron sputtering, and performing high temperature annealing;

[0033] 19) Performing photolithography on the Ga2O3 channel layer, and depositing source and drain metals by metal evaporation or magnetron sputtering, and annealing at high temperature;

[0034] 20) performing photolithography on the Ga2O3 channel layer and the p-GaN layer, depositing source and drain metals by metal evaporation or magnetron sputtering, and depositing gate metals respectively;

[0035] 21) placing the epitaxial wafer after the above steps into a PECVD reaction chamber to deposit a passivation layer;

[0036] 22) Performing photolithography and etching on the passivation layer to form gate, source and drain contact holes, and completing the metal interconnection between the source of the GaN HEMT and the gate of the Ga2O3 FET;

[0037] 23) placing the epitaxial wafer after the above steps into a PECVD reaction chamber to deposit a passivation layer;

[0038] 24) Perform photolithography and etching on the passivation layer to form gate, source and drain contact holes, connect the metal of the drain of GaN HEMT and the source of Ga2O3 FET to complete the device manufacturing.

[0039] Beneficial effects of the present invention:

[0040] (1) The low-voltage enhancement-mode GaN HEMT and the high-voltage depletion-mode Ga2O3 FET are interconnected to form a new cascode structure enhancement-mode power device. The wider bandgap of Ga2O3 can better resist single-particle irradiation;

[0041] (2) Using p-GaN enhanced-mode GaN HEMT to replace Si devices as low-voltage enhancement-mode devices, avoiding the total dose problem introduced by the MIS structure and having better radiation resistance;

[0042] (3) It avoids the parasitic inductance problem introduced in the mainstream Cascode structure hybrid integration method and improves the stability and reliability of the system.

[0043] The technical solution of the present invention is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 It is a cascade diagram of a cascode structure enhanced power device based on cascade connection of GaN and Ga2O3 devices of the present invention;

[0045] Figure 2 The invention is made Figure 1 Structural diagram of device printing transfer monolithic integration;

[0046] Figure 3 The invention is made Figure 1 Flowchart of device printing transfer monolithic integration. DETAILED DESCRIPTION

[0047] The present invention is further described below in conjunction with examples. All chemicals and reagents used in the examples are commercially available unless otherwise specified.

[0048] Example 1

[0049] Fabricate a printed transfer GaN / Ga2O3 cascode power device with single particle effect reinforcement using gallium oxide Ga2O3 as substrate.

[0050] Step 1, pre-treating the surface of the gallium oxide Ga2O3 substrate to eliminate dangling bonds.

[0051] a) Soak the Ga2O3 substrate in HF acid solution for 1 min, then sequentially place it in acetone solution, anhydrous ethanol solution and deionized water for ultrasonic cleaning for 10 min each, and finally blow dry the cleaned Ga2O3 substrate with nitrogen;

[0052] b) The cleaned and dried substrate is heat treated at 1000° C. in a H2 atmosphere reaction chamber to remove surface contaminants.

[0053] Step 2, making a Ga2O3 buffer layer.

[0054] The pretreated Ga2O3 substrate was placed in a metal organic chemical vapor deposition (MOCVD) system, and the reaction chamber pressure was set to 30 Torr and the temperature was set to 900°C. At the same time, a Ga source with a flow rate of 40 μmol / min and an oxygen with a flow rate of 3000 sccm were introduced into the reaction chamber to grow a 1 μm thick GaN buffer layer on the Ga2O3 substrate.

[0055] Step 3, making a Ga2O3 channel layer.

[0056] At the same time, a Ga source with a flow rate of 20 μmol / min and an oxygen with a flow rate of 3000 sccm were introduced into the reaction chamber to grow a 500 nm thick Ga2O3 channel layer on the Ga2O3 buffer layer with a doping concentration of 1×10 15 cm -3 Si.

[0057] Step 4: Make Cascode countertop isolation.

[0058] The entire wafer is masked with photoresist, and the cascode structure area is left through photolithography exposure and development, and then placed in the RIE etching reaction chamber for etching to form a mesa isolation, and finally the photoresist is removed by cleaning with acetone, ethanol, and deionized water.

[0059] Step 5: Make a mask and a GaN HEMT device area window.

[0060] At the same time, silane with a flow rate of 2000sccm and oxygen with a flow rate of 3000sccm are introduced into the reaction chamber to grow a 1μm SiO2 mask layer on the Ga2O3 buffer layer. Then, a photoresist is used for masking, and the GaN HEMT device area is exposed by photolithography. The exposed area is placed in an RIE etching reaction chamber and etched until the substrate is exposed.

[0061] Step 6, ion implantation into the Ga2O3 channel source and drain regions.

[0062] The epitaxial wafer that has completed the above process is placed in RIE to remove the SiO2 mask, grow a new mask and select the source and drain regions of the Ga2O3 channel for Si ion implantation process with an energy of 100 keV and a total dose of 1×10 15 cm -2 After ion implantation, the mask is removed and annealing is performed at 900°C. After completion, the mask is removed.

[0063] Step 7, select another SOI substrate for pretreatment.

[0064] The SOI substrate was sequentially placed in acetone solution, anhydrous ethanol solution and deionized water for ultrasonic cleaning for 10 min each, and finally the cleaned SOI substrate was blown dry with nitrogen;

[0065] Step 8: Prepare an AlN nucleation layer.

[0066] The epitaxial wafer that has completed the above process is placed into the MOCVD system under the same conditions as before, and Al source with a flow rate of 40 μmol / min, hydrogen with a flow rate of 1200 sccm, and ammonia with a flow rate of 3000 sccm are introduced into the chamber at the same time to grow a 50 nm thick AlN nucleation layer on the pretreated sapphire substrate.

[0067] Step 9: fabricate a GaN buffer layer.

[0068] At the same time, a Ga source with a flow rate of 40 μmol / min, a hydrogen with a flow rate of 1200 sccm, and an ammonia with a flow rate of 3000 sccm were introduced into the reaction chamber to grow a 1 μm thick GaN buffer layer on the AlN nucleation layer.

[0069] Step 10: fabricating an AlGaN barrier layer.

[0070] At the same time, Al source with a flow rate of 10 μmol / min, Ga source with a flow rate of 40 μmol / min, hydrogen with a flow rate of 1200 sccm and ammonia with a flow rate of 3000 sccm were introduced into the reaction chamber to grow a 10 nm thick AlGaN barrier layer on the GaN buffer layer.

[0071] Step 11, forming a p-GaN layer.

[0072] At the same time, a Ga source with a flow rate of 40 μmol / min, a hydrogen with a flow rate of 1200 sccm, and an ammonia with a flow rate of 3000 sccm were introduced into the reaction chamber to grow a 50 nm thick p-GaN on the AlGaN barrier layer with a Mg doping concentration of 1×1016 cm-3.

[0073] Step 12: Fabricate GaN HEMT mesa isolation.

[0074] The entire wafer is masked with photoresist, and the GaN HEMT mesa area is left through photolithography exposure and development. It is then placed in the RIE etching reaction chamber for etching to form mesa isolation, and finally the photoresist is removed by cleaning with acetone, ethanol, and deionized water.

[0075] Step 13, partially corroding the buried oxide layer of the SOI substrate.

[0076] The SOI epitaxial wafer that has completed the above process is immersed in a 49% HF solution for 15 minutes to etch away a portion of the exposed SOI buried oxide layer.

[0077] Step 14, make anchor points.

[0078] By using the photolithography process, anchor points are made at the edge of the AlGaN barrier layer film on the SOI substrate to prevent the epitaxial layer on the SOI from falling off after the buried oxide layer is completely corroded.

[0079] Step 15, completely corrode the SOI buried oxide layer.

[0080] The SOI substrate with the anchor point made is further placed in the 49% HF solution for 2 hours to completely etch away the buried oxide layer.

[0081] Step 16, printing and transferring the epitaxial layer on the SOI substrate to the GaN HEMT exposed area described in step 5.

[0082] a) Using solidified polydimethylsiloxane to couple with the p-GaN layer on the upper surface of the epitaxial layer on SOI, and then separating the two systems at a speed of 10 cm / s. Since the adhesion of polydimethylsiloxane is proportional to the separation rate, the faster separation speed allows the epitaxial layer on SOI and the Si film to detach from the substrate and adhere to the polydimethylsiloxane;

[0083] b) coupling the polydimethylsiloxane with the epitaxial layer film on the single crystal silicon with the exposed GaN HEMT region described in step 5, and then separating at a speed of 1 mm / s. Since the separation speed is low, the adhesion of the polydimethylsiloxane is weak. At this time, the adhesion of the polydimethylsiloxane to the p-GaN layer on the upper surface of the epitaxial layer on Si is weaker than the adhesion of the exposed region described in step 5 to the single crystal Si on the lower surface of the epitaxial layer on Si. Therefore, the epitaxial layer on Si can be obtained by the exposed region described in step 5, thereby completing the printing transfer;

[0084] Step 17, etching p-GaN.

[0085] A mask is made on the p-GaN layer using photoresist. After photolithography exposure and development, the epitaxial wafer is placed in the RIE reaction chamber to etch away the p-GaN layer except the p-GaN layer under the gate to expose the AlGaN barrier layer.

[0086] Step 18, fabricating the source and drain of the GaN HEMT.

[0087] A mask is made on the AlGaN barrier layer to form source and drain windows, and then it is placed in a metal evaporation reaction chamber, and the pressure of the reaction chamber is maintained at 8.8×10 -2 Pa, using aluminum and titanium targets with a purity of 99.999%, deposited Ti / Al metal as the source in the source window, and then annealed at a high temperature of 860°C for 30s.

[0088] Step 19, make the Ga2O3 FET source and drain.

[0089] A mask is made on the Ga2O3 channel layer to form source and drain windows, and then it is placed in a metal evaporation reaction chamber, and the pressure of the reaction chamber is maintained at 8.8×10 -2 Pa, using titanium and gold targets with a purity of 99.999%, deposited Ti / Au metal as the source in the source window, and then annealed at a high temperature of 480°C.

[0090] Step 20, fabricating Ga2O3 FET and GaN HEMT gates.

[0091] Masks were made on the Ga2O3 channel layer and the AlGaN barrier layer to form source and drain windows, and then placed in a metal evaporation reaction chamber with a pressure of 8.8×10 -2 Pa, using nickel and gold targets with a purity of 99.999%, metal Ni / Au / Ni with a thickness of 45nm / 200nm / 200nm was deposited on the drain window and the gate window respectively as the gate.

[0092] Step 21, making a passivation layer.

[0093] The sample after the above steps was placed in a plasma chemical vapor deposition (PECVD) reaction chamber, and a 50 nm thick SiN passivation layer was deposited at a high temperature of 400°C.

[0094] Step 22, making contact holes and metal.

[0095] The source and gate are photolithographically processed and etched to form contact holes for the gate and source to complete metal interconnection.

[0096] Step 23, making a passivation layer.

[0097] The sample after the above steps was placed in a plasma chemical vapor deposition (PECVD) reaction chamber, and a 100 nm thick SiN passivation layer was deposited at a high temperature of 400°C.

[0098] Step 24, making contact holes and metal.

[0099] The source and drain are photolithographically etched to form contact holes for the drain and source to complete the device fabrication.

[0100] Example 2

[0101] Fabricate single particle effect reinforced printed transfer GaN / Ga2O3 cascode power devices with silicon Si as substrate.

[0102] Step 1: pre-treat the surface of the Si substrate to eliminate dangling bonds.

[0103] a) Soak the Si substrate in HF acid solution for 1 min, then sequentially place it in acetone solution, anhydrous ethanol solution and deionized water for ultrasonic cleaning for 10 min each, and finally blow dry the cleaned Si substrate with nitrogen;

[0104] b) The cleaned and dried substrate is heat treated at 1100° C. in a H2 atmosphere reaction chamber to remove surface contaminants.

[0105] Step 2, making a Ga2O3 buffer layer.

[0106] The pretreated Ga2O3 substrate was placed in a metal organic chemical vapor deposition (MOCVD) system, and the reaction chamber pressure was set to 30 Torr and the temperature was set to 900°C. At the same time, a Ga source with a flow rate of 40 μmol / min and an oxygen with a flow rate of 3000 sccm were introduced into the reaction chamber to grow a 1 μm thick GaN buffer layer on the Ga2O3 substrate.

[0107] Step 3, making a Ga2O3 channel layer.

[0108] At the same time, a Ga source with a flow rate of 40 μmol / min and an oxygen with a flow rate of 3000 sccm were introduced into the reaction chamber to grow a 800 nm thick Ga2O3 channel layer on the Ga2O3 buffer layer with a doping concentration of 1×10 17 cm -3 Si.

[0109] Step 4: Make Cascode countertop isolation.

[0110] The entire wafer is masked with photoresist, and the cascode structure area is left through photolithography exposure and development, and then placed in the RIE etching reaction chamber for etching to form a mesa isolation, and finally the photoresist is removed by cleaning with acetone, ethanol, and deionized water.

[0111] Step 5: Make a mask and a GaN HEMT device area window.

[0112] At the same time, silane with a flow rate of 2000sccm and oxygen with a flow rate of 3000sccm are introduced into the reaction chamber to grow a 1μm SiO2 mask layer on the Ga2O3 buffer layer. Then, a photoresist is used for masking, and the GaN HEMT device area is exposed by photolithography. The exposed area is placed in an RIE etching reaction chamber and etched until the substrate is exposed.

[0113] Step 6, ion implantation into the Ga2O3 channel source and drain regions.

[0114] The epitaxial wafer that has completed the above process is placed in RIE to remove the SiO2 mask, grow a new mask and select the source and drain area of ​​the Ga2O3 channel for Si ion implantation process with an energy of 100 keV and a total dose of 1×10 17 cm -2 After ion implantation, the mask is removed and annealing is performed at 900°C. After completion, the mask is removed.

[0115] Step 7, select another SOI substrate for pretreatment.

[0116] The SOI substrate was sequentially placed in acetone solution, anhydrous ethanol solution and deionized water for ultrasonic cleaning for 10 min each, and finally the cleaned SOI substrate was blown dry with nitrogen;

[0117] Step 8: Prepare an AlN nucleation layer.

[0118] The epitaxial wafer that has completed the above process is placed into the MOCVD system under the same conditions as before, and Al source with a flow rate of 60 μmol / min, hydrogen with a flow rate of 1200 sccm, and ammonia with a flow rate of 3000 sccm are introduced into the chamber at the same time to grow a 100 nm thick AlN nucleation layer on the pretreated sapphire substrate.

[0119] Step 9: fabricate a GaN buffer layer.

[0120] At the same time, a Ga source with a flow rate of 60 μmol / min, a hydrogen with a flow rate of 1200 sccm, and an ammonia with a flow rate of 3000 sccm were introduced into the reaction chamber to grow a 5 μm thick GaN buffer layer on the AlN nucleation layer.

[0121] Step 10: fabricating an AlGaN barrier layer.

[0122] At the same time, Al source with a flow rate of 20 μmol / min, Ga source with a flow rate of 80 μmol / min, hydrogen with a flow rate of 1200 sccm and ammonia with a flow rate of 3000 sccm were introduced into the reaction chamber to grow a 20 nm thick AlGaN barrier layer on the GaN buffer layer.

[0123] Step 11, forming a p-GaN layer.

[0124] At the same time, a Ga source with a flow rate of 60 μmol / min, a hydrogen with a flow rate of 1200 sccm, and an ammonia with a flow rate of 3000 sccm were introduced into the reaction chamber to grow a 70 nm thick p-GaN on the AlGaN barrier layer with a Mg doping concentration of 1×1018 cm-3.

[0125] Step 12: Fabricate GaN HEMT mesa isolation.

[0126] The entire wafer is masked with photoresist, and the GaN HEMT mesa area is left through photolithography exposure and development. It is then placed in the RIE etching reaction chamber for etching to form mesa isolation, and finally the photoresist is removed by cleaning with acetone, ethanol, and deionized water.

[0127] Step 13, partially corroding the buried oxide layer of the SOI substrate.

[0128] The SOI epitaxial wafer that has completed the above process is immersed in a 49% HF solution for 15 minutes to etch away a portion of the exposed SOI buried oxide layer.

[0129] Step 14, make anchor points.

[0130] By using the photolithography process, anchor points are made at the edge of the AlGaN barrier layer film on the SOI substrate to prevent the epitaxial layer on the SOI from falling off after the buried oxide layer is completely corroded.

[0131] Step 15, completely corrode the SOI buried oxide layer.

[0132] The SOI substrate with the anchor point made is further placed in the 49% HF solution for 2 hours to completely etch away the buried oxide layer.

[0133] Step 16, printing and transferring the epitaxial layer on the SOI substrate to the GaN HEMT exposed area described in step 5.

[0134] a) Using solidified polydimethylsiloxane to couple with the p-GaN layer on the upper surface of the epitaxial layer on SOI, and then separating the two systems at a speed of 10 cm / s. Since the adhesion of polydimethylsiloxane is proportional to the separation rate, the faster separation speed allows the epitaxial layer on SOI and the Si film to detach from the substrate and adhere to the polydimethylsiloxane;

[0135] b) coupling the polydimethylsiloxane with the epitaxial layer film on the single crystal silicon with the exposed GaN HEMT region described in step 5, and then separating at a speed of 1 mm / s. Since the separation speed is low, the adhesion of the polydimethylsiloxane is weak. At this time, the adhesion of the polydimethylsiloxane to the p-GaN layer on the upper surface of the epitaxial layer on Si is weaker than the adhesion of the exposed region described in step 5 to the single crystal Si on the lower surface of the epitaxial layer on Si. Therefore, the epitaxial layer on Si can be obtained by the exposed region described in step 5, thereby completing the printing transfer;

[0136] Step 17, etching p-GaN.

[0137] A mask is made on the p-GaN layer using photoresist. After photolithography exposure and development, the epitaxial wafer is placed in the RIE reaction chamber to etch away the p-GaN layer except the p-GaN layer under the gate to expose the AlGaN barrier layer.

[0138] Step 18, fabricating the source and drain of the GaN HEMT.

[0139] A mask is made on the AlGaN barrier layer to form source and drain windows, and then it is placed in a metal evaporation reaction chamber, and the pressure of the reaction chamber is maintained at 8.8×10 -2 Pa, using aluminum and titanium targets with a purity of 99.999%, deposited Ti / Al metal as the source in the source window, and then annealed at a high temperature of 870°C for 30s.

[0140] Step 19, make the Ga2O3 FET source and drain.

[0141] A mask is made on the Ga2O3 channel layer to form source and drain windows, and then it is placed in a metal evaporation reaction chamber, and the pressure of the reaction chamber is maintained at 8.8×10 -2 Pa, using titanium and gold targets with a purity of 99.999%, deposited Ti / Au metal as the source in the source window, and then annealed at a high temperature of 480°C.

[0142] Step 20, fabricating Ga2O3 FET and GaN HEMT gates.

[0143] Masks were made on the Ga2O3 channel layer and the AlGaN barrier layer to form source and drain windows, and then placed in a metal evaporation reaction chamber with a pressure of 8.8×10 -2 Pa, using nickel and gold targets with a purity of 99.999%, deposited metal Ni / Au with a thickness of 45nm / 200nm as the gate in the drain window and gate window respectively.

[0144] Step 21, making a passivation layer.

[0145] The sample after the above steps was placed in a plasma chemical vapor deposition (PECVD) reaction chamber, and a 100 nm thick SiN passivation layer was deposited at a high temperature of 400°C.

[0146] Step 22, making contact holes and metal.

[0147] The source and gate are photolithographically processed and etched to form contact holes for the gate and source to complete metal interconnection.

[0148] Step 23, making a passivation layer.

[0149] The sample after the above steps is placed in a plasma chemical vapor deposition (PECVD) reaction chamber, and a 200 nm thick SiN passivation layer is deposited at a high temperature of 400°C.

[0150] Step 24, making contact holes and metal.

[0151] The source and drain are photolithographically etched to form contact holes for the drain and source to complete the device fabrication.

[0152] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that they can still modify or replace the technical solution of the present invention with equivalents, and these modifications or equivalent replacements cannot cause the modified technical solution to deviate from the spirit and scope of the technical solution of the present invention.

Claims

1. A single-particle-effect reinforced printed transfer GaN / Ga2O3 cascode power device, characterized in that: The cascade structure includes from left to right: source Source1, gate Gate1, and drain Drain1 of a high-voltage depletion-mode Ga2O3FET, and source Source2, gate Gate2, and drain Drain2 of a low-voltage enhancement-mode GaN HEMT device; The drain Drain2 of the low-voltage enhancement-mode GaN HEMT is connected to the source Source1 of the high-voltage depletion-mode Ga2O3 FET, and the source Source2 of the low-voltage enhancement-mode GaN HEMT is connected to the gate Gate1 of the high-voltage depletion-mode Ga2O3 FET, that is, the gate Gate2 of the low-voltage enhancement-mode GaN HEMT serves as the gate of the cascode structure enhancement power device in which the GaN and Ga2O3 devices are cascaded, the source Source2 of the low-voltage enhancement-mode GaN HEMT serves as the source of the cascode structure enhancement power device in which the GaN and Ga2O3 devices are cascaded, and the drain Drain1 of the high-voltage depletion-mode Ga2O3 FET serves as the drain of the cascode structure enhancement power device in which the GaN and Ga2O3 devices are cascaded. The low-voltage enhancement-mode GaN HEMT and the high-voltage depletion-mode Ga2O3 FET are connected by transferring the printing between each epitaxial wafer structure to form a monolithic integration.

2. The single-particle-effect reinforced printed transfer GaN / Ga2O3 cascode power device according to claim 1, characterized in that: The device substrate adopts one of sapphire, Si, SiC, GaN, and Ga2O3 bulk materials.

3. The single-particle-effect reinforced printed transfer GaN / Ga2O3 cascode power device according to claim 1, characterized in that: The source Source1 and the drain Drain1 of the Ga2O3 FET adopt one of the metal layer combinations of Ti / Al, Ti / Au, Ti / Al / Ni / Au, and Ti / Al / Mo / Au, and the gate Gate1 adopts one of the metal layer combinations of Ni / Au / Ni, Ni / Au, W / Au, and Mo / Au.

4. The single-particle-effect reinforced printed transfer GaN / Ga2O3 cascode power device according to claim 1, characterized in that: The source Source2 and the drain Drain2 of the GaN HEMT adopt one of the metal layer combinations of Ti / Al, Ti / Al / Ni / Au, and Ti / Al / Mo / Au, and the gate Gate2 adopts one of the metal layer combinations of Ni / Au / Ni, Ni / Au or W / Au, and Mo / Au.

5. A method for manufacturing a single particle effect reinforced printed transfer GaN / Ga2O3 Cascode power device according to any one of claims 1 to 4, characterized in that: The steps include: 1) Clean and pre-treat the substrate surface to eliminate surface dangling bonds, and heat-treat at 900°C to 1200°C in a H2 atmosphere reaction chamber to remove surface contaminants; 2) Ga2O3 with a thickness of 100nm~1000nm is deposited on the heat-treated substrate using MOCVD process as a buffer layer for high-voltage depletion-mode Ga2O3 FET devices; 3) On the Ga2O3 buffer layer, a Ga2O3 layer with a thickness of 100nm~1000nm is deposited by MOCVD process as the channel layer of the device, and the doping concentration is 1×10 15 cm -3 -1×10 20 cm -3 Si; 4) Mask the entire cascode structure area and form mutual isolation between cascode structures through photolithography and etching; 5) growing a mask layer on the Ga2O3 channel layer, performing photolithography and etching on the mask layer, and exposing a regional window of the GaN HEMT device on the substrate; 6) Remove the old mask layer from the epitaxial wafer obtained in the above steps, then grow a new mask layer on the Ga2O3 channel layer, expose the source and drain windows by photolithography and etching, and implant Si into the source and drain regions by ion implantation in the source and drain windows; 7) Another SOI substrate with a buried oxide layer thickness of 200 nm was selected, the surface of the SOI substrate was cleaned and pretreated to eliminate surface dangling bonds, and heat-treated at 900°C to 1200°C in a H2 atmosphere reaction chamber to remove surface contaminants; 8) Depositing an AlN nucleation layer with a thickness of 50nm~100nm on the SOI substrate using the MOCVD process; 9) A GaN buffer layer with a thickness of 0.1 μm to 10 μm is deposited on the AlN nucleation layer using a MOCVD process; 10) Depositing an AlGaN barrier layer with a thickness of 10nm~50nm on the GaN buffer layer using MOCVD process; 11) A p-type p-GaN layer with a thickness of 50 nm to 100 nm is deposited on the AlGaN barrier layer by using a MOCVD process. The p-GaN layer is made of GaN with a doping concentration of 1×10 16 cm -3 -1×10 20 cm -3 Mg; 12) Mask the enhanced GaN HEMT device area and form mutual isolation between GaN HEMT devices through photolithography and etching; 13) Soak the SOI epitaxial wafer after the epitaxial layer is grown in the above steps in a 49% HF solution for 15 minutes to etch away part of the exposed SOI buried oxide layer; 14) Using photolithography technology, anchor points are made at the edge of the AlGaN barrier layer film on the SOI substrate to prevent the epitaxial layer on the SOI from falling off after the buried oxide layer is completely corroded; 15) Place the SOI substrate with the anchor point made in 49% HF solution for another 2 hours to completely etch away the buried oxide layer; 16) Using transfer printing technology, transfer the epitaxial layer on the SOI substrate to the GaN HEMT device window described in step 5); 17) Make a mask on the p-GaN, and use photolithography to only keep the p-GaN layer slightly larger than the gate under the GaN HEMT gate, and expose the AlGaN barrier layer in the rest of the area; 18) Perform photolithography on the AlGaN barrier layer, and deposit source and drain metals by metal evaporation or magnetron sputtering, and anneal at high temperature; 19) Perform photolithography on the Ga2O3 channel layer, and deposit source and drain metals by metal evaporation or magnetron sputtering, and anneal at high temperature; 20) Perform photolithography on the Ga2O3 channel layer and the p-GaN layer, and deposit the source and drain metals by metal evaporation or magnetron sputtering, and deposit the gate metal respectively; 21) Place the epitaxial wafer after the above steps into the PECVD reaction chamber to deposit the passivation layer; 22) Perform photolithography and etching on the passivation layer to form gate, source and drain contact holes to complete the metal interconnection between the source of GaN HEMT and the gate of Ga2O3 FET; 23) Place the epitaxial wafer after the above steps into the PECVD reaction chamber to deposit the passivation layer; 24) Perform photolithography and etching on the passivation layer to form gate, source and drain contact holes, connect the metal of the drain of GaN HEMT and the source of Ga2O3FET to complete the device fabrication.

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