semiconductor devices

Abstract

The present invention provides a semiconductor device that reduces the occupied area of ​​a thin film transistor and improves the reliability of the semiconductor device. The semiconductor device includes a thin film transistor in each pixel. The thin film transistor includes: an oxide semiconductor layer; a gate insulating layer; a gate electrode overlapping the oxide semiconductor layer with the gate insulating layer interposed therebetween; a source electrode in contact with the oxide semiconductor layer; a drain electrode in contact with the oxide semiconductor layer; and n (n is a natural number) metal layers in contact with the oxide semiconductor layer and arranged between the source electrode and the drain electrode in a manner that crosses the oxide semiconductor layer. When viewed from above, the oxide semiconductor layer has (n+1) channel regions between the source electrode and the drain electrode.

Description

Technical Field

[0001] One embodiment of the present invention relates to a semiconductor device including a thin film transistor in each pixel. In particular, the present invention relates to a display device including a thin film transistor using an oxide semiconductor. Background Art

[0002] In recent years, liquid crystal displays (LCDs) and organic light-emitting diode (OLED) displays have become commonplace in televisions, mobile devices, and other displays. These displays have multiple pixels in their display sections, with thin-film transistors controlling the bright and dark states of each pixel. Consequently, if a defect such as a short circuit occurs in a thin-film transistor, the pixel containing that thin-film transistor remains permanently in either the bright or dark state, causing it to fail to function properly.

[0003] To address this issue, technologies have been developed that enable pixels to function normally by providing redundancy to thin-film transistors. For example, Patent Document 1 discloses a pixel structure in which two thin-film transistors are connected in series between a source bus line and a pixel electrode. With this pixel structure, even if one thin-film transistor fails due to a short circuit or other reasons, the pixel can maintain normal operation as long as the other thin-film transistor operates normally.

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent No. 2834756. Summary of the Invention

[0007] Problems to be solved by the invention

[0008] As mentioned above, existing pixel structures provide redundancy in each pixel by connecting multiple independently operating thin-film transistors in series. However, in existing pixel structures, the thin-film transistors' semiconductor layers are physically separated, so the thin-film transistors occupy a large area within each pixel. Consequently, with existing pixel structures, the effective pixel area is reduced, leading to reduced brightness when displaying images.

[0009] One of the objects of the present invention is to suppress the occupied area of ​​a thin film transistor and improve the reliability of a semiconductor device (particularly a display device).

[0010] Technical means to solve the problem

[0011] A semiconductor device according to one embodiment of the present invention includes a thin film transistor in each pixel. The thin film transistor includes: an oxide semiconductor layer; a gate insulating layer; a gate electrode overlapping the oxide semiconductor layer with the gate insulating layer interposed therebetween; a source electrode in contact with the oxide semiconductor layer; a drain electrode in contact with the oxide semiconductor layer; and n (n is a natural number) metal layers in contact with the oxide semiconductor layer and arranged between the source electrode and the drain electrode so as to traverse the oxide semiconductor layer. When viewed from above, the oxide semiconductor layer has (n+1) channel regions between the source electrode and the drain electrode.

[0012] According to the present invention, it is possible to suppress the occupied area of ​​a thin film transistor and improve the reliability of a semiconductor device (particularly a display device). BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a plan view showing the structure of the display device according to the first embodiment of the present invention.

[0014] Figure 2 This is a circuit diagram showing a circuit configuration of a pixel in a display device according to the first embodiment of the present invention.

[0015] Figure 3 It is a cross-sectional view showing the structure of a display portion in the display device according to the first embodiment of the present invention.

[0016] Figure 4A It is a cross-sectional view showing the structure of a thin film transistor used in the display device according to the first embodiment of the present invention.

[0017] Figure 4B It is a plan view showing the structure of a thin film transistor used in the display device according to the first embodiment of the present invention.

[0018] Figure 5A It is a cross-sectional view showing a method for manufacturing a thin film transistor used in the display device according to the first embodiment of the present invention.

[0019] Figure 5B It is a plan view showing a method for manufacturing a thin film transistor used in the display device according to the first embodiment of the present invention.

[0020] Figure 6A It is a cross-sectional view showing a method for manufacturing a thin film transistor used in the display device according to the first embodiment of the present invention.

[0021] Figure 6B It is a plan view showing a method for manufacturing a thin film transistor used in the display device according to the first embodiment of the present invention.

[0022] Figure 7A It is a cross-sectional view showing a method for manufacturing a thin film transistor used in the display device according to the first embodiment of the present invention.

[0023] Figure 7B It is a plan view showing a method for manufacturing a thin film transistor used in the display device according to the first embodiment of the present invention.

[0024] Figure 8A It is a cross-sectional view showing a method for manufacturing a thin film transistor used in the display device according to the first embodiment of the present invention.

[0025] Figure 8B It is a plan view showing a method for manufacturing a thin film transistor used in the display device according to the first embodiment of the present invention.

[0026] Figure 9A It is a cross-sectional view showing a method for manufacturing a thin film transistor used in the display device according to the first embodiment of the present invention.

[0027] Figure 9B It is a plan view showing a method for manufacturing a thin film transistor used in the display device according to the first embodiment of the present invention.

[0028] Figure 10A It is a plan view showing a method for manufacturing a thin film transistor used in a display device according to a second embodiment of the present invention.

[0029] Figure 10B It is a plan view showing a method for manufacturing a thin film transistor used in a display device according to a second embodiment of the present invention.

[0030] Description of Reference Numerals

[0031] 10, 10-1, 10-2, 10a, 10a-1, 10a-2, 10a-3, 10b, 10b-1, 10b-2, 10b-3, 10b-4…Thin film transistor, 11…Gate electrode, 12, 13…Insulating layer, 14…Source electrode, 15…Drain electrode, 16…Metal layer, 17, 18…Insulating layer, 30…Oxide semiconductor layer, 31, 32…Channel region, 33…Separation region, 34…Source region, 35…Drain region, 36-39…Low resistance region, 41a, 41b, 42a, 42b, 42c…Metal layer, 51a, 51b, 51c, 52a, 52b, 52c, 52d…Channel region, 100…Display device, 110…Substrate, 12 0…display portion, 121…insulating layer, 122…anode electrode, 123…partition wall layer, 124…organic layer, 125…cathode electrode, 126…sealing layer, 126a, 126c…inorganic insulating layer, 126b…organic insulating layer, 127…adhesive layer, 128…protective glass, 130…driver circuit portion, 140…terminal portion, 141…terminal, 150…flexible printed circuit board, 160…driver IC chip, 200, 200R, 200G, 200B…pixel, 300…pixel circuit, 310…select transistor, 312…gate line, 314…data line, 320…driver transistor, 322…anode power supply line, 324…cathode power supply line, 330…capacitor, 340…light-emitting element. DETAILED DESCRIPTION

[0032] The following describes embodiments of the present invention with reference to the accompanying drawings, etc. However, the present invention can be implemented in various ways without departing from the scope of the present invention. The present invention is not limited to the description of the following embodiments. In the accompanying drawings, the width, thickness, shape, etc. of each part are sometimes schematically shown compared to the actual form to make the description clearer. However, the accompanying drawings are merely examples and do not limit the interpretation of the present invention.

[0033] In the description of the embodiments of the present invention, the direction from the substrate toward the light-emitting element is defined as "up," and the opposite direction is defined as "down." However, the expressions "up" and "down" merely describe the upper limits of the relationships between the various elements. For example, the expression "a light-emitting element is disposed on a substrate" also includes the presence of other components between the substrate and the light-emitting element. Furthermore, the expressions "up" and "down" include not only the case where the various elements overlap when viewed from above, but also the case where they do not overlap.

[0034] In the description of the embodiments of the present invention, elements having the same functions as those already described may be denoted by the same reference numerals or by using symbols such as alphabets instead of the same reference numerals, and their description may be omitted.

[0035] In the description of the embodiments of the present invention, multiple elements formed by etching or other processing on a film may be described as having different functions or effects. These multiple elements have the same layer structure and are made of the same material. Therefore, multiple elements formed from a film may be referred to as being provided in the "same layer."

[0036] In the description of the embodiments of the present invention, expressions such as "α includes A, B, or C," "α includes any one of A, B, and C," and "α includes one selected from the group consisting of A, B, and C" do not exclude the case where α includes multiple combinations of A to C, unless otherwise specified. Furthermore, these expressions do not exclude the case where α includes other elements.

[0037] In the description of the embodiments of the present invention, a "display device" refers to a device that displays an image. Specifically, a "display device" includes not only a display panel or display assembly, but also a device in which other optical components (e.g., a polarizing element, a touch panel, etc.) are mounted on the display panel or display assembly.

[0038] <First embodiment>

[0039] [Structure of Display Device 100]

[0040] Figure 1 1 is a plan view showing the structure of a display device 100 according to a first embodiment of the present invention. The display device 100 includes a display portion 120 , a driver circuit portion 130 , and a terminal portion 140 . The display portion 120 , the driver circuit portion 130 , and the terminal portion 140 are provided on a substrate 110 .

[0041] The display unit 120 includes a plurality of pixels 200R, 200G, and 200B. Pixel 200R corresponds to a pixel that emits red light. Pixel 200G corresponds to a pixel that emits green light. Pixel 200B corresponds to a pixel that emits blue light. The display unit 120 displays an image by controlling the emission and non-emission of the plurality of pixels 200R, 200G, and 200B. In this embodiment, when it is not necessary to specifically distinguish between the RGB colors, they may be simply referred to as pixels 200. The structure of each pixel 200 will be described later.

[0042] The driving circuit section 130 controls each pixel 200 of the display section 120. The driving circuit section 130 includes, for example, a gate line driving circuit. Figure 1 Although not shown in the figure, the driving circuit unit 130 may also include a data line driving circuit.

[0043] The terminal portion 140 functions as a terminal for receiving signals supplied from the outside to the display portion 120 and the driver circuit portion 130. The terminal portion 140 includes a plurality of terminals 141. The terminal portion 140 is connected to the flexible printed circuit board 150, and the plurality of terminals 141 are each connected to a corresponding terminal on the flexible printed circuit board 150. In this embodiment, a driver IC chip 160 is provided on the flexible printed circuit board 150. However, this is not limiting, and the driver IC chip 160 may be omitted.

[0044] exist Figure 1 While the overall structure of display device 100 is shown in plan view, substrate 110 may be folded between display portion 120 and terminal portion 140. In this case, a flexible substrate such as a resin substrate may be used as substrate 110. With this structure, terminal portion 140 and flexible printed circuit board 150 can be folded toward the back side of display device 100, enabling a more compact display device 100.

[0045] [Structure of Pixel Circuit 300]

[0046] Figure 2 1 is a circuit diagram showing a circuit configuration of a pixel 200 in the display device 100 according to the first embodiment of the present invention. The pixel circuit 300 includes a selection transistor 310 , a drive transistor 320 , a capacitor 330 , and a light emitting element 340 .

[0047] The select transistor 310 is connected to a gate line 312 and a data line 314. Specifically, the gate line 312 is connected to the gate of the select transistor 310. The data line 314 is connected to the source of the select transistor 310. The select transistor 310 functions as a switch for selecting whether to input a data signal (image signal Vs) to the pixel circuit 300. The drain of the select transistor 310 is connected to the gate of the drive transistor 320 and the capacitor 330.

[0048] The drive transistor 320 is connected to an anode power supply line 322, a light-emitting element 340, and a capacitor 330. Specifically, the anode power supply line 322 is connected to the drain of the drive transistor 320. The light-emitting element 340 is connected to the source of the drive transistor 320. The capacitor 330 is connected between the gate and source of the drive transistor 320. The drive transistor 320 functions as a valve for controlling the amount of current flowing through the light-emitting element 340. A high-potential power supply voltage (PVDD) is applied to the anode power supply line 322.

[0049] In this embodiment, the selection transistor 310 and the driving transistor 320 substantially have a structure in which two thin film transistors are connected in series. The reason for this will be described later.

[0050] The capacitor 330 holds a data signal input via the selection transistor 310. A voltage corresponding to the data signal held in the capacitor 330 is applied to the gate of the drive transistor 320. Thus, the amount of current flowing through the drive transistor 320 is controlled according to the data signal.

[0051] The light-emitting element 340 is connected between the driving transistor 320 and the cathode power supply line 324. Specifically, the anode of the light-emitting element 340 is connected to the source of the driving transistor 320. In other words, the anode of the light-emitting element 340 is connected to the anode power supply line 322 via the driving transistor 320. The cathode of the light-emitting element 340 is connected to the cathode power supply line 324. A low-potential power supply voltage (PVSS) is applied to the cathode power supply line 324.

[0052] In pixel circuit 300, when select transistor 310 is turned on, a data signal is input from data line 314. A voltage corresponding to the input data signal is held by capacitor 330. Subsequently, during the light-emission period, the voltage held in capacitor 330 controls the gate of drive transistor 320, causing a current corresponding to the data signal to flow through drive transistor 320. When this current flows through light-emitting element 340, light-emitting element 340 emits light at a brightness corresponding to the amount of current.

[0053] [Structure of pixel 200]

[0054] Figure 3 1 is a cross-sectional view showing the structure of the display unit 120 in the display device 100 according to the first embodiment of the present invention. Specifically, Figure 3 The cross-sectional structure shown is the same as that cut by the single-dot chain line AA. Figure 1 The cross-sectional view of the display unit 120 shown in FIG. 2 corresponds to the cross-sectional view of the display unit 120 shown in FIG. 2. Since the basic structure of each pixel 200R, 200G and 200B is the same, Figure 3 The following description focuses on the pixel 200G that emits green light.

[0055] like Figure 3 As shown, a driving transistor 320 is provided on the substrate 110. Figure 3 Although not shown in the figure, various elements constituting the pixel circuit 300 such as a selection transistor 310 and a capacitor 330 are provided on the substrate 110 .

[0056] The driving transistor 320 is covered by an insulating layer 121 comprising a resin layer. The resin layer in the insulating layer 121 has the function of flattening the unevenness caused by the driving transistor 320 and the like. The insulating layer 121 can have a laminated structure of an inorganic insulating layer and a resin layer. Silicon-based inorganic materials such as silicon oxide and silicon nitride can be used as the material for the inorganic insulating layer. Photosensitive organic materials such as acrylic or polyimide can be used as the material for the resin layer.

[0057] An anode electrode 122 is provided on the insulating layer 121. The anode electrode 122 is the anode of the light-emitting element 340 and also functions as a pixel electrode of the pixel 200. The anode electrode 122 is electrically connected to the source electrode of the driving transistor 320 via a contact hole provided in the insulating layer 121. In this embodiment, the anode electrode 122 is composed of a transparent conductive layer. However, this example is not limited thereto, and the anode electrode 122 may be composed of a metal layer or may have a stacked structure of a transparent conductive layer and a metal layer. For example, a transparent conductive layer containing a metal oxide can be used as the anode electrode 122. In this embodiment, a conductive layer formed by stacking a metal layer containing silver and a transparent conductive layer composed of ITO (Indium Tin Oxide) is used as the anode electrode 122. In this case, the conductive layer on the side in contact with the organic layer 124 described later is used as the transparent conductive layer.

[0058] A partition wall layer 123 is provided on the anode electrode 122. The partition wall layer 123 has an opening that exposes a portion of the surface of the anode electrode 122. In other words, the partition wall layer 123 is provided so as to cover the end of the anode electrode 122. The inner wall of the opening of the partition wall layer 123 preferably has a gently tapered shape. By providing the inner wall of the opening of the partition wall layer 123 with a tapered shape, poor coverage of the organic layer 124 or cathode electrode 125 formed on the anode electrode 122 can be reduced. The partition wall layer 123 is sometimes also referred to as a bank or rib.

[0059] An organic layer 124 including at least a hole transport layer, a light-emitting layer, and an electron transport layer is provided on the anode electrode 122. In the case of pixel 200G, the light-emitting layer of organic layer 124 is composed of an organic material that emits green light. Similarly, in the case of pixel 200R and pixel 200B, the light-emitting layer of organic layer 124 is composed of an organic material that emits red light and an organic material that emits blue light, respectively. The hole transport layer and electron transport layer included in the organic layer 124 can also be provided in a manner that spans each pixel 200. The organic layer 124 may also include functional layers, such as an electron injection layer, an electron blocking layer, a hole injection layer, or a hole blocking layer.

[0060] A cathode electrode 125 is provided on the organic layer 124. The cathode electrode 125 may also be provided across each pixel 200. In the present embodiment, the cathode electrode 125 is formed of a metal layer. However, not limited to this example, the cathode electrode 125 may be formed of a transparent conductive layer, or may have a stacked structure of a transparent conductive layer and a metal layer. For example, a metal layer containing an alkali metal or an alkaline earth metal can be used as the cathode electrode 125. In the present embodiment, a metal layer composed of an MgAg alloy (an alloy containing magnesium and silver) is used as the cathode electrode 125. In this case, the film thickness of the cathode electrode 125 is a thickness that can transmit visible light.

[0061] A sealing layer 126 is provided on the cathode electrode 125. The sealing layer 126 has, for example, a structure in which an inorganic insulating layer 126a, an organic insulating layer 126b, and an inorganic insulating layer 126c are stacked. Silicon-based inorganic materials such as silicon oxide and silicon nitride can be used as materials for the inorganic insulating layers 126a and 126c. The inorganic insulating layers 126a and 126c function to prevent moisture from entering from the outside. Therefore, dense insulating layers are preferably used as the inorganic insulating layers 126a and 126c. Resin materials such as acrylic resin, epoxy resin, polyimide resin, silicone resin, fluororesin, or siloxane resin can be used as the material for the organic insulating layer 126b.

[0062] In this embodiment, a protective glass 128 is provided on the sealing layer 126 via an adhesive layer 127. Figure 3 Although not shown in the figure, optical components such as a polarizing plate or a touch sensor may be further provided above or below the protective glass 128. The adhesive layer 127 and the protective glass 128 may also be omitted.

[0063] [Structure of Thin Film Transistor 10]

[0064] Figure 4A It is a cross-sectional view showing the structure of a thin film transistor 10 used in the display device 100 according to the first embodiment of the present invention. Figure 4B FIG1 is a plan view showing the structure of the thin film transistor 10 used in the display device 100 according to the first embodiment of the present invention. Figure 4B For the sake of convenience, the Figure 4A The thin film transistor 10 can be used to Figure 2 At least one of the select transistor 310 and the drive transistor 320 is shown. Figure 4A and Figure 4B The thin film transistor 10 shown is an example of a bottom-gate transistor.

[0065] A gate electrode 11 is provided on a substrate 110 having an insulating surface. For example, a translucent substrate made of glass, quartz, or sapphire can be used as the substrate 110. However, a non-translucent substrate made of silicon or ceramics can also be used as the substrate 110. Furthermore, a flexible substrate made of a resin material such as polyimide resin, acrylic resin, silicone resin, or fluororesin can also be used as the substrate 110.

[0066] The gate electrode 11 is made of a metal material such as titanium, tantalum, tungsten, molybdenum, vanadium, aluminum, copper, or niobium, or an alloy material containing these metals. The gate electrode 11 may have a single-layer structure or a stacked structure.

[0067] Gate electrode 11 is covered by insulating layers 12 and 13. In this embodiment, insulating layer 12 is a silicon nitride layer. Insulating layer 13 is a silicon oxide layer. In this embodiment, insulating layers 12 and 13 are stacked to function as a gate insulating layer. However, this is not limiting; insulating layer 13 may be used as a single layer as a gate insulating layer.

[0068] An oxide semiconductor layer 30 is provided on the insulating layer 13. As a material for the oxide semiconductor layer 30, for example, indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), indium aluminum zinc oxide (IAZO), or zinc oxide (ZnO) can be used. The oxide semiconductor layer 30 may be a single layer or a stacked layer. In this embodiment, indium gallium zinc oxide (IGZO) is used as the oxide semiconductor layer 30. Therefore, the thin film transistor 10 of this embodiment operates as an n-channel transistor in which the majority of carriers are electrons. Details of the structure of the oxide semiconductor layer 30 will be described later.

[0069] A source electrode 14 and a drain electrode 15 are provided on the oxide semiconductor layer 30 in contact with the ends of the oxide semiconductor layer 30. Specifically, in the cross-sectional view, the source electrode 14 is provided in contact with the first end of the oxide semiconductor layer 30, and the drain electrode 15 is provided in contact with the second end opposite to the first end. In this embodiment, the source electrode 14 and the drain electrode 15 are provided at the ends of the oxide semiconductor layer 30 so as to cover three sides, but this is not limited to this example. For example, the source electrode 14 and the drain electrode 15 may also be provided so as to cross the oxide semiconductor layer 30 (i.e., to cover two sides).

[0070] The source electrode 14 and the drain electrode 15 are made of a metal material such as titanium, aluminum, tantalum, tungsten, molybdenum, vanadium, aluminum, copper, or niobium, or an alloy material containing these metals. The source electrode 14 and the drain electrode 15 may have a single-layer structure or a stacked structure. In this embodiment, a metal layer having a three-layer structure of titanium / aluminum / titanium is used as the source electrode 14 and the drain electrode 15.

[0071] In this embodiment, the metal layer 16 is formed simultaneously with the source electrode 14 and the drain electrode 15. That is, the metal layer 16 is provided in the same layer as the source electrode 14 and the drain electrode 15. Therefore, the metal layer 16 of this embodiment has a three-layer structure of titanium / aluminum / titanium, similar to the source electrode 14 and the drain electrode 15. That is, the metal layer 16 has a structure in which the bottommost titanium layer is in contact with the oxide semiconductor layer 30. However, the present invention is not limited to this example, and the metal layer 16 may also be formed of a metal material different from that of the source electrode 14 and the drain electrode 15. As described later, in order to prevent hydrogen from moving inside the oxide semiconductor layer 30, a metal material that easily absorbs hydrogen, such as titanium or molybdenum, is preferably used as the material of the metal layer 16.

[0072] The metal layer 16 is in contact with the oxide semiconductor layer 30 and is spaced apart from the source electrode 14 and the drain electrode 15. Specifically, in this embodiment, the metal layer 16 is spaced apart from the source electrode 14 and the drain electrode 15 at substantially equal distances. However, the present invention is not limited to this example, and the metal layer 16 may be located closer to the source electrode 14 or the drain electrode 15.

[0073] like Figure 4B As shown, the metal layer 16 is arranged so as to traverse the oxide semiconductor layer 30. Here, if the longitudinal direction of the oxide semiconductor layer 30 (the direction connecting the source electrode 14 and the drain electrode 15) is set as the D1 direction, the metal layer 16 has a longitudinal direction in the D2 direction that intersects the D1 direction. In other words, the metal layer 16 is arranged so as to traverse the oxide semiconductor layer 30 along the D2 direction.

[0074] In this embodiment, metal layer 16 is electrically floating. That is, the potentials of metal layers 16 and 17 are undefined. However, this is not limiting, and metal layer 16 may also be fixed to a fixed potential. The width of metal layer 16 is not particularly limited. In this embodiment, the width of metal layer 16 is greater than 1.0 μm and less than 3.0 μm. However, the lower limit of the width of metal layer 16 may be the minimum width that can be exposed.

[0075] like Figure 4AAs shown, insulating layers 17 and 18 are provided on the source electrode 14, the drain electrode 15, and the metal layer 16. The insulating layers 17 and 18 each function as a passivation layer. In this embodiment, a silicon oxide layer is used as the insulating layer 17. In addition, a silicon nitride layer is used as the insulating layer 18. In addition to serving as a passivation layer, the insulating layer 17 also has the function of supplying oxygen to the oxide semiconductor layer 30. Therefore, as the material of the insulating layer 17, a material with a relatively high oxygen content, such as silicon oxide or silicon oxynitride, is preferably used. In contrast, the insulating layer 18 mainly serves as a passivation layer. Therefore, a dense silicon nitride layer is preferably used as the insulating layer 18.

[0076] [Structure of Oxide Semiconductor Layer 30]

[0077] In the thin film transistor 10 of this embodiment, the oxide semiconductor layer 30 is divided into a plurality of channel regions by the metal layer 16. Specifically, the oxide semiconductor layer 30 of this embodiment is divided into two channel regions (channel region 31 and channel region 32) by one metal layer 16. A separation region 33 is provided between the channel region 31 and the channel region 32. The separation region 33 corresponds to the region in contact with the metal layer 16. That is, the separation region 33 is formed along the channel region 31 and the channel region 32. Figure 4B The direction D2 shown is arranged so as to cross the oxide semiconductor layer 30 . Therefore, the channel region 31 and the channel region 32 are separated from each other by the separation region 33 .

[0078] The oxide semiconductor layer 30 of this embodiment is indium gallium zinc oxide (IGZO), so it has the following physical property: when oxygen is released from the inside of the layer to the outside, the resistance of the part where oxygen is released is reduced. Therefore, when other metal layers are in contact with the oxide semiconductor layer 30, the oxidation of the other metal layers causes oxygen to be released from the inside of the oxide semiconductor layer 30. In other words, the oxide semiconductor layer 30 of this embodiment has a physical property that reduces the resistance of the part in contact with the other metal layers and the vicinity thereof. Therefore, in the oxide semiconductor layer 30 of this embodiment, due to the influence of the source electrode 14, the drain electrode 15, and the metal layer 16, multiple regions with lower resistance than the channel regions 31 and 32 are formed.

[0079] Specifically, if Figure 4A As shown, a source region 34 and a drain region 35 are formed in the regions of the oxide semiconductor layer 30 that are in contact with the source electrode 14 and the drain electrode 15, respectively. Furthermore, the aforementioned separation region 33 is formed in the region that is in contact with the metal layer 16. In this case, the separation region 33, the source region 34, and the drain region 35 all have substantially the same resistance (conductivity).

[0080] Furthermore, low-resistance regions 36 to 39 are formed in the oxide semiconductor layer 30 in regions adjacent to the separation region 33, the source region 34, and the drain region 35. Low-resistance regions 36 to 39 are regions where oxygen is released due to the influence of both the source electrode 14, the drain electrode 15, and the metal layer 16. Each of low-resistance regions 36 to 39 has a lower resistance than the channel regions 31 and 32, and a higher resistance than the separation region 33, the source region 34, and the drain region 35. Low-resistance regions 36 to 39 function as buffer regions that mitigate electric field concentration near the drain region 35. Such buffer regions are effective as a countermeasure against hot carriers.

[0081] As described above, the isolation region 33, the source region 34, the drain region 35, and the low-resistance regions 36 to 39 are formed by oxygen desorption from the interior of the oxide semiconductor layer 30. Therefore, the oxygen concentration in these regions is lower than the oxygen concentration in the channel regions 31 and 32. Furthermore, the oxygen concentration in the low-resistance regions 36 to 39 is higher than the oxygen concentration in the isolation region 33, the source region 34, and the drain region 35, and lower than the oxygen concentration in the channel regions 31 and 32.

[0082] As described above, the thin-film transistor 10 of this embodiment has two channel regions 31 and 32 within a single oxide semiconductor layer 30. Here, the gate electrode 11 overlaps both the channel regions 31 and 32 via the insulating layers 12 and 13. Therefore, the thin-film transistor 10 of this embodiment essentially has a structure in which two thin-film transistors are connected in series. In this case, the separation region 33 functions as the drain region of the thin-film transistor 10-1 and as the source region of the thin-film transistor 10-2.

[0083] The thin-film transistor 10 of this embodiment has a structure in which thin-film transistors 10-1 and 10-2 are connected in series. Therefore, even if one thin-film transistor experiences an abnormality such as a short circuit, the entire thin-film transistor can maintain its function as a switching element as long as the other thin-film transistor operates normally. In other words, the thin-film transistor 10 of this embodiment only requires that at least one of the thin-film transistors 10-1 and 10-2 operate normally. This provides redundancy in the thin-film transistor 10.

[0084] An example of a cause of abnormal operation of the thin film transistor 10-1 or 10-2 is that the thin film transistor 10-1 or 10-2 may switch to a depletion-type operation due to the influence of hydrogen mixed into the channel region 31 or 32. In other words, due to the mixing of hydrogen into the channel region 31 or 32, the thin film transistor 10-1 or 10-2 may be permanently in the on state.

[0085] The aforementioned hydrogen incorporation may occur, for example, when impurities containing hydrogen adhere to or enter channel regions 31 or 32. Impurities include, for example, particles resulting from the formation of insulating layers 12, 13, 17, or 18. The raw material gases used to form these insulating layers (silicon oxide layers or silicon nitride layers) contain hydrogen. Therefore, if particles from these insulating layers adhere to or enter channel regions 31 or 32, the particles become a source of hydrogen.

[0086] However, in this embodiment, even if the channel region 32 of the thin-film transistor 10-2 is depleted due to hydrogen, the diffusion of hydrogen stops in the separation region 33, thereby preventing the adjacent channel region 31 from being affected. In other words, the separation region 33 functions as a barrier to the movement of hydrogen between the channel regions 31 and 32. Furthermore, since a metal material capable of absorbing hydrogen, such as titanium or molybdenum, is used as the material for the metal layer 16, the metal layer 16 also functions as a barrier to the movement of hydrogen.

[0087] Therefore, the thin film transistors 10-1 and 10-2 can operate in a complementary manner, providing redundancy to the operation of the thin film transistor 10. Furthermore, according to this embodiment, there is no need to physically separate the oxide semiconductor layer 30; only the metal layer 16 is required. This allows for a reduction in the size of the thin film transistor 10. Thus, according to this embodiment, the area occupied by the thin film transistor 10 can be reduced while improving the reliability of the display device 100.

[0088] [Method of Manufacturing Thin Film Transistor 10]

[0089] Figure 5A 、 Figure 6A 、 Figure 7A 、 Figure 8A and Figure 9A It is a cross-sectional view showing a method for manufacturing the thin film transistor 10 used in the display device 100 according to the first embodiment of the present invention. Figure 5B 、 Figure 6B 、 Figure 7B 、 Figure 8B and Figure 9B It is a plan view showing a method for manufacturing the thin film transistor 10 used in the display device 100 according to the first embodiment of the present invention.

[0090] First, if Figure 5A and Figure 5B As shown, the gate electrode 11 is formed on the substrate 110. Specifically, a metal layer containing a metal material (in this embodiment, aluminum and titanium) constituting the gate electrode 11 is formed. Then, the metal layer composed of the stacked aluminum and titanium is etched to form the gate electrode 11.

[0091] Then, if Figure 6A and Figure 6B As shown, insulating layers 12 and 13 are formed to cover the gate electrode 11. In this embodiment, a silicon nitride layer is first formed as the insulating layer 12. Then, a silicon oxide layer is formed on the insulating layer 12 as the insulating layer 13. After the insulating layer 13 is formed, the oxide semiconductor layer 30 is formed on the insulating layer 13. In this embodiment, an oxide semiconductor layer composed of indium gallium zinc oxide (IGZO) is first formed to a thickness of 40 nm to 100 nm. Then, the oxide semiconductor layer is etched to form the oxide semiconductor layer 30.

[0092] Then, if Figure 7A and Figure 7B As shown, the metal layer 20 is formed so as to cover the oxide semiconductor layer 30. The metal layer 20 is formed by stacking a titanium layer, an aluminum layer, and a titanium layer in this order from the bottom. In this embodiment, by providing a titanium layer as the bottom layer, the oxide semiconductor layer 30 and the aluminum layer are not in direct contact. This prevents excess oxygen from escaping from the oxide semiconductor layer 30 due to oxidation of the aluminum layer. In addition, as described above, the contact between the titanium layer and the oxide semiconductor layer 30 can prevent hydrogen from moving between adjacent channel regions.

[0093] Then, if Figure 8A and Figure 8B As shown in FIG. 1 , the metal layer 20 is etched to form the source electrode 14, the drain electrode 15, and the metal layer 16. Figure 8B As shown, the metal layer 16 is formed so as to cross the oxide semiconductor layer 30 in the direction D2. In this embodiment, the metal layer 16 is formed so as to be at the same or substantially the same distance from the source electrode 14 and the drain electrode 15. In this manner, the source electrode 14, the drain electrode 15, and the metal layer 16 are formed simultaneously using the same process. In other words, the source electrode 14, the drain electrode 15, and the metal layer 16 are elements provided in the same layer. However, this is not limiting, and the metal layer 16 may also be formed of a different metal material from the source electrode 14 and the drain electrode 15.

[0094] Then, if Figure 9A and Figure 9B As shown, an insulating layer 17 is formed to cover the source electrode 14, the drain electrode 15, the metal layer 16, and the oxide semiconductor layer 30. In this embodiment, a silicon oxide layer is formed as the insulating layer 17 to a thickness of not less than 100 nm and not more than 300 nm. In this embodiment, during the process of forming the insulating layer 17, channel regions 31 and 32, a separation region 33, a source region 34, a drain region 35, and low-resistance regions 36 to 39 are formed in the oxide semiconductor layer 30. Alternatively, a baking process may be performed on the insulating layer 17 after its formation.

[0095] During the aforementioned process of forming and baking insulating layer 17, oxygen is supplied from the silicon oxide layer serving as insulating layer 17 to channel regions 31 and 32. This allows the resistance of channel regions 31 and 32 to be adjusted so that they function normally as channels. Oxygen released from insulating layer 17 is also supplied to isolation region 33 and low-resistance regions 36 to 39. However, oxygen is removed from isolation region 33 and low-resistance regions 36 to 39 by the influence of metal layer 16. Consequently, the resistance of isolation region 33 and low-resistance regions 36 to 39 is lower than that of channel regions 31 and 32.

[0096] In completion Figure 9A and Figure 9B After the treatment, an insulating layer 18 is formed on the insulating layer 17. In this embodiment, a silicon nitride layer is formed as the insulating layer 18 with a thickness of 100 nm to 200 nm. Figure 4A and Figure 4B The structure of the thin film transistor 10 is described.

[0097] (Variation 1)

[0098] In this embodiment, examples of the material for the metal layer 16 include metal materials such as titanium, tantalum, tungsten, molybdenum, vanadium, or niobium, or alloy materials containing these metals. However, to further enhance the effect of hindering hydrogen migration, the material for the metal layer 16 may also include an alkali metal or an alkaline earth metal. For example, metal materials such as magnesium, calcium, and lanthanum, or alloy materials containing these metals, may also be used. In this case, for example, a laminated structure may be provided in which a metal layer containing an alkali metal or an alkaline earth metal is sandwiched between more stable metal layers such as titanium or molybdenum.

[0099] <Second embodiment>

[0100] In this embodiment, a display device having thin film transistors 10a and 10b having a structure different from that of the first embodiment is described. Specifically, the thin film transistors 10a and 10b of this embodiment have multiple metal layers in contact with the oxide semiconductor layer 30 between the source electrode and the drain electrode. This embodiment mainly describes the parts that differ from the first embodiment. In the drawings used to describe this embodiment, the same reference numerals are used for the same structures as in the first embodiment, and detailed descriptions are omitted.

[0101] Figure 10A It is a plan view showing the structure of a thin film transistor 10 a used in a display device according to a second embodiment of the present invention. Figure 10B1 is a plan view showing the structure of a thin film transistor 10b used in a display device according to Embodiment 2 of the present invention. In this embodiment, for convenience of description, the low resistance region described in Embodiment 1 is omitted from illustration.

[0102] Figure 10A The thin film transistor 10a shown has two metal layers 41a and 41b between the source electrode 14 and the drain electrode 15. The materials of the metal layers 41a and 41b are the same as those in the first embodiment, so their description is omitted here. By configuring the two metal layers 41a and 41b, three channel regions 51a, 51b, and 51c are formed in the oxide semiconductor layer 30. That is, the thin film transistor 10a essentially has a structure in which three thin film transistors 10a-1, 10a-2, and 10a-3 are connected in series. In this case, if at least any one of the three thin film transistors 10a-1, 10a-2, and 10a-3 operates normally, the thin film transistor 10a can maintain its function as a switching element.

[0103] Figure 10B The thin film transistor 10b shown has three metal layers 42a, 42b, and 42c between the source electrode 14 and the drain electrode 15. The materials of the metal layers 42a, 42b, and 42c are the same as those in the first embodiment, so their description is omitted here. By configuring the three metal layers 42a, 42b, and 42c, four channel regions 52a, 52b, 52c, and 52d are formed in the oxide semiconductor layer 30. That is, the thin film transistor 10b essentially has a structure in which four thin film transistors 10b-1, 10b-2, 10b-3, and 10b-4 are connected in series. In this case, if at least any one of the four thin film transistors 10b-1, 10b-2, 10b-3, and 10b-4 operates normally, the thin film transistor 10b can maintain its function as a switching element.

[0104] As described above, if the number of metal layers overlapping the oxide semiconductor layer 30 is increased, the number of channel regions also increases accordingly. Specifically, by overlapping n (n is a natural number) metal layers on the oxide semiconductor layer 30, (n+1) channel regions can be set between the source region and the drain region when viewed from above. In this way, according to this embodiment, by increasing the number of metal layers, the redundancy of the thin film transistor can be improved. As a result, the reliability of a display device having a thin film transistor with high redundancy as a switching element in each pixel can be improved.

[0105] In each of the above embodiments, an example display device is used for description. However, the present invention is not limited to this example, and each embodiment can be applied to all devices including devices using semiconductors, that is, semiconductor devices. In addition, as long as the above embodiments are not mutually contradictory, they can be appropriately combined and implemented. Based on each embodiment, a person skilled in the art can appropriately add, delete, or design a structure after the constituent elements are added, deleted, or the design is changed, or a structure after the process is added, omitted, or the conditions are changed. As long as the gist of the present invention is included, it is also included in the scope of the present invention.

[0106] Furthermore, other effects different from the effects brought about by the above-described embodiments that are clear from the description of this specification or can be easily predicted by those skilled in the art are of course also understood to be brought about by the present invention.

Claims

1. A semiconductor device having a thin film transistor in each pixel, characterized in that: The thin film transistor has: an oxide semiconductor layer; a gate insulating layer; a gate electrode overlapping the oxide semiconductor layer with the gate insulating layer interposed therebetween; a source electrode in contact with the oxide semiconductor layer; a drain electrode in contact with the oxide semiconductor layer; and n metal layers are in contact with the oxide semiconductor layer and are arranged between the source electrode and the drain electrode in a manner that crosses the oxide semiconductor layer, wherein n is a natural number, In a plan view, when the long side direction of the oxide semiconductor layer is a first direction and the long side directions of the n metal layers are a second direction orthogonal to the first direction, the length of the n metal layers in the second direction is greater than the length of the oxide semiconductor layer in the second direction, In a plan view, the n metal layers are in contact with the oxide semiconductor layer, so that the oxide semiconductor layer has n+1 channel regions separated from each other between the source electrode and the drain electrode. The oxide semiconductor layer has n low-resistance regions that are respectively in contact with the n metal layers and have lower resistance than the channel region. The low-resistance region has an oxygen concentration lower than that of the channel region.

2. The semiconductor device according to claim 1, wherein: When n is 1, the oxide semiconductor layer has a first channel region between the source electrode and the metal layer, and has a second channel region between the drain electrode and the metal layer in a plan view.

3. The semiconductor device according to claim 1, wherein: When n is 2, in a plan view, the oxide semiconductor layer has a first channel region between the source electrode and the first metal layer, a second channel region between the drain electrode and the second metal layer, and a third channel region between the first metal layer and the second metal layer.

4. The semiconductor device according to claim 1, wherein: The metal layer is provided at the same layer as the source electrode and the drain electrode.

5. The semiconductor device according to claim 1, wherein: The metal layer is made of the same metal material as that of the source electrode and the drain electrode.

6. The semiconductor device according to claim 1, wherein: The metal layer is electrically floating.

7. The semiconductor device according to claim 1, wherein: The n+1 channel regions are respectively separated by separation regions serving as the low resistance regions.

8. The semiconductor device according to claim 1, wherein: The metal layer is made of titanium or molybdenum.

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