Semiconductor devices, imaging elements, and electronic devices

Abstract

According to the present disclosure, a semiconductor device includes: a first charge accumulation unit, which is capable of accumulating charge; a first initialization unit, which is connected to the first charge accumulation unit and initializes the first charge accumulation unit; and a first voltage switching unit, which is connected to the first initialization unit and is capable of selectively supplying a first voltage and a second voltage different from the first voltage to the first initialization unit.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device, an imaging element, and an electronic device. Background Art

[0002] In recent years, imaging elements that include photoelectric conversion films sensitive to infrared light have attracted attention. For example, one such imaging element includes a photoelectric conversion element that includes a photoelectric conversion film formed using a III-V compound semiconductor such as indium gallium arsenide (InGaAs) and photoelectrically converts incident light to generate charge; and a semiconductor device that is bonded to the photoelectric conversion element, reads out the charge as a signal, and performs predetermined signal processing on the readout signal. This semiconductor device is sometimes referred to as a readout integrated circuit (ROIC) substrate.

[0003] Reference List

[0004] Patent Literature

[0005] Patent Document 1: JP 2016-213286 A Summary of the Invention

[0006] Technical issues

[0007] When performing the above-mentioned imaging element evaluation (operation test), even if a defect is found, it is sometimes difficult to determine whether the defect is in the photoelectric conversion unit or the ROIC substrate. If the evaluation is performed to detect defects in the ROIC substrate, this evaluation must be performed before the photoelectric conversion unit and ROIC substrate are bonded together.

[0008] Regarding integrated circuit testing, for example, a method for measuring leakage current between well regions formed in a semiconductor substrate is disclosed in Patent Document 1. However, Patent Document 1 does not mention evaluation of an ROIC substrate used with a photoelectric conversion unit or evaluation of an imaging element.

[0009] In view of the above circumstances, the present disclosure provides a readout semiconductor device capable of performing circuit evaluation regardless of the presence or absence of a photoelectric conversion unit, and an image pickup element and an electronic device including the readout semiconductor device.

[0010] Technical solutions to the problem

[0011] According to a first embodiment of the present disclosure, a semiconductor device is provided, which includes: a first charge accumulation unit capable of accumulating charge; a first initialization unit that initializes the first charge accumulation unit; and a voltage switching unit that can selectively supply a first voltage and a second voltage different from the first voltage to the first initialization unit.

[0012] According to a second embodiment of the present disclosure, there is provided an imaging element, which includes: a photoelectric conversion unit that receives light and performs photoelectric conversion on the received light to generate electric charge; a first charge accumulation unit that is capable of accumulating the electric charge; a first initialization unit that is connected to the first charge accumulation unit and initializes the first charge accumulation unit; and a voltage switching unit that is connected to the first initialization unit and is capable of selectively supplying a first voltage and a second voltage different from the first voltage to the first initialization unit.

[0013] According to a third embodiment of the present disclosure, there is provided an imaging element, which includes: a first charge accumulation unit capable of accumulating charge; a first initialization unit connected to the first charge accumulation unit and initializing the first charge accumulation unit; a photoelectric conversion unit that receives light and performs photoelectric conversion on the received light to generate charge; a second charge accumulation unit capable of accumulating the charge generated by the photoelectric conversion unit and transferring the accumulated charge to the first charge accumulation unit; a second initialization unit connected to the second charge accumulation unit and initializing the second charge accumulation unit; and a voltage switching unit connected to the first initialization unit and the second initialization unit and capable of selectively supplying a first voltage and a second voltage different from the first voltage to the first initialization unit and the second initialization unit.

[0014] According to a fourth embodiment of the present disclosure, an electronic device is provided, which includes: an optical system; a photoelectric conversion unit that receives light from the optical system and performs photoelectric conversion on the received light to generate electric charge; a first charge accumulation unit that is capable of accumulating the electric charge; a first initialization unit that is connected to the first charge accumulation unit and initializes the first charge accumulation unit; and a voltage switching unit that is connected to the first initialization unit and is capable of selectively supplying a first voltage and a second voltage different from the first voltage to the first initialization unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is a partial cross-sectional view schematically showing the image pickup element according to the first embodiment.

[0016] Figure 2 is a schematic diagram showing an example of a circuit layout of an image pickup element according to the first embodiment.

[0017] Figure 3 is a schematic circuit diagram showing an example of a circuit configuration of each pixel in a semiconductor device included in the image pickup element according to the first embodiment.

[0018] Figure 4 It is a timing chart regarding the state of each circuit element of each pixel of the semiconductor device included in the image pickup element according to the first embodiment and the signal supplied to each circuit element.

[0019] Figure 5 is a schematic circuit diagram showing a first modification of the image pickup element according to the first embodiment.

[0020] Figure 6 is a schematic circuit diagram showing a second modification of the image pickup element according to the first embodiment.

[0021] Figure 7 is a schematic circuit diagram showing an example of a circuit configuration of each pixel of a semiconductor device included in an image pickup element according to the second embodiment.

[0022] Figure 8 It is a timing chart regarding the state of each circuit element of each pixel of the semiconductor device included in the image pickup element according to the second embodiment and the signal supplied to each circuit element.

[0023] Figure 9A is a partial plan view schematically showing an image pickup element according to a third embodiment.

[0024] Figure 9B is a partial cross-sectional view schematically showing an image pickup element according to a third embodiment.

[0025] Figure 10 is a partial cross-sectional view schematically showing an image pickup element according to a fourth embodiment.

[0026] Figure 11 1 is a schematic diagram illustrating an electronic device to which the image pickup element according to an embodiment of the present disclosure is applied.

[0027] Figure 12 is a block diagram showing an example of a schematic configuration of a vehicle control system to which the technology according to the present disclosure is applicable.

[0028] Figure 13 It is an explanatory diagram showing an example of the installation positions of the vehicle exterior information detection unit and the imaging unit.

[0029] Figure 14 is a diagram showing an example of a schematic configuration of an endoscopic surgery system.

[0030] Figure 15 is a block diagram showing an example of the functional configuration of a camera head and a CCU. DETAILED DESCRIPTION

[0031] Hereinafter, exemplary, non-limiting embodiments of the present disclosure will be described with reference to the accompanying drawings. Note that in the following embodiments, identical or corresponding parts or components will be represented by identical or corresponding reference numerals, and thus their repeated description will be omitted. Furthermore, the accompanying drawings are not intended to illustrate relative ratios between components or circuit elements, or the thicknesses of various layers. Therefore, those skilled in the art will need to determine specific dimensions and thicknesses based on the following non-limiting examples.

[0032] (First embodiment)

[0033] [Configuration of Image Pickup Element According to First Embodiment]

[0034] Will refer to Figure 1 An image pickup element according to a first embodiment of the present disclosure will be described. Figure 1 This is a partial cross-sectional view schematically illustrating an imaging element according to a first embodiment. As shown in the figure, the imaging element 1 includes a photoelectric conversion unit 100 and a readout integrated circuit (ROIC) substrate 200. The photoelectric conversion unit 100 receives light and photoelectrically converts the received light to generate a charge signal. The ROIC substrate 200 is bonded to the photoelectric conversion unit 100 and reads out the charge signal generated by the photoelectric conversion unit 100. The ROIC substrate 200 corresponds to a semiconductor device according to one embodiment of the present disclosure.

[0035] <Structure of Photoelectric Conversion Unit>

[0036] The photoelectric conversion unit 100 includes an insulating layer 11 , a contact layer 12 , a photoelectric conversion film 13 , an upper electrode layer 14 , and a transparent electrode layer 15 .

[0037] The insulating layer 11 is made of silicon oxide (SiO x ) and silicon nitride (SiN) and other insulating materials. The insulating layer 11 is provided with a plurality of lower electrodes 11A that penetrate the insulating layer 11 in the vertical direction (Z direction in the figure). The lower electrodes 11A are formed using a metal such as copper (Cu).

[0038] In this embodiment, contact layer 12 is formed using indium phosphide (InP). Zinc (Zn) is added to contact layer 12, giving it p-type conductivity. Furthermore, contact layer 12 is provided with a plurality of diffusion regions 12A, into which Zn is locally diffused at high concentrations. These diffusion regions 12A are arranged in a matrix within the XY plane defined by the X and Y directions shown in the figure. Lower electrodes 11A are provided corresponding to these diffusion regions 12A and are electrically connected to the corresponding diffusion regions 12A.

[0039] It is possible to use III-V compound semiconductors to form the photoelectric conversion film 13. In this embodiment, undoped indium gallium arsenide (InGaAs) is used to form the photoelectric conversion film 13. According to In x Ga (1-x) In the ratio x of In to Ga in As(x: 0 < x ≤ 1), InGaAs can have different wavelength sensitivity regions. In this embodiment, due to the lattice matching with the contact layer 12 and the upper electrode layer 14 (described later) formed of InP, the ratio x of In is set to 0.53. The energy band gap of InGaAs at this In ratio is approximately 0.728 eV, which corresponds to approximately 1.7 μm when converted to wavelength. The above-mentioned photoelectric conversion film 13 can generally be sensitive to wavelengths from 0.8 μm to 1.7 μm. Note that, without being limited to InGaAs, for example, other III-V compound semiconductors such as indium antimonide arsenide (InAsSb), indium arsenide (InAs), and indium antimonide (InSb), or II-VI compound semiconductors such as mercury cadmium telluride (HgCdTe) can be used to form the photoelectric conversion film 13. Additionally, compound semiconductors having a chalcopyrite structure such as CuGaInS mixed crystal, CuAlGaInS mixed crystal, and CuAlGaInSSe mixed crystal can also be used to form the photoelectric conversion film 13. Furthermore, elemental semiconductors such as silicon (Si), amorphous silicon (α-Si), and germanium (Ge) can also be used to form the photoelectric conversion film 13. Moreover, the photoelectric conversion film 13 can also be a quantum dot photoelectric conversion film, an organic photoelectric conversion film, etc.

[0040] An upper electrode layer 14 is formed on the photoelectric conversion film 13. In this embodiment, InP is used to form the upper electrode layer 14. N-type impurities such as sulfur (S) and selenium (Se) are added to the upper electrode layer 14 so that the upper electrode layer 14 has an n-type conductivity type.

[0041] A transparent electrode layer 15 is formed on the upper electrode layer 14. It is possible to use, for example, indium tin oxide (ITO) and zinc oxide (ZnO) to form the transparent electrode layer 15.

[0042] In the photoelectric conversion unit 100 having the above structure, a photodiode PD is formed by the diffusion region 12A (p + -InP), the photoelectric conversion film 13 (undoped InGaAs) on the diffusion region 12A, and the upper electrode layer 14 (n-InP) on the photoelectric conversion film 13. In this embodiment, one photodiode PD corresponds to one pixel. Since a plurality of diffusion regions 12A are arranged in a matrix, the photodiodes PD and the pixels are also arranged in a matrix.

[0043] <Operation of the photoelectric conversion unit>

[0044] When light is incident on the photoelectric conversion film 13 of the photodiode PD through the transparent electrode layer 15 and the upper electrode layer 14 in the photoelectric conversion unit 100, electron-hole pairs are generated in the photoelectric conversion film 13. At this time, when a reverse bias voltage is applied to the photodiode PD, a large potential gradient is generated in the photoelectric conversion film 13, causing the generated electrons and holes to separate. That is, the electrons reach the upper electrode layer 14, and the holes move to the diffusion region 12A of the contact layer 12. In this way, the charge signal corresponding to the incident light is read out by the readout integrated circuit substrate 200 through the lower electrode 11A.

[0045] <Structure of the ROIC Substrate>

[0046] The ROIC substrate 200 is a so-called multi-layer wiring board and includes an upper insulating layer 21, a lower insulating layer 22, and a silicon layer 23.

[0047] The upper insulating layer 21 is made of insulating materials such as silicon oxide (SiO x ) and silicon nitride (SiN). The upper insulating layer 21 is provided with a plurality of connection electrodes 21A penetrating the upper insulating layer 21 in the vertical direction. The connection electrodes 21A are formed of a metal such as copper (Cu). The connection electrodes 21A are electrically connected to the lower electrodes 11A of the photoelectric conversion unit 100 in a one-to-one relationship. This connection enables the charge signal from the photoelectric conversion unit 100 to be transmitted to the ROIC substrate 200. Note that the electrical connection between the connection electrode 21A and the lower electrode 11A can be achieved by directly bonding them. In addition, the connection electrode 21A and the lower electrode 11A can be electrically connected via metal bumps or the like. The photoelectric conversion unit 100 and the ROIC substrate 200 are integrated by bonding the connection electrode 21A to the lower electrode 11A.

[0048] Similar to the upper insulating layer 21, the lower insulating layer 22 is made of insulating materials such as silicon oxide (SiO x ) and silicon nitride (SiN). A plurality of wirings 22A and a plurality of vias 22B are buried in the lower insulating layer 22.

[0049] In the silicon layer 23, a plurality of metal oxide semiconductor (MOS) transistors 23N and 23P are formed on the interface side between the silicon layer 23 and the lower insulating layer 22. In the present embodiment, the silicon layer 23 is made of p-type silicon. A well region 23W formed using n-type silicon is provided in a portion of the silicon layer 23. Therefore, the MOS transistor 23P formed in the well region 23W is a P-channel MOS transistor, while the other MOS transistors 23N are N-channel MOS transistors. The MOS transistors 23N and 23P are appropriately electrically connected to the wiring 22A and the through-hole 22B in the lower insulating layer 22, thereby forming a pixel readout circuit 20 that reads out a charge signal from the photodiode PD (pixel) of the photoelectric conversion unit 100.

[0050] In addition, the ROIC substrate 200 can include a load transistor unit, a comparator circuit unit, and a counter unit as described later. Furthermore, the ROIC substrate 200 can also include a vertical scanning circuit, a horizontal scanning circuit, and an interface circuit for external devices and the like.

[0051] <Image Sensor Circuit Layout>

[0052] Next, we will refer to Figure 2 The overall circuit layout of the image pickup element 1 according to this embodiment will be described. Figure 2 1 is a schematic diagram illustrating an example of the circuit layout of an imaging element 1 according to this embodiment. As shown, the imaging element 1 includes a pixel array 110, load transistor units LMU and LMD, comparator circuit units CMU and CMD, and counter units CNU and CND. Furthermore, the imaging element 1 includes a horizontal scanning circuit and a vertical scanning circuit (neither shown).

[0053] A plurality of pixels 111 are arranged in a matrix in the pixel array 110 (for ease of explanation, Figure 2 1 shows one of the plurality of pixels 111). The pixel 111 includes a photoelectric conversion unit 100 ( Figure 1 ) and the pixel readout circuit 20 formed in the ROIC substrate 200. Furthermore, the pixel array 110 is provided with vertical signal lines VSL that output signals from the pixels 111. Among the plurality of pixels 111 arranged in a matrix, the plurality of pixels 111 arranged in a column in the vertical direction in the figure (the plurality of pixels 111 in the column direction) are electrically connected to one vertical signal line VSL. That is, the vertical signal lines VSL are provided for the plurality of pixels 111 in the column direction, and the number of columns is the same as the number of vertical signal lines VSL.

[0054] The load transistor unit LMU is arranged on the upper side of the figure relative to the pixel array 110, and the load transistor unit LMD is arranged on the lower side of the figure relative to the pixel array 110. The load transistor unit LMD is provided with a plurality of load transistors (not shown) corresponding to the vertical signal line VSL. The load transistors act as current sources of source followers when reading out pixel signals. The load transistors can be formed using MOS transistors. In addition, a load transistor is also formed in the load transistor unit LMU.

[0055] In addition, in each of the load transistor units LMU and LMD, wiring L VDD , wiring LV, wiring L1 and wiring L2. These wiring L VDD , LV, L1, and L2 extend along the longitudinal direction of the load transistor units LMU and LMD. In addition, a switching unit SW is provided in each of the load transistor units LMU and LMD. The switching unit SW is provided for each column C corresponding to the plurality of pixels 111 in the column direction.

[0056] The wiring L arranged in the load transistor unit LMU VDD and the wiring L arranged in the load transistor unit LMD VDD The pixels 111 are connected by wiring UD, and a power supply voltage is supplied from the wiring UD to each pixel 111. Specifically, the power supply voltage VDD is supplied from the wiring L to the pixel 111. VDD Supply to the following Figure 3 Shown are the storage node (SN) capacitor CPs, the floating diffusion (FD) capacitor CPf, and the drain of the amplification transistor Tamp.

[0057] The wiring LV, the wiring L1 , the wiring L2 , and the switching unit SW will be described in detail later.

[0058] The comparator circuit unit CMU is positioned above the load transistor unit LMU in the figure. Furthermore, the counter unit CNU is positioned above the comparator circuit unit CMU in the figure. The comparator circuit unit CMU and the counter unit CNU function as analog-to-digital conversion units. As a result, the analog charge signal output from the pixel 111 to the vertical signal line VSL via the pixel readout circuit 20 is converted into a digital signal. Under the control of the horizontal scanning circuit, the digital pixel signal is output to the subsequent circuit. The same applies to the comparator circuit unit CMD and the counter unit CND.

[0059] <Circuit Structure of Each Pixel>

[0060] Next, we will refer to Figure 3 An example of a circuit configuration of each pixel provided on the ROIC substrate 200 will be described. Figure 31 and 2 show one pixel 111 and a load transistor unit LMD among a plurality of pixels 111 in the column direction connected to one vertical signal line VSL. Figure 3 In FIG. 1 , the load MOS transistor provided in the load transistor unit LMD is shown as a current source CS. Note that in FIG. Figure 3 , the load transistor unit LMU arranged on the upper side of the pixel array 110 is omitted.

[0061] like Figure 3 As shown, in the pixel 111, the photodiode PD is electrically connected to the pixel readout circuit 20 through the storage node SN. This electrical connection corresponds to Figure 1 The connection between lower electrode 11A and connection electrode 21A is formed for storage node SN. SN capacitor CPs is formed for storage node SN. The charge signal from photodiode PD is accumulated in SN capacitor CPs via storage node SN. As a result, the charge amount of the charge signal is converted into a voltage value. Furthermore, storage node SN is electrically connected to the source of overflow gate (OFG) transistor Tofg and the drain of transfer transistor Ttrg.

[0062] A floating diffusion layer FD is provided on the source side of the transfer transistor Ttrg, and an FD capacitor CPf is formed for the floating diffusion layer FD. The source of the transfer transistor Ttrg is connected to the source of the reset transistor Trst. When a bias voltage (reset signal RST, described later) is applied to the gate of the reset transistor Trst, the reset transistor Trst turns on, and the FD capacitor CPf is reset (discharging the charge stored in the FD capacitor CPf).

[0063] Note that in this embodiment, the OFG transistor Tofg, the transfer transistor Ttrg, and the reset transistor Trst are P-channel MOS transistors (corresponding to Figure 1 MOS transistors 23P in FIG. 1 ). That is, these MOS transistors are normally off and are turned on when a negative voltage is applied to their gates.

[0064] In addition, the floating diffusion layer FD is connected to the gate of the amplifying transistor Tamp. The drain of the amplifying transistor Tamp is connected to the gate of the imaging element 1 ( Figure 1 and Figure 2 ) is external and outputs a predetermined power supply of the voltage VDD, the source of the amplifying transistor Tamp is connected to the drain of the selecting transistor Tsel. The amplifying transistor Tamp and the selecting transistor Tsel are N-channel MOS transistors (corresponding to Figure 1 MOS transistors 23N in FIG. 1 ). That is, these MOS transistors are normally off and are turned on when a positive voltage is applied to their gates.

[0065] When charges are stored in the FD capacitor CPf and a positive voltage is generated in the floating diffusion layer FD, when the selection transistor Tsel is turned on, a signal based on a charge signal generated by the photodiode PD is output to the load transistor unit LMD through the vertical signal line VSL.

[0066] The load transistor unit LMD includes a wiring LV. The wiring LV is connected to the image pickup element 1 ( Figure 2 ) is provided with a pad (not shown) in the outer edge portion (outer edge portion of the imaging element chip), and a predetermined external power source can be electrically connected to this pad. When imaging is performed using the imaging element 1 (during normal operation), power is supplied to supply a reset voltage to the OFG transistor Tofg and the reset transistor Trst. For example, the reset voltage is approximately 1.2V.

[0067] Wiring L VDR Electrically connected to wiring LV. Wiring L VDR The OFG transistor Tofg and the reset transistor Trst of each pixel 111 extend in the column direction (a direction parallel to the vertical signal line VSL) and supply a reset voltage to each pixel 111 in the plurality of pixels 111 arranged in the column direction. Specifically, each pixel 111 is provided with a wiring L VDR Wiring LO electrically connected to the OFG transistor Tofg VDR And the wiring L VDR Wiring LR electrically connected to the reset transistor Trst VDR .

[0068] Furthermore, wiring LV is provided with a switching unit SW. The switching unit SW includes a first switch SW1 and a second switch SW2. The first switch SW1 and the second switch SW2 selectively switch on and off. Specifically, when the first switch SW1 is on, the second switch SW2 is off, and when the first switch SW1 is off, the second switch SW2 is on. Switches SW1 and SW2 of the switching unit SW can be implemented using one or more MOS transistors. In this case, the MOS transistors can be either N-channel MOS transistors or P-channel transistors. Alternatively, the switching unit SW can be implemented using complementary metal oxide semiconductor (CMOS) transistors.

[0069] In detail, the first switch SW1 is connected to the wiring L at one end. VDR , and is connected to the wiring L1 at the other end. The wiring L1 is electrically connected to the imaging element 1 ( Figure 1 and Figure 2 ) is provided with a test pad (not shown) for the wiring L1 in the outer edge portion (outer edge portion of the imaging element chip). If a predetermined external power source that outputs a voltage VDR1 to the test pad is electrically connected, when the first switch SW1 is turned on, the voltage VDR1 can be output through the wiring L1, the wiring LVDR and wiring LO VDR The voltage VDR1 is applied to the drain of the OFG transistor Tofg and can be connected to the drain of the OFG transistor Tofg via the wiring L1 and the wiring L VDR and wiring LR VDR The voltage VDR1 is applied to the drain of the reset transistor Trst. Note that the voltage VDR1 may be any voltage as long as it is lower than the withstand voltage of the reset transistor Trst and the OFG transistor Tofg.

[0070] On the other hand, the second switch SW2 is connected to the wiring L at one end. VDR , and is connected to the wiring L2 at the other end. The wiring L2 is connected to the imaging element 1 ( Figure 1 and Figure 2 ) is used as a test pad for the wiring L2 in the outer edge portion (not shown). If a predetermined external power source that outputs a voltage VDR2 to the test pad is electrically connected, when the second switch SW2 is turned on, the wiring L2, the wiring L VDR and wiring LO VDR The voltage VDR2 is applied to the drain of the OFG transistor Tofg and can be connected to the drain of the OFG transistor Tofg via the wiring L2 and the wiring L VDR and wiring LR VDR The voltage VDR2 is applied to the drain of the reset transistor Trst. For example, the voltage VDR2 may be 1.2 V or approximately 1.2 V. That is, the voltage VDR2 can be made the same as the reset voltage supplied from the wiring LV.

[0071] As described above, the switching unit SW forms a voltage switching unit that supplies voltages having different voltage values ​​to the OFG transistor Tofg and the reset transistor Trst, respectively. Furthermore, the wiring LV, the wiring L1, and the wiring L2 extend horizontally through the load transistor unit LMD, and the switching unit SW is provided for the plurality of pixels 111 arranged in the column direction.

[0072] Notice, Figure 3The wiring L3 shown is a wiring for supplying a drive signal for driving the switching unit SW. The switching unit SW can be operated by supplying a drive signal to the wiring L3 from outside the imaging element 1. In addition, similar to the wiring LV, the wiring L1, and the wiring L2, the wiring L3 is also formed in the load transistor unit LMD. Note that, for example, in the case where the switch SW1 of the switching unit SW is configured using a P-channel MOS transistor and the switch SW2 is configured using an N-channel MOS transistor, by connecting one of the source and drain of the P-channel MOS transistor (SW1) to the wiring LV and the other to the wiring L1, connecting one of the source and drain of the N-channel MOS transistor (SW2) to the wiring LV and the other to the wiring L2, and connecting the gates of these two MOS transistors to the wiring L3, the wiring L3 can be used to selectively turn on and off the switches SW1 and SW2. In addition, when switches SW1 and SW2 are constructed using P-channel MOS transistors (or N-channel MOS transistors), by providing an additional wiring L3, connecting one wiring L3 to the gate of one P-channel MOS transistor (or N-channel MOS transistor), and connecting another wiring L3 to the gate of another P-channel MOS transistor (or N-channel MOS transistor), and alternately applying gate voltages, switches SW1 and SW2 can be selectively turned on and off.

[0073] like Figure 2 As shown, the voltage to be supplied to the corresponding wiring in the load transistor unit LMD is supplied from a predetermined external power supply to the wiring LV, wiring L1, wiring L2, and wiring L3 arranged in the load transistor unit LMU. In addition, the switching unit SW of the load transistor unit LMU and the switching unit SW of the load transistor unit LMD can be synchronously controlled. For example, when it is difficult to sufficiently ensure the wiring L provided on the ROIC substrate 200 VDR When the line width is equal to that of VDR The resistance may increase, but if the switching unit SW, wiring LV, wiring L1, wiring L2 and wiring L3 on both sides of the pixel array 110 are used, a predetermined voltage can be easily supplied to all pixels 111 of the pixel array 110.

[0074] [Operation of Pixel Readout Circuit of Image Pickup Element During Image Pickup According to First Embodiment]

[0075] Next, we will refer to Figures 1 to 3 The operation of the pixel readout circuit 20 of the image pickup element 1 during image pickup (normal operation) will be described.

[0076] During image pickup, a predetermined external power source for outputting a reset voltage (eg, 1.2 V) is connected to the wiring LV, but corresponding power sources are not connected (not supplying voltage) to the wiring L1 and the wiring L2 .

[0077] First, under the control of the vertical scanning circuit, the OFG transistor Tofg and the transfer transistor Ttrg are turned off. Next, when a negative voltage is applied to the gate so that the OFG transistor Tofg is turned on, the OFG transistor Tfg is turned on by the wiring L VDR and wiring LV to reset the photodiode PD and the SN capacitor CPs.

[0078] Next, after a predetermined time has passed, the reset transistor Trst is turned on under the control of the vertical scanning circuit, and the FD capacitor CPf is reset. After a predetermined time has passed, the reset transistor Trst is turned off again, and the resetting of the FD capacitor CPf is completed.

[0079] Then, the photodiode PD is exposed. As a result, charge is generated in the photodiode PD, and the generated charge is accumulated in the SN capacitor CPs. During the exposure of the photodiode PD, under the control of the vertical scanning circuit, a positive voltage is applied to the gate of the selection transistor Tsel, so that the selection transistor Tsel is turned on. As a result, the charge of the reset FD capacitor CPf is read out to the vertical signal line VSL. That is, the readout of the noise component of the pixel 111 (readout of the pre-charge phase (hereinafter referred to as P-phase readout)) is performed. After the P-phase readout is completed, the reset transistor Trst and the selection transistor Tsel are turned off.

[0080] After the exposure of the photodiode PD is completed, when a negative voltage is applied to the gate of the transfer transistor Ttrg under the control of the vertical scanning circuit, the transfer transistor Ttrg turns on, and the charge accumulated in the SN capacitor CPs is transferred to the FD capacitor CPf. When the select transistor Tsel turns on again at the timing predicted to complete the transfer, the voltage of the floating diffusion layer FD is output to the vertical signal line VSL. The voltage of the floating diffusion layer FD at this time is based on the charge generated by the photodiode PD, that is, the charge signal based on the amount of light received is read out to the vertical signal line VSL. In other words, the data (Data) phase readout during imaging is performed (hereinafter referred to as D-phase readout). Under the control of the horizontal scanning circuit and the vertical scanning circuit, this operation is performed for all pixels 111, and signals are read out from all pixels 111 to form an image.

[0081] Here, by obtaining the difference between the signal read out by the D-phase readout and the signal read out by the P-phase readout, offset noise can be removed, essentially extracting only the signal component. This signal component undergoes analog-to-digital conversion via the load transistor unit LMU (LMD) and the comparator circuit unit CMU (CMD) and the counter unit CNU (CND). This digital signal is output to the outside of the imaging element 1 via a predetermined logic circuit.

[0082] [Operation of the Pixel Readout Circuit of the Image Pickup Element During Evaluation According to the First Embodiment]

[0083] Next, in addition to Figure 3 In addition, reference will be made to Figure 4 The operation for evaluating the pixel readout circuit 20 will be described. Figure 4 1 is a timing chart showing ON / OFF timing of signals supplied to each circuit element of the pixel readout circuit 20 and the state of each circuit element.

[0084] Note that the operations to be described below are not Figure 1 and Figure 2 ) during imaging (or in a normal state), but rather the operation of the ROIC substrate 200 of the imaging element 1 during evaluation. In addition, during operation, the connection to Figure 2 That is, instead of supplying voltage to the wiring LV from the external power supply, the wiring L1 or the wiring L2 is selectively connected to the wiring LV by the switching unit SW to supply different voltages to the wiring LV (and the wiring L1). VDR ), which is different from when shooting. In addition, the following operation can be achieved using a predetermined evaluation device. That is, the following operation can be achieved by supplying various signals described below from the evaluation device to the ROIC substrate 200.

[0085] refer to Figure 4 In the initial state before time t0 (left side in the figure), the selection signal SEL, reset signal RST, transfer signal TRG, and overflow gate signal OFG are disconnected under the control of the evaluation device. Here, the selection signal SEL is a signal supplied to the gate of the selection transistor Tsel, the reset signal RST is a signal supplied to the gate of the reset transistor Trst, the transfer signal TRG is a signal supplied to the gate of the transfer transistor Ttrg, and the overflow gate signal OFG is a signal supplied to the gate of the OFG transistor Tofg.

[0086] In addition, in the initial state, the switching unit SW ( Figure 3 ), the first switch SW1 is set to OFF and the second switch SW2 is set to ON. Therefore, the voltage of the drain of the reset transistor Trst and the OFG transistor Tofg is equal to the voltage VDR2 (for example, 1.2 V) of the wiring L2.

[0087] At time t0, the output from the evaluation device to the wiring L3 ( Figure 3) command signal switches the first switch SW1 and the second switch SW2 of the switching unit SW. Specifically, the first switch SW1 is turned on, and the second switch SW2 is turned off. As a result, the voltage VDR1 of the wiring L1 is applied to the drains of the reset transistor Trst and the OFG transistor Tofg. In this embodiment, the voltage VDR1 of the wiring L1 is set to a voltage lower than the withstand voltage of the reset transistor Trst and the OFG transistor Tofg, and higher than the voltage VDR2 of the wiring L2. Consequently, the voltage VDR of the drains of the reset transistor Trst and the OFG transistor Tofg increases compared to the voltage in the initial state.

[0088] At time t1, when overflow gate signal OFG is turned on under the control of the evaluation device—that is, when a predetermined negative voltage is applied to the gate of OFG transistor Tofg—OFG transistor Tofg turns on. As a result, the voltage of storage node SN reaches voltage VDR1, and charge accumulates in SN capacitor CPs. For convenience, the amount of charge in SN capacitor CPs at this time is denoted by Csn.

[0089] At time t2, when the overflow gate signal OFG is turned off under the control of the evaluation device, the OFG transistor Tofg is turned off and the storage node SN is electrically isolated. At this time, the voltage Vsn of the storage node SN is still the voltage VDR1 because the charge is accumulated in the SN capacitor CPs.

[0090] At time t3 , when the first switch SW1 is turned off and the second switch SW2 is turned on by the instruction signal output from the evaluation device to the wiring L3 , the voltage VDR of the drains of the reset transistor Trst and the OFG transistor Tofg becomes the voltage VDR2 (the voltage of the wiring L2 ) again.

[0091] At time t4, when the reset signal RST is turned on under the control of the evaluation device and a predetermined negative voltage is applied to the gate of the reset transistor Trst, the reset transistor Trst turns on. As a result, the floating diffusion layer FD (FD capacitor CPf) is reset. Thereafter, at time t5, the reset signal RST is turned off. Note that the storage node SN is also electrically isolated between times t4 and t5, and the charge level of the SN capacitor CPs remains substantially unchanged. That is, the voltage Vsn of the storage node SN remains at the voltage VDR1.

[0092] At time t6, when the transfer signal TRG is turned on under the control of the evaluation device and a predetermined negative voltage is applied to the gate of the transfer transistor Ttrg, the transfer transistor Ttrg turns on. As a result, conduction is achieved between the storage node SN and the floating diffusion layer FD, and a portion of the charge accumulated in the SN capacitor CPs moves to the FD capacitor CPf. Here, the voltage Vsn of the storage node SN and the voltage Vfd of the floating diffusion layer FD are divided by the charge Csn of the SN capacitor CPs and the charge Cfd of the FD capacitor CPf. Since the charge Csn and the charge Cfd are equal, the voltage Vsn of the storage node SN and the voltage Vfd of the floating diffusion layer FD are equal. Specifically, these voltages Vsn and Vfd are (voltage VDR1 + voltage VDR2) / 2. In this embodiment, since voltage VDR1 is higher than voltage VDR2, voltages Vsn and Vfd at this time are higher than voltage VDR2 as shown in the figure.

[0093] At time t7 when a time sufficient for a part of the charge accumulated in the SN capacitor CPs to move to the FD capacitor CPf has passed, the transfer signal TRG is turned off.

[0094] Subsequently, at time t8, when overflow gate signal OFG is turned on under the control of the evaluation device, OFG transistor Tofg turns on. At this point, second switch SW2 turns on, causing voltage Vsn of storage node SN to become substantially equal to voltage VDR2 of wiring L2. In other words, the state of storage node SN returns to its initial state. On the other hand, since transfer transistor Ttrg is off, voltage Vfd of floating diffusion layer FD remains (voltage VDR1 + voltage VDR2) / 2.

[0095] Then, at time t9, when the selection signal SEL is turned on under the control of the evaluation device, turning on the selection transistor Tsel, the voltage Vfd of the floating diffusion layer FD is read out to the vertical signal line VSL. As described above, the voltage Vfd of the floating diffusion layer FD at this time is higher than 1.2V (voltage VDR2). When imaging is performed using the imaging element 1, this voltage is obtained by transferring the charge accumulated in the SN capacitor CPs to the FD capacitor CPf as a charge signal from the photodiode PD. In other words, this readout of the voltage Vfd of the floating diffusion layer FD corresponds to the readout of the data phase during imaging (hereinafter referred to as D-phase readout).

[0096] Next, at time t10, the selection signal SEL is turned off, and then at time t11, the reset signal RST is turned on. As a result, the reset transistor Trst is turned on, and the FD capacitor CPf is reset. That is, the voltage Vfd of the floating diffusion layer FD becomes the voltage VDR2.

[0097] Subsequently, at time t13, when the selection signal SEL is turned on again under the control of the evaluation device, turning on the selection transistor Tsel, the voltage Vfd of the floating diffusion layer FD is read out to the vertical signal line VSL. The voltage Vfd of the floating diffusion layer FD at this time is voltage VDR2. This readout corresponds to noise readout, i.e., P-phase readout.

[0098] Note that the period between time t9 and time t14 corresponds to one AD period. The AD period is a period required for a charge signal based on the charge generated in the photodiode PD of the photoelectric conversion unit 100 to be read out by the pixel readout circuit 20, and to be analog-to-digital converted by the comparator circuit unit CMU (CMD) and the counter unit CNU (CND) after passing through the load transistor unit LMU (LMD).

[0099] Finally, at time t14, the selection signal SEL is turned off under the control of the evaluation device, and the series of evaluation operations ends. Under the control of the horizontal scanning circuit and the vertical scanning circuit, this series of evaluation operations is performed on all pixels 111, and the evaluation of the pixel readout circuit 20 for all pixels 111 of the ROIC substrate 200 ends.

[0100] As described above, with the image sensor 1 according to this embodiment, by operating the switching unit SW provided in the load transistor unit LMD (LMU) of the ROIC substrate 200, different voltages can be applied from the wirings L1 and L2 to the drain of the OFG transistor Tofg and the drain of the reset transistor Trst. This allows the voltage Vfd of the floating diffusion layer FD to have a voltage value corresponding to the voltage value during D-phase readout, even when no charge signal is output from the photodiode PD of each pixel 111. In other words, it is possible to generate a situation where the voltage Vfd corresponding to D-phase readout differs from that corresponding to P-phase readout. Therefore, the pixel readout circuit 20 can be evaluated for both D-phase and P-phase readout without using the charge signal from the photodiode PD. Therefore, even when the photoelectric conversion unit 100 and the ROIC substrate 200 are bonded, it is possible to evaluate whether the ROIC substrate 200 is operating normally, independent of the operation of the pixels 111 of the photoelectric conversion unit 100.

[0101] Furthermore, since the photoelectric conversion unit 100 does not need to be irradiated with light, the ROIC substrate 200 can be evaluated even before the two are bonded. Therefore, by bonding the photoelectric conversion unit 100 to the ROIC substrate 200 after evaluating the ROIC substrate 200 before bonding, the photoelectric conversion unit 100 can be easily evaluated as an imaging element after bonding. Furthermore, imaging elements with higher reliability can be manufactured using ROIC substrates 200 that have been confirmed to be operating normally through this evaluation. This can also reduce costs and prices by improving manufacturing yields for imaging elements.

[0102] The photoelectric conversion unit 100 of the imaging element 1 includes an InGaAs film as the photoelectric conversion film 13. However, the present invention is not limited to this, and various photoelectric conversion units 100 having wavelength sensitivities corresponding to the type of III-V compound semiconductor and the composition of the III-V compound semiconductor mixed crystal can be prepared. When the photoelectric conversion unit 100 and the ROIC substrate 200 are bonded together, various imaging elements can be manufactured. In other words, the ROIC substrate 200 can exist as a single semiconductor device.

[0103] In addition, it is also possible to repeat the above timing chart ( Figure 4 ) is used to evaluate the linearity of the output characteristics of the ROIC substrate 200. Even when the photoelectric conversion unit 100 and the ROIC substrate 200 are bonded, this evaluation can be performed by measuring the output of the ROIC substrate 200 while varying the intensity of the light irradiating the photoelectric conversion unit 100. However, the above-described operation makes it easier to evaluate the linearity than when controlling the intensity of the light irradiating the photoelectric conversion unit 100.

[0104] Note that during image capture by the image sensor 1, the second switch SW2 of the switching unit SW can be turned on. Consequently, a voltage VDR2 (1.2 V) can be supplied from a predetermined external power source to the wiring L2, and a reset voltage (1.2 V) can be supplied from both the wiring LV and the wiring L2 to the OFG transistor Tofg and the reset transistor Trst. Consequently, the reset voltage can be stably supplied to each pixel 111 in the pixel array 110.

[0105] [Modification (1) of the first embodiment]

[0106] Next, we will refer to Figure 5A first modification of the image pickup element 1 according to the first embodiment will be described. The first modification differs from the first embodiment in that a switching unit SWA is used instead of the switching unit SW in the load transistor units LMU and LMD, and the wiring L2 is not provided. Apart from these differences and the changes caused by these differences, the first modification is basically the same as the first embodiment in other configurations including the overall circuit layout. Hereinafter, the differences from the ROIC substrate 200 in the first embodiment will be mainly described. Note that even in Figure 5 , the load transistor unit LMU arranged on the upper side of the pixel array 110 is also omitted.

[0107] like Figure 5 As shown, in the first modification, the wiring LV and the wiring L1 are provided in the load transistor unit LMD, and the wiring L1 of the first embodiment (see FIG. 1 ) is not provided. Figure 3 ) in the wiring L2. In addition, the load transistor unit LMD is provided with a switching unit SWA instead of the switching unit SW in the first embodiment. The switching unit SWA has one contact at one end and two contacts at the other end. One contact at the one end is connected to the wiring L VDR One of the two contacts at the other end is connected to the wiring L1, and the other contact is connected to the wiring LV. The switching unit SWA operates so that the wiring LV and the wiring L1 are selectively connected to the wiring L1. VDR The switching unit SWA constructed in this manner can also be formed using one or more MOS transistors. For example, one of the source and drain of an N-channel MOS transistor can be connected to the wiring L1, and the other can be connected to the wiring L2. VDR , connect one of the source and drain of the P-channel MOS transistor to the wiring LV, and connect the other to the wiring L VDR , and the gates of these two MOS transistors are connected to the wiring L3. As a result, the switching unit SWA can be operated so that the wiring LV and the wiring L1 are selectively connected to the wiring L3. VDR In addition, the switching unit SWA can be formed using CMOS transistors.

[0108] As described above, the wiring L1 is electrically connected to a predetermined external power source that outputs the voltage VDR1 via a predetermined test pad. When the switching unit SWA is switched to the wiring L1 side, the wiring L1 is electrically connected to a predetermined external power source that outputs the voltage VDR1. VDR and wiring LO VDR The voltage VDR1 is applied to the drain of the OFG transistor Tofg and is connected to the drain of the OFG transistor Tofg via the wiring L VDR and wiring LR VDR The voltage VDR1 is applied to the drain of the reset transistor Trst.

[0109] As described above, the wiring LV is electrically connected to a predetermined external power source that outputs a reset voltage via a predetermined pad. When the switching unit SWA is switched to the wiring LV side, the wiring LV is electrically connected to a predetermined external power source that outputs a reset voltage via the wiring LV. VDR and wiring LO VDR A reset voltage is applied to the drain of the OFG transistor Tofg and is reset through the wiring L VDR and wiring LR VDR A reset voltage is applied to the drain of the reset transistor Trst.

[0110] Here, for example, the reset voltage is approximately 1.2V, and is therefore substantially equal to the voltage supplied from the wiring L2 to the drain of the OFG transistor Tofg and the drain of the reset transistor Trst in the first embodiment. In other words, it can be said that instead of supplying the voltage VDR2 (for example, 1.2V) from the wiring L2, a substantially equal voltage is supplied from the wiring LV. Therefore, in the ROIC substrate according to this modification, it is also possible to implement the reference Figure 4 That is, even with this modification, the ROIC substrate can be evaluated regardless of whether the photoelectric conversion unit 100 is irradiated with light or whether the photoelectric conversion unit 100 is provided.

[0111] In addition, in the first modification, since the wiring LV can be used instead of the wiring L2 of the ROIC substrate 200 according to the first embodiment, the number of wirings formed in the ROIC substrate can be reduced.

[0112] Note that when imaging is performed in the imaging element to which the ROIC substrate according to the first modification is applied (in the case of normal operation), the switching unit SWA switches to the wiring LV side, and the reset voltage is supplied to the OFG transistor Tofg and the reset transistor Trst through the wiring LV and the switching unit SWA.

[0113] [Variation (2) of the first embodiment]

[0114] Then, reference will be made to Figure 6 A second modification of the image sensor 1 according to the first embodiment will be described. In the second modification, an ROIC substrate having a different structure from the ROIC substrate 200 of the image sensor 1 is used. The ROIC substrate in the second modification differs from the ROIC substrate 200 according to the first embodiment in that a switching unit SWB is used instead of the switching unit SW ( Figure 3 ). Except for these differences and the changes caused by these differences, the second modification and the first embodiment are basically the same in other configurations including the overall circuit layout. Note that even in Figure 6 , the load transistor unit LMU arranged on the upper side of the pixel array 110 is also omitted.

[0115] Switching unit SWB includes a first switch SW1 disposed between wiring LV and wiring L1, and second switches SW21 and SW22 disposed between wiring LV and wiring L2. Second switches SW21 and SW22 are simultaneously turned on and off, and are selectively turned on and off relative to first switch SW1. Specifically, when second switches SW21 and SW22 are on, first switch SW1 is off; when second switches SW21 and SW22 are off, first switch SW1 is on. Switching unit SWB can be constructed using MOS transistors, etc., similar to switching unit SW in the first embodiment.

[0116] With the above configuration, it is possible to perform reference to the pixel readout circuit 20. Figure 4 The evaluation operation is described in the timing diagram shown in FIG. Figure 4 The second switches SW21 and SW22 of this modification are similarly operated. As a result, even in the ROIC substrate according to the second modification, the same effects as those of the ROIC substrate 200 in the first embodiment can be exerted.

[0117] In addition, by turning on the second switches SW21 and SW22 of the switching unit SWB and supplying the voltage VDR2 (1.2V) from a predetermined external power source to the wiring L2, a reset voltage (1.2V) can be supplied from the wiring LV and the wiring L2 to the OFG transistor Tofg and the reset transistor Trst. As a result, the reset voltage can be stably supplied to each pixel 111 in the pixel array 110. In this case, only one of the second switches SW21 and SW22 can be turned on.

[0118] (Second embodiment)

[0119] Next, we will refer to Figure 7 The imaging element according to the second embodiment of the present disclosure is described. In the second embodiment, as Figure 7 As shown, the pixel 111 ( Figure 3 ) different pixel 111A, and the pixel 111A is provided with a pixel readout circuit 20A. Except for these differences and changes based on these differences, the second embodiment and the first embodiment are basically the same in other configurations. Note that even in Figure 7 , the load transistor unit LMU arranged on the upper side of the pixel array 110 is also omitted.

[0120] The pixel readout circuit 20A is different from the pixel readout circuit 20 ( Figure 3) differs from the SN capacitor CPs and the OFG transistor Tofg in that they are not provided. In the pixel readout circuit 20A, the charge signal from the photodiode PD is accumulated in the FD capacitor CPf via the transfer transistor Ttrg. Even with this configuration, when the select transistor Tsel is turned on, the floating diffusion layer voltage Vfd is output to the vertical signal line VSL. Furthermore, when the reset transistor Trst is turned on, the FD capacitor CPf is reset. This means that both D-phase and P-phase readout are performed.

[0121] Next, we will refer to Figure 8 The evaluation operation of the pixel readout circuit 20A will be described. Figure 8 20A is a timing chart illustrating an exemplary evaluation operation of the pixel readout circuit 20A.

[0122] refer to Figure 8 In the initial state before time t0 (left side in the figure), the selection signal SEL and the reset signal RST are disconnected. In addition, in the initial state, the switching unit SW ( Figure 7 ) is turned off, and the second switch SW2 is turned on. Therefore, the voltage VDR of the drain of the reset transistor Trst becomes the voltage VDR2 (for example, 1.2 V) of the wiring L2.

[0123] Next, at time t0, the first switch SW1 and the second switch SW2 of the switching unit SW are switched. That is, the first switch SW1 is turned on, and the second switch SW2 is turned off. As a result, the voltage VDR1 of the wiring L1 is applied to the drain of the reset transistor Trst. In this embodiment, the voltage VDR1 of the wiring L1 is set to a voltage that is lower than the withstand voltage of the reset transistor Trst and higher than the voltage VDR2 of the wiring L2. As a result, the voltage VDR of the drain of the reset transistor Trst rises compared to the voltage before time t0.

[0124] At time t1, when the reset signal RST is turned on, that is, when a predetermined negative voltage is applied to the gate of the reset transistor Trst, the reset transistor Trst turns on. As a result, conduction is achieved between the wiring L1 and the floating diffusion layer FD, the voltage of the floating diffusion layer FD becomes equal to the voltage VDR1 of the wiring L1, and charge is accumulated in the FD capacitor CPf.

[0125] At time t2, the reset signal RST is turned off. Subsequently, at time t3, the first switch SW1 and the second switch SW2 of the switching unit SW are switched. Specifically, the first switch SW1 is turned off, and the second switch SW2 is turned on. As a result, the voltage VDR at the drain of the reset transistor Trst becomes equal to the voltage VDR2 of the wiring L2. However, since the transfer transistor Ttrg and the reset transistor Trst are turned off, the FD capacitor CPf is electrically isolated. Therefore, the voltage Vfd of the floating diffusion layer FD remains at the voltage VDR1.

[0126] Then, at time t4, when the selection signal SEL is turned on, turning on the selection transistor Tsel, the voltage Vfd of the floating diffusion layer FD is read out to the vertical signal line VSL. When the selection signal SEL is turned off at time t5 and the reset signal RST is turned on at time t6, the FD capacitor CPf is reset, and the voltage Vfd of the floating diffusion layer FD becomes equal to the voltage VDR2 of the wiring L2 (for example, 1.2V).

[0127] Thereafter, at time t8, when the selection signal SEL is turned on again to turn on the selection transistor Tsel, the voltage Vfd (eg, 1.2 V) of the floating diffusion layer FD is read out to the vertical signal line VSL. Subsequently, at time t9, the selection signal SEL is turned off.

[0128] As described above, the select signal SEL is turned on twice, but the first time the signal is turned on, the readout corresponds to D-phase readout, while the second time the signal is turned on, the readout corresponds to P-phase readout. That is, the period from time t4 to time t9 is a single AD period. The voltage Vfd of the floating diffusion layer FD during D-phase readout is voltage VDR1, and the voltage Vfd of the floating diffusion layer FD during P-phase readout is voltage VDR2. That is, the voltage Vfd of the floating diffusion layer FD has different voltage values ​​between D-phase readout and P-phase readout. Therefore, the pixel readout circuit 20A can be evaluated for both D-phase and P-phase readout without using the charge signal from the photodiode PD. In other words, even with the imaging element according to the second embodiment, the ROIC substrate can be evaluated regardless of whether the photoelectric conversion unit 100 is illuminated with light or whether the photoelectric conversion unit 100 is provided.

[0129] (Third embodiment)

[0130] Next, we will refer to Figure 9A and Figure 9B An image pickup element according to a third embodiment of the present disclosure will be described. Figure 9A and Figure 9B is a diagram schematically showing the configuration of an image pickup element 1A according to a third embodiment. Figure 9A : shows the planar structure of the imaging element 1A, Figure 9B Indicates along Figure 9A The cross-sectional structure taken along the line BB' of FIG. For example, the imaging element 1A is suitable for an infrared sensor or the like using a compound semiconductor material such as a III-V semiconductor, and responds to light having a wavelength ranging from, for example, a visible region (e.g., 380 nm or more and less than 780 nm) to a short infrared region (e.g., 780 nm or more and less than 2400 nm). For example, the imaging element 1A is provided with a plurality of light receiving unit regions P (pixels P) arranged in a two-dimensional manner ( Figure 9B ).

[0131] The image sensor 1A includes an element region R1 as a central portion and a peripheral region R2 ( Figure 9A The imaging element 1A includes a conductive film 65B extending from the element region R1 to a portion of the peripheral region R2. The conductive film 65B includes an opening in a region facing the center portion of the element region R1.

[0132] The image sensor 1A has a stacked structure of a photoelectric conversion unit 100A and an ROIC substrate 200A ( Figure 9B One surface of the photoelectric conversion unit 100A is a light incident surface (light incident surface S1 ), and the surface opposite to the light incident surface S1 (the other surface) is a bonding surface (bonding surface S2 ) with the ROIC substrate 200A.

[0133] The photoelectric conversion unit 100A includes, in order from a position closer to the ROIC substrate 200A, a wiring layer 60W, a first electrode 61, a semiconductor layer 60S (first semiconductor layer), a second electrode 65, and a passivation film 66. The surface and end surface (side surface) of the semiconductor layer 60S facing the wiring layer 60W are covered with an insulating film 67. The ROIC substrate 200A includes a wiring layer 70W and a multilayer wiring layer 72C that are in contact with the bonding surface S2 of the photoelectric conversion unit 100A, and a semiconductor substrate 71 that faces the photoelectric conversion unit 100A via the wiring layer 70W and the multilayer wiring layer 72C.

[0134] The photoelectric conversion unit 100A has a semiconductor layer 60S in the element region R1. In other words, the area where the semiconductor layer 60S is provided is the element region R1 of the imaging element 1A. In the element region R1, the area exposed from the conductive film 65B (the area facing the opening of the conductive film 65B) is the light receiving area. In the element region R1, the area covered by the conductive film 65B is the optical black (OPB) area R1B. The OPB area R1B is provided to surround the light receiving area. The OPB area R1B is used to obtain a pixel signal at a black level. The photoelectric conversion unit 100A has an insulating film 67 and a buried layer 68 in the peripheral region R2. The peripheral region R2 is provided with holes H1 and H2 that penetrate the photoelectric conversion unit 100A and reach the ROIC substrate 200A. In the imaging element 1A, light is incident on the semiconductor layer 60S from the light incident surface S1 of the photoelectric conversion unit 100A through the passivation film 66, the second electrode 65 and the second contact layer 64. The signal charge photoelectrically converted by the semiconductor layer 60S moves via the first electrode 61 and the wiring layer 60W and is read out to the ROIC substrate 200A. Hereinafter, the configuration of each portion will be described.

[0135] The wiring layer 60W is provided in both the element region R1 and the peripheral region R2, and has a bonding surface S2 with the ROIC substrate 200A. In the imaging element 1A, the bonding surface S2 of the photoelectric conversion unit 100A is provided in both the element region R1 and the peripheral region R2. For example, the bonding surface S2 of the element region R1 and the bonding surface S2 of the peripheral region R2 form the same plane. As described later, in the imaging element 1A, the bonding surface S2 of the peripheral region R2 is formed by providing a buried layer 68.

[0136] For example, the wiring layer 60W includes a contact electrode 69E and a dummy electrode 69ED in interlayer insulating films 69A and 69B. For example, the interlayer insulating film 69B is arranged on the ROIC substrate 200A side, and the interlayer insulating film 69A is arranged on the first contact layer 62 side, and these interlayer insulating films 69A and 69B are stacked. The interlayer insulating films 69A and 69B are made of, for example, an inorganic insulating material. Examples of inorganic insulating materials include silicon nitride (SiN), aluminum oxide (Al2O3), silicon oxide (SiO2), and hafnium oxide (HfO2). The interlayer insulating films 69A and 69B can be made of the same inorganic insulating material.

[0137] The contact electrode 69E is, for example, provided in the element region R1. The contact electrode 69E is configured to electrically connect the first electrode 61 and the ROIC substrate 200A and is provided for each pixel P in the element region R1. Adjacent contact electrodes 69E are electrically separated by the buried layer 68 and the interlayer insulating films 69A and 69B. For example, the contact electrode 69E is made of a copper (Cu) pad, and the contact electrode 69E is exposed on the joint surface S2. For example, a dummy electrode 69ED is provided in the peripheral region R2. The dummy electrode 69ED is connected to the dummy electrode 72ED of the wiring layer 70W described later. Since the dummy electrode 69ED and the dummy electrode 72ED are provided, the strength of the peripheral region R2 can be improved. For example, the dummy electrode 69ED is formed in the same process as the contact electrode 69E. For example, the dummy electrode 69ED is made of a copper (Cu) pad, and the dummy electrode 69ED is exposed on the joint surface S2.

[0138] The first electrode 61 provided between the contact electrode 69E and the semiconductor layer 60S is an electrode (anode) to which a voltage for reading signal charges (holes or electrons, for convenience, it is assumed that the signal charges are holes) generated in the photoelectric conversion film 63 is supplied, and the first electrode 61 is provided in the element region R1 for each pixel P. The first electrode 61 is provided so as to be buried in the opening of the insulating film 67 and in contact with the semiconductor layer 60S (more specifically, the diffusion region 62A described later). For example, the first electrode 61 is larger than the opening of the insulating film 67, and the first electrode 61 is partially provided in the buried layer 68. That is, the upper surface of the first electrode 61 (the surface on the semiconductor layer 60S side) is in contact with the diffusion region 62A, and a portion of the lower surface and side surface of the first electrode 61 are in contact with the buried layer 68. Adjacent first electrodes 61 are electrically separated by the insulating film 67 and the buried layer 68.

[0139] The first electrode 61 is made of, for example, any single substance selected from titanium (Ti), tungsten (W), titanium nitride (TiN), platinum (Pt), gold (Au), germanium (Ge), palladium (Pd), zinc (Zn), nickel (Ni), and aluminum (Al), or an alloy containing at least one of these. The first electrode 61 may be a single film made of such a constituent material, or may be a laminated film obtained by combining two or more of these constituent materials. For example, the first electrode 61 is made of a laminated film of titanium and tungsten. For example, the thickness of the first electrode 61 is several tens of nanometers to several hundred nanometers.

[0140] For example, the semiconductor layer 60S includes, from a position closer to the wiring layer 60W, a first contact layer 62, a photoelectric conversion film 63, and a second contact layer 64. The first contact layer 62, the photoelectric conversion film 63, and the second contact layer 64 have the same planar shape, and their end faces are arranged at the same position in a plan view.

[0141] The first contact layer 62 is, for example, provided to be common to all pixels P and disposed between the insulating film 67 and the photoelectric conversion film 63. The first contact layer 62 is configured to electrically separate adjacent pixels P and is provided with, for example, a plurality of diffusion regions 62A. Dark current can also be suppressed when the first contact layer 62 is formed using a compound semiconductor material having a band gap greater than the band gap of the compound semiconductor material forming the photoelectric conversion film 63. For example, n-type indium phosphide (InP) can be used for the first contact layer 62.

[0142] The diffusion regions 62A provided on the first contact layer 62 are arranged to be spaced apart from each other. The diffusion region 62A is provided for each pixel P, and the first electrode 61 is connected to each diffusion region 62A, respectively. A diffusion region 62A is also provided in the OPB region R1B. The diffusion region 62A is configured to read out the signal charge generated in the photoelectric conversion film 63 for each pixel P, and the diffusion region 62A contains, for example, p-type impurities. Examples of p-type impurities include zinc (Zn) and the like. As a result, a pn junction interface is formed between the diffusion region 62A and the first contact layer 62 outside the diffusion region 62A, and adjacent pixels P are electrically separated. For example, the diffusion region 62A is provided in the thickness direction of the first contact layer 62, and is also provided in a portion of the photoelectric conversion film 63 in the thickness direction.

[0143] The photoelectric conversion film 63 between the first electrode 61 and the second electrode 65, more specifically, the photoelectric conversion film 63 between the first contact layer 62 and the second contact layer 64, is, for example, provided to be common to all pixels P. The photoelectric conversion film 63 absorbs light having a predetermined wavelength to generate signal charges, and the photoelectric conversion film 63 is made of, for example, a compound semiconductor material such as an i-type III-V semiconductor. Examples of compound semiconductor materials forming the photoelectric conversion film 63 include indium gallium arsenide (InGaAs), indium antimony arsenide (InAsSb), indium arsenide (InAs), indium antimonide (InSb), and mercury cadmium telluride (HgCdTe). The photoelectric conversion film 63 can be made of germanium (Ge). The photoelectric conversion film 63 is capable of photoelectrically converting light having a wavelength from the visible region to the short infrared region.

[0144] The second contact layer 64 is, for example, provided in common to all pixels P. The second contact layer 64 is provided between the photoelectric conversion film 63 and the second electrode 65 and is in contact with the photoelectric conversion film 63 and the second electrode 65. The second contact layer 64 is a region to which charges discharged from the second electrode 65 move, and is made of, for example, a compound semiconductor containing n-type impurities. For example, n-type indium phosphide (InP) can be used for the second contact layer 64.

[0145] The second electrode 65 is provided on the second contact layer 64 (on the light incident side) as, for example, an electrode common to each pixel P, and is in contact with the second contact layer 64. The second electrode 65 is configured to discharge charges (cathode) that are not used as signal charges among the charges generated in the photoelectric conversion film 63. For example, when holes are read out from the first electrode 61 as signal charges, for example, electrons can be discharged through the second electrode 65. The second electrode 65 is made of a conductive film that can transmit incident light such as infrared rays. For example, for the second electrode 65, indium tin oxide (ITO) or ITiO (In2O3-TiO2) can be used. For example, the second electrode 65 can be arranged in a matrix to separate adjacent pixels P. For the second electrode 65, a conductive material with low light transmittance can be used.

[0146] The passivation film 66 covers the second electrode 65 from the light incident surface S1 side. The passivation film 66 may have an anti-reflection function. For example, silicon nitride (SiN), aluminum oxide (Al2O3), silicon oxide (SiO2), and tantalum oxide (Ta2O3) can be used for the passivation film 66. The passivation film 66 has an opening 66H in the OPB region R1B. The opening 66H is provided in a frame shape (for example, surrounding the light receiving region) Figure 9A ). The opening 66H may be, for example, a hole having a square shape or a circular shape in a plan view. The conductive film 65B is electrically connected to the second electrode 65 through the opening 66H of the passivation film 66 .

[0147] The insulating film 67 is provided between the first contact layer 62 and the buried layer 68, covers the end surface of the first contact layer 62, the end surface of the photoelectric conversion film 63, the end surface of the second contact layer 64, and the end surface of the second electrode 65, and is in contact with the passivation film 66 in the peripheral region R2. For example, the insulating film 67 contains a material such as silicon oxide (SiO x ) and oxides such as aluminum oxide (Al2O3). The insulating film 67 can be formed using a stacked structure including a plurality of films. For example, the insulating film 67 can be made of a silicon (Si)-based insulating material such as silicon oxynitride (SiON), carbon-containing silicon oxide (SiOC), silicon nitride (SiN), and silicon carbide (SiC). For example, the thickness of the insulating film 67 is several tens of nm to several hundred nm.

[0148] The conductive film 65B extends from the OPB region R1B to the hole H1 in the peripheral region R2. The conductive film 65B contacts the second electrode 65 at the opening 66H of the passivation film 66 provided in the OPB region R1B, and also contacts the wiring (wiring 72CB described later) of the ROIC substrate 200A through the hole H1. As a result, voltage is supplied from the ROIC substrate 200A to the second electrode 65 via the conductive film 65B. The conductive film 65B not only serves as such a voltage supply path to the second electrode 65, but also serves as a light shielding film and forms the OPB region R1B. For example, the conductive film 65B is made of a metal material containing tungsten (W), aluminum (Al), titanium (Ti), molybdenum (Mo), tantalum (Ta), or copper (Cu). A passivation film may be provided on the conductive film 65B.

[0149] An adhesive layer B may be provided between the end of the second contact layer 64 and the second electrode 65. As described later, the adhesive layer B is used when forming the imaging element 1A and serves to bond the semiconductor layer 60S to the temporary substrate. For example, the adhesive layer B is made of tetraethoxysilane (TEOS) or silicon oxide (SiO2). The adhesive layer B is provided to be wider than the end face of the semiconductor layer 60S and is covered with the buried layer 68 together with the semiconductor layer 60S. An insulating film 67 is formed between the adhesive layer B and the buried layer 68.

[0150] During the manufacturing process of the imaging element 1A, the buried layer 68 fills the step between the temporary substrate and the semiconductor layer 60S. Although the details will be described later, in this embodiment, the formation of the buried layer 68 suppresses the occurrence of defects during the manufacturing process caused by the step between the semiconductor layer 60S and the temporary substrate.

[0151] The buried layer 68 in the peripheral region R2 is arranged between the wiring layer 60W and the insulating film 67 and between the wiring layer 60W and the passivation film 66, and has a thickness greater than, for example, the thickness of the semiconductor layer 60S. Here, the buried layer 68 surrounds the semiconductor layer 60S, thereby forming an area around the semiconductor layer 60S (peripheral region R2). As a result, the bonding surface S2 with the ROIC substrate 200A can be arranged in the peripheral region R2. The thickness of the buried layer 68 can be reduced as long as the bonding surface S2 is formed in the peripheral region R2, but preferably, the buried layer 68 covers the semiconductor layer 60S in the thickness direction so that the entire end face of the semiconductor layer 60S is covered by the buried layer 68. The buried layer 68 covers the entire end face of the semiconductor layer 60S through the insulating film 67, thereby effectively suppressing moisture from invading the semiconductor layer 60S. The buried layer 68 in the element region R1 is arranged between the semiconductor layer 60S and the wiring layer 60W to cover the first electrode 61.

[0152] The surface of the buried layer 68 on the bonding surface S2 side is flattened, and the wiring layer 60W is provided on the flattened surface of the buried layer 68 in the peripheral region R2. For example, a material such as silicon oxide (SiO x ), inorganic insulating materials such as silicon nitride (SiN), silicon oxynitride (SiON), carbon-containing silicon oxide (SiOC) and silicon carbide (SiC).

[0153] For example, during the manufacturing process of the imaging element 1A, a buried layer 68 is formed. Thereafter, a wiring layer 60W including interlayer insulating films 69A and 69B and a contact electrode 69E is formed above the buried layer 68. The ROIC substrate 200A including the wiring layer 70W is bonded to the photoelectric conversion unit 100A including the wiring layer 60W to form the imaging element 1A. At this point, the contact electrode 69E of the wiring layer 60W is connected to the contact electrode 72E of the wiring layer 70W. For example, the contact electrodes 69E and 72E may have Cu pads, and these Cu pads are directly bonded to connect the contact electrodes 69E and 72E. When forming the contact electrode 69E using chemical mechanical polishing (CMP), the buried layer 68, which is positioned below the copper film to be polished, needs to have a hardness sufficient to withstand the stress during polishing. Furthermore, in order to directly bond the Cu pads of the contact electrodes 69E and 72E, the photoelectric conversion unit 100A and the ROIC substrate 200A must be formed to be very flat. Therefore, the buried layer 68 disposed below the copper film preferably has a hardness that can withstand the stress during polishing. Specifically, the material constituting the buried layer 68 is preferably a material having a higher hardness than the sealant or organic material disposed around the die in a typical semiconductor package. Examples of such high-hardness materials include inorganic insulating materials. For example, the buried layer 68 can be formed by depositing the inorganic insulating material using a chemical vapor deposition (CVD) method, a sputtering method, or a coating method.

[0154] The buried layer 68 has holes H1 and H2 that penetrate the buried layer 68. The holes H1 and H2 penetrate the wiring layer 60W and the buried layer 68 and reach the ROIC substrate 200A. For example, the holes H1 and H2 have a square planar shape, and a plurality of holes H1 and a plurality of holes H2 are provided so as to surround the element region R1 ( Figure 9A The hole H1 is provided at a position closer to the element region R1 than the hole H2, and the sidewalls and bottom surface of the hole H1 are covered by the conductive film 65B. The hole H1 is configured to connect the second electrode 65 (conductive film 65B) and the wiring (wiring 72CB) of the ROIC substrate 200A, and penetrates the passivation film 66, the buried layer 68, and the wiring layer 60W.

[0155] Hole H2 is provided closer to the chip end E than hole H1. Hole H2 penetrates the passivation film 66, the buried layer 68, and the wiring layer 60W, and reaches the pad electrode (pad electrode 72P described later) of the ROIC substrate 200A. The external device and the imaging element 1A are electrically connected via hole H2. Holes H1 and H2 do not necessarily need to reach the ROIC substrate 200A. For example, holes H1 and H2 may reach the wiring of the wiring layer 60W, and this wiring may be connected to the wiring 72CB and the pad electrode 72P of the ROIC substrate 200A. Holes H1 and H2 may also penetrate the adhesive layer B.

[0156] The holes and electrons generated in the photoelectric conversion film 63 are read out from the first electrode 61 and the second electrode 65. To perform this readout operation at high speed, the distance between the first electrode 61 and the second electrode 65 is preferably set to a distance sufficient for photoelectric conversion but not too long. In other words, the thickness of the photoelectric conversion unit 100A is preferably reduced. For example, the distance between the first electrode 61 and the second electrode 65 or the thickness of the photoelectric conversion unit 100A is 10 μm or less, further 7 μm or less, and further 5 μm or less.

[0157] The semiconductor substrate 71 of the ROIC substrate 200A faces the photoelectric conversion unit 100A via the wiring layer 70W and the multilayer wiring layer 72C. For example, the semiconductor substrate 71 is made of silicon (Si). A plurality of transistors are provided near the surface of the semiconductor substrate 71 (the surface on the wiring layer 70W side). For example, the plurality of transistors correspond to the pixel readout circuit 20 ( Figure 3 ) in the OFG transistor Tofg, the transfer transistor Ttrg, the reset transistor Trst, the amplifying transistor Tamp and the selecting transistor Tsel.

[0158] For example, the wiring layer 70W has an interlayer insulating film 72A and an interlayer insulating film 72B in sequence from the photoelectric conversion unit 100A side, and these interlayer insulating films 72A and 72B are stacked. For example, a contact electrode 72E and a dummy electrode 72ED are provided in the interlayer insulating film 72A. The multilayer wiring layer 72C is provided to face the photoelectric conversion unit 100A across the wiring layer 70W. For example, a pad electrode 72P and a plurality of wirings 72CB are provided in the multilayer wiring layer 72C. For example, the interlayer insulating films 72A and 72B are made of an inorganic insulating material. Examples of inorganic insulating materials include silicon nitride (SiN), aluminum oxide (Al2O3), silicon oxide (SiO2), and hafnium oxide (HfO2).

[0159] The contact electrode 72E is configured to electrically connect the first electrode 61 and the wiring 72CB, and is provided for each pixel P in the element region R1. The contact electrode 72E contacts the contact electrode 69E at the bonding surface S2 of the photoelectric conversion unit 100A. Adjacent contact electrodes 72E are electrically separated by the interlayer insulating film 72A.

[0160] The dummy electrode 72ED provided in the peripheral region R2 contacts the dummy electrode 69ED at the bonding surface S2 of the photoelectric conversion unit 100A. For example, the dummy electrode 72ED is formed in the same process as the contact electrode 72E. For example, the contact electrode 72E and the dummy electrode 72ED are made of copper (Cu) pads and are exposed on the surface of the ROIC substrate 200A facing the photoelectric conversion unit 100A. That is, for example, a Cu-Cu bond is obtained between the contact electrode 69E and the contact electrode 72E, and between the dummy electrode 69ED and the dummy electrode 72ED. Since the photoelectric conversion unit 100A having the photoelectric conversion film 63 and the ROIC substrate 200A having the pixel readout circuit 20 and the predetermined wiring are manufactured separately and bonded by Cu-Cu bonding, the size of the pixel P can be reduced.

[0161] The wiring 72CB connected to the contact electrode 69E is connected to a transistor provided near the surface of the semiconductor substrate 71, and the first electrode 61 is connected to the pixel readout circuit. For example, the wiring 72CB connected to the conductive film 65B through the hole H1 is connected to a predetermined potential. In this way, one type of charge generated in the photoelectric conversion film 63 (for example, holes) is read out from the first electrode 61 via the contact electrodes 69E and 72E to the pixel readout circuit, and the other type of charge generated in the photoelectric conversion film 63 (for example, electrons) is discharged from the second electrode 65 via the conductive film 65B to a predetermined potential.

[0162] The pad electrode 72P provided in the peripheral region R2 is configured for electrical connection to the outside. A hole H2 is formed near the chip end E of the imaging element 1A, penetrating the photoelectric conversion unit 100A and reaching the pad electrode 72P. Electrical connection to the outside is achieved through hole H2. This connection can be achieved, for example, by methods such as wire bonding or bumps. For example, a predetermined potential can be supplied from an external terminal arranged in hole H2 to the second electrode 65 via wiring 72CB and conductive film 65B of the ROIC substrate 200A. Alternatively, the signal voltage read from the first electrode 61 as a result of photoelectric conversion by the photoelectric conversion film 63 is read out to a readout circuit via contact electrodes 69E and 72E, and output via the readout circuit to the external terminal arranged in hole H2. The signal voltage can be output from the readout circuit to the external terminal via the load transistor unit LMD (LMU), the comparator circuit unit CMU (CMD), and the counter unit CNU (CND).

[0163] In the ROIC substrate 200A of the image pickup element 1A according to the present embodiment, the OFG transistor Tofg, the transfer transistor Ttrg, the reset transistor Trst, the amplifying transistor Tamp, and the selecting transistor Tsel are formed on the semiconductor substrate 71. In addition, the wirings L1 and L2, the switching unit SW that selectively connects the wirings L1 and L2 to the wiring LV, and the switching unit SW that selectively connects the wirings L1 and L2 to the wiring LV via the wiring L VDR The wiring LV is connected to the wiring LR of the drain of the reset transistor Trst. VDR And through the wiring L VDR The wiring LV is connected to the wiring LO of the drain of the OFG transistor Tofg. VDR That is, on the ROIC substrate 200A of the image pickup element 1A according to this embodiment, a pixel readout circuit 20 ( Figure 3 ).

[0164] Therefore, even in the ROIC substrate 200A of the image pickup element 1A according to this embodiment, the reference Figure 4 Therefore, the image pickup element 1A according to the present embodiment exerts the same effects as the image pickup element 1 according to the first embodiment.

[0165] Note that the multilayer wiring layer 72C in the ROIC substrate 200A may be provided with a switching unit SWA instead of the switching unit SW, and may be provided with wiring corresponding to the switching unit SWA (see Figure 5 ). In addition, a switching unit SWB may be provided instead of the switching unit SW, and wiring corresponding to the switching unit SWB may be provided (see Figure 6 ). These can also be implemented as reference Figure 4 Therefore, even before the photoelectric conversion unit 100A is bonded to the ROIC substrate 200A, the ROIC substrate 200A can be evaluated regardless of whether the photoelectric conversion unit 100A is irradiated with light.

[0166] In addition, the multilayer wiring layer 72C of the ROIC substrate 200A may be provided with a pixel readout circuit 20A (see Figure 7 ), the switching unit SW corresponding to the pixel readout circuit 20A and the wiring corresponding to the switching unit SW. As a result, it is possible to implement the reference Figure 8 Describes the operation.

[0167] (Fourth embodiment)

[0168] Next, an image pickup element according to a fourth embodiment of the present disclosure will be described. Figure 101 is a partial cross-sectional view schematically showing an image pickup element 1B according to the fourth embodiment. As shown in the figure, the image pickup element 1B according to the present embodiment includes a photoelectric conversion unit 100B and an ROIC substrate 200B bonded to the photoelectric conversion unit 100B.

[0169] Even in the ROIC substrate 200B of the image pickup element 1B according to this embodiment, a reference circuit is formed for each pixel 111B. Figure 3 However, in the pixel readout circuit 20 described above, Figure 10 In FIG, reference numerals of transistors and capacitors included in the pixel readout circuit 20 are omitted. Figure 10 In the Figure 3 Shown are a switching unit SW and wirings LV, L1 and L2.

[0170] An N-type photoelectric conversion film 41 is formed on the entire surface of the photoelectric conversion unit 100B. In the present embodiment, the photoelectric conversion film 41 is made of InGaAs. However, without being limited to InGaAs, compound semiconductors having a chalcopyrite structure such as InGaP, InAlP, and InAlAs can be used to form the photoelectric conversion film 41. Compound semiconductors having a chalcopyrite structure are materials that can obtain a high light absorption coefficient and high sensitivity in a wide wavelength region, and are preferably used as the photoelectric conversion film 41. Elements such as Cu, Al, Ga, In, S, and Se are used to form such compound semiconductors having a chalcopyrite structure, and examples thereof include CuGaInS mixed crystals, CuAlGaInS mixed crystals, and CuAlGaInSSe mixed crystals. In addition, as materials for the photoelectric conversion film 41, in addition to the above-mentioned compound semiconductors, amorphous silicon (Si), germanium (Ge), quantum dot photoelectric conversion films, and organic photoelectric conversion films can also be exemplified.

[0171] On the lower side of the photoelectric conversion film 41 (on the ROIC substrate 200B side), a P-type layer 42 having a high acceptor concentration and forming a pixel electrode is formed for each pixel 111B. Furthermore, between the P-type layers 42 having a high acceptor concentration formed for each pixel 111B, an N-type layer 43 is formed using a compound semiconductor such as InP, for example, to serve as a pixel isolation region that separates each pixel 111B. The N-type layer 43 not only functions as a pixel isolation region but also prevents dark current.

[0172] At the same time, on the upper side (light incident side) of the photoelectric conversion film 41, an N-type layer 44 having a higher donor concentration than that of the photoelectric conversion film 41 is formed using a compound semiconductor such as InP as a pixel separation region. The N-type layer 44 having a high donor concentration acts as a blocking layer to prevent the reverse flow of charges generated by the photoelectric conversion film 41. For example, the N-type layer 44 having a high donor concentration can be formed using a compound semiconductor such as InGaAs, InP, and InAlAs.

[0173] An antireflection film 45 is formed as a barrier layer on the N-type layer 44 having a high donor concentration. For example, the antireflection film 45 can be formed using silicon nitride (SiN), hafnium oxide (HfO2), aluminum oxide (Al2O3), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), or titanium oxide (TiO2).

[0174] Any one of the N-type layer 44 with a high donor concentration and the antireflection film 45 also functions as an upper electrode vertically sandwiching the upper side of the photoelectric conversion film 41. A predetermined voltage Va is applied to the N-type layer 44 with a high donor concentration or the antireflection film 45 serving as the upper electrode.

[0175] A color filter 46 and an on-chip lens 47 are further formed on the anti-reflection film 45. The color filter 46 is a filter that transmits any one color (wavelength) of red (R), green (G), and blue (B), and is, for example, formed in the pixel array 110 ( Figure 2 ) are arranged according to a so-called Bayer array.

[0176] A passivation layer 51 is formed under the P-type layer 42 having a high acceptor concentration and serving as a pixel electrode and the N-type layer 43 serving as a pixel isolation region. A connection electrode 53A is formed to penetrate the passivation layer 51 .

[0177] The connection electrode 53A is electrically connected to the connection electrode 53B formed on the upper surface of the ROIC substrate 200B via the bump electrode 54. As a result, the P-type layer 42 in the photoelectric conversion unit 100B, which forms the pixel electrode and has a high acceptor concentration, is electrically connected to the pixel readout circuit 20. Furthermore, the photoelectric conversion unit 100B is mechanically bonded to the ROIC substrate 200B by connecting the connection electrode 53A and the connection electrode 53B via the bump electrode 54. Note that the region between the connected connection electrode 53A, the bump electrode 54, and the connection electrode 53B is filled with the insulating layer 52. As a result, the photoelectric conversion unit 100B and the ROIC substrate 200B can be securely bonded.

[0178] Since the image pickup element 1B according to the present embodiment having the above-described configuration includes the pixel readout circuit 20 similarly to the image pickup element 1 in the first embodiment, it is possible to implement the reference image pickup element 1B. Figure 4The evaluation operation described above is performed. Therefore, even before the photoelectric conversion unit 100B is bonded to the ROIC substrate 200B, the ROIC substrate 200B can be evaluated regardless of whether the photoelectric conversion unit 100B is irradiated with light. Note that the ROIC substrate 200B of the imaging element 1B may be provided with the pixel readout circuit of the imaging element according to the modification of the first embodiment or the second embodiment instead of the pixel readout circuit 20 of the imaging element 1 according to the first embodiment. In this case, even before the photoelectric conversion unit 100B is bonded to the ROIC substrate 200B, the ROIC substrate 200B can be evaluated regardless of whether the photoelectric conversion unit 100B is irradiated with light.

[0179] Note that the image sensor 1B includes a pixel 111B and a pixel 111C that is different from the pixel 111B. The pixel 111B is a pixel that outputs a charge signal based on charges generated by photoelectric conversion and contributes to image formation.

[0180] On the other hand, for example, the pixels 111C are arranged in the pixel array 110 ( Figure 2 ) in the peripheral edge portion. Pixel 111C has a pixel readout circuit 20C. The pixel readout circuit 20C is formed on the ROIC substrate 200B and includes a capacitor element 80, a reset transistor Trst, an amplifying transistor Tamp, and a selecting transistor Tsel. In addition, the difference between pixel 111C and pixel 111B is that a gate voltage is always applied to the gate of the reset transistor Trst. Therefore, the charge generated by photoelectric conversion in the pixel 111C can be discharged to the ground through the reset transistor Trst.

[0181] In the rectangular pixel array 110 ( Figure 2 ) in the pixel 111C in the peripheral edge portion, as shown in FIG. Figure 10 As shown, interface defects and the like occur at the interface of the processing portion (end face of the processing portion) of the photoelectric conversion film 41, making it easy for dark current to occur due to the influence of the interface defects and the like. In particular, when the readout circuit formed on the ROIC substrate 200B is a source follower type circuit, the potential difference of the pixel decreases as the charge accumulates, and therefore, the dark current component successively affects the adjacent pixels 111B due to blooming. In this embodiment, the reset transistor Trst can be continuously turned on in the pixel 111C. Therefore, the charge generated in the pixel 111C can be discharged to the ground, and the charge flowing into the pixel 111B can be reduced.

[0182] Note that the pixels 111C may be formed in a plurality of rows and columns other than the outermost row and column of the rectangular pixel array 110 .

[0183] The present disclosure has been described with reference to several embodiments, but the present disclosure is not limited to the above-described embodiments, and various changes and modifications can be made.

[0184] For example, in the first embodiment (including the second modification ( Figure 6 )) In the second embodiment, the wiring LV, the wiring L1, the wiring L2, the wiring L3 and the switching unit SW (SWB) are provided in both the load transistor unit LMU and the LMD (see Figure 2 ), but not limited to this, the wirings LV, L1, L2, and L3 and the switching unit SW (SWB) may be provided in either the load transistor unit LMU or LMD. However, in this case, the load transistor unit LMU and LMD must be formed in separate manufacturing processes. On the other hand, if the wirings LV, L1, L2, and L3 and the switching unit SW (SWB) are provided in both the load transistor unit LMU and LMD, the load transistor unit LMU and LMD can be formed in the same manufacturing process, thereby reducing the number of manufacturing processes.

[0185] In addition, when only one of the load transistor units LMU and LMD is provided due to size limitations of the ROIC substrate 200 , the wirings LV, L1 , L2 , and L3 and the switching unit SW (SWB) may be provided in the provided load transistor unit.

[0186] In addition, the wirings LV, L1, L2 and L3 and the switching unit SW (SWB) can be appropriately formed in an area where the density of circuit elements such as wirings, vias and transistors is low, for example in the ROIC substrate 200, without being provided in the load transistor unit LMU and / or LMD.

[0187] In addition, compared with the first modification of the first embodiment ( Figure 5 ) Similarly, the wirings LV and L1 and the switching unit SWA may be provided in any one of the load transistor units LMU and LMD, or may be appropriately formed in a region where the density of circuit elements is low.

[0188] Furthermore, when the switching unit SW (SWA, SWB) is provided in both the load transistor unit LMU and the load transistor unit LMD, for example, the wiring L1 and the wiring L2 provided in the load transistor unit LMU and the wiring L1 and the wiring L2 provided in the load transistor unit LMD can be connected separately. As a result, the number of pads connected to the wiring L1 and the number of pads connected to the wiring L2 can be reduced.

[0189] For example, without being limited to the photoelectric conversion unit 100 formed using a III-V compound semiconductor, a CMOS image sensor or a CCD image sensor can be combined with the ROIC substrate in the embodiments of the present disclosure. The aforementioned effects can also be achieved in an imaging element obtained through such a combination. Furthermore, such an imaging element can be applied to, for example, still cameras or video cameras. Therefore, by using an imaging element evaluated using the aforementioned evaluation operation, the reliability of still cameras or video cameras can also be improved.

[0190] In addition, the ROIC substrate 200 according to the embodiment of the present disclosure can also be provided with a circuit (sometimes referred to as a pseudo source follower) that outputs a signal equivalent to a signal from a pixel to a vertical signal line in a pseudo manner. Figure 4 and Figure 8 The evaluation described in the timing diagram is different from the evaluation of other evaluation items.

[0191] Note that, as referenced Figure 4 As described in the timing diagram of FIG, by changing the voltage Vfd of the floating diffusion layer FD from the voltage VDR2 (1.2V) to (voltage VDR1 + voltage VDR2) / 2 which is different from the voltage VDR2, reading the voltage of the floating diffusion layer FD in this state, changing the voltage Vfd of the floating diffusion layer FD to the voltage VDR2, and reading the voltage Vfd of the floating diffusion layer FD again, the ROIC substrate of the image pickup element according to the first embodiment (including the modified example) of the present disclosure can be evaluated. In addition, as described in reference Figure 8 As described in the timing diagram, by changing the voltage Vfd of the floating diffusion layer FD from the voltage VDR2 (1.2 V) to the voltage VDR1 different from the voltage VDR2, reading the voltage of the floating diffusion layer FD in this state, changing the voltage Vfd of the floating diffusion layer FD to the voltage VDR2, and reading the voltage Vfd of the floating diffusion layer FD again, the ROIC substrate of the image pickup element according to the second embodiment of the present disclosure can be evaluated.

[0192] In the above description, the term "column direction" is used for convenience of explanation only and is not used to clearly distinguish between the vertical and horizontal directions. For example, in the above embodiments (including modifications), a single switching unit SW (SWA or SWB) is provided for a plurality of pixels arranged in the column direction. However, a single switching unit SW (SWA or SWB) may also be provided for a plurality of pixels arranged in the row direction.

[0193] <Application Examples>

[0194] The imaging element according to the embodiment of the present disclosure described above can be applied to various electronic devices, for example, imaging devices such as digital still cameras and digital video cameras, mobile phones with an imaging function, or other devices with an imaging function.

[0195] Figure 11 : is a block diagram showing a configuration example of an imaging device as an electronic device to which the present technology is applied. Figure 11 The illustrated imaging device 201 includes an optical system 202 , a shutter device 203 , an imaging element 204 , a control circuit 205 , a signal processing circuit 206 , a monitor 207 , and a memory 208 , and is capable of capturing still images or moving images.

[0196] The optical system 202 includes one or more lenses, guides light from a subject (incident light) to the imaging element 204 , and forms an image on a light-receiving surface of the imaging element 204 .

[0197] The shutter device 203 is arranged between the optical system 202 and the imaging element 204 , and controls a light irradiation period and a light shielding period of the imaging element 204 according to control of the control circuit 205 .

[0198] The imaging element 204 includes the imaging element according to each of the above-described embodiments (including modifications). The imaging element 204 accumulates signal charge for a certain period of time based on the light formed on the light receiving surface via the optical system 202 and the shutter device 203. The signal charge accumulated in the imaging element 204 is transferred based on the drive signal (timing signal) supplied from the control circuit 205.

[0199] The control circuit 205 outputs a drive signal for controlling the transfer operation of the imaging element 204 and the shutter operation of the shutter device 203 to drive the imaging element 204 and the shutter device 203 .

[0200] The signal processing circuit 206 performs various signal processing on the signal charge output from the imaging element 204. An image (image data) obtained by the signal processing performed by the signal processing circuit 206 is supplied to the monitor 207 and displayed on the monitor 207, or is supplied to the memory 208 and stored (recorded) in the memory 208.

[0201] In the imaging device 201 configured as described above, since the imaging element 204 includes the imaging element according to each of the above-described embodiments (including the modified examples), the imaging device 201 can be manufactured using the imaging element 204 whose reliability has been confirmed through the evaluation operation described above. That is, the imaging element according to the embodiment of the present disclosure contributes to improving the reliability of electronic equipment serving as an imaging device using the imaging element.

[0202] <Other application examples 1>

[0203] The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure can be implemented as a device installed on any type of mobile object, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobile device, an airplane, an unmanned aerial vehicle, a ship, and a robot.

[0204] Figure 12 : is a block diagram showing a schematic configuration example of a vehicle control system as an example of a mobile body control system to which the technology according to the present disclosure is applicable.

[0205] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. Figure 12 In the illustrated example, a vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an exterior information detection unit 12030, an interior information detection unit 12040, and an integrated control unit 12050. Furthermore, as a functional configuration of the integrated control unit 12050, a microcomputer 12051, a sound and image output unit 12052, and an in-vehicle network interface (I / F) 12053 are illustrated.

[0206] The drive system control unit 12010 controls the operation of devices related to the vehicle's drive system according to various programs. For example, the drive system control unit 12010 functions as a control device for the following devices: a drive force generating device configured to generate drive force for the vehicle, such as an internal combustion engine and a drive motor; a drive force transmission mechanism configured to transmit drive force to the wheels; a steering mechanism for adjusting the steering angle of the vehicle; and a brake device for generating braking force for the vehicle.

[0207] The body system control unit 12020 controls the operation of various devices installed on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for the following devices: the keyless entry system; the smart key system; the power windows; or various lights such as the headlights, taillights, brake lights, turn signals, and fog lights. In this case, the body system control unit 12020 can receive input from radio waves or signals from various switches transmitted from a portable device that replaces a key. The body system control unit 12020 receives these radio waves or signals to control the vehicle's door locks, power windows, lights, and other devices.

[0208] The vehicle exterior information detection unit 12030 detects information outside the vehicle in which the vehicle control system 12000 is installed. For example, the vehicle exterior information detection unit 12030 is connected to the camera unit 12031. The vehicle exterior information detection unit 12030 causes the camera unit 12031 to capture images of the vehicle exterior and receives the captured images. Based on the received images, the vehicle exterior information detection unit 12030 can perform object detection or distance detection processing on people, vehicles, obstacles, signs, or text on the road surface.

[0209] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output this electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 can be visible light or non-visible light such as infrared light.

[0210] The in-vehicle information detection unit 12040 detects information about the interior of the vehicle. For example, the in-vehicle information detection unit 12040 is connected to a driver state detection unit 12041 for detecting the driver's state. For example, the driver state detection unit 12041 includes a camera for capturing an image of the driver. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's level of fatigue or concentration, or determine whether the driver is dozing off.

[0211] Based on the information outside or inside the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, the microcomputer 12051 can calculate a control target value of the driving force generating device, the steering mechanism, or the braking device, and can output a control command to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control for implementing advanced driver assistance system (ADAS) functions, such as collision avoidance or impact mitigation, following driving based on vehicle-to-vehicle distance, constant speed driving, vehicle collision warning, or lane departure warning.

[0212] In addition, the microcomputer 12051 is capable of controlling the driving force generating device, steering mechanism or braking device, etc. based on the information around the vehicle obtained by the external information detection unit 12030 or the internal information detection unit 12040, thereby performing collaborative control such as automatic driving aimed at enabling the vehicle to drive autonomously without relying on the driver's operation.

[0213] Furthermore, based on information outside the vehicle acquired by the vehicle exterior information detection unit 12030, the microcomputer 12051 can output a control command to the body system control unit 12020. For example, the microcomputer 12051 can control the headlights based on the positions of the preceding vehicle or oncoming vehicles detected by the vehicle exterior information detection unit 12030, thereby performing cooperative control for glare prevention, such as switching the high beam to the low beam.

[0214] The sound and image output unit 12052 transmits an output signal of at least one of sound and image to an output device that can visually or auditorily notify information to a passenger of the vehicle or outside the vehicle. Figure 12 In the example of FIG, as the output device, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are exemplified. For example, the display unit 12062 may include at least one of an in-vehicle display and a head-up display.

[0215] Figure 13 12031 is a diagram showing an example of the installation position of the imaging unit 12031.

[0216] exist Figure 13 In the figure, as the imaging unit 12031, imaging units 12101, 12102, 12103, 12104 and 12105 are provided.

[0217] For example, camera units 12101, 12102, 12103, 12104, and 12105 are installed in locations such as the front nose, rearview mirror, rear bumper, rear door, and upper portion of the windshield inside the vehicle 12100. Camera unit 12101 installed in the front nose and camera unit 12105 installed in the upper portion of the windshield inside the vehicle primarily capture images of the area in front of vehicle 12100. Camera units 12102 and 12103 installed in the rearview mirror primarily capture images of the sides of vehicle 12100. Camera unit 12104 installed in the rear bumper or rear door primarily captures images of the area behind vehicle 12100. Camera unit 12105 installed in the upper portion of the windshield inside the vehicle primarily detects vehicles or pedestrians ahead, obstacles, traffic lights, traffic signs, lanes, and the like.

[0218] Notice, Figure 13The figure shows examples of the imaging ranges of imaging units 12101 to 12104. Imaging range 12111 represents the imaging range of imaging unit 12101, which is located on the front nose. Imaging ranges 12112 and 12113 represent the imaging ranges of imaging units 12102 and 12103, respectively, which are located on the rearview mirrors. Imaging range 12114 represents the imaging range of imaging unit 12104, which is located on the rear bumper or rear door. For example, by superimposing the image data captured by imaging units 12101 to 12104, a bird's-eye view image of vehicle 12100 can be obtained from above.

[0219] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera including a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0220] For example, based on the distance information obtained from imaging units 12101-12104, microcomputer 12051 determines the distance to each three-dimensional object within imaging ranges 12111-12114 and the change in this distance over time (relative speed to vehicle 12100). This allows microcomputer 12051 to identify the three-dimensional object closest to vehicle 12100 on the road and traveling at a predetermined speed (e.g., 0 km / h or higher) in substantially the same direction as vehicle 12100 as the leading vehicle. Furthermore, microcomputer 12051 can pre-set the required inter-vehicle distance behind the leading vehicle and execute automatic braking control (including follow-up stop control) and automatic acceleration control (including follow-up start control). In this way, cooperative control, such as automated driving, can be implemented, enabling autonomous driving without relying on driver input.

[0221] For example, based on distance information obtained from camera units 12101-12104, microcomputer 12051 classifies three-dimensional object data related to three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, and other three-dimensional objects such as utility poles, and extracts data for automatic obstacle avoidance. For example, microcomputer 12051 classifies obstacles near vehicle 12100 into those that the driver of vehicle 12100 can visually identify and those that are difficult for the driver to visually identify. Microcomputer 12051 then determines a collision risk, indicating the degree of risk of collision with each obstacle. If the collision risk exceeds a set value and a collision is likely, microcomputer 12051 can output a warning to the driver via audio speaker 12061 and / or display unit 12062, or perform driving assistance to avoid a collision by initiating forced deceleration or evasive steering via drive system control unit 12010.

[0222] At least one of the imaging units 12101-12104 may be an infrared camera for detecting infrared rays. For example, the microcomputer 12051 can identify a pedestrian by determining whether the pedestrian exists in the images captured by the imaging units 12101-12104. For example, this pedestrian identification is performed by extracting feature points from the images captured by the imaging units 12101-12104, which function as infrared cameras; and performing pattern matching on a series of feature points representing the outline of an object to determine whether the object corresponds to a pedestrian. When the microcomputer 12051 determines that a pedestrian exists in the images captured by the imaging units 12101-12104 and identifies the pedestrian, the audio and video output unit 12052 controls the display unit 12062 to superimpose and display a rectangular outline on the identified pedestrian for emphasis. Furthermore, the audio and video output unit 12052 may control the display unit 12062 to display an icon representing the pedestrian at a desired location.

[0223] An example of a vehicle control system to which the technology of the present disclosure can be applied has been described above. The technology of the present disclosure can be applied to the imaging units 12101 to 12105 in the above-described configuration. Specifically, as the imaging units 12101 to 12105, imaging elements applicable to the semiconductor devices (ROIC substrates) according to the first to fourth embodiments (including modifications) can be applied. For example, since the highly reliable imaging elements evaluated as described above can be used as the imaging units 12101 to 12105, pedestrians can be recognized with high reliability.

[0224] <Other application examples 2>

[0225] For example, the technology according to the present disclosure (the present technology) can be applied not only to the above-mentioned electronic equipment and vehicle control systems but also to endoscopic surgery systems.

[0226] Figure 14 : is a diagram showing an example of a schematic configuration of an endoscopic surgery system to which the technology according to the present disclosure (the present technology) can be applied.

[0227] Figure 14 The figure shows a state where a surgeon (doctor) 11131 performs surgery on a patient 11132 on a bed 11133 using an endoscopic surgery system 11000. As shown in the figure, the endoscopic surgery system 11000 includes an endoscope 11100, other surgical tools 11110 such as a pneumoperitoneum tube 11111 and an energy therapy tool 11112, a support arm device 11120 for supporting the endoscope 11100, and a cart 11200 on which various devices used for endoscopic surgery are installed.

[0228] The endoscope 11100 includes a lens barrel 11101, a region having a predetermined length from a distal end of which is inserted into a body cavity of a patient 11132, and a camera 11102 connected to a proximal end of the lens barrel 11101. In the illustrated example, the endoscope 11100 is configured as a so-called rigid scope having a rigid lens barrel 11101, but the endoscope 11100 may also be configured as a so-called flexible scope having a flexible lens barrel.

[0229] The distal end of the lens barrel 11101 is provided with an opening, and the objective lens is mounted in this opening. A light source device 11203 is connected to the endoscope 11100 so that light generated by the light source device 11203 is guided to the distal end of the lens barrel via a light guide extending within the lens barrel 11101, and the light is irradiated toward an observation target in the body cavity of the patient 11132 via the objective lens. Note that the endoscope 11100 can be a direct-viewing endoscope, or can be an oblique-viewing endoscope or a side-viewing endoscope.

[0230] The camera head 11102 includes an optical system and an imaging element. Light reflected from an observation target (observation light) is focused onto the imaging element through the optical system. The observation light is photoelectrically converted by the imaging element, generating an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observed image. This image signal is transmitted as RAW data to the camera control unit (CCU) 11201.

[0231] The CCU 11201 is configured using a central processing unit (CPU) or a graphics processing unit (GPU), and the CCU 11201 integrally controls the operations of the endoscope 11100 and the display device 11202. In addition, the CCU 11201 receives an image signal from the camera 11102 and performs various image processing such as development processing (demosaicing processing) on ​​the image signal for displaying an image based on the image signal.

[0232] Under the control of the CCU 11201 , the display device 11202 displays an image based on the image signal processed by the CCU 11201 .

[0233] For example, the light source device 11203 is configured using a light source such as a light emitting diode (LED), and supplies irradiation light to the endoscope 11100 when photographing a surgical site or the like.

[0234] The input device 11204 is an input interface of the endoscopic surgery system 11000. The user can input various information and input commands to the endoscopic surgery system 11000 via the input device 11204. For example, the user can input commands for changing the imaging conditions of the endoscope 11100 (such as the type of irradiation light, magnification, or focal length).

[0235] The treatment tool control device 11205 controls the driving of the energy treatment tool 11112 for purposes such as cauterization, cutting, and blood vessel sealing. The pneumoperitoneum device 11206 delivers gas into the body cavity of the patient 11132 via the pneumoperitoneum tube 11111 to inflate the cavity, thereby ensuring the field of view of the endoscope 11100 and the surgeon's working space. The recorder 11207 is a device capable of recording various surgical information. The printer 11208 is a device capable of printing various surgical information in various formats, such as text, images, and charts.

[0236] Note that the light source device 11203 that supplies irradiation light to the endoscope 11100 when photographing the surgical site can be configured using, for example, an LED, a laser light source, or a white light source composed of a combination of an LED and a laser light source. When the white light source is configured by a combination of RGB laser light sources, since the output intensity and output timing of each color (each wavelength) can be controlled with high precision, the white balance of the captured image can be adjusted by the light source device 11203. In this case, by irradiating the observation target with laser beams from each of the RGB laser light sources in a time-division manner and controlling the drive of the imaging element of the camera 11102 in synchronization with the irradiation timing, images corresponding to R, G, and B can be captured in a time-division manner. According to this method, a color image can be obtained even if a color filter is not provided in the imaging element.

[0237] In addition, the light source device 11203 can be controlled to change the intensity of the output light at predetermined time intervals. By controlling the driving of the imaging element of the camera 11102 in synchronization with the timing of the light intensity change, images are acquired in a time-division manner and synthesized, and a high dynamic range image without so-called blackouts or whiteouts can be produced.

[0238] In addition, the light source device 11203 can be configured to supply light in a predetermined wavelength band corresponding to special light observation. Special light observation performs so-called narrowband imaging: this narrowband imaging captures predetermined tissues such as blood vessels in the surface layer of the mucosa with high contrast by, for example, utilizing the wavelength dependence of light absorption in human tissue and irradiating light in a band narrower than the band of irradiation light (i.e., white light) during ordinary observation. Alternatively, in special light observation, fluorescence observation can be performed to obtain an image using fluorescence generated by irradiating excitation light. In fluorescence observation, fluorescence from human tissue can be observed by irradiating the human tissue with excitation light (autofluorescence observation), or a fluorescent image can be obtained by locally injecting a reagent such as indocyanine green (ICG) into the human tissue and irradiating the human tissue with excitation light corresponding to the fluorescence wavelength of the reagent. The light source device 11203 can be configured to supply narrowband light and / or excitation light compatible with such special light observation.

[0239] Figure 15 It shows Figure 14 A block diagram of an example of the functional configuration of the camera 11102 and CCU 11201 is shown.

[0240] The camera 11102 includes a lens unit 11401, an imaging unit 11402, a driving unit 11403, a communication unit 11404, and a camera control unit 11405. The CCU 11201 has a communication unit 11411, an image processor 11412, and a control unit 11413. The camera 11102 and the CCU 11201 are connected via a transmission cable 11400 so as to be able to communicate with each other.

[0241] The lens unit 11401 is an optical system provided at the connection portion with the lens barrel 11101. Observation light obtained from the distal end of the lens barrel 11101 is guided to the camera 11102 and is incident on the lens unit 11401. The lens unit 11401 is constructed by combining a plurality of lenses (including a zoom lens and a focus lens).

[0242] The imaging unit 11402 is constructed using imaging elements. The number of imaging elements forming the imaging unit 11402 may be one (so-called single-board type) or multiple (so-called multi-board type). For example, when the imaging unit 11402 is a multi-board type, image signals corresponding to R, G, and B are generated by each imaging element, and the generated image signals are combined to obtain a color image. Alternatively, the imaging unit 11402 may include a pair of imaging elements configured to acquire a right-eye image signal and a left-eye image signal compatible with a three-dimensional (3D) display. Through the 3D display, the surgeon 11131 can more accurately grasp the depth of living tissue in the surgical site. Note that when the imaging unit 11402 is a multi-board type, a plurality of lens units 11401 can be provided corresponding to each imaging element.

[0243] In addition, the imaging unit 11402 does not have to be provided on the camera head 11102. For example, the imaging unit 11402 can be provided just behind the objective lens in the lens barrel 11101.

[0244] The drive unit 11403 is configured using an actuator and, under the control of the camera control unit 11405, moves the zoom lens and focus lens of the lens unit 11401 by a predetermined distance along the optical axis. As a result, the magnification and focus of the image captured by the imaging unit 11402 can be appropriately adjusted.

[0245] The communication unit 11404 is configured using a communication device that transmits and receives various information to and from the CCU 11201. The communication unit 11404 transmits an image signal obtained from the imaging unit 11402 to the CCU 11201 via the transmission cable 11400 as RAW data.

[0246] In addition, the communication unit 11404 receives a control signal for controlling the driving of the camera 11102 from the CCU 11201, and supplies the control signal to the camera control unit 11405. Examples of the control signal include information associated with imaging conditions, such as information specifying the frame rate of the captured image, information specifying the exposure value when capturing an image, and / or information specifying the magnification and focus of the captured image.

[0247] Note that the above-mentioned imaging conditions such as the frame rate, exposure value, magnification, and focus can be appropriately specified by the user, or can be automatically set based on the acquired image signal by the control unit 11413 of the CCU 11201. In the latter case, the so-called automatic exposure (AE) function, automatic focus (AF) function, and automatic white balance (AWB) function are installed in the endoscope 11100.

[0248] The camera control unit 11405 controls the driving of the camera 11102 based on a control signal received from the CCU 11201 via the communication unit 11404 .

[0249] The communication unit 11411 is configured using a communication device that transmits and receives various information to and from the camera 11102. The communication unit 11411 receives an image signal transmitted from the camera 11102 via the transmission cable 11400.

[0250] Furthermore, the communication unit 11411 transmits a control signal for controlling the driving of the camera 11102 to the camera 11102. The image signal and the control signal can be transmitted through electrical communication, optical communication, or the like.

[0251] The image processor 11412 performs various image processing on the image signal transmitted from the camera 11102 as RAW data.

[0252] The control unit 11413 performs various controls related to imaging the surgical site, etc. through the endoscope 11100 and displaying the captured image obtained by imaging the surgical site, etc. For example, the control unit 11413 generates a control signal for controlling the driving of the camera head 11102 .

[0253] Furthermore, based on the image signal processed by the image processor 11412, the control unit 11413 causes the display device 11202 to display a captured image including the surgical site. In this case, the control unit 11413 can utilize various image recognition technologies to identify various objects in the captured image. For example, the control unit 11413 can detect the edge shape or color of objects included in the captured image to identify surgical tools such as forceps, specific living body parts, bleeding, and mist during the use of the energy therapy tool 11112. When causing the display device 11202 to display the captured image, the control unit 11413 can use the recognition results to overlay various surgical assistance information on the image of the surgical site. Since this surgical assistance information is overlaid and presented to the surgeon 11131, the burden on the surgeon 11131 can be reduced, allowing the surgeon 11131 to perform the surgery reliably.

[0254] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 is an electric signal cable compatible with electric signal communication, an optical fiber compatible with optical communication, or a composite cable compatible with electric and optical communication.

[0255] Here, in the example shown, communication is performed in a wired manner using the transmission cable 11400, but communication between the camera 11102 and the CCU 11201 can also be performed in a wireless manner.

[0256] An example of an endoscopic surgical system to which the technology of the present disclosure can be applied has been described above. The technology of the present disclosure can be applied to the imaging unit 11402 of the camera head 11102 in the above-described configuration. Specifically, an imaging element applicable to the semiconductor device (ROIC substrate) according to the first to fourth embodiments (including modifications) can be used as the imaging unit 11402. For example, since a highly reliable imaging element evaluated as described above can be used as the imaging unit 11402, it is possible to observe an observation target in a patient's body cavity with high reliability.

[0257] Note that although the description here is given taking an endoscopic surgical system as an example, the technology according to the present disclosure can also be applied to, for example, a microscope surgical system or the like.

[0258] In addition, as described above, although the technology according to the present disclosure (the present technology) has been illustrated as being applied to an electronic device or a mobile body (specifically, the above-mentioned vehicle control system) as a camera device, the present technology can also be used in fields such as medical diagnosis, agricultural product inspection, and remote monitoring.

[0259] Note that while the above description describes various effects achieved by the semiconductor device and imaging element according to the embodiments of the present disclosure, these effects do not limit the semiconductor device and imaging element of the present disclosure. Furthermore, not all of the various effects may be achieved. Furthermore, the semiconductor device and imaging element of the present disclosure may also achieve additional effects not described herein.

[0260] Note that the present disclosure can also have the following configurations. (1)

[0262] A semiconductor device comprising:

[0263] a first charge accumulation unit capable of accumulating charge;

[0264] a first initializing unit that is connected to the first charge accumulation unit and initializes the first charge accumulation unit; and

[0265] A first voltage switching unit is connected to the first initialization unit and is capable of selectively supplying a first voltage and a second voltage different from the first voltage to the first initialization unit. (2)

[0267] The semiconductor device according to (1), further comprising:

[0268] a first wiring that supplies the first voltage to the first voltage switching unit; and

[0269] a second wiring that supplies the second voltage to the first voltage switching unit. (3)

[0271] The semiconductor device according to (2), further comprising:

[0272] a third wiring connected to the first initialization unit,

[0273] The first voltage switching unit selectively supplies the first voltage and the second voltage to the first initialization unit by selectively connecting the first wiring and the second wiring to the third wiring. (4)

[0275] The semiconductor device according to (2), further comprising:

[0276] a third wiring connected to the first initialization unit,

[0277] Wherein, the first voltage switching unit includes:

[0278] a first changeover switch provided between the first wiring and the third wiring; and

[0279] A second changeover switch is provided between the second wiring and the third wiring and is capable of switching alternately with the first changeover switch. (5)

[0281] The semiconductor device according to (4), wherein

[0282] The first voltage switching unit further includes a third switch that is provided between the second wiring and the third wiring and is capable of switching in synchronization with the second switch. (6)

[0284] The semiconductor device according to (1), further comprising:

[0285] a second charge accumulation unit capable of accumulating the charge transferred to the first charge accumulation unit; and

[0286] a second initializing unit that is connected to the second charge accumulation unit and initializes the second charge accumulation unit,

[0287] In addition to the first initialization unit, the first voltage switching unit can also selectively supply the first voltage and the second voltage to the second initialization unit. (7)

[0289] The semiconductor device according to (6), further comprising a switch unit that controls connection between the first electric-charge accumulation unit and the second electric-charge accumulation unit. (8)

[0291] The semiconductor device according to (1), further comprising:

[0292] a first analog-to-digital conversion unit that is arranged in the second region and is configured to receive an input of a signal based on the charge accumulated in the first charge accumulation unit through a signal line and perform analog-to-digital conversion on the input signal,

[0293] wherein the first charge accumulation unit is arranged in the first region, and

[0294] The first voltage switching unit is disposed in a third region between the first region and the second region. (9)

[0296] The semiconductor device according to (8), further comprising:

[0297] a second analog-to-digital conversion unit arranged in a fourth region located at a position symmetrical to the second region with the first region as the center, and configured to receive an input of a signal based on the charge accumulated in the first charge accumulation unit through the signal line and perform analog-to-digital conversion on the input signal; and

[0298] A second voltage switching unit is arranged in a fifth area, connected to the first initialization unit, and capable of selectively supplying a first voltage and a second voltage different from the first voltage to the first initialization unit, wherein the fifth area is located at a position symmetrical to the third area with the first area as the center. (10)

[0300] The semiconductor device according to (9), further comprising:

[0301] a second charge accumulation unit capable of accumulating the charge transferred to the first charge accumulation unit; and

[0302] a second initializing unit that is connected to the second charge accumulation unit and initializes the second charge accumulation unit,

[0303] In addition to the first initialization unit, the second voltage switching unit can also selectively supply the first voltage and the second voltage to the second initialization unit. (11)

[0305] An imaging element, comprising:

[0306] a photoelectric conversion unit that receives light and performs photoelectric conversion on the received light to generate electric charges;

[0307] a first charge accumulation unit capable of accumulating the charge;

[0308] a first initializing unit that is connected to the first charge accumulation unit and initializes the first charge accumulation unit; and

[0309] A voltage switching unit is connected to the first initialization unit and is capable of selectively supplying a first voltage and a second voltage different from the first voltage to the first initialization unit. (12)

[0311] The imaging element according to (11), wherein

[0312] The photoelectric conversion unit includes a plurality of pixels arranged in a matrix, receives light, and performs photoelectric conversion on the received light to generate electric charge.

[0313] The first charge accumulation unit and the first initialization unit are provided in each pixel among the plurality of pixels, and

[0314] For a plurality of pixels arranged in one direction among the plurality of pixels, only one voltage switching unit is provided. (13)

[0316] The imaging element according to (11), wherein

[0317] The photoelectric conversion unit is formed on a first substrate,

[0318] The first charge accumulation unit, the first initialization unit, and the voltage switching unit are formed on a second substrate, and

[0319] A first electrode is formed on a surface of the first substrate facing a light incident surface and capable of extracting the charges, and a second electrode is formed on one surface of the second substrate and connected to the first charge accumulation unit. (14)

[0321] An imaging element, comprising:

[0322] a first charge accumulation unit capable of accumulating charge;

[0323] a first initializing unit that is connected to the first charge accumulation unit and initializes the first charge accumulation unit;

[0324] a photoelectric conversion unit that receives light and performs photoelectric conversion on the received light to generate electric charges;

[0325] a second charge accumulation unit capable of accumulating the charges generated by the photoelectric conversion unit and transferring the accumulated charges to the first charge accumulation unit;

[0326] a second initializing unit that is connected to the second charge accumulation unit and initializes the second charge accumulation unit; and

[0327] A voltage switching unit is connected to the first initialization unit and the second initialization unit and is capable of selectively supplying a first voltage and a second voltage different from the first voltage to the first initialization unit and the second initialization unit. (15)

[0329] The imaging element according to (13), wherein

[0330] The photoelectric conversion unit includes a plurality of pixels arranged in a matrix, receives light, and performs photoelectric conversion on the received light to generate electric charge.

[0331] The first charge accumulation unit, the second charge accumulation unit, the first initialization unit, and the second initialization unit are provided in each pixel among the plurality of pixels, and

[0332] For a plurality of pixels arranged in one direction among the plurality of pixels, only one voltage switching unit is provided. (16)

[0334] The imaging element according to (14), wherein

[0335] The photoelectric conversion unit is formed on a first substrate,

[0336] The first charge accumulation unit, the first initialization unit, the second charge accumulation unit, the second initialization unit, and the voltage switching unit are formed on a second substrate, and

[0337] A first electrode is formed on a surface of the first substrate facing a light incident surface and capable of extracting the charges, and a second electrode is formed on one surface of the second substrate and connected to the first charge accumulation unit. (17)

[0339] The imaging element according to (11) or (14), wherein the photoelectric conversion unit contains any one of a compound semiconductor, silicon, germanium, a quantum dot material, and an organic material. (18)

[0341] The image pickup element according to (17), wherein the photoelectric conversion unit is formed using a Group III-V compound semiconductor. (19)

[0343] The imaging element according to (18), wherein the Group III-V compound semiconductor is indium gallium arsenide. (20)

[0345] The image pickup element according to (11) or (14), wherein the photoelectric conversion unit is a silicon image sensor. (twenty one)

[0347] The semiconductor device according to (3), wherein the first voltage switching unit includes a first transistor, one of a source and a drain of the first transistor being connected to the first wiring, and the remaining one of the source and the drain being connected to the third wiring. (twenty two)

[0349] The semiconductor device according to (21), wherein the first voltage switching unit includes a second transistor, one of a source and a drain of the second transistor is connected to the second wiring, and the remaining one of the source and the drain is connected to the third wiring. (twenty three)

[0351] An electronic device comprising:

[0352] Optical system;

[0353] a photoelectric conversion unit that receives light from the optical system and performs photoelectric conversion on the received light to generate electric charge;

[0354] a first charge accumulation unit capable of accumulating the charge;

[0355] a first initializing unit that is connected to the first charge accumulation unit and initializes the first charge accumulation unit; and

[0356] A voltage switching unit is connected to the first initialization unit and is capable of selectively supplying a first voltage and a second voltage different from the first voltage to the first initialization unit. (twenty four)

[0358] An electronic device comprising:

[0359] Optical system;

[0360] a first charge accumulation unit capable of accumulating charge;

[0361] a first initializing unit that is connected to the first charge accumulation unit and initializes the first charge accumulation unit;

[0362] a photoelectric conversion unit that receives light from the optical system and performs photoelectric conversion on the received light to generate electric charge;

[0363] a second charge accumulation unit capable of accumulating the charges generated by the photoelectric conversion unit and transferring the accumulated charges to the first charge accumulation unit;

[0364] a second initializing unit that is connected to the second charge accumulation unit and initializes the second charge accumulation unit; and

[0365] A voltage switching unit is connected to the first initialization unit and the second initialization unit and is capable of selectively supplying a first voltage and a second voltage different from the first voltage to the first initialization unit and the second initialization unit.

[0366] Reference Signs List

[0367] 1, 1A, 1B camera element

[0368] 100, 100A, 100B photoelectric conversion unit

[0369] 11 Insulation layer

[0370] 11A lower electrode

[0371] 12 Contact layer

[0372] 12A Diffusion Area

[0373] 13.41 Photoelectric conversion film

[0374] 14 Upper electrode layer

[0375] 15. Transparent electrode layer

[0376] 200, 200A ROIC substrate

[0377] 21 Upper insulation layer

[0378] 21A connection electrode

[0379] 22 Lower insulation layer

[0380] 22A wiring

[0381] 22B through hole

[0382] 23 silicon layer

[0383] 23N, 23P MOS transistors

[0384] 110-pixel array

[0385] 111, 111A, 111B, 111C, P pixels

[0386] LMU, LMD Load Transistor Unit

[0387] CMU, CMD comparator circuit unit

[0388] CNU, CND counter unit

[0389] CPs storage node capacitor

[0390] CPf floating diffusion capacitor

[0391] CS current source

[0392] FD floating diffusion layer

[0393] PD Photodiode

[0394] SN Storage Node

[0395] Tofg Overflow Gate Transistor

[0396] Ttrg pass transistor

[0397] Trst reset transistor

[0398] Tamp amplifier transistor

[0399] Tsel select transistor

[0400] VSL Vertical Signal Line

[0401] L1, L2, L VDR Wiring

[0402] LO VDR , LR VDR Wiring

[0403] R1 component area

[0404] R2 surrounding area

[0405] S1 Light incident surface

[0406] S2 joint surface

[0407] 60W wiring layer

[0408] 61 first electrode

[0409] 62 first contact layer

[0410] 62A Diffusion Region

[0411] 60S semiconductor layer

[0412] 64 Second contact layer

[0413] 65 Second electrode

[0414] 65B conductive film

[0415] 66 passivation film

[0416] 66H Open

[0417] 67 Insulation Film

[0418] 68 buried layer

[0419] 69A, 69B interlayer insulating film

[0420] 69E, 72E contact electrodes

[0421] 69ED dummy electrode

[0422] 70W wiring layer

[0423] 71 semiconductor substrate

[0424] 72A interlayer insulating film

[0425] 72C multi-layer wiring layer

[0426] 72P pad electrode

[0427] H1, H2 holes

[0428] R1B OPB area

[0429] 42 P-type layer

[0430] 43, 44 N-type layer

[0431] 45 Anti-reflective film

[0432] 46 color filters

[0433] 47 On-chip lens

[0434] 51 passivation layer

[0435] 53A, 53B connection electrodes

[0436] 54 bump electrodes

[0437] 80 Capacitor Components

[0438] 12100 vehicles

[0439] 12000 Vehicle Control Systems

[0440] 12001 Communication Network

[0441] 12030 External vehicle information detection unit

[0442] 12050 Integrated Control Unit

[0443] 12051 Microcomputer

[0444] 12053 In-vehicle Network I / F

[0445] 11000 Endoscopic Surgery System

[0446] 11100 Endoscope

[0447] 11110 Surgical Tools

[0448] 11111 Insufflable tube

[0449] 11112 Energy Healing Tools

[0450] 11120 Support Arm Device

[0451] 11101 Lens Tube

[0452] 11102 Camera

[0453] 11200 Cart

[0454] 11201 CCU

[0455] 11202 Display Device

[0456] 11203 Light Source Device

[0457] 11204 Input Device

[0458] 11205 Treatment tool control device

[0459] 11206 Pneumoperitoneum device

[0460] 11207 Recorder

[0461] 11400 Transmission Cable

[0462] 11401 lens unit

[0463] 11402 Camera Unit

[0464] 11403 drive unit

[0465] 11404, 11411 communication units

[0466] 11405 Camera Control Unit

[0467] 11412 Image Processor

[0468] 11413 Control Unit

Claims

1. A semiconductor device comprising: a first charge accumulation unit capable of accumulating charge; a first initializing unit that is connected to the first charge accumulation unit and initializes the first charge accumulation unit; a first voltage switching unit connected to the first initialization unit and capable of selectively supplying a first voltage and a second voltage different from the first voltage to the first initialization unit, a second charge accumulation unit capable of accumulating the charge transferred to the first charge accumulation unit; and a second initializing unit that is connected to the second charge accumulation unit and initializes the second charge accumulation unit, In addition to the first initialization unit, the first voltage switching unit can also selectively supply the first voltage and the second voltage to the second initialization unit.

2. The semiconductor device according to claim 1, further comprising: a first wiring that supplies the first voltage to the first voltage switching unit; and a second wiring that supplies the second voltage to the first voltage switching unit.

3. The semiconductor device according to claim 2, further comprising: a third wiring connected to the first initialization unit, The first voltage switching unit selectively supplies the first voltage and the second voltage to the first initialization unit by selectively connecting the first wiring and the second wiring to the third wiring.

4. The semiconductor device according to claim 2, further comprising: a third wiring connected to the first initialization unit, Wherein, the first voltage switching unit includes: a first changeover switch provided between the first wiring and the third wiring; and A second changeover switch is provided between the second wiring and the third wiring and is capable of switching alternately with the first changeover switch.

5. The semiconductor device according to claim 4, wherein The first voltage switching unit further includes a third switch that is provided between the second wiring and the third wiring and is capable of switching in synchronization with the second switch. 6 . The semiconductor device according to claim 1 , further comprising a switch unit that controls connection between the first charge accumulation unit and the second charge accumulation unit.

7. The semiconductor device according to any one of claims 1 to 5, further comprising: a first analog-to-digital conversion unit that is arranged in the second region and is configured to receive an input of a signal based on the charge accumulated in the first charge accumulation unit through a signal line and perform analog-to-digital conversion on the input signal, wherein the first charge accumulation unit is arranged in the first region, and The first voltage switching unit is disposed in a third region between the first region and the second region.

8. The semiconductor device according to claim 7, further comprising: a second analog-to-digital conversion unit arranged in a fourth region located at a position symmetrical to the second region with the first region as the center, and configured to receive an input of a signal based on the charge accumulated in the first charge accumulation unit through the signal line and perform analog-to-digital conversion on the input signal; and A second voltage switching unit is arranged in a fifth region, connected to the first initialization unit, and capable of selectively supplying the first voltage and the second voltage to the first initialization unit. The fifth region is located at a position symmetrical to the third region with the first region as the center.

9. The semiconductor device according to claim 8, in, The second voltage switching unit is capable of selectively supplying the first voltage and the second voltage to the second initialization unit in addition to the first initialization unit.

10. The semiconductor device according to claim 3, wherein The first voltage switching unit includes a first transistor having one of a source and a drain connected to the first wiring and the remaining one of the source and the drain connected to the third wiring.

11. The semiconductor device according to claim 10, wherein The first voltage switching unit includes a second transistor having one of a source and a drain connected to the second wiring and the remaining one of the source and the drain connected to the third wiring.

12. An imaging element, comprising: a photoelectric conversion unit that receives light and performs photoelectric conversion on the received light to generate electric charges; a first charge accumulation unit capable of accumulating the charge; a first initializing unit that is connected to the first charge accumulation unit and initializes the first charge accumulation unit; a first voltage switching unit connected to the first initialization unit and capable of selectively supplying a first voltage and a second voltage different from the first voltage to the first initialization unit, a second charge accumulation unit capable of accumulating the charge transferred to the first charge accumulation unit; and a second initializing unit that is connected to the second charge accumulation unit and initializes the second charge accumulation unit, In addition to the first initialization unit, the first voltage switching unit can also selectively supply the first voltage and the second voltage to the second initialization unit.

13. The imaging element according to claim 12, wherein: The photoelectric conversion unit includes a plurality of pixels arranged in a matrix, receives light, and performs photoelectric conversion on the received light to generate electric charge. The first charge accumulation unit and the first initialization unit are provided in each pixel among the plurality of pixels, and For a plurality of pixels arranged in one direction among the plurality of pixels, only one first voltage switching unit is provided.

14. The imaging element according to claim 12, wherein The photoelectric conversion unit is formed on a first substrate, The first charge accumulation unit, the first initialization unit, and the first voltage switching unit are formed on a second substrate, and A first electrode is formed on a surface of the first substrate facing a light incident surface and capable of extracting the charges, and a second electrode is formed on one surface of the second substrate and connected to the first charge accumulation unit.

15. The imaging element according to any one of claims 12 to 14, wherein The photoelectric conversion unit contains any one of a compound semiconductor, silicon, germanium, a quantum dot material, and an organic material.

16. The imaging element according to claim 15, wherein The photoelectric conversion unit is formed using a Group III-V compound semiconductor.

17. An imaging element, comprising: a first charge accumulation unit capable of accumulating charge; a first initializing unit that is connected to the first charge accumulation unit and initializes the first charge accumulation unit; a photoelectric conversion unit that receives light and performs photoelectric conversion on the received light to generate electric charges; a second charge accumulation unit capable of accumulating the charges generated by the photoelectric conversion unit and transferring the accumulated charges to the first charge accumulation unit; a second initializing unit that is connected to the second charge accumulation unit and initializes the second charge accumulation unit; and A voltage switching unit is connected to the first initialization unit and the second initialization unit and is capable of selectively supplying a first voltage and a second voltage different from the first voltage to the first initialization unit and the second initialization unit.

18. The imaging element according to claim 17, wherein The photoelectric conversion unit includes a plurality of pixels arranged in a matrix, receives light, and performs photoelectric conversion on the received light to generate electric charge. The first charge accumulation unit, the second charge accumulation unit, the first initialization unit, and the second initialization unit are provided in each pixel among the plurality of pixels, and For a plurality of pixels arranged in one direction among the plurality of pixels, only one voltage switching unit is provided.

19. The imaging element according to claim 17, wherein The photoelectric conversion unit is formed on a first substrate, The first charge accumulation unit, the first initialization unit, the second charge accumulation unit, the second initialization unit, and the voltage switching unit are formed on a second substrate, and A first electrode is formed on a surface of the first substrate facing a light incident surface and capable of extracting the charges, and a second electrode is formed on one surface of the second substrate and connected to the first charge accumulation unit.

20. The imaging element according to any one of claims 17 to 19, wherein The photoelectric conversion unit contains any one of a compound semiconductor, silicon, germanium, a quantum dot material, and an organic material.

21. The imaging element according to claim 20, wherein The photoelectric conversion unit is formed using a Group III-V compound semiconductor.

22. An electronic device comprising: Optical system; and The imaging element according to any one of claims 12 to 21.

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