A method for generating a decoding circuit and related apparatus

Abstract

The application discloses a decoding circuit generation method and related equipment, relates to the technical field of integrated circuits, and can realize automatic splicing and expansion of decoding circuit layouts corresponding to different capacity SRAMs according to different words and the number of multiplexers. The decoding circuit generation method comprises the following steps: in a circuit layout design environment, determining the number and types of binary decoders required by a first-stage row decoding module and the number of logic decoders required by a second-stage row decoding module according to the target storage capacity of a target memory; calling a decoder structure package according to the number and types of binary decoders required by the first-stage row decoding module and the number of logic decoders required by the second-stage row decoding module; and connecting the called decoder structure package.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a method for generating a decoding circuit and related equipment. Background Technology

[0002] Memory, as a crucial component of large-scale integrated circuits, improves system efficiency, reduces power consumption, and lowers packaging costs. Typically, during the design phase, the required memory can be generated using a memory compiler generator. The area, power consumption, and speed of the generated memory are all critical factors for the user. To achieve a memory compiler that generates small-area, low-power, and high-speed memory, the layout generation method of its SRAM (Static Random Access Memory) decoding circuit module is essential. The SRAM structure mainly includes decoding circuitry and memory arrays. On the entire SRAM chip, the memory array occupies the largest area, followed by the decoding circuitry. The decoding circuitry is a vital structure used to select specific rows and columns of memory cells.

[0003] However, existing SRAM layouts are typically customized for single-capacity SRAMs, with custom-designed decoding circuits, making them unsuitable for implementing memory compilers. When the number of words and multiplexer channels changes, the single-capacity customized decoding circuit layout generation method cannot meet the automation requirements of memory compiler design. Summary of the Invention

[0004] This application provides a method for generating a decoding circuit, a decoding circuit, and a memory circuit, which can automatically splice and expand the decoding circuit layout corresponding to SRAM of different capacities for different words and the number of multiplexers.

[0005] A first aspect of this application provides a method for generating a decoding circuit, characterized in that it includes:

[0006] In the circuit layout design environment, based on the target storage capacity of the target memory, determine the number of binary decoders required for the first-level row decoding module and the corresponding binary decoder types, as well as the number of logic decoders required for the second-level row decoding module;

[0007] Based on the number of binary decoders required by the first-level row decoding module and the corresponding binary decoder types, as well as the number of logic decoders required by the second-level row decoding module, the decoder structure package is invoked;

[0008] The decoder structure package invoked via connection.

[0009] In some embodiments, before the connecting the decoder structure package called by the first row decoding module and the decoder structure package called by the second row decoding module through the splicing module, further comprising:

[0010] In the circuit layout design environment, the decoder structure package is constructed, wherein the decoder structure package comprises a first decoder structure package and a second decoder structure package, the first decoder structure package has the circuit structure of the corresponding binary decoder, and the second decoder structure package has the circuit structure of the corresponding logic decoder;

[0011] The determining, in the circuit layout design environment, the number of binary decoders and the corresponding binary decoder types required by the first row decoding module and the number of logic decoders required by the second row decoding module according to the target storage capacity of the target memory comprises:

[0012] In the circuit layout design environment, the number of first decoder structure packages and the corresponding circuit structures of binary decoders required by the first row decoding module and the number of second decoder structure packages required by the second row decoding module are determined according to the target storage capacity of the target memory.

[0013] In some embodiments, before the connecting the decoder structure package called by the first row decoding module and the decoder structure package called by the second row decoding module through the splicing module, further comprising:

[0014] In the circuit layout design environment, a splicing module is constructed.

[0015] The connecting the decoder structure package called comprises:

[0016] According to the number of binary decoders and the corresponding binary decoder types required by the first row decoding module and the number of logic decoders required by the second row decoding module, the splicing module is called.

[0017] The corresponding decoder structure package of the first row decoding module and the corresponding decoder structure package of the second row decoding module are connected through the splicing module.

[0018] In some embodiments, the determining, in the circuit layout design environment, the number of binary decoders and the corresponding binary decoder types required by the first row decoding module and the number of logic decoders required by the second row decoding module according to the target storage capacity of the target memory comprises:

[0019] determining the target storage capacity of the target memory according to the number of memory cells of the target memory and the number of paths of the multiplexer;

[0020] determining the number and the type of the binary decoders required by the primary row decoding module and the number of the logic decoders required by the secondary row decoding module according to the target storage capacity.

[0021] In some embodiments, the target storage capacity comprises a target word line number, and the determining the target storage capacity of the target memory according to the number of memory cells of the target memory and the number of paths of the multiplexer comprises:

[0022] determining the target word line number of the target memory according to the number of memory cells of the target memory and the number of paths of the multiplexer by the following formula:

[0023] WL = W / M,

[0024] wherein, WL is the target word line number, W is the number of memory cells of the target memory, and M is the number of paths of the multiplexer of the target memory.

[0025] In some embodiments, the determining the number and the type of the binary decoders required by the primary row decoding module and the number of the logic decoders required by the secondary row decoding module according to the target storage capacity comprises:

[0026] when WL = 32, determining that the number of the binary decoders required by the primary row decoding module is two, the corresponding types of the binary decoders are 3-line-8-line decoders and 2-line-4-line decoders respectively, and the number of the logic decoders required by the secondary row decoding module is 32;

[0027] when 33 ≤ WL ≤ 64, determining that the number of the binary decoders required by the primary row decoding module is two, the corresponding types of the binary decoders are both 3-line-8-line decoders, and the number of the logic decoders required by the secondary row decoding module is the same as the value of the target word line number;

[0028] when 65 ≤ WL ≤ 128, determining that the number of the binary decoders required by the primary row decoding module is three, the corresponding types of the binary decoders are one 1-line-2-line decoder and two 3-line-8-line decoders respectively, and the number of the logic decoders required by the secondary row decoding module is the same as the value of the target word line number;

[0029] When 129≤WL≤256, the number of the binary decoders required by the primary row decoding module is determined to be three, the corresponding binary decoder types are one 2-wire-4-wire decoder and two 3-wire-8-wire decoders respectively, and the number of the logical decoders required by the secondary row decoding module is determined to be the same as the value of the target word line number;

[0030] When 257≤WL≤512, the number of the binary decoders required by the primary row decoding module is determined to be three, the corresponding binary decoder types are all 3-wire-8-wire decoders, and the number of the logical decoders required by the secondary row decoding module is determined to be the same as the value of the target word line number.

[0031] In a second aspect, the embodiment of the present application provides a generation apparatus of a decoding circuit, which comprises:

[0032] A decoder determining module is configured to determine, in a circuit layout design environment, the number of binary decoders required by a primary row decoding module and the corresponding binary decoder types according to a target storage capacity of a target memory, and determine the number of logical decoders required by a secondary row decoding module.

[0033] A structure package calling module is configured to call a decoder structure package according to the number of binary decoders required by the primary row decoding module and the corresponding binary decoder types, and the number of logical decoders required by the secondary row decoding module.

[0034] A connecting module is configured to connect the called decoder structure package.

[0035] In a third aspect, the embodiment of the present application provides an electronic device, which comprises:

[0036] A memory, in which a computer program is stored.

[0037] A processor, which is configured to implement the generation method of the decoding circuit according to the first aspect when the computer program is executed.

[0038] In a fourth aspect, the embodiment of the present application provides a computer readable storage medium, in which a computer program is stored, and the computer program is configured to implement the generation method of the decoding circuit according to the first aspect when executed by a processor.

[0039] In a fifth aspect, the embodiment of the present application provides a decoding circuit, which is generated by using the generation method of the decoding circuit according to the first aspect, and the decoding circuit comprises:

[0040] A primary row decoding module, which comprises at least one binary decoder.

[0041] The secondary row decoding module includes at least one logic decoder, one end of the secondary row decoding module is electrically connected with the primary row decoding module, and the other end is used for electrically connecting a memory.

[0042] The generation method of the decoding circuit and the related device provided by the embodiment of the application can realize two-stage decoding by setting the primary row decoding module and the secondary row decoding module, the cascade connection of the primary row decoding module and the secondary row decoding module can increase the number of decoding bits, increase the decoding capacity, improve the decoding rate, reduce the delay and power consumption, and the decoding circuit occupies a smaller area under the same decoding capacity. After the number and types of the binary decoders required by the primary row decoding module and the number of the logic decoders required by the secondary row decoding module are determined, the corresponding number and types of the decoder structure packages can be directly called, and the generation efficiency of the decoding circuit can be improved. Different capacity decoding circuits can be generated according to the demand of the target storage capacity, and the expansion of the decoding circuit of the corresponding memory can be adapted. The called decoder structure packages can be connected, specifically, the binary decoder structure package corresponding to the primary row decoding module and the logic decoder structure package corresponding to the secondary row decoding module can be connected, and the decoding circuit can be generated. The automatic generation of the decoding circuit can be realized, the target storage capacity can be input, and the decoding circuit can be automatically obtained, and the design technology of the decoding circuit is simplified. BRIEF DESCRIPTION OF DRAWINGS

[0043] Figure 1 The generation method of the decoding circuit provided by the embodiment of the application is shown in the schematic flowchart;

[0044] Figure 2 The generation device of the decoding circuit provided by the embodiment of the application is shown in the schematic structural block diagram;

[0045] Figure 3 The electronic device provided by the embodiment of the application is shown in the schematic structural block diagram;

[0046] Figure 4 The computer readable storage medium provided by the embodiment of the application is shown in the schematic structural block diagram;

[0047] Figure 5 The decoding circuit provided by the embodiment of the application is shown in the schematic structural block diagram;

[0048] Figure 6 The decoding circuit provided by the embodiment of the application is shown in the schematic structural block diagram. DETAILED DESCRIPTION

[0049] In order to better understand the technical solutions provided by the embodiments of the present specification, the technical solutions of the embodiments of the present specification will be described in detail below through the accompanying drawings and specific embodiments. It should be understood that the specific features in the embodiments of the present specification and the embodiments are detailed descriptions of the technical solutions of the embodiments of the present specification, and are not limitations of the technical solutions of the present specification. In the case of no conflict, the technical features in the embodiments of the present specification and the embodiments can be combined with each other.

[0050] In this document, relational terms such as first and second and the like can be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without more constraints, exclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element. The term "two or more" includes two or more than two.

[0051] Memory as an important part of large-scale integrated circuits, can improve the efficiency of the system, reduce power consumption and reduce packaging costs. Generally in the design phase, the required memory can be generated according to the generator of Memory Compiler, and the area, power consumption and speed of the generated memory are very important to the user. To realize the generation of memory compiler with small area, low power consumption and high speed, the layout generation method of SRAM decoding circuit module is crucial. The SRAM structure mainly includes decoding circuit and storage array. On the whole SRAM chip, the storage array occupies the most area, followed by the decoding circuit. The decoding circuit is an important structure for selecting a specific row and column storage unit. However, the existing SRAM layout structure is usually a single capacity customized SRAM, and its decoding circuit is customized and not suitable for implementing Memory Compiler. When the number of words and the number of multiplexers change, the decoding circuit layout generation method of single capacity customization cannot meet the automation needs of Memory Compiler design.

[0052] Therefore, the embodiments of the present application provide a decoding circuit generation method and related equipment, which can realize the automatic splicing and expansion of the decoding circuit layout corresponding to SRAM of different capacities for different words and the number of multiplexers.

[0053] In a first aspect, the present application provides a generation method of a decoding circuit, Figure 1 A schematic flowchart of the generation method of the decoding circuit is shown in FIG. 1. As shown in FIG. 1, the generation method of the decoding circuit comprises the following steps. Figure 1

[0054] In the circuit layout design environment, the number and type of binary decoders required by the first-level row decoding module and the number of logic decoders required by the second-level row decoding module are determined according to the target storage capacity of the target memory. Since the direct decoding decoding circuit will cause the problems of large layout area requirement of the decoding circuit and slow decoding rate, it is difficult to meet the SRAM with large storage capacity. The decoding circuit generated by the generation method of the decoding circuit provided by the present application sets the first-level row decoding module and the second-level row decoding module, which can realize two-stage decoding. The cascaded first-level row decoding module and second-level row decoding module can increase the number of decoding bits, increase the decoding capacity, improve the decoding rate, reduce the delay and power consumption, and occupy a smaller area under the same decoding capacity. In the design stage of the decoding circuit or in the design stage of the memory, the decoding circuit can be generated in the circuit layout design environment. Therefore, the number of binary decoders required by the first-level row decoding module in the decoding circuit and the type of binary decoders required by the first-level row decoding module can be determined according to the target storage capacity of the target memory. The types of binary decoders required by the first-level row decoding module usually include 1-line-2-line decoders, 2-line-4-line decoders and 3-line-8-line decoders. The 1-line-2-line decoder represents a binary decoder with 1 input line and 2 output lines. The 2-line-4-line decoder represents a binary decoder with 2 input lines and 4 output lines. The 3-line-8-line decoder represents a binary decoder with 3 input lines and 8 output lines. The corresponding binary decoders can be 1-line-2-line decoders, 2-line-4-line decoders and 3-line-8-line decoders. The output lines of the binary decoders in the first-level row decoding module are connected to the input lines of the logic decoders in the second-level row decoding module. The logic decoders can be logic gate cascaded devices, which are not limited in the present application.

[0055] ​S200: According to the number and type of binary decoders required by the primary row decoding module and the number of logic decoders required by the secondary row decoding module, a decoder structure package is called. The decoder structure package can be a circuit structure of a decoder ready in a circuit layout design environment. After the number and type of binary decoders required by the primary row decoding module and the number of logic decoders required by the secondary row decoding module are determined, the corresponding number and type of decoder structure packages can be directly called, which can improve the generation efficiency of the decoding circuit. Different capacity decoding circuits can also be generated according to the demand of the target storage capacity, which can adapt to the expansion of the decoding circuit of the corresponding memory. For example, each decoder structure package includes a circuit structure of a binary decoder or a circuit structure of a logic gate-level device, and the embodiments of the present application are not limited specifically.

[0056] S300: The called decoder structure package is connected. The called decoder structure package can be connected to generate a decoding circuit. For example, the decoder structure package corresponding to the primary row decoding module and the decoder structure package corresponding to the secondary row decoding module can be connected to generate a decoding circuit. The automatic generation of the decoding circuit can be realized, and for example, the target storage capacity can be input to automatically obtain the decoding circuit, which simplifies the technicality of the decoding circuit design.

[0057] The generation method of the decoding circuit provided by the embodiments of the present application can realize two-stage decoding by setting the primary row decoding module and the secondary row decoding module. The cascaded primary row decoding module and the secondary row decoding module can increase the decoding bit number, increase the decoding capacity, improve the decoding rate, reduce the delay and power consumption, and occupy a smaller area under the same decoding capacity. After the number and type of binary decoders required by the primary row decoding module and the number of logic decoders required by the secondary row decoding module are determined, the corresponding number and type of decoder structure packages can be directly called, which can improve the generation efficiency of the decoding circuit. Different capacity decoding circuits can also be generated according to the demand of the target storage capacity, which can adapt to the expansion of the decoding circuit of the corresponding memory. The called decoder structure package can be connected to generate a decoding circuit. For example, the decoder structure package corresponding to the primary row decoding module and the decoder structure package corresponding to the secondary row decoding module can be connected to generate a decoding circuit. The automatic generation of the decoding circuit can be realized, and for example, the target storage capacity can be input to automatically obtain the decoding circuit, which simplifies the technicality of the decoding circuit design.

[0058] In some embodiments, before step S100, the method can further include:

[0059] In a circuit layout design environment, a decoder structure package is constructed, wherein the decoder structure package includes a first decoder structure package and a second decoder structure package, the first decoder structure package has circuit structures of corresponding binary decoders therein, and the second decoder structure package has circuit structures of corresponding logic decoders therein. The first decoder structure package can be used to construct a first-level row decoding module, and the second decoder structure package can be used to construct a second-level row decoding module. The first decoder structure package and the second decoder structure package can be different types of decoders. For example, the circuit structures corresponding to the first decoder structure package are circuit structures of binary decoders, such as 1-line-2-line decoders, 2-line-4-line decoders, and 3-line-8-line decoders. The circuit structures corresponding to the second decoder structure package are logic gate cascaded devices, which can perform decoding operation processing on data output by the first-level row decoding module. The embodiments of the present application are not limited in this regard.

[0060] Step S100 can include:

[0061] In a circuit layout design environment, according to a target storage capacity of a target memory, the number of first decoder structure packages required by a first-level row decoding module and the circuit structures of corresponding binary decoders, and the number of second decoder structure packages required by a second-level row decoding module are determined.

[0062] The generation method of the decoding circuit provided in the embodiments of the present application can pre-construct decoder structure packages according to different requirements, construct different decoder structure packages according to different decoder circuit structures, and directly call the pre-constructed decoder structure packages in the process of generating the decoding circuit, which can improve the efficiency of generating the decoding circuit.

[0063] In some embodiments, before step S300, the method further includes:

[0064] In a circuit layout design environment, a splicing module is constructed. The splicing module can be used to connect the first decoder structure package corresponding to the first-level row decoding module and the second decoder structure package corresponding to the second-level row decoding module.

[0065] Step S300 includes:

[0066] According to the number and types of binary decoders required by the first-level row decoding module and the number of logic decoders required by the second-level row decoding module, the splicing module is called. The splicing module can have multiple types, different types of splicing modules are provided with different connection schemes or numbers of connection lines, and can be used for multiple combination schemes of the first decoder structure package and the second decoder structure package. Pre-constructing multiple splicing modules can improve the splicing efficiency.

[0067] The decoder structure package corresponding to the called first row decoding module is connected with the decoder structure package corresponding to the second row decoding module through the splicing module.

[0068] The method for generating the decoding circuit provided in the embodiments of the present application can be used in a combination scheme of a plurality of first decoder structure packages and second decoder structure packages, a plurality of splicing modules are constructed in advance, and the splicing efficiency can be improved.

[0069] In some embodiments, in a circuit layout design environment, according to a target storage capacity of a target memory, the number of binary decoders required by the first row decoding module and the corresponding binary decoder types are determined, and the number of logic decoders required by the second row decoding module is determined, including:

[0070] According to the number of storage units of the target memory and the number of paths of the multiplexer, the target storage capacity of the target memory is determined. It should be noted that the target memory is a memory required to be accessed by the decoding circuit, and the number of storage units in the memory can also be referred to as a word or an information unit, etc. The number of paths of the multiplexer can be understood as the number of data multiplexing.

[0071] According to the target storage capacity, the number of binary decoders required by the first row decoding module and the corresponding binary decoder types are determined, and the number of logic decoders required by the second row decoding module is determined.

[0072] In some embodiments, the target storage capacity can be represented by the number of target word lines, and according to the number of storage units of the target memory and the number of paths of the multiplexer, the target storage capacity of the target memory is determined, including:

[0073] According to the number of storage units of the target memory and the number of paths of the multiplexer, the number of target word lines of the target memory is calculated according to the following formula:

[0074] WL=W / M,

[0075] Wherein, WL is the number of target word lines, W is the number of storage units of the target memory, and M is the number of paths of the multiplexer of the target memory. The ratio of the word of the target memory to the number of paths of the multiplexer can be regarded as the number of rows of storage units or storage blocks in the target memory, and can represent the target storage capacity of the target memory, which is not limited in the embodiments of the present application.

[0076] In some embodiments, in a circuit layout design environment, according to a target storage capacity, the number and corresponding types of binary decoders required by a primary row decoding module and the number of logic decoders required by a secondary row decoding module are determined, including:

[0077] When WL=32, the number of binary decoders required by the primary row decoding module is determined to be two, the corresponding types of binary decoders are 3-to-8 decoder and 2-to-4 decoder respectively, and the number of logic decoders required by the secondary row decoding module is determined to be 32. Wherein, the primary row decoding module can include low bit decoders, middle bit decoders and high bit decoders, the 2-to-4 decoder can be used as the middle bit decoder, the 3-to-8 decoder can be used as the low bit decoder, and when WL=32, the corresponding decoding capacity can be completed without the high bit decoder. Then the output results of the 3-to-8 decoder and the 2-to-4 decoder of the primary row decoding module can have 4x8 combinations, i.e. 32 combination results, the secondary row decoding module can be used for decoding operation, which can be similar to the function of AND operation, the output of any low bit decoder and the output of any middle bit decoder are operated to obtain the output result, then any two of the output of the 3-to-8 decoder and the output of the 2-to-4 decoder are combined and operated, there can be 32 results, then the number of logic decoders required by the secondary row decoding module is also 32. Each logic decoder in the secondary row decoding module corresponds to an address of a storage unit, and there will always be one output result as a global pulse control signal in the 32 secondary row decoding modules. Then the corresponding logic decoder in the secondary row decoding module outputting the global pulse control signal can correspond to the position of a storage unit in the memory, and can complete row address decoding to store the data to be stored in a storage unit in the row. The output results of the secondary row decoding module are input to the corresponding storage array to select the storage unit of the corresponding row, and complete row decoding, then the target data can be stored in a storage unit in the selected row. Exemplarily, the global pulse control signal can be 0 or 1, which is not limited in the embodiments of the present application.

[0078] When 33≤WL≤64, the number of binary decoders required by the first-level row decoding module is determined to be two, the corresponding binary decoder types are both 3-line-8-line decoders, and the number of logic decoders required by the second-level row decoding module is determined to be the same as the value of the target word line number. The low-bit decoder and the middle-bit decoder are both 3-line-8-line decoders. For example, when WL=48, the first-level row decoding module composed of two 3-line-8-line decoders corresponds to the second-level row decoding module that can have 64 output results, but since the target word line number is only 48, 16 output results do not have corresponding memory cell arrays, that is, useless, so the number of decoders of the second-level row decoding module can be set to only 48. Starting from the low-bit decoder of the first-level row decoding module, after the low-bit decoder is arranged, the middle-bit decoder is arranged, and the useless 16 positions can be the corresponding positions of the middle-bit decoder.

[0079] When 65≤WL≤128, the number of binary decoders required by the first-level row decoding module is determined to be three, the corresponding binary decoder types are respectively one 1-line-2-line decoder and two 3-line-8-line decoders, and the number of logic decoders required by the second-level row decoding module is determined to be the same as the value of the target word line number. The 1-line-2-line decoder can be used as a high-bit decoder, and the two 3-line-8-line decoders are a middle-bit decoder and a low-bit decoder, respectively.

[0080] When 129≤WL≤256, the number of binary decoders required by the first-level row decoding module is determined to be three, the corresponding binary decoder types are respectively one 2-line-4-line decoder and two 3-line-8-line decoders, and the number of logic decoders required by the second-level row decoding module is determined to be the same as the value of the target word line number. The 2-line-4-line decoder can be used as a high-bit decoder, and the two 3-line-8-line decoders are a middle-bit decoder and a low-bit decoder, respectively.

[0081] When 257≤WL≤512, the number of binary decoders required by the first-level row decoding module is determined to be three, the corresponding binary decoder types are all 3-line-8-line decoders, and the number of logic decoders required by the second-level row decoding module is determined to be the same as the value of the target word line number. The low-bit decoder, the middle-bit decoder, and the high-bit decoder are all 3-line-8-line decoders.

[0082] The method for generating a decoding circuit provided in the embodiments of the present application comprises the following steps: calculating the number of target word lines of a target memory according to the number of memory cells of the target memory and the number of paths of a multiplexer; determining the number of binary decoders required in a first row decoding module and the type of the binary decoders corresponding to the binary decoders, and determining the number of logic decoders required in a second row decoding module based on the number of target word lines; when the number of target word lines is less than the maximum output combination number of decoders in the first row decoding module, the number of target word lines can be used as the number of logic decoders required in the second row decoding module, so that the area of the second row decoding module and the number of logic decoders in the second row decoding module can be saved, and unnecessary device waste can be avoided. Based on the number of target word lines, the number of binary decoders and logic decoders is determined, so that the automation of the generation of the decoding circuit can be realized, and the automatic splicing and expansion of the layout of the decoding circuit corresponding to different capacity SRAMs can be realized according to different words and the number of paths of the multiplexer.

[0083] In a second aspect, the embodiments of the present application provide a decoding circuit generation device, Figure 2 A schematic structural block diagram of a decoding circuit generation device provided in the embodiments of the present application is shown in FIG. 6. Figure 2 As shown in FIG. 6, the decoding circuit generation device comprises the following modules:

[0084] The decoder determination module 610 is configured to determine the number of binary decoders required in a first row decoding module and the type of the binary decoders corresponding to the binary decoders, and determine the number of logic decoders required in a second row decoding module according to the target storage capacity of a target memory in a circuit layout design environment.

[0085] The structure package calling module 620 is configured to call a decoder structure package according to the number of binary decoders required in the first row decoding module and the type of the binary decoders corresponding to the binary decoders, and the number of logic decoders required in the second row decoding module.

[0086] The connection module 630 is configured to connect the called decoder structure package.

[0087] The generation device of the decoding circuit provided in the embodiments of the present application can realize two-stage decoding by setting a first-stage row decoding module and a second-stage row decoding module, the cascaded first-stage row decoding module and second-stage row decoding module can increase the number of decoding bits, increase the decoding capacity, improve the decoding rate, reduce the delay and power consumption, and the decoding circuit occupies a smaller area under the condition of the same decoding capacity. After the number and type of the binary decoders required by the first-stage row decoding module and the number of the logic decoders required by the second-stage row decoding module are determined, the corresponding number and type of the decoder structure package can be directly called, and the generation efficiency of the decoding circuit can be improved. Different capacity decoding circuits can be generated according to the demand of the target storage capacity, and the expansion of the decoding circuit of the corresponding memory can be adapted. The called decoder structure package can be connected, specifically, the decoder structure package corresponding to the first-stage row decoding module and the decoder structure package corresponding to the second-stage row decoding module can be connected, and the decoding circuit can be generated. The automatic generation of the decoding circuit can be realized, the target storage capacity can be input, and the decoding circuit can be automatically obtained, and the design technology of the decoding circuit is simplified.

[0088] In a third aspect, the embodiments of the present application provide an electronic device, Figure 3 A schematic structural block diagram of an electronic device provided in the embodiments of the present application is shown in FIG. 7. Figure 3 As shown in FIG. 7, the electronic device includes:

[0089] A memory 710, in which a computer program is stored;

[0090] A processor 720, configured to implement the generation method of the decoding circuit according to the first aspect when the computer program is executed.

[0091] The generation method of the decoding circuit includes:

[0092] In the circuit layout design environment, the number and type of the binary decoders required by the first-stage row decoding module and the number of the logic decoders required by the second-stage row decoding module are determined according to the target storage capacity of the target memory;

[0093] The decoder structure package is called according to the number and type of the binary decoders required by the first-stage row decoding module and the number of the logic decoders required by the second-stage row decoding module;

[0094] The called decoder structure package is connected.

[0095] In a fourth aspect, the embodiments of the present application provide a computer readable storage medium, Figure 4 A schematic structural block diagram of a computer readable storage medium provided in the embodiments of the present application is shown in FIG. 8. Figure 4As shown, the computer readable storage medium 800 stores a computer program 810, which, when executed by a processor, implements the generation method of the decoding circuit according to the first aspect.

[0096] The generation method of the decoding circuit comprises:

[0097] In the circuit layout design environment, according to a target storage capacity of a target memory, the number and corresponding types of binary decoders required by the primary row decoding module are determined, and the number of logic decoders required by the secondary row decoding module is determined;

[0098] According to the number and corresponding types of binary decoders required by the primary row decoding module and the number of logic decoders required by the secondary row decoding module, a decoder structure package is invoked;

[0099] The invoked decoder structure package is connected.

[0100] The fifth aspect of the embodiments of the present application provides a decoding circuit, which is generated by applying the generation method of the decoding circuit according to the first aspect, Figure 5 A schematic structural block diagram of a decoding circuit provided by the embodiments of the present application is shown in FIG. 1. Figure 5 As shown, the decoding circuit provided by the embodiments of the present application comprises: a primary row decoding module 100, the primary row decoding module 100 comprising at least one binary decoder; a secondary row decoding module 200, the secondary row decoding module 200 comprising at least one logic decoder, one end of the secondary row decoding module 200 being electrically connected to the primary row decoding module 100, and the other end being used for electrically connecting a memory cell array 2000. It should be noted that the types of the binary decoders in the primary row decoding module 100 and the logic decoders in the secondary row decoding module 200 can be different. The output of the secondary row decoding module 200 can be used as the output of the decoding circuit, and the decoding circuit can decode an address signal to obtain a target storage address, which can be the address path of any memory cell in the memory cell array 2000. The embodiments of the present application do not make specific limitations. It should be noted that the memory cell array 2000 can represent a target memory.

[0101] The decoding circuit provided by the embodiments of the present application sets the primary row decoding module 100 and the secondary row decoding module 200, which can realize two-stage decoding. The cascaded primary row decoding module 100 and secondary row decoding module 200 can increase the number of decoding bits, increase the decoding capacity, improve the decoding rate, reduce the delay and power consumption, and occupy a smaller area under the same decoding capacity.

[0102] In some embodiments, Figure 6 A schematic structural block diagram of another decoding circuit provided by the embodiments of the present application is shown in FIG. 2.Figure 6 As shown, the decoding circuit can further include a splicing module 300, the splicing module 300 including a splicing connection line; the first-level row decoding module 100 and the second-level row decoding module 200 can be electrically connected through the splicing connection line in the splicing module 300. Different decoders in the first-level row decoding module 100 can correspondingly use different splicing modules to adapt to the line connection.

[0103] In some embodiments, with continued reference to Figure 6 The decoding circuit provided by the embodiments of the present application can further include a column decoding module 400, a column input end of the column decoding module 400 being electrically connected with an address signal; and a column gate module 500, the column gate module 500 being electrically connected with a column output end of the column decoding module 400.

[0104] For example, the position of the column gate module 500 can also be other functional modules, such as Figure 6 As shown, the arrow in the figure shows the data flow direction, that is, the decoded row address data is input to the first-level row decoding module 100, the data decoded by the first-level row decoding module 100 is input to the second-level row decoding module 200, the data processed by the second-level row decoding module 200 is transmitted to the storage unit array 2000, and the row address decoding is completed; the decoded column address data is input to the column decoding module. For example, when M = 4, a 1-line-2-line decoder can be used as a high-bit column decoder, and a 1-line-2-line decoder can be used as a low-bit column decoder; when M = 8, a 2-line-4-line decoder can be used as a high-bit column decoder, and a 1-line-2-line decoder can be used as a low-bit column decoder; when M = 16, a 3-line-8-line decoder can be used as a high-bit column decoder, and a 1-line-2-line decoder can be used as a low-bit column decoder.

[0105] In a sixth aspect, the present application provides a memory circuit, with reference to Figure 5 As shown, the memory circuit provided by the embodiments of the present application includes the decoding circuit as described in the first aspect; and a storage unit array 2000, the storage unit array 2000 being electrically connected with the second-level row decoding module 200 of the decoding circuit.

[0106] The memory circuit provided by the embodiments of the present application can realize two-stage decoding by setting a first-stage row decoding module and a second-stage row decoding module in the decoding circuit. The cascaded first-stage row decoding module and second-stage row decoding module can increase the number of decoding bits, increase the decoding capacity, improve the decoding rate, reduce the delay and power consumption, and occupy a smaller area in the case of the same decoding capacity. After the number and types of binary decoders required by the first-stage row decoding module and the number of decoders required by the second-stage row decoding module are determined, the corresponding number and types of binary decoder structure packages can be directly called to improve the generation efficiency of the decoding circuit. Different capacity decoding circuits can also be generated according to the demand of the target word line number, which can adapt to the expansion of the decoding circuit of the corresponding memory. The called decoder structure package can be connected, specifically, the decoder structure package corresponding to the first-stage row decoding module and the decoder structure package corresponding to the second-stage row decoding module can be connected to generate a decoding structure circuit. The automatic generation of the decoding circuit can be realized. For example, the target word line number is input, and the decoding circuit can be automatically obtained, which simplifies the technicality of the decoding circuit design.

[0107] It should be noted that in the above embodiments, the description of each embodiment has its own emphasis, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments.

[0108] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system, or a computer program product. Therefore, the present application can adopt a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer-readable storage media (including but not limited to disk memory, CD-ROM, optical memory, etc.) containing computer-readable program code.

[0109] The present application is described with reference to flowcharts and / or block diagrams according to the methods, devices (systems), and computer program products of the embodiments of the present application. It should be understood that each flow and / or block in the flowcharts and / or block diagrams, and the combination of the flows and / or blocks in the flowcharts and / or block diagrams can be realized by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded computer, or other programmable data processing devices to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing devices produce a machine that implements the functions specified in the flowcharts and / or block diagrams. Figure 1 The functions specified in one flow or multiple flows and / or blocks Figure 1 The device that realizes the functions specified in one block or multiple blocks.

[0110] These computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture including instructions which implement the flow Figure 1 one or more flow or block Figure 1 one or more flow or block

[0111] These computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions executed on the computer or other programmable apparatus provide steps for implementing the flow Figure 1 one or more flow or block Figure 1 one or more flow or block

[0112] The embodiments of the present application also provide a computer program product, which comprises computer software instructions, when the computer software instructions are executed on a processing device, the processing device executes the flow of the method for generating a decoding circuit.

[0113] The computer program product comprises one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the flow or function according to the embodiments of the present application is produced. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another, for example, the computer instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center through wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) mode. The computer readable storage medium can be any available medium that the computer can store or the data storage device such as server, data center, etc. integrated with one or more available media. The available media can be magnetic media (for example, floppy disk, hard disk, magnetic tape), optical media (for example, DVD), or semiconductor media (for example, solid state disk (SSD)) and the like.

[0114] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the above described system, device and unit can refer to the corresponding process in the foregoing method embodiments, which will not be described here.

[0115] In several embodiments provided in the present application, it should be understood that the disclosed devices, apparatuses and methods can be implemented in other manners. For example, the embodiments of the apparatus described above are merely schematic. For example, the division of the units is only a logical function division. There can be another division manner for the actual implementation. For example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections between the units can be indirect couplings or communication connections through some interfaces, devices or units, and can be electrical, mechanical or in other forms.

[0116] The units described as separated components can or can not be physically separated, and the components displayed as units can or can not be physical units, i.e., can be located in one place, or can be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purposes of the embodiments of the present application.

[0117] In addition, each functional unit in the embodiments of the present application can be integrated in a processing unit, or each unit can exist physically as a separate unit, or two or more units can be integrated in one unit. The integrated unit can be implemented in the form of hardware, or in the form of a software functional unit.

[0118] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on such an understanding, the technical solutions of the present application essentially or substantially, or all or part of the technical solutions, can be embodied in the form of a software product. The computer software product is stored in a storage medium, and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods in the embodiments of the present application. The foregoing storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), magnetic disk or optical disk, and various media that can store program codes.

[0119] The above, the above embodiments are only used to illustrate the technical solutions of the present application, rather than limit them; although the present application is described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

[0120] While the preferred embodiments of the application have been described, additional variations and modifications can be made to the preferred embodiments by those skilled in the art once they learn of the basic inventive concepts. Therefore, the appended claims are intended to encompass within their scope all such variations and modifications as are included within the scope of the present description.

[0121] Obviously, numerous modifications and variations of the present application are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims and their equivalents, the application can be practiced otherwise than as specifically described.

Claims

1. A method of generating a decoding circuit, characterized by, Comprising: In the circuit layout design environment, a splicing module is constructed; In the circuit layout design environment, according to the target storage capacity of the target memory, the number and corresponding binary decoder types of binary decoders required by the first row decoding module are determined, and the number of logic decoders required by the second row decoding module is determined; According to the number and corresponding binary decoder types of binary decoders required by the first row decoding module, and the number of logic decoders required by the second row decoding module, a decoder structure package is called; The called decoder structure package is connected; The called decoder structure package includes: According to the number and corresponding binary decoder types of binary decoders required by the first row decoding module, and the number of logic decoders required by the second row decoding module, the splicing module is called; The corresponding decoder structure package of the called first row decoding module and the corresponding decoder structure package of the second row decoding module are connected through the splicing module.

2. The method of claim 1, wherein Before the step of determining, in the circuit layout design environment, according to the target storage capacity of the target memory, the number and corresponding binary decoder types of binary decoders required by the first row decoding module, and the number of logic decoders required by the second row decoding module, the method further includes: In the circuit layout design environment, the decoder structure package is constructed, wherein the decoder structure package includes a first decoder structure package and a second decoder structure package, the first decoder structure package has corresponding circuit structures of the binary decoders, and the second decoder structure package has corresponding circuit structures of the logic decoders; The step of determining, in the circuit layout design environment, according to the target storage capacity of the target memory, the number and corresponding binary decoder types of binary decoders required by the first row decoding module, and the number of logic decoders required by the second row decoding module, includes: In the circuit layout design environment, according to the target storage capacity of the target memory, the number of the first decoder structure packages required by the first row decoding module and corresponding circuit structures of the binary decoders, and the number of the second decoder structure packages required by the second row decoding module are determined.

3. The method of claim 1, wherein The step of determining, in the circuit layout design environment, according to the target storage capacity of the target memory, the number and corresponding binary decoder types of binary decoders required by the first row decoding module, and the number of logic decoders required by the second row decoding module, includes: According to the number of storage units of the target memory and the number of multiplexers, the target storage capacity of the target memory is determined; According to the target storage capacity, the number and corresponding binary decoder types of binary decoders required by the first row decoding module, and the number of logic decoders required by the second row decoding module are determined.

4. The method of claim 3, wherein The target storage capacity includes a target word line number, and the target storage capacity of the target memory is determined according to the number of storage units of the target memory and the number of paths of a multiplexer, and the method comprises the following steps: The target word line number of the target memory is calculated according to the number of storage units of the target memory and the number of paths of a multiplexer, and the calculation formula is as follows: WL = W / M, Wherein, WL is the target word line number, W is the number of storage units of the target memory, and M is the number of paths of a multiplexer of the target memory.

5. The method of claim 4, wherein The number of binary decoders required by the primary row decoding module and the corresponding binary decoder types are determined according to the target storage capacity, and the number of logical decoders required by the secondary row decoding module is determined, which comprises the following steps: When WL = 32, it is determined that the number of binary decoders required by the primary row decoding module is two, the corresponding binary decoder types are 3-line-8-line decoder and 2-line-4-line decoder respectively, and the number of logical decoders required by the secondary row decoding module is 32; When 33 ≤ WL ≤ 64, it is determined that the number of binary decoders required by the primary row decoding module is two, the corresponding binary decoder types are both 3-line-8-line decoder, and the number of logical decoders required by the secondary row decoding module is the same as the value of the target word line number; When 65 ≤ WL ≤ 128, it is determined that the number of binary decoders required by the primary row decoding module is three, the corresponding binary decoder types are one 1-line-2-line decoder and two 3-line-8-line decoders respectively, and the number of logical decoders required by the secondary row decoding module is the same as the value of the target word line number; When 129 ≤ WL ≤ 256, it is determined that the number of binary decoders required by the primary row decoding module is three, the corresponding binary decoder types are one 2-line-4-line decoder and two 3-line-8-line decoders respectively, and the number of logical decoders required by the secondary row decoding module is the same as the value of the target word line number; When 257 ≤ WL ≤ 512, it is determined that the number of binary decoders required by the primary row decoding module is three, the corresponding binary decoder types are all 3-line-8-line decoders, and the number of logical decoders required by the secondary row decoding module is the same as the value of the target word line number.

6. An apparatus for generating a decoding circuit, characterized by The method comprises the following steps: A decoder determination module is used to determine the number of binary decoders required by a primary row decoding module and the corresponding binary decoder types according to the target storage capacity of a target memory, and to determine the number of logical decoders required by a secondary row decoding module in a circuit layout design environment; A structure package calling module is used to call a decoder structure package according to the number of binary decoders required by the primary row decoding module and the corresponding binary decoder types, and the number of logical decoders required by the secondary row decoding module. A connection module is used to connect the called decoder structure package; A splicing module is constructed in a circuit layout design environment; The connection module is used to connect the called decoder structure package; According to the number of binary decoders required by the primary row decoding module and the corresponding binary decoder types, and the number of logic decoders required by the secondary row decoding module, the splicing module is called; The decoder structure package corresponding to the primary row decoding module and the decoder structure package corresponding to the secondary row decoding module are connected through the splicing module.

7. An electronic device, comprising: It comprises: A memory in which a computer program is stored; A processor for executing the computer program to implement the generation method of the decoding circuit according to any one of claims 1-5.

8. A computer-readable storage medium, characterized in that, The computer program is stored on the computer readable storage medium, and the computer program is executed by the processor to implement the generation method of the decoding circuit according to any one of claims 1-5.

9. A decoding circuit, characterized by comprising: The decoding circuit is generated by the generation method of the decoding circuit according to any one of claims 1-5, and the decoding circuit comprises: A primary row decoding module comprising at least one binary decoder; A secondary row decoding module comprising at least one logic decoder, one end of the secondary row decoding module being electrically connected to the primary row decoding module, and the other end being used to electrically connect a memory.

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