Mram read circuit and its reading method, memory

Abstract

The application provides a MRAM reading circuit and a reading method thereof and a memory. The MRAM reading circuit comprises a first data path for storing first data; a first reference path connected with the first data path and having a first reading point as a connection point, wherein the first reference path and the first data path have consistent opening states; a second data path for storing second data, wherein the second data path has an opening state opposite to that of the first data path during a reading operation; a second reference path connected with the second data path and having a second reading point as a connection point, wherein the second reference path and the second data path have consistent opening states; and a comparison module connected with the first reading point and the second reading point and used for reading data of the first data path or the second data path. The MRAM reading circuit and the reading method thereof can improve the reading performance of the MRAM.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of storage, and in particular to an MRAM reading circuit, an MRAM reading method and a memory. BACKGROUND

[0002] Magnetic Random Access Memory (MRAM) has high read-write speed, high density, low power consumption, long data retention time and high life, and thus has an immeasurable broad prospect. Since MRAM has resistance variability, it can store data information through different resistance states.

[0003] In the prior art, there are still some defects in storing data. For example, due to process limitations, the Tunnel Magneto Resistance (TMR) ratio of the high resistance state and the low resistance state of the cell is low, resulting in a relatively small window for the readout circuit to distinguish between the two states. Furthermore, when the MRAM state is obtained by comparing the sizes of the read current and the reference current of the MRAM, due to the small TMR, the current difference for writing "0" and "1" is small.

[0004] Therefore, how to improve the reading performance of MRAM has become a problem to be solved at present. SUMMARY

[0005] The technical problem solved by the present application is how to improve the reading performance of MRAM.

[0006] To solve the above technical problem, the technical scheme of the present application provides an MRAM reading circuit, comprising: a first data path for storing first data; a first reference path connected with the first data path and a connection point being a first reading point, the first reference path and the first data path being consistent in the opening state; a second data path for storing second data, the second data path being opposite to the opening state of the first data path in the read operation; a second reference path connected with the second data path and a connection point being a second reading point, the second reference path and the second data path being consistent in the opening state; and a comparison module connected with the first reading point and the second reading point, for reading the data of the first data path or the second data path.

[0007] In the embodiment of the present application, the first data path comprises: a first memory cell array for storing first data; and a first data selector connected with the first memory cell array and the first reference path, for selecting the data to be read in the first memory cell array.

[0008] In the embodiment of the present application, the second data path comprises: a second memory cell array, configured to store second data; and a second data selector, connected to the second memory cell array and the second reference path, configured to select data to be read in the second memory cell array.

[0009] In the embodiment of the present application, the current flow directions of the first memory cell array and the second memory cell array are opposite in the write operation.

[0010] In the embodiment of the present application, a data signal is output at a path where a reading point in a data path in an open state is located, a reference signal is output at a path where a reading point in a data path in a non-open state is located, the reading point is a connection point of the corresponding data path and reference path, and the comparison module obtains a reading result by comparing the data signal and the reference signal.

[0011] In the embodiment of the present application, the data signal is a data voltage, and the reference signal is a reference voltage.

[0012] In the embodiment of the present application, in the reading operation, the paths where the first reading point and the second reading point are located are pre-charged to a specific level, and the reference voltage is equal in size to the specific level.

[0013] In the embodiment of the present application, the comparison module comprises a sensitive amplifier, a positive electrode of the sensitive amplifier is connected to the first reading point, and a negative electrode of the sensitive amplifier is connected to the second reading point.

[0014] The technical scheme of the present application further provides a memory comprising the MRAM reading circuit.

[0015] The technical scheme of the present application further provides a reading method of the MRAM reading circuit, comprising: opening a data path to be read and a corresponding reference path, closing a data path not to be read and a corresponding reference path, and selecting data to be read; pre-charging paths where a first reading point and a second reading point are located to a specific level, wherein the first reading point is a connection point of the data path to be read and the corresponding reference path, and the second reading point is a connection point of the data path not to be read and the corresponding reference path; keeping a voltage of the path where the second reading point is located at the specific voltage as a reference voltage, obtaining a data voltage when a voltage of the path where the first reading point is located reaches a stable value; and comparing sizes of the data voltage and the reference voltage to obtain a reading result.

[0016] In the embodiment of the present application, the data path to be read is a first data path or a second data path, wherein the first data path is used to store first data, and the first data path corresponds to a first reference path; the second data path is used to store second data, and the second data path corresponds to a second reference path.

[0017] In the embodiment of the present application, the first data path comprises: a first memory cell array used to store data; and a data selector connected to the first memory cell array and the first reference path, used to select the data to be read in the first memory cell array.

[0018] In the embodiment of the present application, the second data path comprises: a second memory cell array used to store data; and a data selector connected to the second memory cell array and the second reference path, used to select the data to be read in the second memory cell array.

[0019] In the embodiment of the present application, the current flow directions of the first memory cell array and the second memory cell array are opposite in the write operation.

[0020] In the embodiment of the present application, the path where the second read point is located is floating, and the voltage of the path where the second read point is located is maintained at the specific voltage through the parasitic capacitance.

[0021] In the embodiment of the present application, the data voltage is greater than the reference voltage, and the read result is 1; the data voltage is less than the reference voltage, and the read result is 0.

[0022] The MRAM read circuit of the technical scheme of the present application sets two data paths, and the two data paths are connected to the comparison module respectively, so that a first selector on the detection path is omitted. According to the comparison result of the embodiment, after the first selector is omitted, the current difference between the high resistance and the low resistance is increased by 13.6%, so that the high resistance and the low resistance are more easily distinguished, and the read performance of the MRAM is significantly improved. Further, the write modes of the two data paths are opposite, so that the comparison module can read the correct result.

[0023] The read method of the MRAM read circuit of the technical scheme of the present application opens the data path to be read and the corresponding reference path, and closes the data path not to be read and the corresponding reference path, so as to replace the use of the selector to select the data path to be read, so that the high resistance and the low resistance of the memory cell are more easily distinguished, and the read performance is further improved. BRIEF DESCRIPTION OF DRAWINGS

[0024] The following drawings detail the exemplary embodiments disclosed in this application. Identical reference numerals in the several views of the drawings represent similar structures. Those skilled in the art will appreciate that the embodiments are non-limiting, exemplary embodiments, and the drawings are for illustrative and descriptive purposes only and are not intended to limit the scope of the application, as other embodiments can equally well accomplish the inventive intent of this application. It is to be understood that the drawings are not drawn to scale. Among other things:

[0025] Figure 1 Structure diagram of MRAM read circuit of an embodiment of the application;

[0026] Figure 2 Structure diagram of MRAM read circuit of a specific example of the application;

[0027] Figure 3 Structure diagram of a read mode of MRAM read circuit of an embodiment of the application;

[0028] Figure 4 Structure diagram of another read mode of MRAM read circuit of an embodiment of the application;

[0029] Figure 5 Equivalent detection path when there is a first-stage data comparator for MRAM read circuit of an embodiment of the application;

[0030] Figure 6 Equivalent detection path when there is no first-stage data comparator for MRAM read circuit of an embodiment of the application. DETAILED DESCRIPTION

[0031] The following description provides specific applications and requirements of the application, in order to enable those skilled in the art to manufacture and use the content of the application. Various partial modifications of the disclosed embodiments are apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of the application. Therefore, the application is not limited to the embodiments shown, but is consistent with the widest scope of the claims.

[0032] Two inputs of a conventional sense amplifier, one connected to a reference level V ref , and the other connected to a reference current I ref , are compared with the comparison point V data of the current I cell of the bitcell to be measured, and the comparison result is output as V ref and V data, to get the state of the bitcell. Usually a set of sense amplifiers will correspond to the upper and lower database (TOP BANK and BOT BANK), first select one of the TOP BANK and BOT BANK through the selector (MUX), and then select the bitcell to be tested through the selector (YMUX).

[0033] Because the difference between the low resistance R P and the high resistance R AP of the MTJ is usually very small, and the additional MUX and YMUX in the detection path will cause voltage drop, further compressing the distinction between high resistance and low resistance, resulting in limited read performance. The current solution is to increase the size of MUX and YMUX in the detection path to reduce their equivalent resistance, but this will consume a lot of area and increase the parasitic capacitance, affecting the read speed.

[0034] In view of this, the technical scheme of the present application takes a different approach, by setting up two data paths, and connecting the two data paths to the two ends of the comparison module respectively, while also making the writing methods of the two data paths opposite, so that the comparison module can read the correct result. This way can save a level selector on the detection path, making it easier to distinguish between high resistance and low resistance of the storage unit, and thus improving the read performance.

[0035] The technical scheme of the present application will be described in detail below in conjunction with the embodiments and the accompanying drawings.

[0036] Referring to Figure 1 , the embodiment of the present application provides an MRAM read circuit, comprising: a first data path 11, a first reference path 21, a second data path 12, a second reference path 22, and a comparison module 3.

[0037] The first data path 11 is used to store the first data, and the second data path 12 is used to store the second data. The first data and the second data can be the same or different binary data. The open state of the first data path 11 and the second data path 12 is opposite, that is, during the read operation, only one path is read at a time, and the read data path is open and the non-read data path is closed. The non-read data path provides the same read conditions for the read data path. For example, when reading the first data path 11, the first data path 11 is open and the second data path 12 is closed; when reading the second data path 12, the second data path 12 is open and the first data path 11 is closed.

[0038] During the read process, if the first data path 11 is in an open state and the second data path 12 is in a closed state, a first read current I cell1; if the first data path 11 is in the closed state and the second data path 12 is in the open state, the second data path 12 generates a second read current I cell2 .

[0039] The first reference path 21 is connected with the first data path 11, and the connection point is the first read point. The second reference path 22 is connected with the second data path 12, and the connection point is the second read point. In the read operation, the first reference path 21 and the first data path 11 are in the same open state, and the second reference path 22 and the second data path 12 are in the same open state. In the read process, if the first reference path 21 is open and the second reference path 22 is closed, the first reference path 21 generates a first reference current I ref1 , and if the first reference path 21 is closed and the second reference path 22 is open, the second reference path 22 generates a second reference current I ref2 .

[0040] When reading the first data path 11, the first data path 11 and the first reference path 21 are open, and the second data path 12 and the second reference path 22 are closed. The first read current I cell1 generated by the first data path 11 competes with the first reference current I ref1 generated by the first reference path 21, and a stable voltage V data1 is obtained at the path where the first read point is located. The path where the first read point is located in the embodiment of the application refers to the path connected with the first read point and the comparison module 3. Similarly, when reading the second data path 12, the second data path 12 and the second reference path 22 are open, and the first data path 11 and the first reference path 21 are closed. The second read current I cell2 generated by the second data path 12 competes with the second reference current I ref2 generated by the second reference path 22, and a stable voltage V data2 is obtained at the path where the second read point is located. The path where the second read point is located in the embodiment of the application refers to the path connected with the second read point and the comparison module 3. The stable voltage V data1 and the stable voltage V data2 are output to the comparison module 3 as the data signals of the corresponding data paths to be read, and the reference signals of the reference paths are described later.

[0041] The comparison module 3 is connected with the first reading point and the second reading point, and is configured to read data of the first data path 11 or the second data path 12. In some embodiments, the comparison module 3 can include a sensitive amplifier, a positive electrode of the sensitive amplifier is connected with the first reading point, and a negative electrode of the sensitive amplifier is connected with the second reading point, or a positive electrode of the sensitive amplifier is connected with the second reading point, and a negative electrode of the sensitive amplifier is connected with the first reading point.

[0042] With reference to Figure 2 The first data path 11 includes a first storage unit array 111 and a first data selector 112. The first storage unit array 111 is configured to store first data, and in some embodiments, the first storage unit array 111 includes a plurality of first data units configured to store data. The first data selector 112 is connected with the first storage unit array 111 and the first reference path 21, and is configured to select data to be read in the first storage unit array 111.

[0043] The second data path 12 has a structure substantially same as that of the first data path 11, and includes a second storage unit array 121 and a second data selector 122. The second storage unit array 121 can include a plurality of second data units configured to store data. The second data selector 122 is connected with the second storage unit array 121 and the second reference path 22, and is configured to select data to be read in the second storage unit array 121.

[0044] The first storage unit array 111 and the second storage unit array 121 can have a structure of a conventional storage unit, and the first data selector 112 and the second data selector 122 can be conventional data selectors MUX, which will not be described in detail herein.

[0045] The MRAM reading circuit of the embodiments of the present application directly connects the first data path 11 and the second data path 12 with the comparison module, omits a data selector of a first selection data path, and selects a data path to be read through a switch control structure in each data path, thereby avoiding a voltage drop caused by an unnecessary data selector and improving a differential voltage collected by the comparison module.

[0046] Since the first reading point and the second reading point are connected with a positive electrode and a negative electrode of the comparison module 3 respectively, results read by the first storage unit array 111 and the second storage unit array 121 in a same state (for example, both in a high resistance state or both in a low resistance state) are opposite. In order to ensure that results read by the two storage unit arrays are correct, different writing schemes need to be used.

[0047] The first storage unit array 111 and the second storage unit array 121 have opposite current flow directions during the write operation, so that the two storage unit arrays have correct read results. For example, when writing 0, the current of the first storage unit array 111 flows from the bit line to the source line, and the current of the second storage unit array 121 flows from the source line to the bit line; when writing 1, the current of the first storage unit array 111 flows from the source line to the bit line, and the current of the second storage unit array 121 flows from the bit line to the source line; or, when writing 0, the current of the first storage unit array 111 flows from the source line to the bit line, and the current of the second storage unit array 121 flows from the bit line to the source line; when writing 1, the current of the first storage unit array 111 flows from the bit line to the source line, and the current of the second storage unit array 121 flows from the source line to the bit line.

[0048] The first reference path 21 generates the first reference current I ref1 The second reference path 22 generates the second reference current I ref2 The voltages provided by the first voltage VDD1 and the second voltage VDD2 are determined according to actual conditions.

[0049] When reading data, a data signal is output at the path where the read point of the data path in the open state is located, and a reference signal is output at the path where the read point of the data path in the unopened state is located, wherein the read point is the connection point of the corresponding data path and reference path, the path where the read point of the data path in the open state is located refers to the path connected to the comparison module 3 through the read point of the data path in the open state, and the path where the read point of the unopened data path is located refers to the path connected to the comparison module 3 through the read point of the unopened data path. The comparison module 3 obtains the read result by comparing the data signal and the reference signal. In the embodiment of the application, the data signal is a data voltage, and the reference signal is a reference voltage.

[0050] Reference Figure 3 When reading data of the first data path 11, the first data path 11 and the first reference path 21 are opened, and the second data path 12 and the second reference path 22 are closed (the “X” in the figure represents the closed state), the first data selector 112 selects the data in the first storage unit array 111 as the data to be read, and the first data path 11 generates a first data current I cell1 The first reference path 21 generates a first reference current I ref1 During the read operation, the paths where the first read point and the second read point are located are pre-charged to a specific voltage V Band the voltage of the path where the second reading point is located is kept at a certain voltage V B as reference voltage by the parasitic capacitor C2. The first data current I cell1 competes with the first reference current I ref1 , and the voltage of the path where the first reading point is located reaches a stable value, and the data voltage V data1 is obtained. The comparison module 3 obtains the reading result by comparing the reference voltage V B and the data voltage V data1 . When the bitcell to be measured is high resistance (i.e. writing "1"), I ref1 >I cell1 , so that V data1 >V B , and 1 is read out; when the bitcell to be measured is low resistance (i.e. writing "0"), I ref1 <I cell1 , so that V data1 <V B , and 0 is read out, and the data is normally read out.

[0051] Referring to Figure 4 , when reading the data of the second data path 12, the second data path 12 and the second reference path 22 are opened, and the first data path 11 and the first reference path 12 are closed (the "X" in the figure represents the closed state), the second data selector 122 selects the data in the second memory cell array 121 as the data to be read, and the second data path 12 generates a second data current I cell2 , and the second reference path 22 generates a second reference current I ref2 . In the reading operation, the paths where the first reading point and the second reading point are located are pre-charged to a certain voltage V B , then the path where the first reading point is located is grounded, and the voltage of the path where the first reading point is located is kept at a certain voltage V B as reference voltage by the parasitic capacitor C1. The second data current I cell2 competes with the second reference current I ref2 , and the voltage of the path where the second reading point is located reaches a stable value, and the data voltage V data2 is obtained. The comparison module 3 obtains the reading result by comparing the reference voltage V B and the data voltage V data2 . When the bitcell to be measured is high resistance (i.e. writing "0"), I ref2 >I cell2 , so that V data2 >V B, read 0; the bitcell under test is low resistance (i.e. write "1"), I ref2 <I cell2 , so that V data2 <I B , read 1, data is read normally.

[0052] In the above embodiment, when the first memory cell array 111 writes 0, the current flows from the bit line to the source line, and the current of the second memory cell array 121 flows from the source line to the bit line; when writing 1, the current of the first memory cell array 111 flows from the source line to the bit line, and the current of the second memory cell array 121 flows from the bit line to the source line. In other embodiments, it can also be designed by oneself.

[0053] The equivalent detection paths with and without a first-level data comparator (MUX) are compared as follows. Figure 5 For the equivalent detection path with a first-level data comparator (MUX), Figure 6 For the equivalent detection path without a first-level data comparator (MUX).

[0054] Assuming the equivalent resistance R MUX of the MUX is 200 ohm, the equivalent resistance R YMUX of the YMUX is 200 ohm, the equivalent resistance R mos of the MOS tube in the bitcell is 400 ohm, the high resistance R AP of the MTJ is 3600 ohm, and the low resistance R P of the MTJ is 1500 ohm (assuming TMR = 140%). In the precharge phase, V data node is charged to V B level.

[0055] For the equivalent detection path with a first-level data comparator (MUX), the current (Icell ap ) of the high resistance and the current (Icell p ) of the low resistance are respectively:

[0056] Icell ap = V B / (R MUX + 2 x R YMUX + R mos + R AP );

[0057] Icell p = V B / (R MUX + 2 x R YMUX + R mos + R P ).

[0058] Icell ap and Icell p The current difference formula of Icell

[0059]

[0060] The known values are brought into the above current difference formula, and the calculation result is 1.826 x 10 -4 V B .

[0061] For the equivalent detection path without the first-stage data comparator (MUX), the high-resistance current (Icell ap ) and the low-resistance current (Icell p ) are respectively:

[0062] Icell ap = V B / (2 x R YMUX + R mos + R AP );

[0063] Icell p = V B / (2 x R YMUX + R mos + R P ).

[0064] The current difference formula of Icell ap and Icell p is as follows:

[0065]

[0066] The known values are brought into the above current difference formula, and the calculation result is 2.075 x 10 -4 V B .

[0067] According to the calculation result of the current difference value, it can be seen that after the first-stage selector (MUX) on the detection path is omitted, the current difference between the high resistance and the low resistance is increased by 13.6%. The greater current difference means better reading performance, and therefore the MRAM reading circuit of the embodiment has excellent reading performance.

[0068] The embodiment also provides a memory comprising the above MRAM reading circuit, and since the MRAM reading circuit has high reading performance, the memory also has excellent reading performance.

[0069] The embodiment also provides a reading method of the MRAM reading circuit, comprising:

[0070] opening the to-be-read data path and the corresponding reference path, closing the non-to-be-read data path and the corresponding reference path, and selecting data to be read;

[0071] pre-charging the paths at the first read point and the second read point to a specific voltage, wherein the first read point is a connection point of the to-be-read data path and the corresponding reference path, and the second read point is a connection point of the non-to-be-read data path and the corresponding reference path;

[0072] keeping the voltage of the path at the second read point at the specific voltage as a reference voltage, and obtaining a data voltage when the voltage of the path at the first read point reaches a stable value;

[0073] comparing the data voltage and the reference voltage to obtain a read result.

[0074] In some embodiments, the to-be-read data path is a first data path or a second data path, wherein the first data path is used to store first data, and the first data path corresponds to a first reference path; and the second data path is used to store second data, and the second data path corresponds to a second reference path.

[0075] The first data path includes a first storage unit array used to store data, and a data selector connected to the first storage unit array and the first reference path, and used to select to-be-read data of the first storage unit array. The second data path includes a second storage unit array used to store data, and a data selector connected to the second storage unit array and the second reference path, and used to select to-be-read data of the second storage unit array.

[0076] In the embodiments of the present application, the current flow directions of the first storage unit array and the second storage unit array are opposite during a write operation. For example, when writing 0, the current of the first storage unit array 111 flows from a bit line to a source line, and the current of the second storage unit array 121 flows from the source line to the bit line; when writing 1, the current of the first storage unit array 111 flows from the source line to the bit line, and the current of the second storage unit array 121 flows from the bit line to the source line; or, when writing 0, the current of the first storage unit array 111 flows from the source line to the bit line, and the current of the second storage unit array 121 flows from the bit line to the source line; when writing 1, the current of the first storage unit array 111 flows from the bit line to the source line, and the current of the second storage unit array 121 flows from the source line to the bit line.

[0077] In the embodiments of the present application, the voltage of the path at the second read point is kept at the specific voltage by means of parasitic capacitance when the path at the second read point is floating.

[0078] In the embodiment of the present application, a sensitive amplifier can be used to compare the sizes of the data voltage and the reference voltage, and when the data voltage is greater than the reference voltage, the read result is 1; and when the data voltage is less than the reference voltage, the read result is 0.

[0079] The read method of the MRAM read circuit in the embodiment of the present application selects the data path to be read by opening or closing the data path and the corresponding reference path, thereby omitting the first selector, and can significantly improve the read performance of the MRAM read circuit.

[0080] In summary, after reading the content of the present application, those skilled in the art can understand that the foregoing content of the application can be presented only in an exemplary manner and can not be limiting. Although not explicitly stated herein, those skilled in the art can understand that the present application is intended to encompass various reasonable changes, improvements and modifications to the embodiments. These changes, improvements and modifications are within the spirit and scope of the exemplary embodiments of the present application.

[0081] It should be understood that the term "and / or" used in the embodiments of the present application includes any or all combinations of one or more associated listed items. It should be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there can be an intermediate element.

[0082] Similarly, it should be understood that when an element such as a layer, a region or a substrate is referred to as being "on" another element, it can be directly on the other element, or there can be an intermediate element. In contrast, the term "directly" means that there is no intermediate element. It should also be understood that the terms "comprise", "comprising", "include", or "including" as used in the present application refer to the presence of the recited features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or combinations thereof.

[0083] It should also be understood that although the terms first, second, third and the like can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, the first element in some embodiments can be referred to as the second element in other embodiments without departing from the teachings of the present application. The same reference numbers or the same reference signs represent the same elements throughout the specification.

[0084] Furthermore, the description herein describes example embodiments by reference to idealized illustrative cross-sectional and / or plan and / or perspective views. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, the example embodiments should not be construed as limited to the precise shapes illustrated herein but are to include deviations in shapes that result from such tollerances and / or manufacturing techniques. For example, an etched region illustrated as a rectangle will, typically, have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the example embodiments.

Claims

1. An MRAM read circuit, comprising: include: The first data path is used to store the first data; A first reference path is connected to the first data path, and the connection point is the first read point. The first reference path and the first data path are in the same open state. The second data path is used to store the second data, and the second data path is in the opposite open state to the first data path during a read operation. The second reference path is connected to the second data path and the connection point is the second read point. The second reference path and the second data path are in the same open state. The comparison module has its input connected to the first reading point and the second reading point. It is used to read data from the first data path or the second data path. It outputs a data signal in the path where the reading point of the data path is in the open state, and outputs a reference signal in the path where the reading point of the data path is in the closed state. The reading point is the connection point of the corresponding data path and the reference path. The comparison module obtains the reading result by comparing the data signal and the reference signal.

2. The MRAM read circuit of claim 1, wherein, The first data path includes: A first storage cell array is used to store the first data; A first data selector, connected to the first storage cell array and the first reference path, is used to select data to be read from the first storage cell array.

3. The MRAM read circuit of claim 2, wherein, The second data path includes: A second storage cell array is used to store the second data; The second data selector, connected to the second storage cell array and the second reference path, is used to select the data to be read from the second storage cell array.

4. The MRAM read circuit of claim 3, wherein, The current flows in opposite directions during write operations in the first and second memory cell arrays.

5. The MRAM read circuit of claim 1, wherein, The data signal is a data voltage, and the reference signal is a reference voltage.

6. The MRAM read circuit of claim 5, wherein, During the read operation, the paths containing the first read point and the second read point are pre-charged to a specific voltage, wherein the reference voltage is equal to the magnitude of the specific voltage.

7. The MRAM read circuit of claim 1, wherein, The comparison module includes a sensitive amplifier, the positive terminal of which is connected to the first reading point and the negative terminal of which is connected to the second reading point.

8. A memory, comprising: Includes the MRAM read circuit as described in any one of claims 1 to 7.

9. A read method of an MRAM read circuit, characterized by, The MRAM read circuit according to any one of claims 1 to 8 comprises: Open the data path to be read and the corresponding reference path, close the data path not to be read and the corresponding reference path, and select the data to be read; The paths containing the first read point and the second read point are pre-charged to a specific voltage, wherein the first read point is the connection point between the data path to be read and the corresponding reference path, and the second read point is the connection point between the data path not to be read and the corresponding reference path; The voltage of the path where the second reading point is located is maintained at the specific voltage as a reference voltage. Once the voltage of the path where the first reading point is located reaches a stable value, the data voltage is obtained. The reading result is obtained by comparing the data voltage with the reference voltage.

10. The read method of the MRAM read circuit according to claim 9, wherein, The data path to be read is either a first data path or a second data path, wherein... The first data path is used for storing first data, and a corresponding reference circuit of the first data path is a first reference path; The second data path is used for storing second data, and a corresponding reference circuit of the second data path is a second reference path.

11. The read method of the MRAM read circuit according to claim 10, wherein, The first data path comprises: a first memory cell array used for storing data; a data selector connected to the first memory cell array and the first reference path, and used for selecting data to be read from the first memory cell array.

12. The read method of the MRAM read circuit according to claim 11, wherein, The second data path comprises: a second memory cell array used for storing data; a data selector connected to the second memory cell array and the second reference path, and used for selecting data to be read from the second memory cell array.

13. The read method of the MRAM read circuit according to claim 12, wherein, Currents flowing directions of the first memory cell array and the second memory cell array are opposite in a write operation.

14. The read method of the MRAM read circuit of claim 9, wherein, The path where the second read point is located is floated, and a voltage of the path where the second read point is located is maintained at the specific voltage through a parasitic capacitor.

15. The read method of the MRAM read circuit of claim 9, wherein, The data voltage is greater than the reference voltage, and a read result is 1; the data voltage is less than the reference voltage, and the read result is 0.

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