Semiconductor device and method for manufacturing the same

Abstract

The present invention aims to provide a semiconductor device and a method for manufacturing the same that can easily improve gate breakdown voltage. The semiconductor device according to the present invention comprises: a first conductive type silicon substrate having a cell portion and an end portion surrounding the cell portion when viewed from above; a first conductive type emitter layer provided on the surface of the silicon substrate in the cell portion; a second conductive type collector layer provided on the back surface of the silicon substrate in the cell portion; a first conductive type drift layer provided between the emitter layer and the collector layer; a trench gate provided so as to extend from the surface of the emitter layer to the drift layer; and a second conductive type well layer provided on the surface of the silicon substrate in the end portion, wherein the number of vacancies contained in the crystal defects in the cell portion is smaller than the number of vacancies contained in the crystal defects in the end portion.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same. Background Art

[0002] Wafers used for power semiconductors such as IGBTs (Insulated Gate Bipolar Transistors) and diodes are mainly manufactured using the FZ (Floating Zone) method when the size is 6 inches or 8 inches. On the other hand, in order to reduce direct material costs and wafer processing costs, the diameter of wafers is constantly increasing. For example, 12-inch wafers are mainly manufactured using the MCZ (Magnetic field applied Czochralski) method. Compared with wafers manufactured using the FZ method, wafers manufactured using the MCZ method contain a higher oxygen concentration. The oxygen concentration is related to crystal defects such as COP (Crystal Originated Particle), and there is a problem that the gate withstand voltage is reduced due to crystal defects caused by oxygen. Therefore, in order to increase the gate withstand voltage, it is preferable to reduce the oxygen concentration contained in the wafer.

[0003] As a method for reducing the oxygen concentration contained in chips manufactured by the MCZ method, a technology has been disclosed in the past, in which a carrier chip is bonded to a device chip and oxygen is diffused from the device chip to the carrier chip during any beneficial heat treatment, thereby maintaining a low oxygen concentration in the device chip (for example, see Patent Document 1).

[0004] Patent Document 1: Japanese Patent Application Laid-Open No. 2016-111337

[0005] The technique of Patent Document 1 has the following problem: a carrier wafer is required in addition to the device wafer, which increases the number of steps and costs required to maintain a low oxygen concentration within the device wafer. Thus, the technique of Patent Document 1 does not easily improve the gate breakdown voltage. Summary of the Invention

[0006] The present invention has been made to solve such a problem, and an object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can easily increase a gate breakdown voltage.

[0007] In order to solve the above-mentioned problems, the semiconductor device according to the present invention comprises: a first conductive type silicon substrate, which has a unit portion and an end portion surrounding the unit portion when viewed from above; a first conductive type emitter layer, which is arranged on the surface of the silicon substrate of the unit portion; a second conductive type collector layer, which is arranged on the back side of the silicon substrate of the unit portion; a first conductive type drift layer, which is arranged between the emitter layer and the collector layer; a trench gate, which is arranged in a manner of reaching the drift layer from the surface of the emitter layer; and a second conductive type well layer, which is arranged on the surface of the silicon substrate of the end portion, wherein the vacancies contained in the crystal defects at the unit portion are fewer than the vacancies contained in the crystal defects at the end portion.

[0008] Effects of the Invention

[0009] According to the present invention, since the number of vacancies included in the crystal defects at the cell portion is smaller than that at the terminal portion, the gate breakdown voltage can be easily increased. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 This is a cross-sectional view showing the structure of the semiconductor device according to the first embodiment.

[0011] Figure 2 sectional views showing the manufacturing process of the semiconductor device according to the first embodiment.

[0012] Figure 3 sectional views showing the manufacturing process of the semiconductor device according to the first embodiment.

[0013] Figure 4 sectional views showing the manufacturing process of the semiconductor device according to the first embodiment.

[0014] Figure 5 sectional views showing the manufacturing process of the semiconductor device according to the first embodiment.

[0015] Figure 6 sectional views showing the manufacturing process of the semiconductor device according to the first embodiment.

[0016] Figure 7 sectional views showing the manufacturing process of the semiconductor device according to the first embodiment.

[0017] Figure 8 sectional views showing the manufacturing process of the semiconductor device according to the first embodiment.

[0018] Figure 9 sectional views showing the manufacturing process of the semiconductor device according to the first embodiment.

[0019] Figure 10 sectional views showing the manufacturing process of the semiconductor device according to the first embodiment.

[0020] Figure 11 sectional views showing the manufacturing process of the semiconductor device according to the first embodiment.

[0021] Figure 12 sectional views showing the manufacturing process of the semiconductor device according to the first embodiment.

[0022] Figure 13 This is a diagram for explaining how crystal defects are eliminated in the semiconductor device according to the first embodiment.

[0023] Figure 14 This is a graph showing the relationship between the depth from the surface and the oxygen concentration after the wafer process of the semiconductor device according to the second embodiment is completed.

[0024] Figure 15 This is a graph showing the relationship between the oxygen concentration and the gate breakdown voltage after the wafer process of the semiconductor device according to the second embodiment is completed.

[0025] Figure 16 This is a graph showing the relationship between the oxygen concentration before the start of the wafer process and after the completion of the wafer process for the semiconductor device according to the second embodiment. DETAILED DESCRIPTION

[0026] <Implementation Method 1>

[0027] <Structure>

[0028] Figure 1 This is a cross-sectional view showing the structure of a semiconductor device according to Embodiment 1. While the following description assumes that n-type is the first conductivity type and p-type is the second conductivity type, p-type may be the first conductivity type and n-type may be the second conductivity type. The semiconductor device described below is an IGBT.

[0029] The semiconductor device according to the first embodiment includes an n-type (first conductivity type) n-type silicon substrate 1 having a unit portion and an end portion surrounding the unit portion in a plan view. The n-type silicon substrate 1 includes an n-type drift layer. Figure 1 In FIG. 5 , a layer existing between the p-base layer 2 and the buffer layer 9 in the cell portion corresponds to a drift layer.

[0030] A p-type (second conductivity type) base layer 2 is provided on the surface side of the n-type silicon substrate 1 of the cell portion. In addition, an n-type n-type silicon substrate 2 is provided on the outermost surface of the n-type silicon substrate 1 of the cell portion. + Emitter layer 3 and p-type p + Layer 6.

[0031] In the unit department, from n +The surface of the emitter layer 3 is n + A trench gate 4 is provided so as to penetrate the emitter layer 3 and the p-base layer 2 and reach the drift layer. A gate oxide film 5 is provided on the inner wall of the trench gate 4. Polysilicon 13 is filled in the trench gate 4 through the gate oxide film 5. In addition, an interlayer insulating film 7 is provided so as to cover the surface of the trench gate 4 so as to isolate the n-type silicon from the p-type silicon. + Emitter layer 3, p + The surface electrode 8 is provided so as to cover the layer 6 and the interlayer insulating film 7 .

[0032] A p-type p-well layer 12 is provided on the surface of the n-type silicon substrate 1 at the end portion. Polysilicon 13 and an interlayer insulating film 7 are provided on the surface of the p-well layer 12. The interlayer insulating film 7 is selectively provided with an opening, and a surface electrode 8 is provided so as to fill the opening and partially expose the surface of the interlayer insulating film 7. The surface electrode 8 is also provided on the polysilicon 13.

[0033] A buffer layer 9 and a p-type p-collector layer 10 are provided on the back surface of the n-type silicon substrate 1 in the cell portion and the terminal portion. A back surface electrode 11 is provided on the p-collector layer 10 .

[0034] The surface layer at the cell portion of the n-type silicon substrate 1 has fewer vacancies than the surface layer at the end portion due to the removal of oxygen contained in the inner wall oxide film from crystal defects. Details of vacancies will be described later.

[0035] <Manufacturing method>

[0036] use Figures 1 to 12 A method for manufacturing the semiconductor device according to the first embodiment will be described.

[0037] First, if Figure 2 As shown, an n-type silicon substrate 1 having an n-type drift layer is prepared. The n-type silicon substrate 1 is produced by dicing a large-diameter wafer produced by the MCZ method. The n-type impurity concentration of the drift layer is determined by the withstand voltage of the semiconductor device.

[0038] Then, if Figure 3 As shown, in order to form a p-well layer 12 on the surface of the end portion of the n-type silicon substrate 1, a thick oxide film 14 is formed on the surface of the n-type silicon substrate 1. Specifically, the oxide film 14 is formed on the surface of the n-type silicon substrate 1 using photolithography. At this time, the oxide film 14 is continuously formed on the surface of the n-type silicon substrate 1 in the cell portion, while the oxide film 14 is selectively formed by etching the surface of the n-type silicon substrate 1 at the end portion. In other words, the oxide film 14 formed on the surface of the n-type silicon substrate 1 at the end portion is formed to have an opening. The surface of the n-type silicon substrate 1 is exposed at the bottom of this opening.

[0039] Then, if Figure 4 As shown, the underlying oxide film 15 is formed so as to cover the bottom of the opening of the oxide film 14 formed on the surface of the n-type silicon substrate 1 at the end portion.

[0040] Then, if Figure 5 As shown, p-type impurities such as boron (B) are ion-implanted into n-type silicon substrate 1 from the surface side of n-type silicon substrate 1. In the first embodiment, ion implantation is performed using thick oxide film 14 as a mask, but ion implantation may also be performed using a resist layer.

[0041] Then, if Figure 6 As shown in FIG. 1 , the p-well layer 12 is formed by performing a heat treatment in a nitrogen environment at a high temperature of 1000° C. or higher for 240 minutes or higher. Alternatively, the heat treatment may be performed while performing oxidation in an oxygen environment. Figure 13 , explaining the mechanism by which the gate breakdown voltage is improved by performing such high-temperature heat treatment.

[0042] Silicon wafers are produced by slicing a single crystal ingot pulled using the CZ (Czochralski) method (including the MCZ method). The crystal structure of single crystal silicon is a diamond structure consisting of a unit cell with 8 silicon atoms, with each silicon atom bonded to the surrounding 4 silicon atoms via 4 bonds.

[0043] However, in reality, if pulling is performed at high speed in order to improve productivity, a homogeneous single crystal cannot be formed, and various crystal defects such as line defects, dislocations, or atomic vacancies formed by agglomeration will occur. As for the silicon atoms present around the vacancies, which are one of the crystal defects, not all of the four bonds are used for bonding. Therefore, the silicon atoms present around the vacancies form a complex with the large amount of oxygen contained in the wafer manufactured by the CZ method to form an oxide film (inner wall oxide film). If there are many such complexes, a high-quality oxide film cannot be formed when silicon is oxidized, which will cause the withstand voltage of the oxide film to decrease. In particular, in the case of an oxide film such as a gate oxide film that plays an important role in the operation of the device, the withstand voltage of the oxide film will decrease, which will cause the reliability of the device to decrease. Therefore, in order to prevent the adverse effects on the device caused by the vacancies from becoming apparent, it is necessary to improve the quality of the wafer and to construct the wafer process.

[0044] In Embodiment 1, since the heat treatment is performed while the oxide film 14 is continuously formed on the surface of the n-type silicon substrate 1 in the cell section, fewer vacancies are created by oxygen removal in the cell section than in the terminal section. Furthermore, since the oxide film 14 is continuously formed on the surface of the n-type silicon substrate 1 in the cell section, interstitial silicon (also known as "interstitial Si") can be easily implanted into the vacancies created in the cell section, reducing crystal defects and improving the gate breakdown voltage. More preferably, the heat treatment is performed at a temperature of 1150°C or higher for 360 minutes or longer to further enhance the effect.

[0045] In addition, as far as heat treatment is concerned, the temperature when the wafer boat is inserted is about 500°C, and it gradually rises from this temperature to the desired processing temperature. However, by setting the heating and cooling rates at this time to less than or equal to 2°C / minute, dislocation defects, namely sliding dislocations, can be prevented from occurring in the wafer.

[0046] exist Figure 6 In the example, the underlying oxide film 15 is formed to cover the bottom of the opening of the oxide film 14 selectively formed at the end portion, but since the thickness of the underlying oxide film 15 is thin, oxygen is removed from the n-type silicon substrate 1 during heat treatment, resulting in more vacancies than in the unit portion.

[0047] Returning to the description of the method for manufacturing a semiconductor device, Figure 6 Afterwards Figure 7 As shown, p-type impurities such as boron are ion-implanted into n-type silicon substrate 1 from the surface side of the cell portion to form p-base layer 2. Then, heat treatment is performed to activate p-base layer 2.

[0048] Then, if Figure 8 As shown, n-type impurities such as phosphorus and arsenic are selectively ion-implanted from the surface side of the n-type silicon substrate 1 of the cell portion to form n-type silicon substrates. + Emitter layer 3.

[0049] Then, if Figure 9 As shown, in the unit part, from n + The surface of the emitter layer 3 is n + The emitter layer 3 and the p-base layer 2 are etched through to reach the drift layer, forming a trench. A gate oxide film 5 is then formed on the inner wall of the trench, and the trench is filled with polysilicon 13 through the gate oxide film 5, thereby forming a trench gate 4. The polysilicon 13 also serves as gate wiring.

[0050] In addition, the heat treatment for increasing the gate withstand voltage described above can also be performed after etching to form the trench. In this case, it is speculated that the heat treatment is performed at the timing described above (at Figure 6Compared with the case where heat treatment is performed in the process, the crystal defects near the gate oxide film 5 can be reduced.

[0051] Then, if Figure 10 As shown, p-type impurities such as boron are ion-implanted into the n-type silicon substrate 1 from the surface side of the cell portion to form a p-type silicon substrate. + Layer 6. Then, heat treatment is performed to make p + Layer 6 activated.

[0052] Then, if Figure 11 As shown in FIG. 1 , an interlayer insulating film 7 is formed in the cell portion and the terminal portion. Figure 12 As shown in FIG. 1 , surface electrodes 8 are formed on the cell portion and the terminal portion. Thereafter, a surface protection film (not shown) such as silicon nitride or polyimide is formed as needed.

[0053] Next, processing of the back surface side of the n-type silicon substrate 1 will be described.

[0054] First, the back side of the n-type silicon substrate 1 is polished until it reaches a thickness corresponding to the withstand voltage of the semiconductor device. Then, n-type impurities such as phosphorus or arsenic are ion-implanted from the back side of the n-type silicon substrate 1, and annealing is performed to form a buffer layer 9. Similarly, p-type impurities such as boron are ion-implanted and annealed to form a p-collector layer 10. Alternatively, these anneals can be performed simultaneously to activate both n-type and p-type impurities. As an annealing method, laser annealing or low-temperature furnace annealing is performed to avoid affecting the surface electrode 8.

[0055] After that, the back electrode 11 is formed. Figure 1 The semiconductor device according to the first embodiment is shown.

[0056] <Effect>

[0057] During the heat treatment at the highest temperature in the manufacturing process of the semiconductor device according to the first embodiment, the heat treatment is performed in a state where an oxide film is continuously formed on the cell portion and an oxide film is selectively formed on the terminal portion. By performing the heat treatment in a state where an oxide film is formed, Si is implanted into the vacancies after oxygen removal, thereby assisting in eliminating crystal defects caused by oxygen (see Figure 13 In addition, since the oxide film is continuously formed in the cell portion, the injection efficiency of Si into the vacancies can be improved, which can contribute to the improvement of the gate withstand voltage.

[0058] During the heat treatment, an oxide film is continuously formed on the cell portion, while an oxide film is selectively formed on the end portion. Therefore, the density of vacancies at the surface layer of the cell portion is lower than that at the end portion.

[0059] By performing a heat treatment at 1000°C or higher for 240 minutes or longer, more preferably at 1150°C or higher for 360 minutes or longer, crystal defects caused by oxygen can be reduced. Furthermore, by performing a heat treatment at 1000°C or higher for 240 minutes or longer, more preferably at 1150°C or higher for 360 minutes or longer, the oxygen concentration on the surface side of n-type silicon substrate 1 can be reduced.

[0060] As described above, according to the first embodiment, by improving the efficiency of Si injection into vacancies generated in the cell portion, the gate breakdown voltage can be easily improved compared to the related art.

[0061] <Implementation Method 2>

[0062] As described in Embodiment 1, in order to reduce crystal defects, the following three points are important: reducing the oxygen concentration contained in the wafer that forms crystal defects, performing high-temperature heat treatment to remove the inner wall oxide film combined with the crystal defects, and efficiently supplying interstitial silicon into the block.

[0063] In the manufacturing process of the semiconductor device, in order to maintain the withstand voltage, when forming a deep p-well layer 12 at the end portion, heat treatment is performed at a temperature of 1150° C. or higher for 360 minutes or higher. However, at this time, it is effective to leave the oxide film 14 formed in the unit portion thick to allow oxygen to diffuse.

[0064] Figure 14 This graph shows the relationship between depth from the surface and oxygen concentration after wafer processing is completed for a semiconductor device according to Embodiment 2. The depth on the horizontal axis represents the depth from the surface of n-type silicon substrate 1. "Low oxygen concentration" indicates that the initial wafer before wafer processing begins has a low oxygen concentration, "medium oxygen concentration" indicates that the initial wafer before wafer processing begins has a medium oxygen concentration, and "high oxygen concentration" indicates that the initial wafer before wafer processing begins has a high oxygen concentration. The structure and manufacturing method of the semiconductor device according to Embodiment 2 are the same as those of Embodiment 1.

[0065] like Figure 14 As shown in FIG, oxygen is released from the surface side by outward diffusion, so the oxygen concentration on the surface side decreases. The oxygen concentration becomes high at the outermost surface because an oxide film is formed on the surface.

[0066] Figure 15 This is a graph showing the relationship between the oxygen concentration and the gate breakdown voltage after the wafer process of the semiconductor device according to the second embodiment is completed. Since the trench is formed with a depth of about 3 to 8 μm in the IGBT, Figure 15Graph 2 shows the relationship between the oxygen concentration at a depth of 8 μm and the gate breakdown voltage.

[0067] Generally, in the case of an IGBT, the p collector layer 10 and the n + The withstand voltage between the emitter layer 3 is greater than or equal to 600V, and the thickness of the gate insulating film formed on the inner wall of the trench is As described above, according to the present invention, a high gate withstand voltage can be ensured by reducing the oxygen concentration, so the thickness of the gate oxide film 5 can be reduced to That is, the thickness of the gate oxide film 5 can be set to This can improve the current carrying capacity and reduce the conduction loss.

[0068] In addition, by setting the oxygen concentration to be less than or equal to 1.8E17 / cm 3 Specifically, when the depth of the trench gate 4 from the surface is set to D1, the oxygen concentration at a depth less than D1 from the surface in the cell portion is less than or equal to 1.8E17 / cm 3 .

[0069] As described in Embodiment 1, after the structure of the surface side of the n-type silicon substrate 1 is formed, the back side of the n-type silicon substrate 1 is ground to form a diffusion layer, etc. The oxygen is discharged by the surface heat treatment to a depth of about 50 μm from the surface of the n-type silicon substrate 1. In the case where the initial thickness of the wafer is 700 to 800 μm, if the withstand voltage of the IGBT is set to 600 to 6500 V, the final thickness of the wafer is 60 to 650 μm, and the wafer is ground down by more than or equal to 50 μm by grinding the back side. Therefore, the oxygen concentration on the collector side is the same as the initial oxygen concentration of the wafer. According to Figure 16 The correlation between the initial oxygen concentration of the wafer and the oxygen concentration after the wafer process is completed is shown. The oxygen concentration on the surface side is 1.8E17 / cm 3 In the case of the collector side, there is 4.0E17 / cm 3 of oxygen.

[0070] Furthermore, the various embodiments can be freely combined within the scope of the present invention, and the various embodiments can be appropriately modified or omitted.

[0071] Description of the label

[0072] 1n-type silicon substrate, 2p base layer, 3n + Emitter layer, 4 trench gate, 5 gate oxide film, 6p + layer, 7 interlayer insulating film, 8 surface electrode, 9 buffer layer, 10p collector layer, 11 back electrode, 12p well layer, 13 polysilicon, 14 oxide film, 15 bottom oxide film.

Claims

1. A semiconductor device comprising: a first conductive type silicon substrate having a unit portion and a terminal portion surrounding the unit portion in a plan view; an emitter layer of a first conductivity type provided on a surface of the silicon substrate of the cell portion; a collector layer of a second conductivity type provided on the back surface of the silicon substrate of the cell portion; a first conductive type drift layer disposed between the emitter layer and the collector layer; a trench gate disposed so as to extend from a surface of the emitter layer to the drift layer; as well as a second conductive type well layer provided on the surface of the silicon substrate at the end portion; The number of vacancies included in the crystal defects at the unit portion is smaller than the number of vacancies included in the crystal defects at the terminal portion, The interstitial silicon in the cell portion is larger than that in the terminal portion.

2. The semiconductor device according to claim 1, wherein The depth of the trench gate from the surface is D1, The oxygen concentration at a depth less than D1 from the surface of the unit portion is less than or equal to 1.8E17 / cm 3 .

3. The semiconductor device according to claim 2, wherein The D1 is 3 to 8 μm.

4. The semiconductor device according to any one of claims 1 to 3, wherein The oxygen concentration of the collector layer is less than or equal to 4.0E17 / cm 3 .

5. The semiconductor device according to any one of claims 1 to 3, wherein The oxygen concentration of the drift layer is the same as the oxygen concentration of the collector layer.

6. The semiconductor device according to any one of claims 1 to 3, wherein The semiconductor device further comprises a gate oxide film, which is provided on the inner wall of the trench gate. The withstand voltage between the collector layer and the emitter layer is greater than or equal to 600V, and the thickness of the gate oxide film is 7. A method for manufacturing a semiconductor device, comprising the following steps: Step (a) of preparing a first conductive type silicon substrate, the first conductive type silicon substrate being manufactured by MCZ (magnetic control Czochralski) method and having a unit portion and an end portion surrounding the unit portion when viewed from above; Step (b) of forming a first conductivity type emitter layer by ion implantation into the surface of the silicon substrate of the cell portion; Step (c) of forming a second conductivity type well layer by implanting ions into the surface of the silicon substrate at the terminal portion; Step (d), etching the surface of the emitter layer to form a trench gate; as well as Step (e) of performing heat treatment in a state where an oxide film is continuously formed on the surface of the unit portion and an oxide film is selectively formed on the terminal portion, The interstitial silicon in the cell portion is larger than that in the terminal portion.

8. The method for manufacturing a semiconductor device according to claim 7, wherein: The heat treatment is performed at 1150° C. or higher for 360 minutes or higher.

9. The method for manufacturing a semiconductor device according to claim 7 or 8, wherein: After the step (e), the following steps are further performed: Step (f), grinding the back side of the silicon substrate; and In step (g), ion implantation is performed on the back surface of the polished silicon substrate to form a collector layer of the second conductivity type.

10. The method for manufacturing a semiconductor device according to claim 7 or 8, wherein: The heating and cooling rates of the heat treatment at a temperature greater than or equal to 500° C. are less than or equal to 2° C. / minute.

11. The method for manufacturing a semiconductor device according to claim 7 or 8, wherein: The step (e) is performed after the step (d).

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