Method for limiting switching frequency of single-phase half-bridge pfc controlled by crm and pfc converter

Abstract

The application provides a single-phase half-bridge PFC converter based on CRM control with limited switching frequency, which comprises a main circuit module and a driving module, the driving module is used for generating a first driving signal and a second driving signal, and performing logical AND operation on the first driving signal and the second driving signal to generate a third driving signal used for controlling a switching tube of the main circuit module, wherein the first driving signal outputs a high level when a zero-crossing point of an inductance current of the main circuit module is detected, the second driving signal outputs a low level after delaying for a first preset time, and the second driving signal outputs a high level after delaying for a second preset time. The application increases a second driving signal on the hardware, performs logical AND operation on the initial first driving signal and the second driving signal to generate the driving signal of the switching tube, thereby limiting the driving frequency of the switching tube by adjusting the low level width of the second driving signal, and the distortion is small when the inductance current envelope is near the zero-crossing point, and the influence on the input current THDi is extremely small.

Description

Technical Field

[0001] This invention relates to the field of data circuit technology, and more particularly to a single-phase bridged PFC converter with limited switching frequency based on CRM control and a method for limiting the switching frequency. Background Technology

[0002] In mining power supplies, operating conditions are often heavy-load, resulting in significant energy consumption; therefore, an overall efficiency of ≥95% is required. To meet this efficiency target, the efficiency of the front-end power factor correction (PFC) circuit must be at least ≥98%, and the efficiency of the rear-end LLC (Inductance Inductance Capacitance) resonant circuit must be at least ≥97%. To ensure that the front-end PFC efficiency is ≥98%, Critical Conduction Mode (CRM) control must be used, i.e., the inductor current is critically turned on. When the Boost PFC converter inductor current operates at CRM, zero-voltage turn-on of the MOSFET and zero-current turn-off of the boost diode can be achieved. This reduces system losses and improves efficiency without changing the hardware.

[0003] When PFC uses CRM control, it typically uses software algorithms to calculate a compensation amount based on the current load and input voltage, which is then used to adjust the turn-on time T in real time. ON This achieves the purpose of limiting the switching frequency. However, the biggest drawback of this method is that forcibly adjusting T... ON Suppressing excessively high switching frequencies can introduce large harmonics, degrade the inductor current waveform, and worsen the total harmonic current distortion (THDi) of the input current. To meet the product standard of THDi < 5%, the input EMC circuit needs to be optimized, which increases the hardware cost. Summary of the Invention

[0004] The purpose of this invention is to provide a single-phase bridged PFC converter with limited switching frequency based on CRM control and a method for limiting the switching frequency, so as to reduce system cost while meeting the requirements of system performance.

[0005] According to one aspect of the present invention, a single-phase bridged PFC converter with limited switching frequency based on CRM control is provided, comprising a main circuit module and a drive module. The drive module is used to generate a first drive signal and a second drive signal, and to perform AND logic on the first drive signal and the second drive signal to generate a third drive signal for controlling the switching transistor of the main circuit module. When the zero-crossing point of the inductor current of the main circuit module is detected, the first drive signal outputs a high level, the second drive signal outputs a low level after a first preset time delay, and the second drive signal outputs a high level after a second preset time.

[0006] In the single-phase bridged PFC converter with limited switching frequency based on CRM control provided by the present invention, the main circuit module includes an input voltage source, a rectifier bridge, a first inductor, a first capacitor, a switching transistor, a first diode, a second capacitor, and a load. The two ends of the input voltage source are connected to the L and N ends of the rectifier bridge. The positive terminal of the rectifier bridge is connected to the first end of the first capacitor and the first end of the first inductor. The second end of the first inductor is connected to the drain of the switching transistor and the anode of the first diode. The cathode of the first diode is connected to the first end of the second capacitor and the first end of the load. The negative terminal of the rectifier bridge is connected to the second end of the first capacitor, the source of the switching transistor, the second end of the second capacitor, and the second end of the load.

[0007] In the single-phase bridged PFC converter with limited switching frequency based on CRM control provided by the present invention, the driving module includes a first driving unit, a second driving unit and an AND gate. The first driving unit and the second driving unit are connected to the input terminal of the AND gate, and the output terminal of the AND gate is connected to the gate of the switching transistor.

[0008] In the single-phase bridged PFC converter with limited switching frequency based on CRM control provided by the present invention, the first drive signal outputs a low level after the conduction time of the switching transistor is reached. The conduction time is determined by the given voltage of the second capacitor and the real-time sampling voltage.

[0009] In the single-phase bridged PFC converter with limited switching frequency based on CRM control provided by the present invention, the first preset time is greater than the transmission time of the third drive signal of the drive module to the gate of the switch transistor.

[0010] In the single-phase bridged PFC converter with finite switching frequency based on CRM control provided by this invention, T limit = 1 / f, where T limit The second preset time is given, and f is the maximum value of the switching frequency of the switching transistor.

[0011] According to another aspect of the present invention, a method for limiting the switching frequency of a single-phase bridged PFC based on CRM control is also provided, comprising the following steps:

[0012] The first driving unit outputs a first driving signal, the second driving unit outputs a second driving signal, and the first driving signal and the second driving signal are ANDed to generate a third driving signal for the switching transistor.

[0013] The current of the first inductor is detected. When the zero-crossing point of the current of the first inductor is detected, the first drive signal outputs a high level. After a first preset time delay, the second drive signal outputs a low level. After the conduction time of the switch is reached, the first drive signal outputs a low level, and after a second preset time, the second drive signal outputs a high level.

[0014] In the method provided by the present invention for limiting the switching frequency of a single-phase bridged PFC based on CRM control, the conduction time is determined by the given voltage of the second capacitor and the real-time sampled voltage.

[0015] In the method for limiting the switching frequency of a single-phase bridged PFC based on CRM control provided by the present invention, the first preset time is greater than the transmission time of the third drive signal of the drive module to the drive terminal of the switch tube.

[0016] In the method provided by this invention for limiting the switching frequency of a single-phase bridged PFC based on CRM control, T limit = 1 / f, where T limit The second preset time is given, and f is the maximum value of the switching frequency of the switching transistor.

[0017] The single-phase bridged PFC converter with limited switching frequency based on CRM control and its frequency limiting method, as described in this invention, has the following beneficial effects: This invention generates the drive signal for the switching diode by adding a second drive signal in the hardware and performing a logical AND operation with the initial first drive signal; when the zero-crossing point of the inductor current of the main circuit module is detected, the first drive signal outputs a high level, and after a first preset time delay, the second drive signal outputs a low level, and after a second preset time, the second drive signal outputs a high level; thus, by adjusting the low-level width of the second drive signal, the drive frequency of the switching diode is limited. When the inductor current envelope is near the zero-crossing point, the distortion is small, and the impact on the input current THDi is minimal. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort:

[0019] Figure 1 The diagram shown is a schematic of a single-phase bridged PFC converter with limited switching frequency based on CRM control, according to an embodiment of the present invention.

[0020] Figure 2 What is shown is Figure 1 The topology diagram of the main circuit module is shown below;

[0021] Figure 3 What is shown is Figure 2 The diagram shown is a flowchart for calculating the on-time of the switching transistor.

[0022] Figure 4 The figure shown is a waveform diagram of a single-phase bridged PFC converter with limited switching frequency based on CRM control, according to an embodiment of the present invention.

[0023] Figure 5 This is the inductor current waveform of a PFC converter in the prior art;

[0024] Figure 6 The inductor current waveform of a single-phase bridged PFC converter with limited switching frequency based on CRM control is provided in an embodiment of the present invention. Detailed Implementation

[0025] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0026] When the inductor current of the Boost PFC converter operates in critical continuous mode, the switching frequency of the MOSFET can be calculated using the following formula (1). As can be seen from formula 1, the system switching frequency is determined by three variables: the effective value of the input voltage, the instantaneous value of the input voltage, and the load power, and is in a time-varying state.

[0027]

[0028] The meanings of the variables in the formula are as follows: F SW The system switching frequency is the switching frequency of the switching transistor S1, V.im Peak input voltage, V o Output bus voltage; L: PFC boost inductance; P o : Load power, η: PFC efficiency, PF: PFC power factor.

[0029] Under traditional CCM control, the switching frequency of the MOSFET, i.e. the carrier frequency, is set by software. However, under CRM control, the switching frequency of the system is completely determined by hardware (for the reason, refer to formula (1)). For the mining power supply, the maximum effective value of the input voltage is 285V. At this voltage level, near the zero-crossing point of the instantaneous value of the input voltage, the theoretical switching frequency of the system will reach 500kHz. However, the recommended operating frequency of the MOSFET selected in the project is below 200kHz, which will cause significant losses to the MOSFET and create safety hazards for the product itself. Therefore, under CRM control, the switching frequency of the MOSFET must be limited, while not affecting the performance of the system.

[0030] The overall idea of ​​this invention is to generate a drive signal for the switching transistor by adding a second drive signal to the hardware and performing a logical AND operation with the initial first drive signal. The drive frequency of the switching transistor is limited by adjusting the low-level width of the second drive signal, so that when the inductor current envelope is near the zero crossing point, a slight distortion is caused, which has a minimal impact on the input current THDi. In this way, the switching frequency can be limited without affecting the performance of the system.

[0031] Figure 1 The diagram shown is a schematic of a single-phase bridged PFC converter with finite switching frequency based on CRM control, according to an embodiment of the present invention. Figure 1As shown, the single-phase bridged PFC converter with limited switching frequency based on CRM control provided by the present invention includes a main circuit module 10 and a drive module. The drive module generates drive signals to control the switching transistors of the main circuit module 10. In this embodiment, the drive module generates a first drive signal and a second drive signal, both of which are PWM signals, and performs AND logic on the first drive signal and the second drive signal to generate a third drive signal for controlling the switching transistors. When the inductor current of the main circuit module crosses zero, the first drive signal outputs a high level. After a first preset time delay, the second drive signal outputs a low level. Thus, within the first preset time, both the first and second drive signals are high, and the third drive signal is high, driving the switching transistors of the main circuit module to conduct. After the conduction time of the switching transistors of the main circuit module is reached, the first drive signal outputs a low level. After a second preset time, the second drive signal outputs a high level. Thus, within the second preset time, the second drive signal remains low, and the third drive signal is also low, unable to drive the switching transistors of the main circuit module to conduct. Therefore, the driving frequency of the switching transistor of the main circuit module can be limited by adjusting the low-level width of the second driving signal (i.e., the length of the second preset time).

[0032] Specifically, such as Figure 2 As shown, in one embodiment of the present invention, the main circuit module includes an input voltage source u. s The components include a rectifier bridge, a first inductor L1, a first capacitor C1, a switching transistor S1, a first diode D1, a second capacitor C2, and a load R. Load The input voltage source is connected to the L and N terminals of the rectifier bridge. The positive terminal of the rectifier bridge is connected to the first terminal 101 of the first capacitor C1 and the first terminal 102 of the first inductor L1. The second terminal 103 of the first inductor L1 is connected to the drain of the switching transistor S1 and the anode of the first diode D1. The cathode of the first diode D1 is connected to the first terminal 104 of the second capacitor C2 and the load R. Load The first terminal 105 is connected to the negative terminal of the rectifier bridge, which is connected to the second terminal 106 of the first capacitor C1, the source of the switching transistor S1, the second terminal 107 of the second capacitor C2, and the load R. Load The second end is 108.

[0033] Specifically, such as Figure 1 As shown, in one embodiment of the present invention, the driving module includes a first driving unit 210, a second driving unit 220, and an AND gate 230. The first driving unit 210 and the second driving unit 220 are connected to the input terminal of the AND gate 230, and the output terminal of the AND gate 230 is connected to the gate of the switching transistor. When the first driving unit detects the zero-crossing point of the current of the first inductor, the first driving unit outputs a high-level first driving signal ePWM1. When time T elapses... onThen, the first drive unit outputs a low-level first drive signal to turn off the drive of the switching transistor; before the zero-crossing point of the current of the first inductor is reached, the second drive unit outputs a high-level second drive signal ePWM2. When the second drive unit detects the zero-crossing point of the current of the first inductor, it continues to wait for a first preset time, and then the second drive unit outputs a low-level second drive signal. After a second preset time, the second drive unit outputs a high-level second drive signal.

[0034] Specifically, such as Figure 3 As shown, the conduction time of the switching transistor is determined by the given voltage of the second capacitor and the real-time sampled voltage. First, the given voltage U of the second capacitor... DC_Ref and real-time sampling voltage U DC_fdb The subtraction operation is performed, and then the result is passed through a PI controller. The output is the conduction time.

[0035] Specifically, in one embodiment of the present invention, if the second driving unit directly outputs a low level when it detects the zero-crossing point of the inductor current of the first inductor, then the third driving signal will directly become 0. Therefore, it is necessary to ensure that the first driving unit outputs a high level before the second driving unit outputs a low level. Furthermore, the first preset time is greater than the transmission time of the third driving signal of the driving module to the gate of the switching transistor.

[0036] Specifically, in one embodiment of the present invention, after the second driving unit outputs a low level, it outputs a high level again after a second preset time, until the next zero-crossing signal of the inductor current arrives. During the entire second preset time, the driving signal of the switching transistor is at a low level; therefore, the second preset time is the frequency limiting period, and its specific value can be flexibly set according to the actual type of switching transistor and the actual debugging situation. Further, T... limit = 1 / f, where T limit The second preset time is given, and f is the maximum value of the switching frequency of the switching transistor.

[0037] Figure 4 The figure shows the operating waveforms of a single-phase bridged PFC converter with limited switching frequency based on CRM control, according to an embodiment of the present invention. The figure illustrates the inductor current i over three switching cycles. L .from Figure 4 It can be seen that at a certain moment, the switching period is continuously increasing, T3>T2>T1, so the switching frequency is decreasing. At t=0, t1, t2, t3, that is, when the inductor current crosses zero, the main circuit module will send a level signal. When the first drive unit detects the rising edge of this level signal, the first drive unit outputs a high-level first drive signal ePWM1. When T... onUpon arrival, a low-level first drive signal ePWM1 is output. When the second drive unit detects the rising edge of this signal, after a first preset time (e.g., 100ns), the second drive unit outputs a low-level second drive signal ePWM2. Limit During the first preset time period, the second drive unit outputs a high-level second drive signal ePWM2 until the next inductor current zero-crossing signal arrives. Thus, during the first preset time period, both the first drive signal ePWM1 and the second drive signal ePWM2 are high, and the third drive signal ePWM3 generated by the logical AND operation is also high, turning on the switch. During the second preset time period T... limit Within this timeframe, the second drive signal ePWM2 remains low. Therefore, regardless of whether the first drive signal ePWM1 is high or low during this period, the third drive signal ePWM3, generated through a logical AND operation, will always be low, and the switching transistor will not conduct. Figure 4 It can be seen that after adding a second drive signal with frequency limiting function, the second switching cycle will disappear, thereby limiting the system switching frequency to the set value.

[0038] Figure 5 This is the inductor current waveform of a PFC converter in the prior art; Figure 6 This is the inductor current waveform of the PFC converter implemented according to the present invention. Formula (1) describes three key factors affecting the switching frequency: input voltage, instantaneous value of input voltage, and load power. Therefore, the present invention conducted a comparative experiment, testing the inductor current waveforms (the ripple frequency of the inductor current is the system switching frequency) of the existing PFC converter and the PFC converter implementing the present invention, respectively. The test conditions are as follows: AC input side connected to a Chroma source, 220V, 50Hz; DC bus connected to a resistive load, test power 700W. Figure 5 The inductor current waveform is shown when using an existing PFC converter. Statistical analysis reveals that the maximum switching frequency of the system is 170.64kHz. Figure 6 The inductor current waveform when using the PFC converter of this invention is shown in the data statistics, with a maximum switching frequency of 106.18kHz. Through experimental comparison, when the input is 220V and the load is 700W, this invention can effectively reduce the switching frequency from 170.64kHz to 106.18kHz. This invention generates the drive signal for the switching transistor by adding a second drive signal in hardware and performing a logical AND operation with the initial first drive signal. By adjusting the low-level width of the second drive signal, the drive frequency of the switching transistor is limited. When the inductor current envelope is near the zero-crossing point, the distortion is small, and the impact on the input current THDi is minimal.

[0039] This invention provides a method for limiting the switching frequency of a single-phase bridged PFC based on CRM control, comprising the following steps:

[0040] The first driving unit outputs a first driving signal, the second driving unit outputs a second driving signal, and the first driving signal and the second driving signal are ANDed to generate a third driving signal for controlling the switching transistor.

[0041] The current of the first inductor is detected. When the zero-crossing point of the current of the first inductor is detected, the first drive signal outputs a high level. After a first preset time delay, the second drive signal outputs a low level. After the conduction time of the switching transistor is reached, the first drive signal outputs a low level, and after a second preset time, the second drive signal outputs a high level.

[0042] Certain specific embodiments of the invention have been described above. Note that the terminology used herein is for the purpose of describing specific embodiments only and is not intended to be limiting. For example, unless the context clearly indicates otherwise, the singular forms “a” and “the” as used herein are intended to also include the plural forms. It will also be understood that the word “comprising”, when used in this specification, specifies the presence of the stated features, integrals, steps, operations, units, and / or components without excluding the presence or addition of one or more other features, integrals, steps, operations, units, components, and / or combinations thereof.

[0043] Although several embodiments of the invention have been described above with reference to the accompanying drawings, it should be understood that the invention is not limited to the specific embodiments disclosed. The invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. The scope of the appended claims is to be interpreted in the broadest possible sense, thus encompassing all such modifications and equivalent structures and functions.

Claims

1. A single-phase bridged PFC converter with finite switching frequency based on CRM control, characterized in that, The system includes a main circuit module and a drive module. The drive module generates a first drive signal and a second drive signal, and performs an AND logic operation on the first and second drive signals to generate a third drive signal for controlling the switching transistor of the main circuit module. Specifically, when a zero-crossing point of the inductor current of the main circuit module is detected, the first drive signal outputs a high level; after a first preset time delay, the second drive signal outputs a low level; after a second preset time delay, the second drive signal outputs a high level again. limit =1 / f, where T limit The second preset time is given, and f is the maximum value of the switching frequency of the switching transistor.

2. The single-phase bridged PFC converter with limited switching frequency based on CRM control according to claim 1, characterized in that, The main circuit module includes an input voltage source, a rectifier bridge, a first inductor, a first capacitor, a switching transistor, a first diode, a second capacitor, and a load. The two ends of the input voltage source are respectively connected to the L and N ends of the rectifier bridge. The positive terminal of the rectifier bridge is connected to the first end of the first capacitor and the first end of the first inductor. The second end of the first inductor is connected to the drain of the switching transistor and the anode of the first diode. The cathode of the first diode is connected to the first end of the second capacitor and the first end of the load. The negative terminal of the rectifier bridge is connected to the second end of the first capacitor, the source of the switching transistor, the second end of the second capacitor, and the second end of the load.

3. The single-phase bridged PFC converter with limited switching frequency based on CRM control according to claim 2, characterized in that, The driving module includes a first driving unit, a second driving unit, and an AND gate. The first driving unit and the second driving unit are connected to the input terminal of the AND gate, and the output terminal of the AND gate is connected to the gate of the switching transistor.

4. The single-phase bridged PFC converter with limited switching frequency based on CRM control according to claim 2, characterized in that, After the on-time of the switch is reached, the first drive signal outputs a low level. The on-time is determined by the given voltage of the second capacitor and the real-time sampled voltage.

5. The single-phase bridged PFC converter with limited switching frequency based on CRM control according to claim 2, characterized in that, The first preset time is greater than the transmission time of the third drive signal of the drive module to the gate of the switching transistor.

6. A method for limiting the switching frequency of a single-phase bridged PFC based on CRM control, characterized in that, Includes the following steps: The first driving unit outputs a first driving signal, the second driving unit outputs a second driving signal, and after performing an AND operation on the first driving signal and the second driving signal, a third driving signal for controlling the switching transistor is generated. The current of the first inductor is detected. When the zero-crossing point of the first inductor current is detected, the first drive signal outputs a high level. After a first preset time delay, the second drive signal outputs a low level. After the conduction time of the switching transistor is reached, the first drive signal outputs a low level, and after a second preset time, the second drive signal outputs a high level. T limit =1 / f, where T limit The second preset time is given, and f is the maximum value of the switching frequency of the switching transistor.

7. The method for limiting the switching frequency of a single-phase bridged PFC based on CRM control according to claim 6, characterized in that, The conduction time is determined by the given voltage of the second capacitor and the real-time sampled voltage.

8. The method for limiting the switching frequency of a single-phase bridged PFC based on CRM control according to claim 6, characterized in that, The first preset time is greater than the transmission time of the third drive signal of the drive module to the gate of the switching transistor.

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