Multioctave broadband power amplifier
By introducing an LC input matching network and a high-order matching network into the power amplifier, combined with transformer and capacitor/inductor configuration, the problems of poor matching and high-frequency loss in multi-octave broadband design of traditional matching networks are solved, achieving wider bandwidth and more efficient signal gain.
Patent Information
- Application Number
- CN202210404227.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-04-18
- Publication Date
- 2025-11-14
- Estimated Expiration
- 2042-04-18
AI Technical Summary
Traditional transformer-based matching networks cannot achieve good matching across the entire frequency band in multi-octave broadband designs, and suffer from severe losses in the high-frequency band, which limits the operating bandwidth and efficiency of power amplifiers.
By employing an LC input matching network, an inter-stage high-order matching network, and an output high-order matching network, combined with the configuration of transformers, capacitors, and inductors, the order of the matching circuit is increased and the network area on the SOC chip is reduced, thereby achieving broadband matching with multiple octave bands and reducing high-frequency losses.
Better signal gain and flatness are achieved over a wider frequency range, especially with high signal gain and good flatness in the 6GHz to 18GHz range, reducing the loss of the on-chip matching network.
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Figure CN114598276B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of electronic circuit technology, and in particular to a multi-octave broadband power amplifier. Background Technology
[0002] Figure 1 This is a schematic diagram of a traditional transformer-matched broadband power amplifier circuit. Its input, interstage, and output matching are composed of transformers T1, T2, and T3, and parallel capacitors C1, C2, C3, C4, C5, and C6, respectively. Key parameters include primary coil inductance, secondary coil inductance, coupling coefficient k, and parallel capacitors on both the primary and secondary coil sides. Traditional transformer-based matching networks can only match the load impedance to the target impedance at two frequency points. Outside these frequencies, mismatch and transformer losses affect the power amplifier's gain, output power, and efficiency, thus limiting its operating bandwidth. Especially in multi-octave broadband designs, this network cannot achieve good matching across the entire frequency band. Furthermore, at high frequencies, the losses of the on-chip transformer are not negligible, further reducing the power amplifier's operating bandwidth.
[0003] The information disclosed in this background section is intended only to enhance the understanding of the overall background of the invention and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention
[0004] The purpose of this invention is to provide a multi-octave broadband power amplifier that can achieve matching within a multi-octave broadband range and reduce the loss of the on-chip matching network in the high-frequency band.
[0005] To achieve the above objectives, embodiments of the present invention provide a multi-octave broadband power amplifier, comprising: an LC input matching network, a driving network, an interstage high-order matching network, an amplification network, and an output high-order matching network connected in sequence. The interstage high-order matching network includes a first transformer, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a third inductor, and a fourth inductor. The primary coil of the first transformer is connected to the driving network. The two ends of the third capacitor are connected to the two ends of the secondary coil of the first transformer. The third inductor and the fourth inductor are connected in series and then in parallel with the sixth capacitor, with one end connected to one end of the secondary coil of the first transformer through the fourth capacitor and the other end connected to the other end of the secondary coil of the first transformer through the fifth capacitor.
[0006] In one or more embodiments of the present invention, the output high-order matching network includes a second transformer, a ninth capacitor, a tenth capacitor, a fifth inductor, and an eleventh capacitor. The primary coil of the second transformer is connected to the amplification network. The two ends of the ninth capacitor are connected to the two ends of the secondary coil of the second transformer. One end of the fifth inductor and the eleventh capacitor connected in parallel is connected to the output terminal and is connected to one end of the primary coil of the second transformer through the tenth capacitor. The other end is connected to the other end of the primary coil of the second transformer and grounded.
[0007] In one or more embodiments of the present invention, the LC input matching network includes a first inductor and a second inductor, one end of the first inductor is connected to a first input terminal and the other end is connected to a driving network, and one end of the second inductor is connected to a second input terminal and the other end is connected to a driving network.
[0008] In one or more embodiments of the present invention, the equivalent capacitance of the driving network is the matching capacitance of the LC input matching network.
[0009] In one or more embodiments of the present invention, the driving network includes a first transistor, a second transistor, a first capacitor, a second capacitor, and a first resistor. One end of the first capacitor is connected to the gate of the second transistor, one end of the first resistor, and an LC input matching network, and the other end is connected to the drain of the first transistor and an interstage higher-order matching network. One end of the second capacitor is connected to the gate of the first transistor, the other end of the first resistor, and an LC input matching network, and the other end is connected to the drain of the second transistor and an interstage higher-order matching network. The source of the first transistor and the source of the second transistor are connected to and grounded.
[0010] In one or more embodiments of the present invention, the amplification network includes a seventh capacitor, an eighth capacitor, a third resistor, a third transistor, and a fourth transistor. One end of the seventh capacitor is connected to one end of the third resistor, the gate of the fourth transistor, and the interstage high-order matching network, and the other end is connected to the drain of the third transistor and the output high-order matching network. One end of the eighth capacitor is connected to the other end of the third resistor, the gate of the third transistor, and the interstage high-order matching network, and the other end is connected to the drain of the fourth transistor. The source of the third transistor and the source of the fourth transistor are connected together and grounded.
[0011] In one or more embodiments of the present invention, the LC input matching network is a second-order LC input matching network based on a Chebyshev low-pass filter.
[0012] In one or more embodiments of the present invention, the connection point between the third inductor and the fourth inductor is connected to a bias voltage via a second resistor.
[0013] In one or more embodiments of the present invention, the diameters of the first inductor and the second inductor are 60 to 90 μm.
[0014] In one or more embodiments of the present invention, the first inductor, the second inductor, the third inductor, the fourth inductor and / or the fifth inductor are replaced by transmission lines.
[0015] Compared with the prior art, the multi-octave broadband power amplifier according to embodiments of the present invention reduces the area of the inter-stage and output matching networks by setting up an LC input matching network, an inter-stage high-order matching network, and an output high-order matching network, thereby achieving multi-octave bandwidth within the limited area of the SOC chip; at the same time, by configuring the inter-stage high-order matching network and the output high-order matching network, the order of the matching circuit is higher in the impedance matching of the fundamental signal, thereby allowing the power amplifier to have better signal gain and flatness over a wider bandwidth. Attached Figure Description
[0016] Figure 1 This is a circuit schematic of a broadband power amplifier based on transformer matching in the prior art.
[0017] Figure 2 This is a circuit schematic diagram of a multi-octave broadband power amplifier according to an embodiment of the present invention.
[0018] Figure 3 This is a gain-bandwidth diagram of a multi-octave broadband power amplifier according to an embodiment of the present invention. Detailed Implementation
[0019] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings, but it should be understood that the scope of protection of the present invention is not limited to the specific embodiments.
[0020] Unless otherwise expressly stated, throughout the specification and claims, the term "comprising" or its variations such as "including" or "comprises" shall be understood to include the stated elements or components without excluding other elements or other components.
[0021] Example 1
[0022] like Figure 2 As shown, a multi-octave broadband power amplifier includes: an LC input matching network 10, a drive network 20, an interstage high-order matching network 30, an amplification network 40, and an output high-order matching network 50 connected in sequence.
[0023] like Figure 2As shown, the LC input matching network 10 includes a first inductor L1 and a second inductor L2, as well as matching capacitors connected to the first inductor L1 and the second inductor L2 respectively. One end of the first inductor L1 is connected to the first input terminal Input+, and the other end is connected to the driving network 20. One end of the second inductor L2 is connected to the second input terminal Input-, and the other end is connected to the driving network 20. In this embodiment, the LC input matching network 10 is a second-order LC input matching network based on a Chebyshev low-pass filter. In the LC input matching network 10, the matching capacitors connected to the first inductor L1 and the second inductor L2 respectively are the equivalent capacitances of the driving network 20.
[0024] In this embodiment, the diameters of the first and second inductors are 60–90 μm, preferably 80 μm, indicating that both inductors have very small areas. Since the power amplifier also serves as the load of the previous stage, the target impedance of the LC input matching network 10 is determined by the previous stage. By using small-area first and second inductors, the impedance transformation requirements of the previous stage can be met, thereby occupying a smaller area on the chip while ensuring impedance transformation.
[0025] like Figure 2 As shown, the driving network 20 includes a first transistor M1, a second transistor M2, a first capacitor C1, a second capacitor C2, and a first resistor R1. One end of the first capacitor C1 is connected to the gate of the second transistor M2, one end of the first resistor R1, and the second inductor L2 of the LC input matching network 10; the other end is connected to the drain of the first transistor M1 and the interstage high-order matching network 30. One end of the second capacitor C2 is connected to the gate of the first transistor M1, the other end of the first resistor R1, and the first inductor L1 of the LC input matching network 10; the other end is connected to the drain of the second transistor M2 and the interstage high-order matching network 30. The sources of the first transistor M1 and the second transistor M2 are connected to and grounded.
[0026] like Figure 2As shown, the interstage high-order matching network 30 includes a first transformer T1, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, a third inductor L3, and a fourth inductor L4. The primary winding of the first transformer T1 is connected to the drain of the first transistor M1 and the drain of the second transistor M2 in the drive network 20, respectively. The two ends of the third capacitor C3 are connected to the two ends of the secondary winding of the first transformer T1. The third inductor L3 and the fourth inductor L4 are connected in series and then in parallel with the sixth capacitor C6, with one end connected to one end of the secondary winding of the first transformer T1 through the fourth capacitor C4, and the other end connected to the other end of the secondary winding of the first transformer T1 through the fifth capacitor C5. The two ends of the series connection of the third inductor L3 and the fourth inductor L4 and the parallel connection with the sixth capacitor C6 are simultaneously connected to the amplification network 40. The connection point of the third inductor L3 and the fourth inductor L4 is connected to the bias voltage V through the second resistor R2. G2 In this embodiment, since the area of a chip on a SOC (System-on-a-Chip) is always limited, a higher order can be achieved on the same area using the first transformer T1, thereby occupying a smaller area while ensuring matching bandwidth and reducing the area of the inter-stage matching network.
[0027] like Figure 2 As shown, the amplification network 40 includes a seventh capacitor C7, an eighth capacitor C8, a third resistor R3, a third transistor M3, and a fourth transistor M4. One end of the seventh capacitor C7 is connected to one end of the third resistor R3 and the gate of the fourth transistor M4, as well as one end of the sixth capacitor C6 of the interstage high-order matching network 30; the other end is connected to the drain of the third transistor M3 and the output high-order matching network 50. One end of the eighth capacitor C8 is connected to the other end of the third resistor R3 and the gate of the third transistor M3, as well as the other end of the sixth capacitor C6 of the interstage high-order matching network 30; the other end is connected to the drain of the fourth transistor M4. The sources of the third transistor M3 and the fourth transistor M4 are connected together and grounded.
[0028] like Figure 2As shown, the output high-order matching network 50 includes a second transformer T2, a ninth capacitor C9, a tenth capacitor C10, a fifth inductor L5, and an eleventh capacitor C11. The primary winding of the second transformer T2 is connected to the drain of the third transistor M3 and the drain of the fourth transistor M4 in the amplification network 40, respectively. The ninth capacitor C9 is connected to the secondary winding of the second transformer T2. One end of the fifth inductor L5, connected in parallel with the eleventh capacitor C11, is connected to the output terminal Output+ and, through the tenth capacitor C10, is connected to one end of the secondary winding of the second transformer T2, while the other end is connected to the other end of the secondary winding of the second transformer T2 and grounded (END). In this embodiment, since the chip area on a System-on-Chip (SoC) is always limited, the second transformer T2 allows for a higher order to be achieved within the same area, thus occupying a smaller area while maintaining matching bandwidth, thereby reducing the area of the output matching network. Furthermore, the second transformer T2 can also function as a balun at the output, enabling differential-to-single-ended conversion.
[0029] In this embodiment, by reducing the area of the LC input matching network 10, the inter-stage high-order matching network 30, and the output high-order matching network 50, a bandwidth of multiple octaves can be achieved within a limited area.
[0030] In this embodiment, the third inductor L3 and the fourth inductor L4, the third capacitor C3 and the sixth capacitor C6, which are connected in series, are connected in parallel with the first transformer T1. The fifth inductor L5, the ninth capacitor, and the eleventh capacitor C11 are connected in parallel with the second transformer T2. Each transformer, capacitor, and inductor directly participates in the impedance matching of the fundamental signal. Since each inductor, capacitor, and transformer participates in the fundamental matching, the fundamental matching circuit in this circuit has a higher order, which allows the power amplifier to have better signal gain and flatness over a wider bandwidth. Figure 3 The horizontal axis represents frequency, and the vertical axis represents gain. Figure 3 As can be seen, the power amplifier in this embodiment has very high signal gain and excellent flatness within a bandwidth of 6GHz to 18GHz, especially at a frequency of 9GHz, where it has the highest signal gain of 20.9dB.
[0031] In other embodiments, the first inductor L1, the second inductor L2, the third inductor L3, the fourth inductor L4, and the fifth inductor L5 can all be replaced by transmission lines.
[0032] The foregoing description of specific exemplary embodiments of the invention is for illustrative and explanatory purposes. These descriptions are not intended to limit the invention to the precise forms disclosed, and it will be apparent that many changes and variations can be made in accordance with the foregoing teachings. The exemplary embodiments were chosen and described in order to explain the specific principles of the invention and its practical application, thereby enabling those skilled in the art to implement and utilize various different exemplary embodiments of the invention, as well as various different choices and variations. The scope of the invention is intended to be defined by the claims and their equivalents.
Claims
1. A multi-octave broadband power amplifier, characterized in that, include: The LC input matching network, drive network, interstage high-order matching network, amplification network, and output high-order matching network are connected in sequence. The interstage high-order matching network includes a first transformer, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a third inductor, and a fourth inductor. The primary coil of the first transformer is connected to the drive network. The two ends of the third capacitor are connected to the two ends of the secondary coil of the first transformer. The third and fourth inductors are connected in series and then in parallel with the sixth capacitor, with one end connected to one end of the secondary coil of the first transformer through the fourth capacitor, and the other end connected to the other end of the secondary coil of the first transformer through the fifth capacitor. The LC input matching network includes... The system includes a first inductor and a second inductor. One end of the first inductor is connected to a first input terminal and the other end is connected to a driving network. One end of the second inductor is connected to a second input terminal and the other end is connected to a driving network. The output high-order matching network includes a second transformer, a ninth capacitor, a tenth capacitor, a fifth inductor, and an eleventh capacitor. The primary coil of the second transformer is connected to an amplification network. The two ends of the ninth capacitor are connected to the two ends of the secondary coil of the second transformer. One end of the fifth inductor and the eleventh capacitor connected in parallel is connected to the output terminal and is connected to one end of the primary coil of the second transformer through the tenth capacitor. The other end is connected to the other end of the primary coil of the second transformer and grounded. The LC input matching network is a second-order LC input matching network based on a Chebyshev low-pass filter.
2. The multi-octave broadband power amplifier as described in claim 1, characterized in that, The equivalent capacitance of the driving network is the matching capacitance of the LC input matching network.
3. The multi-octave broadband power amplifier as described in claim 1, characterized in that, The driving network includes a first transistor, a second transistor, a first capacitor, a second capacitor, and a first resistor. One end of the first capacitor is connected to the gate of the second transistor, one end of the first resistor, and an LC input matching network, and the other end is connected to the drain of the first transistor and an interstage higher-order matching network. One end of the second capacitor is connected to the gate of the first transistor, the other end of the first resistor, and an LC input matching network, and the other end is connected to the drain of the second transistor and an interstage higher-order matching network. The source of the first transistor and the source of the second transistor are connected to and grounded.
4. The multi-octave broadband power amplifier as described in claim 1, characterized in that, The amplification network includes a seventh capacitor, an eighth capacitor, a third resistor, a third transistor, and a fourth transistor. One end of the seventh capacitor is connected to one end of the third resistor, the gate of the fourth transistor, and the interstage high-order matching network, and the other end is connected to the drain of the third transistor and the output high-order matching network. One end of the eighth capacitor is connected to the other end of the third resistor, the gate of the third transistor, and the interstage high-order matching network, and the other end is connected to the drain of the fourth transistor. The source of the third transistor and the source of the fourth transistor are connected together and grounded.
5. The multi-octave broadband power amplifier as described in claim 1, characterized in that, The connection point between the third and fourth inductors is connected to a bias voltage via a second resistor.
6. The multi-octave broadband power amplifier as described in claim 1, characterized in that, The diameters of the first and second inductors are 60–90 μm.
7. The multi-octave broadband power amplifier as described in claim 1, characterized in that, The first inductor, the second inductor, the third inductor, the fourth inductor and / or the fifth inductor are replaced by transmission lines.
Citation Information
Patent Citations
Multi-octave broadband power amplifier
CN217116038U