Low latency cache for non-volatile memory in hybrid dimm

Abstract

Systems and methods are disclosed that include a first memory device, a second memory device coupled to the first memory device, where the second memory device has a lower access latency than the first memory device and acts as a cache for the first memory device. A processing device, which is operatively coupled to the first and second memory devices, can track access statistics for a section of data stored at the second memory device, the section having a first granularity, and based on the access statistics, determine to update the section of data stored at the second memory device from the first granularity to a second granularity. The processing device can further retrieve additional data associated with the section of data from the first memory device and store the additional data at the second memory device to form a new section having the second granularity.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to memory subsystems, and more specifically, to a low-latency cache for non-volatile memory in a hybrid dual in-line memory module (DIMM). Background Technology

[0002] The memory subsystem may include one or more memory devices for storing data. For example, the memory devices may be non-volatile memory devices and volatile memory devices. Generally, the host system can utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Attached Figure Description

[0003] This disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments thereof.

[0004] Figure 1 This describes an example computing system including a memory subsystem according to some embodiments of the present disclosure.

[0005] Figure 2 This is a flowchart of an example method for tracking and managing a data cache according to some embodiments of the present disclosure.

[0006] Figure 3 This is a flowchart of an example method for performing operations in response to page cache misses and sector cache misses, according to some embodiments of the present disclosure.

[0007] Figure 4 This is a flowchart of an example method for performing a cleaning operation according to some embodiments of the present disclosure.

[0008] Figure 5 This is a flowchart of another example method for tracking and managing data cache according to some embodiments of the present disclosure.

[0009] Figure 6 This is a block diagram of an example computer system in which embodiments of this disclosure may be operated. Detailed Implementation

[0010] This disclosure relates to a low-latency cache for non-volatile memory in a hybrid dual in-line memory module. The memory subsystem may be a storage device, a memory module, or a hybrid of a storage device and a memory module. The following is in conjunction with... Figure 1Describe examples of storage devices and memory modules. Generally, a host system may utilize a memory subsystem comprising one or more components, such as a memory device for storing data. The host system can provide data to be stored in the memory subsystem and can request data to be retrieved from the memory subsystem.

[0011] The memory subsystem may include both non-volatile and volatile memory devices. One example of a non-volatile memory device is a NAND flash memory device. Another example is a three-dimensional cross-point (“3D cross-point”) memory device, which is a cross-point array of non-volatile memory cells. The following section combines... Figure 1 Other examples of non-volatile memory devices are described. A non-volatile memory device is a package of one or more dies. The dies in the package can be assigned to one or more channels for communication with a memory subsystem controller. Each die may contain a set of memory cells (“cells”). A cell is an electronic circuit that stores information. Depending on the cell type, a cell may store one or more bits of binary information and has various logic states related to the number of bits stored. The logic states may be represented by binary values, such as “0” and “1”, or combinations of such values.

[0012] Non-volatile memory devices may include three-dimensional cross-point (“3D cross-point”) memory devices, which are cross-point arrays of non-volatile memory cells and can be combined with stackable cross-grid data access arrays to perform bit storage based on changes in volume resistance. Furthermore, unlike many flash-based memories, 3D cross-point memory devices can perform in-situ write operations, where non-volatile memory cells can be programmed without prior erasing of them. This non-volatile memory device can group pages across the die and channels to form management units (MUs).

[0013] The memory subsystem may be a hybrid DIMM, comprising a first type of memory device (e.g., 3D cross-point media) and a second type of memory device (e.g., dynamic random access memory (DRAM)) within a single DIMM package. The first type of memory device (i.e., the first memory type) may have a large storage capacity but high access latency, while the second type of memory device (i.e., the second memory type) has a smaller storage capacity but lower access latency. A cache manager manages the retrieval, storage, and delivery of data to and from the first type of memory device and the second type of memory device. In conventional memory systems, the cache manager resides in the host system and is operatively coupled to a first controller communicating with the first type of memory device and a second controller communicating with the second type of memory device. However, implementing a cache manager in the host system can lead to inefficiencies. For example, data traffic between the first and second memory types may be restricted by a channel protocol, resulting in reduced cache hit rates and poor performance.

[0014] This disclosure addresses the aforementioned and other shortcomings by implementing a hybrid DIMM that incorporates a cache manager within a DIMM package. The cache manager allows a second type of memory to act as a cache for a first memory type. Therefore, if the cache hit rate is high, the high latency of the first memory type can be masked by the low latency of the second memory type. For example, a DRAM memory device or other volatile memory can be used as a cache for a 3D cross-point memory device or other non-volatile memory devices (e.g., storage class memory (SCM)). The host system can utilize the hybrid DIMM to retrieve and store data at the 3D cross-point memory. The hybrid DIMM can be coupled to the host system via a bus interface (e.g., a DIMM connector). The DIMM connector can be a synchronous or asynchronous interface between the hybrid DIMM and the host system. When the host system provides a memory access operation (e.g., a read operation), the corresponding data can be returned to the host system from the 3D cross-point memory or from another memory device within the hybrid DIMM that serves as a cache for the 3D cross-point memory.

[0015] In an illustrative example, DRAM can be configured as a cache to store recently accessed and / or frequently accessed data, enabling fast access to such data by the host system. The DRAM data cache can be partitioned into two distinct caches managed with different data sizes. One partition may contain a page cache with a larger granularity (i.e., a larger size), and the second partition may contain a sector cache with a smaller granularity (i.e., a smaller size). Because the page cache uses a larger data size, less metadata is used to manage the data (e.g., only a single valid bit for the entire page). The smaller data size of the sector cache allows for a larger amount of metadata (e.g., a larger number of valid bits and dirty bits, and tags, etc.), but allows for more detailed tracking of host access data, thus increasing the overall cache hit rate in the DRAM data cache. Increasing the hit rate in the DRAM data cache provides performance comparable to a DIMM with only DRAM memory devices, but offers additional memory capacity, lower cost, and support for persistent memory. Additionally, tracking data at the sector granularity can reduce bandwidth utilization between the DRAM and 3D cross-point memory when filling lost data into the sector cache or writing dirty data from the DRAM memory device to the 3D cross-point memory. In some embodiments, the controller can track access statistics for data segments stored at the DRAM memory device with a smaller granularity. Based on the access statistics, the controller can update the data segments to a larger granularity by retrieving additional data associated with the data segments and forming new segments (containing the data segments and the additional data) at a larger granularity. The larger the granularity, the less metadata is used to represent the data segments. Therefore, less processing overhead is incurred when managing frequently accessed segments whose metadata is frequently updated.

[0016] The advantages of this disclosure include (but are not limited to) the improved performance of hybrid DIMMs leading to higher quality of service for host systems. For example, caching operations between the first and second memory devices can be performed within the hybrid DIMM. Therefore, when data is transferred from the 3D crossover memory to be stored in the DRAM data cache, the data transfer does not utilize the external bus or interface that the host system also uses for receiving and transmitting write and read operations. Thus, traffic between DRAM and the 3D crossover memory is not limited by the NVDIMM-P protocol, thereby improving hit rates and performance. Furthermore, sector caches and page caches reside in the same memory device, rather than using additional cache components to store sectors. Transfers between the sector cache and page cache can be solely for metadata exchange, further reducing bandwidth usage to and from DRAM. Because DRAM supports both large and small cache lines, it offers the advantage of lower cost (large cache lines) while improving performance (small cache lines). Additionally, the cache manager on the hybrid DIMM can work with any host CPU that supports the NVDIMM-P protocol.

[0017] Figure 1 This description describes an example computing system 100 including a memory subsystem 110 according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination thereof.

[0018] The memory subsystem 110 may be a storage device, a memory module, or a hybrid of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0019] The computing system 100 may be a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), Internet of Things (IoT) enabled device, embedded computer (e.g., a computer contained in a vehicle, industrial equipment or networked business device), or the computing device containing memory and processing devices.

[0020] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1 This describes an example of a host system 120 coupled to a memory subsystem 110. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intermediary component), whether wired or wireless, including, for example, electrical, optical, magnetic, etc.

[0021] Host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). Host system 120, for example, uses memory subsystem 110 to write data to and read data from memory subsystem 110.

[0022] Host system 120 may be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include (but are not limited to) Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect Fast (PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Double Data Rate (DDR) memory bus, Small Computer System Interface (SCSI), Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM slot interfaces supporting Double Data Rate (DDR)), etc. The physical host interface can be used to transfer data between host system 120 and memory subsystem 110. Host system 120 may further utilize an NVM Fast (NVMe) interface to access components (e.g., memory device 130) when memory subsystem 110 is coupled to host system 120 via the physical host interface (e.g., PCIe bus). The physical host interface provides an interface for passing control, address, data, and other signals between memory subsystem 110 and host system 120. Figure 1 The memory subsystem 110 is described as an example. Generally, the host system 120 can access multiple memory subsystems via the same communication connection, multiple individual communication connections, and / or combinations of communication connections.

[0023] Memory devices 130 and 140 may include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be (but are not limited to) random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0024] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND flash memory and in-place write memory, such as three-dimensional crosspoint ("3D crosspoint") memory devices, which are crosspoint arrays of non-volatile memory cells. The crosspoint array of non-volatile memory can be combined with a stackable cross-grid data access array to perform bit storage based on changes in volume resistance. Furthermore, unlike many flash-based memories, crosspoint non-volatile memory can perform in-place write operations, where non-volatile memory cells can be programmed without prior erasing of the non-volatile memory cells. NAND flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0025] Each of the memory devices 130 may include one or more arrays of memory cells. One type of memory cell (e.g., a single-level cell (SLC)) may store one bit per cell. Other types of memory cells (e.g., multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), and five-level cell (PLC)) may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or PLC, or any combination thereof. In some embodiments, a particular memory device may include SLC portions and MLC portions, TLC portions, QLC portions, or PLC portions of memory cells. The memory cells of the memory device 130 may be grouped into pages that can be referenced to logical cells of the memory device used for storing data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0026] Although a non-volatile memory assembly, such as a non-volatile memory cell and a 3D cross-point array of NAND flash memory (e.g., 2D NAND, 3D NAND), is described, the memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), self-select memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0027] The memory subsystem controller 115 (or, for simplicity, controller 115) can communicate with the memory device 130 to perform operations such as reading data, writing data, or erasing data at the memory device 130, and other such operations. The memory subsystem controller 115 may include hardware such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0028] The memory subsystem controller 115 may be a processing device that includes one or more processors (e.g., processor 117) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store operations for performing various processes, operations, logical flows, and controlling the operation of the memory subsystem 110 (including handling communication between the memory subsystem 110 and the host system 120).

[0029] In some embodiments, local memory 119 may include memory registers storing memory pointers, fetched data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although Figure 1 The instance memory subsystem 110 in the present disclosure has been described as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0030] Generally, the memory subsystem controller 115 can receive commands or operations from the host system 120 and can translate these commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. The memory subsystem controller 115 may be responsible for other operations, such as wear leveling, garbage collection, error detection and error correction code (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses (LBAs), namespaces) and physical addresses (e.g., physical MU addresses, physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into command instructions to access the memory device 130 and translate responses associated with the memory device 130 into information for the host system 120.

[0031] The memory subsystem 110 may also include additional circuitry or components not described. In some embodiments, the memory subsystem 110 may include caches or buffers (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) capable of receiving addresses from the memory subsystem controller 115 and decoding the addresses to access the memory device 130.

[0032] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with a memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory subsystem 110 is a managed memory device that includes the original memory device 130 having control logic (e.g., local media controller 135) on a die and a controller (e.g., memory subsystem controller 115) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0033] In one embodiment, memory subsystem 110 includes cache manager 113, which can be used to track and manage data in memory devices 130 and 140. In some embodiments, memory subsystem controller 115 includes at least a portion of cache manager 113. In some embodiments, cache manager 113 is part of host system 120, an application, or an operating system. In other embodiments, local media controller 135 includes at least a portion of cache manager 113 and is configured to perform the functionality described herein. Cache manager 113 can communicate directly with memory devices 130 and 140 via a synchronization interface. Furthermore, data transfer between memory devices 130 and 140 can be completed within memory subsystem 110 without accessing host system 120.

[0034] Memory device 140 may include a data cache that stores data from memory device 130, enabling faster service of future data requests. A cache line is the basic unit of cache storage and may contain multiple bytes and / or data words. Smaller cache line sizes have higher hit rates but require more tag memory than larger cache line sizes. A tag is a unique identifier for a group of data that can be used to distinguish different areas of mapped memory.

[0035] In some embodiments, all data stored by memory subsystem 110 may be stored at memory device 130. Some data stored at memory device 130 may also be stored at a data cache of memory device 140. For example, data determined to be accessed more frequently or more recently by host system 120 may be stored at the data cache to enable faster host access. When host system 120 provides a read request for data stored at the data cache (i.e., a cache hit), the data may be retrieved from the data cache instead of from memory device 130. The bandwidth or capability for retrieving data at the data cache may be faster than the bandwidth or capability for retrieving data at memory device 130.

[0036] The data cache of memory device 140 can be partitioned and includes a sector cache 142 for storing small cache lines (hereinafter referred to as "sectors") and a page cache 144 for storing large cache lines (hereinafter referred to as "pages"). The sector cache 142 and page cache 144 can be managed with different data sizes. The sector cache 142 can utilize a smaller granularity (smaller size), and the page cache 144 can utilize a larger granularity (larger size). In an example, the page size can be 2 kilobytes, and the sector size can be 64 bytes. A page can contain one or more sectors. The page cache 144 may require less metadata to manage data (e.g., only a single valid bit for the entire page) and utilize a larger data size. The smaller data size of the sector cache 142 may require a larger amount of metadata (e.g., a larger number of valid bits and / or dirty bits, tags, etc.). Pages in the page cache 144 can be organized into one or more groups. In an example, a page group contains 24 pages. Similarly, sectors in sector cache 142 can be organized into one or more groups. In this example, the sector group contains 16 sectors.

[0037] Memory device 130 can store and manage data in a small granularity, similar to a sector cache. For example, data can be stored in memory device 130 at a data payload size, which may include one or more sectors in sector cache 142. Therefore, data can be transferred between memory device 130 and sector cache 142 at data payload sizes (e.g., one or more sectors at a time).

[0038] In sector cache 142, the metadata associated with a "page" in sector cache 142 (referred to herein as a "sector group") may include a validity bit for each sector to indicate whether the sector contains valid data (e.g., whether the cache line associated with the sector is allocated for transfer (invalid) or to receive transfer (valid)). Additionally, the metadata may include a dirty bit for each data payload in the sector group, allowing determination of whether a data payload has been modified in sector cache 142 and therefore needs to be written back to memory device 130. Thus, the metadata associated with the sector group can be used to track and manage each sector in sector cache 142. The sector group metadata may also contain heuristic fields that help inform cache retention and prefetching policies.

[0039] Similar to sector cache 142, metadata can be associated with each page in page cache 144 to manage the corresponding page. For example, the metadata associated with a page in page cache 144 may include a single valid bit and a single dirty bit, since page cache 144 is managed at the page level. Additional metadata can be associated with each page to determine eviction procedures in other management tasks. When cache manager 113 determines that a group of sectors in sector cache 142 will be moved to page cache 144 (e.g., because it is frequently accessed), cache manager 113 can fill the remaining portion of the pages in sector cache 142 with the corresponding sector / data payload from memory device 130. Once the pages are filled with the remaining sectors in the sector group, rather than transferring data between caches, the metadata associated with the pages in which the sectors reside can be copied to the page cache metadata. For example, cache manager 113 can identify pages in page cache 144 according to an eviction policy, and then swap the metadata (i.e., addresses) of the pages in page cache with the metadata of the pages in sector cache 142. Thus, no data is transferred, but pages can be switched between page-level management (e.g., in page cache 144) and sector-level management (e.g., in sector cache 142) within the data cache.

[0040] Specifically, cache entries can be created when cache lines are copied from memory device 130 to memory device 140 (e.g., sector cache 142 or page cache 144). A cache entry may contain copied data and the memory location of the copied data (e.g., a tag memory entry). Tag memory entries can be used to track sectors, a group of sectors (e.g., a sector group), and / or pages. Sectors within a sector group can be tracked using a single tag memory entry to reduce the amount of tag memory required by sector cache 142.

[0041] Each page tag memory entry may contain a tag (e.g., one or more host address bits) and associated page metadata. The associated page metadata may contain a dirty bit, a valid bit, LRU (Least Recently Accessed) data, etc. The dirty bit can be used to indicate whether the page has data inconsistent with non-volatile memory (e.g., memory device 130). The valid bit can be used to indicate whether the page is valid (e.g., whether the cache line associated with the page is allocated for eviction (invalid) or received for eviction (valid)). The LRU data may contain an LRU value and can be used to indicate whether the page has been least recently accessed by the host system 120. For example, when a page is accessed, the LRU value for that page may be set to a predetermined value (e.g., 24). The LRU value may be reduced by an amount (e.g., reduced by 1) for every other page in the page cache 144 or for every other page in a set of pages. The LRU data can be used for eviction procedures. The cache manager 113 can use page tag memory entries and / or page metadata to track and manage each page in the page cache 144.

[0042] Each sector-tagged memory entry may contain a tag (e.g., host address bits) and associated sector metadata for the sector or sector group. The sector metadata associated with a sector in the sector group may contain a valid bit for each sector to indicate whether the sector is a valid data slice. The sector group metadata may further contain a dirty bit for each data payload in the sector group, allowing determination of whether a data payload has been modified in the sector cache. The sector group metadata may further contain LRU data for the eviction process, indicating that the sector has been least recently accessed by the host. The sector group metadata may also contain heuristic fields that help inform cache retention and prefetching policies. Cache manager 113 may use sector-tagged memory entries and / or sector metadata to track and manage each sector and sector group in sector cache 142.

[0043] In one example, sector cache 142 may use 32 valid bits to indicate which sectors in a sector group are valid. In another example, sector cache 142 may use 16 dirty bits to indicate a dirty condition for every two sectors or per sector pair. When a sector is about to be evicted (i.e., dirty), the valid bit of the other sector in the sector pair can be checked. If it is set, then the other sector can also be evicted. Two sectors can be read from memory device 130. If the valid bit of the other sector in the same sector pair is not set, then both sectors can be written to memory device 140. Otherwise, only the sector that is being filled can be written. In some embodiments, cache manager 113 may use heuristics to indicate the number of sector accesses.

[0044] In some embodiments, page metadata may be associated with each page in page cache 144 to manage each page. For example, page metadata associated with a page in page cache may include a single valid bit and a single dirty bit. Additional metadata may be associated with each page to determine eviction procedures in other management tasks.

[0045] In some embodiments, when host access (e.g., a read or write operation) occurs at the memory subsystem, cache manager 113 can use the host address associated with the access to query the tag associated with each page in page cache 144 and each sector in sector cache 142. If cache manager 113 finds a match in page cache 144 (using page tag memory entry), then the data requested by the host system is in page cache 144. Cache manager 113 can then provide the access (e.g., a read or write) requested by host system 120. If cache manager 113 (using sector tag memory entry) finds a match in sector cache 142, then data can be retrieved or accessed from sector cache 142. Otherwise, any cache miss can be handled by sector cache 142. For example, if a read operation is received and a cache miss occurs (i.e., the data is not in page cache 144 or sector cache 142), then cache manager 113 may evict the sector group based on its own eviction policy. For example, the sector group to be evicted may be the least recently used. Any data with dirty bits may be written back to memory device 130. Cache manager 113 may then retrieve the requested data payload from memory device 130 and replace the evicted sector group in sector cache 142 with the sector group containing the retrieved data payload.

[0046] In some embodiments, when data is in sector cache 142, data access patterns and data access history of sectors can be tracked to determine whether data should be cached in page cache 144 for a longer period. The hit rate of the data cache (both page cache 144 and sector cache 142) can be increased by identifying general access patterns and by aggregating a sufficient amount of data about host access to each sector group in sector cache 142. Cache manager 113 can use the collected access data to determine the temperature of sector groups (e.g., access rate), access patterns of sectors and their corresponding pages, and then select an appropriate strategy to maximize the data cache hit rate. For example, cache manager 113 may include a set of cache management policies to be selected based on the access data collected for the sector cache.

[0047] As discussed above, cache manager 113 may perform an eviction procedure (hereinafter referred to as "eviction") using an eviction mode before data can be stored in sector cache 142. The eviction mode may be sector-based, page-based, or any combination thereof. In sector-based eviction mode, cache manager 113 may select sectors in sector cache 142. In one example, cache manager 113 uses LRU data selection for sectors. If the selected sector contains dirty bits, cache manager 113 may send the sector to non-volatile memory (e.g., memory device 130). In page-based eviction mode, one or more evicted sectors may be sent to page cache 144.

[0048] In some embodiments, a heuristic may be used to determine the eviction mode. A heuristic is a technique or algorithm designed to solve a problem using non-standard methods. In one instance, if the heuristic exceeds a threshold, the eviction mode may be page-based. Otherwise, the eviction mode may be sector-based. In other embodiments, the algorithm may check the number of valid bit sets and the number of dirty bit sets. When the heuristic, the number of valid bit sets, and / or the number of dirty bit sets exceed one or more thresholds, the eviction mode may be page-based. Otherwise, the eviction mode may be sector-based. In some embodiments, cache manager 113 may use a second page cache lookup using the sector eviction address to locate the LRU page to be evicted. If the selected page is dirty, cache manager 113 may first send the entire page to non-volatile memory (e.g., memory device 130). If the page mark memory is divided into two separate segments (e.g., a first segment for a first page set and a second segment for a second page set), a second page cache lookup may be avoided. In some embodiments, cache manager 113 may evict LRU pages when all sectors or pages of a group are used (e.g., are available) and a new page needs to be inserted into the entire group. However, cache manager 113 may move the sector group page cache 144 instead of evicting it when the sector group needs to be evicted but its heuristics indicate that keeping it in the cache may be beneficial. If page cache 144 is full, then cache manager 113 may evict LRU pages.

[0049] A sector can be uniquely associated with a page in a single segment. Depending on the value of the host address bits, one of the two lookup results from two corresponding page groups can be selected as the final page lookup result. The sector to be evicted can have the same index as the sector selected by using the host address. The cache manager 113 can select its corresponding page by using the LSB (least significant byte) of its tag value. Since the two lookup results of the first lookup may already be available after the first lookup, the second lookup result using the sector evictment address can be available at any time by selecting one of the two first page lookup results using the LSB of the sector tag (to be evicted).

[0050] In some embodiments, cache manager 113 may perform a filling operation. In one example, cache manager 113 may determine that a group of sectors in a sector cache should be moved to a page cache. Cache manager 113 may fill the remaining portion of a page in sector cache 142 with corresponding sectors from non-volatile memory (e.g., memory device 130). Once cache manager 113 has filled the page with the remaining sectors from the sector group, cache manager 113 copies the metadata associated with the page in which the sector resides to the page metadata. For example, cache manager 113 may identify a page in page cache 144 based on an eviction pattern and then swap the metadata (i.e., address) of the page in page cache with the metadata of the page in sector cache 142. Thus, no data is moved, but pages can be swapped between page-level management (e.g., page cache 144) and sector-level management (e.g., sector cache 142) within memory device 140.

[0051] In some embodiments, to minimize bandwidth usage when reading non-volatile memory, data is not read from non-volatile memory to fill page cache 144 for page cache lookup misses. Instead, cache manager 113 reads data from sector cache 142 into page cache 144. In one instance, cache manager 113 uses a heuristic algorithm to read data from sector cache 142 into page cache 144 for cache hits. For example, when the total number of sector accesses in a sector group exceeds a threshold, cache manager can move valid sectors to page cache 144 and read invalid sectors from non-volatile memory to fill newly formed pages. Once a page is filled, cache manager 113 can set the page's valid bit to 1, and if any sector in the original sector group is dirty, then the page's dirty bit is set to 1.

[0052] In page eviction mode, valid sectors can be moved to page cache 144. Cache manager 113 can read invalid sectors from non-volatile memory to completely fill newly formed pages (e.g., a fill operation). In addition to the total number of accesses, cache manager 113 can determine the number of valid bit sets and the number of dirty bit sets. In some embodiments, if the number of accesses exceeds a predetermined threshold, and / or the number of valid bit sets exceeds another predetermined threshold, and / or the number of dirty bit sets exceeds yet another predetermined threshold, then cache manager 113 can perform a page fill operation.

[0053] In some embodiments, cache manager 113 may perform a cleaning operation. In an example, to proactively evict sectors and pages (e.g., LRU sectors and pages) before eviction, cache manager 113 may perform a cleaning operation to send any dirty sectors or pages to non-volatile memory when its LRU value is below a threshold. Cache manager 113 may trigger the cleaning operation after the LRU has been updated. In some embodiments, cache manager 113 may use an LRU update algorithm that causes the LRU values ​​to change in a fixed pattern. For example, for sector cache 142, after a reset, all LRU values ​​may be set to zero. After a first access to a first sector in sector cache 142, the LRU value for the first sector may be set (e.g., to 15). After a subsequent access to a second sector in sector cache 142, a second LRU value for the second sector may be set (e.g., to 15), while the first LRU value may be decreased (e.g., set to 14). This process may continue for each subsequent access. When a cleanup operation is enabled by cache manager 113, a threshold (e.g., 4) can be set. When the LRU value of a sector reaches the threshold, cache manager 113 can send the sector to non-volatile memory. It should be noted that a cleanup operation can clean a cache line (e.g., a sector, a page) (e.g., setting the dirty bit from 1 to 0), but will not evict the cache line or change its LRU value.

[0054] In some embodiments, cache manager 113 may use a mapping scheme to store the bandwidth required to move data from sector cache 142 to page cache 144. When data moves from sector cache 142 to page cache 144, a page may be selected first. For a sector line, depending on the LSB (least significant bit) of the sector tag, there may be two possible corresponding page lines. For example, if the LSB of the sector tag of the first sector line is 0, then the first sector line may correspond to the first page line, and if the LSB of the sector tag of the first sector line is 1, then the first sector line may correspond to the second page line; if the LSB of the sector tag of the second sector line is 0, then the second sector line may correspond to the third page line adjacent to the first page line, and if the LSB of the sector tag of the second sector line is 1, then the second sector line may correspond to the fourth page line adjacent to the second page line, and so on. Sector cache lines and page cache lines together may form a page mapping set, where data does not need to be moved, but the pages of the physical memory device 140 for each cache line are interchangeable. To enable page swapping, each tokenized storage entry can have an additional field (e.g., a page index).

[0055] Figure 2 This is a flowchart of an example method 200 for tracking and managing a data cache according to some embodiments of the present disclosure. Method 200 can be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 200 is performed by… Figure 1 The cache manager 113 executes. Although shown in a specific sequence or order, the order of processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0056] Method 200 may involve a first memory device (e.g., memory device 130) and a second memory device (e.g., memory device 140). Memory device 130 may be coupled to memory device 140. Memory device 140 may act as a cache to memory device 130. Memory device 130, memory device 140, and processing logic may be contained within a hybrid dual in-line memory module. The first memory device may be a cross-point array memory device. The second memory device may be DRAM, SDRAM, or any other volatile memory or any combination thereof.

[0057] In operation 210, the processing logic tracks access statistics for data segments stored at memory device 140, said segments having a first granularity. The first granularity may be utilized by sector cache 142. A data segment may comprise one or more sectors, or a group of sectors. Statistics may include the number of accesses to data, the access rate of data (e.g., hit rate or frequency of data access), etc. In some embodiments, the data may be associated with metadata, such as (for example) the number of valid bit groups for each sector or group of sectors, and the number of dirty bit groups for each sector or group of sectors.

[0058] At operation 220, the processing logic determines to update a data segment stored in memory device 140 from a first granularity to a second granularity based on access statistics. The second granularity can be utilized by page cache 144 and can be larger than the first granularity. The processing logic determines to update the data segment from the first granularity to the second granularity when the access statistics meet a threshold criterion. In one example, the processing logic determines that the threshold criterion is met when the total number of lookups meets or exceeds an access count threshold. In another example, the processing logic determines that the threshold criterion is met when the access rate meets or exceeds an access rate threshold. In some embodiments, the processing logic may first evict the least recently used data from page cache 144 and / or sector cache 142 based on an eviction policy.

[0059] At box 230, the processing logic retrieves additional data associated with the data segment from memory device 130. This additional data may include the corresponding sector of the page that is not present in sector cache 142.

[0060] At box 240, the processing logic stores additional data in a second memory device to form a new segment that includes the additional data and a data segment. The new segment may have a second granularity. In this example, the update includes identifying the physical address of the evicted page, identifying the physical address of the new segment, and swapping the physical address of the new segment with the physical address of the least recently used page.

[0061] Figure 3 This is a flowchart of an example method 300 that performs operations in response to page cache misses and sector cache misses according to some embodiments of the present disclosure. Method 300 may be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 300 is performed by… Figure 1The cache manager 113 executes. Although shown in a specific sequence or order, the order of processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0062] At operation 310, in response to a lookup miss in page cache 144 and a lookup miss in sector cache 142, the processing logic may select sectors in sector cache 142 for eviction. Eviction may be based on an eviction policy (e.g., sector-based eviction or page-based eviction). The processing logic may select sectors based on LRU data that meets a threshold criterion. For example, the processing logic may select sectors with the lowest LRU value, or sectors with LRU values ​​below the threshold.

[0063] At operation 320, the processing logic determines whether the selected sector contains dirty bits. Dirty bits can indicate whether the sector has been modified in sector cache 142 and therefore needs to be written back to memory device 130. In response to determining that the selected sector contains dirty bits, the processing logic determines the eviction mode type at operation 330, which can be sector-based eviction or page-based eviction. The eviction mode can be selected by determining whether the heuristic of the sector group associated with the sector meets a threshold criterion, whether the number of valid bit groups in the sector group meets a threshold criterion, whether the number of dirty bits in the sector group meets a threshold criterion, or any combination thereof. For example, the processing logic can determine whether the heuristic, the number of valid bit groups, and / or the number of dirty bit groups exceed a corresponding threshold. If the selected sector does not contain dirty bits, the processing logic proceeds to operation 360.

[0064] In response to determining that the eviction mode type is page-based, the processing logic sends (e.g., copies) the data at the selected sector to page cache 144 at operation 340. In response to determining that the eviction mode type is sector-based, the processing logic sends the data at the selected sector to a non-volatile memory device (e.g., memory device 130) at operation 350.

[0065] At operation 360, the processing logic evicts the selected sector from sector cache 142. At operation 370, the processing logic reads the new sector associated with page cache misses and sector cache misses into sector cache 142. The new sector can be associated with an LRU value for further eviction procedures.

[0066] Figure 4This is a flowchart of an example method 400 for performing a cleaning operation according to some embodiments of the present disclosure. Method 400 may be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 400 is performed by… Figure 1 The cache manager 113 executes. Although shown in a specific sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible. By way of example, Figure 4 Sectors in sector cache 142 will be discussed. However, method 400 can be similarly executed on pages in page cache 144.

[0067] At operation 410, in response to a memory access to sector cache 142, the processing logic may update the LRU value for each sector in the sector cache. The LRU value can be used to indicate whether the host system 120 has recently accessed a page. For example, when accessing a sector, the LRU value for that sector may be set to a predetermined value (e.g., 15). The LRU value for every other sector in sector cache 144 may be reduced by a certain amount (e.g., 1).

[0068] At operation 420, the processing logic can determine whether the LRU value associated with a sector in sector cache 142 meets a threshold criterion. For example, the processing logic can determine whether the LRU value is at or below the threshold.

[0069] At operation 430, in response to determining that a sector contains a dirty bit, the processing logic can copy data from the sector to a non-volatile memory device (e.g., memory device 130). The dirty bit can indicate whether the sector has been modified in sector cache 142.

[0070] At operation 440, the processing logic can clear the dirty bit. In this example, the dirty bit is cleared by setting it from 1 to 0. Note that the sector's LRU value is not reset to its predetermined value.

[0071] Figure 5This is a flowchart of another example method 500 for tracking and managing a data cache according to some embodiments of this disclosure. Method 500 can be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 500 is performed by… Figure 1 The cache manager 113 executes. Although shown in a specific sequence or order, the order of processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0072] At operation 510, the processing logic maintains a set of host data at memory device 130. At operation 520, the processing logic maintains a subset of the host data at memory device 140. Memory device 140 may have lower access latency than memory device 130 and may be used as a cache for memory device 130. Memory device 140 maintains metadata for a first segment of the subset of host data, the first segment having a first size. In this example, the first segment contains sectors.

[0073] At operation 530, the processing logic determines that one or more access statistics of at least one first segment of a subset of host data satisfy a threshold criterion. In one instance, the processing logic may determine that the threshold criterion is satisfied when the total number of lookups exceeds an access count threshold. In another instance, the processing logic may determine that the threshold criterion is satisfied when the access rate exceeds an access rate threshold. In some embodiments, the processing logic may first evict the least recently used data from page cache 144 and / or sector cache 142 based on an eviction policy.

[0074] At operation 540, the processing logic may associate one or more first segments of a subset of the host data together as a second segment. The one or more first segments may contain at least one first segment. The memory device 140 may maintain metadata for the second segment of the host data. The second segment may have a second size. For example, the second segment may be a page.

[0075] Figure 6 An example machine illustrating computer system 600 is described, within which a set of instructions is executable to cause the machine to perform any or more of the methods discussed herein. In some embodiments, computer system 600 may correspond to a host system (e.g., Figure 1The host system 120), which includes or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110), or may be used to perform controller operations (e.g., execute an operating system to perform operations corresponding to...). Figure 1 (Operation of the cache manager 113). In an alternative embodiment, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The computer may operate as a server or client machine in a client-server network environment, as a peer-to-peer machine in a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment.

[0076] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network device, server, network router, switch, or bridge, or any machine capable of executing a set of instructions (sequentially or otherwise) specifying actions to be taken by said machine. Furthermore, while a single machine is described, the term "machine" should also be considered to include any collection of machines that individually or collectively execute a set (or more) of instructions to perform any or more of the methods discussed herein.

[0077] Example computer system 600 includes processing device 602 and main memory 604 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (e.g., synchronous DRAM (SDRAM) or Rambus). The computer system 600 includes DRAM (RDRAM, etc.), static memory 606 (e.g., flash memory, static random access memory (SRAM, etc.), and data storage device 618, which communicate with each other via bus 630. Processing device 602 represents one or more general-purpose processing devices, such as microprocessors, central processing units, or the like. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a processor implementing a combination of instruction sets. Processing device 602 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, or the like. Processing device 602 is configured to execute instructions 626 for performing the operations and steps discussed herein. Computer system 600 may further include a network interface device 608 for communication via network 620.

[0078] Data storage system 618 may include machine-readable storage medium 624 (also referred to as computer-readable medium) on which one or more sets of instructions 626 or software embodying any or more of the methods or functions described herein are stored. During execution of instructions 626 by computer system 600, instructions 626 may also reside wholly or at least partially in main memory 604 and / or processing device 602, which also constitute machine-readable storage medium. Machine-readable storage medium 624, data storage system 618, and / or main memory 604 may correspond to... Figure 1 The memory subsystem 110.

[0079] In one embodiment, instruction 626 includes instructions for implementing the corresponding Figure 1 The cache manager 113 provides functional instructions. Although the machine-readable storage medium 624 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions for machine execution and causing the machine to perform any or more of the methods of this disclosure. Therefore, the term "machine-readable storage medium" should be considered to include (but is not limited to) solid-state memory, optical media, and magnetic media.

[0080] Certain portions of the foregoing detailed description have been presented based on algorithms and symbolic representations of operations on data bits within computer memory. These algorithmic descriptions and representations are the most effective way for those skilled in the art of data processing to communicate the essence of their work to others skilled in the art. Here, an algorithm is generally considered to be a self-consistent sequence of operations that leads to a desired result. These operations are those requiring physical manipulation of physical quantities. Typically, but not necessarily, these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has proven convenient, sometimes primarily for general reasons, to refer to these signals as bits, values, elements, symbols, characters, items, numbers, or the like.

[0081] However, it should be remembered that all these and similar terms should be associated with appropriate physical quantities and are merely convenient labels applied to those quantities. This disclosure may relate to the operation and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) numbers in the registers and memories of the computer system into physical quantities similarly represented as those in the computer system's memory or registers or other such information storage systems.

[0082] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically configured for its intended purpose, or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. This computer program may be stored in a computer-readable storage medium, such as (but not limited to) any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0083] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the programs taught herein, or it may prove convenient to construct more specialized devices to perform the methods. The structures of various such systems will appear as described below. Furthermore, this disclosure is described without reference to any particular programming language. It will be understood that the teachings of this disclosure as described herein can be implemented using various programming languages.

[0084] This invention can be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, said instructions being usable for programming a computer system (or other electronic device) to perform processes according to the invention. The machine-readable medium includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. For example, machine-readable (e.g., computer-readable) media includes machine-readable storage media such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory devices, etc.

[0085] In the foregoing description, embodiments of the invention have been described with reference to specific examples. It will be apparent that various modifications can be made without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be considered illustrative rather than restrictive.

Claims

1. A system comprising: First memory device; A second memory device coupled to the first memory device, wherein the second memory device has a lower access latency than the first memory device and serves as a cache for the first memory device; and A processing device, operatively coupled to the first and second memory devices, to perform operations including: Access statistics of data segments stored in the second memory device are tracked, wherein the segments have a first granularity, and wherein the access statistics include at least one of access rates to one or more of the segments or values ​​indicating multiple accesses to one or more of the segments. In response to the access statistics satisfying a threshold criterion, the data segment stored in the second memory device is updated from the first granularity to the second granularity, wherein the update includes: Retrieve additional data associated with the data segment from the first memory device; and The additional data is stored in the second memory device to form a new segment including the additional data and the data segment, wherein the new segment has the second granularity.

2. The system of claim 1, wherein the first memory device, the second memory device, and the processing device are included in a hybrid dual in-line memory module, and wherein the first memory device is a cross-point array memory device.

3. The system of claim 1, wherein the processing device is configured to perform further operations including: Evict the old segment with the second granularity from the second memory device.

4. The system of claim 3, wherein the processing device is configured to perform further operations including: Identify the physical address of the old segment; Identify the physical address of the new segment; and The physical address of the new segment is swapped with the physical address of the old segment.

5. The system of claim 3, wherein the eviction is based on Least Recently Used (LRU) data.

6. The system of claim 1, wherein determining to update the data stored in the second memory device from the first granularity to the second granularity comprises: The total number of lookups from the access statistics is determined to satisfy a threshold criterion.

7. The system of claim 1, wherein the data segment is associated with at least one of a valid bit or a dirty bit.

8. The system of claim 1, wherein the first memory device comprises a non-volatile memory device, and the second memory device comprises a volatile memory device.

9. A method comprising: A set of host data is maintained at the first memory device of the memory subsystem; A subset of the host data is maintained at a second memory device of the memory subsystem, wherein the second memory device has lower access latency than the first memory device and serves as a cache for the first memory device, and wherein the second memory device maintains metadata for a first segment of the subset of the host data, the first segment having a first size; Determine that one or more access statistics of at least one first segment of the subset of the host data satisfy a threshold criterion, wherein the one or more access statistics include at least one of access rates to one or more of the segments or values ​​indicating multiple accesses to one or more of the segments. and A plurality of first segments of the subset of the host data are associated together as a second segment, the plurality of first segments including the at least one first segment, wherein the second memory device maintains metadata for the second segment of the host data, the second segment having a second size.

10. The method of claim 9, wherein the first memory device, the second memory device, and the processing device are contained within a hybrid dual in-line memory module, and wherein the second memory device is a cross-point array memory device.

11. The method of claim 9, further comprising: Evict the old segment with the second granularity from the second memory device.

12. The method of claim 11, further comprising: Identify the physical address of the old segment; Identify the physical address of the new segment; and The physical address of the new segment is swapped with the physical address of the old segment.

13. The method of claim 11, wherein the eviction is based on least recently used (LRU) data.

14. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing means operatively coupled to a first memory device and a second memory device, perform operations including: Access statistics of data segments stored in the second memory device are tracked, wherein the segments have a first granularity, and wherein the access statistics include at least one of access rates to one or more of the segments or values ​​indicating multiple accesses to one or more of the segments. In response to the access statistics meeting a threshold criterion, the data segment stored in the second memory device is updated from the first granularity to the second granularity, wherein the update includes; Retrieve additional data associated with the data segment from the first memory device; and The additional data is stored in the second memory device to form a new segment including the additional data and the data segment, wherein the new segment has the second granularity.

15. The non-transitory computer-readable storage medium of claim 14, wherein the first memory device, the second memory device, and the processing device are contained within a hybrid dual in-line memory module, and wherein the first memory device is a cross-point array memory device.

16. The non-transitory computer-readable storage medium of claim 14, wherein the processing means is configured to perform the following further operations: Evict the old segment with the second granularity from the second memory device.

17. The non-transitory computer-readable storage medium of claim 16, wherein the processing means is configured to perform the following further operations: Identify the physical address of the old segment; Identify the physical address of the new segment; and The physical address of the new segment is swapped with the physical address of the old segment.

18. The non-transitory computer-readable storage medium of claim 16, wherein the eviction is based on least recently used (LRU) data.

19. The non-transitory computer-readable storage medium of claim 14, wherein the data segment is associated with at least one of a valid bit or a dirty bit.

20. The non-transitory computer-readable storage medium of claim 14, wherein determining to update the data stored at the second memory device from the first granularity to the second granularity comprises: The total number of lookups from the access statistics is determined to satisfy a threshold criterion.

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