Dimm memory module having electronic fuse

Abstract

The present invention relates to a memory module having an electronic fuse which protects devices within the memory module by shutting off excessive current or voltage in an electrical overstress condition in which the excessive current or voltage is applied, the memory module comprising: a memory device array composed of a DDR SDRAM; a register clock driver chip which distributes signals received from a memory controller to the memory device array; a power management integrated circuit chip which distributes and supplies input power to components including the memory device array and an RCD; a serial configuration recognition chip which stores initial device information; and an electronic fuse which shuts off the input power when the input power is under electrical overstress, wherein the memory module may further comprise an electronic fuse integrated package in which the register clock driver chip or the power management integrated circuit chip and the electronic fuse are embedded in a single package.

Description

DIMM memory module including electronic fuse

[0001] The present invention relates to a memory module, and more specifically, to a memory module comprising an electronic fuse that operates to protect devices within the memory module by blocking an electrical overstress condition in which an excessive current or voltage is applied.

[0002] Dynamic Random Access Memory (DRAM) is a volatile memory used to read and write data and program code necessary for computer processors to operate. DRAM memory is widely used in various devices, including personal computers (PCs), laptops, workstations, and servers.

[0003] The commonly used DRAM memory device is SDRAM (Synchronous DRAM), designed to synchronize with the CPU timing of a computer. DDR SDRAM (Double Data Rate SDRAM) is primarily used, which doubles the transfer speed without increasing the clock frequency by configuring it to transmit data on the rising and falling edges of the CPU clock signal. DDR memory has evolved through DDR2, DDR3, DDR4, and DDR5 as it has been improved to operate at lower operating voltages and currents while maintaining faster transfer speeds.

[0004] DDR5 is a standard released in 2021 that supports approximately twice the bandwidth of DDR4 and features faster transfer speeds and lower operating voltages. Characteristic improvements over DDR4 include performance optimization, enhanced channel efficiency, and improved power management. In particular, regarding power management, a significant change is that while it was handled by the computer's motherboard up to DDR4, it is now managed by a PMIC (Power Management IC) integrated directly into the memory module in DDR5. This allows the operating voltage of DDR5 memory devices to be lowered to 1.1V, compared to the 1.2V of DDR4.

[0005] These memory devices are used in the form of modules in which multiple DRAM devices are combined on a single PCB board. DIMM (Dual in-line Memory Module) is a commonly used memory module standard that provides a 64-bit data path by configuring connection pins on both sides of the module. DIMMs are classified into UDIMM (Un-buffered DIMM), RDIMM (Registered DIMM), and FB-DIMM (Fully Buffered DIMM) based on their major architecture, and are also classified into Standard DIMM, SO-DIMM (Small Outline DIMM), Micro-DIMM, etc., based on their size or form factor.

[0006] The present invention aims to provide a memory module comprising an electronic fuse having the function of blocking excessive current when it is applied to the memory module from the outside.

[0007] In addition, the present invention aims to provide a memory module with improved reliability by preventing damage to the memory module from overcurrent or overvoltage.

[0008] In addition, the present invention aims to provide a memory module that can minimize the area of ​​the memory module substrate while incorporating an electronic fuse.

[0009] In addition, the present invention aims to provide a highly reliable memory module by duplicating the electronic fuse embedded in the memory module.

[0010] A DIMM memory module according to the present invention for achieving the aforementioned purpose may include: a memory device array composed of DDR SDRAM; a register clock driver chip that distributes a signal received from a memory controller to the memory device array; a power management integrated circuit chip that distributes and supplies input power to components including the memory device array and the register clock driver chip; a serial configuration recognition chip that stores initial device information; and an electronic fuse that cuts off the input power when the input power is in an electrical transient stress situation.

[0011] In addition, the DIMM memory module may further include an electronic fuse integrated package in which the register clock driver chip or the power management integrated circuit chip and the electronic fuse are embedded in a single package.

[0012] Additionally, the electronic fuse integrated package may include a first die constituting the register clock driver chip or the power management integrated circuit chip, a second die constituting the electronic fuse, a package substrate to which the first die and the second die are combined, and a molding compound that seals the upper surface of the package substrate.

[0013] In addition, the DIMM memory module may include two or more electronic fuses connected in parallel, and the DIMM memory module may include a redundancy control circuit that controls the two or more electronic fuses connected in parallel.

[0014] In addition, the redundancy control circuit may include a monitoring unit that detects power output from two or more electronic fuses connected in parallel, and a control logic unit that operates to switch an electronic fuse connected to an input power source when an electrical overstress state is detected by the monitoring unit.

[0015] In addition, the redundancy control circuit can be configured within the electronic fuse integrated package.

[0016] In addition, another DIMM memory module according to the present invention for achieving the aforementioned purpose comprises: a memory device array composed of DDR SDRAM; a register clock driver chip that distributes a signal received from a memory controller to the memory device array; a power management integrated circuit chip that distributes and supplies input power to components including the memory device array and the register clock driver chip; and an electronic fuse that cuts off the input power when the input power is in an electrically transient stress situation, and the DIMM memory module may further include an electronic fuse integrated package in which the register clock driver chip and the electronic fuse are embedded in a single package.

[0017] In addition, another DIMM memory module according to the present invention for achieving the aforementioned purpose comprises: a memory device array composed of DDR SDRAM; a power management integrated circuit chip that distributes and supplies input power to components including the memory device array; and an electronic fuse that cuts off input power when the input power is in an electrically transient stress situation, and the DIMM memory module may further include an electronic fuse integrated package in which the power management integrated circuit chip and the electronic fuse are embedded in a single package.

[0018] The present invention includes an electronic fuse that cuts off the input power when the input power is in an electrically overstressed state, thereby protecting components within the memory module and increasing the reliability of the product.

[0019] In addition, the present invention allows the electronic fuse to be configured as an integrated chip together with an RCD or PMIC, thereby preventing the waste of substrate area for separate chip placement.

[0020] In addition, the present invention has the effect of preventing problems caused by electronic fuse malfunctions or defects and providing a highly reliable memory module by configuring two or more electronic fuses within the memory module to be connected in parallel and configuring a redundant control circuit to control them.

[0021] FIG. 1 is a schematic drawing illustrating a first surface and a second surface of a memory module substrate according to a preferred embodiment of the present invention.

[0022] FIG. 2 is a schematic diagram illustrating an electronic fuse integrated with a PMIC or RCD in a memory module according to another embodiment of the present invention.

[0023] FIG. 3 is a block diagram schematically illustrating the circuit configuration of a memory module according to a preferred embodiment of the present invention.

[0024] FIG. 4 is a block diagram schematically illustrating an electronic fuse redundancy control circuit in a memory module according to a preferred embodiment of the present invention.

[0025] Various embodiments of the present invention will be described in detail below with reference to the drawings. The embodiments described below may be modified in various ways by those skilled in the art to which the present invention pertains. The embodiments described below are not intended to limit the present invention to such embodiments. The present invention should be understood to include various modifications, substitutions, and equivalents within the scope of the technical concept understood from the entire specification as well as the embodiments described below.

[0026] Expressions such as “include,” “consist of,” and “have” used below should be understood as not excluding additional components or functions.

[0027] Expressions such as “the first…”, “the second…”, “first”, “second”, etc., that may be used below shall not be interpreted as limiting the order or importance of the components unless explicitly stated otherwise.

[0028] Expressions such as “combined” and “connected” used below should be understood to mean that, unless explicitly stated otherwise, they are directly combined or connected, and that other components may exist or be interposed in between.

[0029] In the following use of terms, singular expressions should be understood as not excluding plural expressions unless explicitly stated otherwise.

[0030]

[0031] FIG. 1 schematically illustrates an example of a memory module of the present invention, in which the first surface (a) and the second surface (b) of the memory module are arranged vertically.

[0032] The memory module (1) according to the present invention may include DRAM (Dynamic Random Access Memory), DIMM (Dual In-line Memory Module), and DDR (Double Data Rate) RAM memory. Additionally, the memory module (1) according to the present invention may be implemented as DDR5 (DDR 5th Generation) SDRAM (Synchronous Dynamic Random Access Memory) memory or any other generation of DDR memory. Furthermore, the memory module (1) according to the present invention may be implemented as RDIMM (Registered Dual In-Line Memory Module), UDIMM (Unbuffered Dual In-Line Memory Module), LRDIMM (Load Reduced Dual In-Line Memory Module), FBDIMM (Fully Buffered Dual In-Line Memory Module), and SODIMM (Small Outline Dual In-Line Memory Module).

[0033]

[0034] In the present invention, the memory module (1) includes a substrate (11), a memory device (20), a data buffer (30), a Registered Clock Driver chip (hereinafter “RCD”) (40), a Power Management Integrated Circuit chip (hereinafter “PMIC”) (50), a Serial Presence Detect chip (hereinafter “SPD”) (60), a temperature sensor (70), a connector (80), and an electronic fuse (90). The memory module (1) is connected to a memory controller of a computer device.

[0035]

[0036] The substrate (11) is composed of a printed circuit board (PCB), and each chip constituting the memory module (1) is attached to both sides (first side and second side). The size of the substrate (11) may vary depending on the DDR standard or DIMM type.

[0037]

[0038] The memory device (20) may be composed of, for example, a DDR5 standard DRAM chip. The memory device (20) may be configured in a predetermined number, for example, 20, on the first surface and the second surface of the memory module (1) substrate (11). The 20 memory devices (20) may be spaced apart in the middle and arranged in groups of 10 on the top and 10 on the bottom. A plurality of memory devices (20) are combined to form an array.

[0039]

[0040] The data buffer (30) is configured to buffer the transmission and reception of data between the memory controller and the memory device (20). Depending on the DIMM specification, the data buffer (30) may not be configured in the case of a UDIMM or RDIMM.

[0041]

[0042] The RCD (40) is configured to communicate with the memory device (20), data buffer (30), PMIC (50), SPD (60), and temperature sensor (70). The RCD (40) receives commands, addresses, clock signals, and control signals from the memory controller of the computer device and performs a buffer function that distributes the received signals to the memory device (20). The RCD (40) may be configured as a single semiconductor chip. Depending on the DIMM specification, the RCD (40) may not be configured in the case of a UDIMM.

[0043]

[0044] The PMIC (50) is configured to perform power management for the memory module (1). The PMIC (50) may be configured to expand or contract the voltage input to the memory module (1), perform DC-DC conversion, or perform other power management operations. The PMIC (50) may generate and provide the required power voltage to each component within the memory device (20) or memory module (1) based on the voltage input to the memory module (10). The memory device (20) may operate based on the power voltage provided by the PMIC (50). The PMIC (50) may be composed of a single semiconductor chip. In the case of DDR5, the PMIC (50) may be configured to generate a power voltage of 1.1V based on an input voltage of 12V or 5V and distribute it to each memory device (20). As illustrated, the RCD (40) and the PMIC (50) may be coupled to different sides of the substrate (10).

[0045]

[0046] The SPD (60) may include initial information or device information of the memory module (1), such as the form, configuration, capacity, and execution environment of the memory module (1). When the computer boots up, the memory controller can read device information from the SPD (60) to recognize the memory module (1) and perform control. The SPD (60) may be composed of a single semiconductor chip.

[0047]

[0048] The temperature sensor (70) is used to detect the operating temperature of the memory module (1) and to control it so that it does not overheat.

[0049]

[0050] The connector (80) is used to connect the memory module (1) to the motherboard or other components of a computer device. The connector (80) can be implemented, for example, in the form of pins configured on the bottom of the board (11). The connector (80) can be configured with a total of 288 pins, for example, 144 pins on each side of the board (11).

[0051]

[0052] An electronic fuse (eFuse) (90) operates to protect internal elements of a memory module (1), including a substrate (1) and a memory device (20), by blocking an Electrical Overstress (EOS) of overcurrent or overvoltage when it is applied to the memory module (1). The EOS condition for the memory module (1) may vary depending on the type of DIMM. For example, the EOS condition for an RDIMM may be set based on an input voltage of 12V, while the EOS condition for a UDIMM or SODIMM may be set based on an input voltage of 5V.

[0053]

[0054] In the embodiment of FIG. 1, the electronic fuse (90) is configured as a single individual chip on the second side of the memory module (1). However, the electronic fuse (90) may be integrated with the PMIC (50) or RCD (40) and embedded within a single package. That is, it may be implemented as an integrated chip in the form of a multi-chip package or a multi-die package together with the PMIC (50) or RCD (40).

[0055]

[0056] FIG. 2 illustrates an example of such an integrated chip. Referring thereto, the electronic fuse integrated chip (100) may include a first die (110) composed of a PMIC or RCD, a second die (120) composed of an electronic fuse chip, a package substrate (130), a solder ball (140), and a molding compound (150).

[0057]

[0058] The first die (110) may have the same circuit configuration and function as the PMIC die or RCD die described in the embodiment of FIG. 1. The second die (120) may have the same circuit configuration and function as the aforementioned electronic fuse (90). The first die (110) and the second die (120) are mounted on a single package substrate (130) and encapsulated with a molding compound (150). The molding compound (150) may be, for example, a plastic epoxy resin.

[0059]

[0060] The first die (110) and the second die (120) can be electrically connected to each other. And each of the first die (110) and the second die (120) can be electrically connected to the package substrate (130). Electrical connections between the dies (110, 120) or between the dies (110, 120) and the package substrate (130) can be implemented in various ways, such as wires, bumps, interposers, or redistribution layers. The solder balls (140) can be implemented as a Ball Grid Array (BGA). The solder balls (140) electrically connect the package substrate (130) and the memory module (10) substrate (11).

[0061]

[0062] The electronic fuse integrated chip (100) reduces the need to secure a separate memory module substrate area for the electronic fuse by integrating the electronic fuse chip with the PMIC or RCD. In other words, by integrating the two chips into one, the complexity of the memory module substrate design is reduced, and productivity can be improved by reducing the assembly time.

[0063]

[0064] Since the PMIC and RCD occupy a relatively large area among the chips constituting the memory module (1), excluding the memory device, it is desirable for the electronic fuse to be integrated with either of these two.

[0065]

[0066] FIG. 3 illustrates the circuit configuration of a memory module according to an embodiment of the present invention. Referring thereto, an electronic fuse (90) controls the power (V_in) input from the memory controller (2) of a computer device to the PMIC (50). The PMIC (50) converts the power (V_in) input via the electronic fuse (90) into the voltage (V_dd) required by each component, such as the memory device (20) array and the RCD (40), and supplies it.

[0067]

[0068] The electronic fuse (90) operates to cut off the input power (V_in) when the input power (V_in) is in an electrically overstressed state. The input power (V_in) may be, for example, 12V when the memory module (1) is an RDIMM, or 5V when it is a UDIMM or SODIMM. The electronic fuse (90) operates to protect each component within the memory module (1) in the event of electrically overstress. The memory module (1) according to the present invention includes the electronic fuse (90) to prevent damage to the module and protect each component when excessive current and excessive voltage are applied. Therefore, it provides superior product reliability compared to conventional memory modules.

[0069]

[0070] FIG. 4 is a block diagram schematically illustrating a redundancy control circuit comprising two or more electronic fuses in a memory module according to one embodiment of the present invention.

[0071] Referring to this, the memory module includes two electronic fuses (91, 92) and a redundancy control circuit that controls the connection of these electronic fuses (91, 92). The redundancy control circuit operates by switching the connection to another electronic fuse when a fault occurs in the electronic fuse currently in use connected to the input power supply, thereby maintaining the fuse function.

[0072] As shown, the two electronic fuses (91, 92) are connected in parallel.

[0073] The redundancy control circuit includes a monitoring unit (93) that detects power output from electronic fuses (91, 92) connected to an input power source, and a control logic unit (94) that controls the input power to each of the two electronic fuses (91, 92). When the redundancy control circuit detects an electrical overstress state from the monitoring unit (93), it determines that the electronic fuse (91, 92) connected to the input power source (V_in) is malfunctioning or defective, and switches the electronic fuse connected to the input power source to another one. The redundancy of the electronic fuses maintains the fuse function to prevent failure of the memory module and ensures high reliability.

[0074] In this embodiment, two electronic fuses are used as an example in the redundancy control circuit, but the electronic fuses may be configured with three or more as needed. Also, as shown, the redundancy control circuit may be configured within an electronic fuse integrated chip (100).

[0075] <Explanation of Drawing Symbols>

[0076] 1 : Memory module

[0077] 11 : Substrate

[0078] 20 : Memory device

[0079] 30: Data buffer

[0080] 40 : RCD

[0081] 50 : PMIC

[0082] 60 : SPD

[0083] 70: Temperature sensor

[0084] 80 : Connector

[0085] 90: Electronic fuse

[0086] 93 : Monitoring Department

[0087] 94: Control Logic Section

[0088] 100: Electronic fuse integrated chip

[0089] 110 : 1st die

[0090] 120 : 2nd Die

[0091] 130: Package substrate

[0092] 140 : Solder ball

[0093] 150 : Molding Compound

[0094] The present invention can be widely used in industrial fields such as memory modules including DRAM elements, storage devices, and electronic devices.

Claims

1. Memory device array composed of DDR SDRAM; A register clock driver chip that distributes signals received from a memory controller to the memory device array; A power management integrated circuit chip that distributes and supplies input power to components including the memory device array and the register clock driver chip; Serial configuration recognition chip that stores initial device information; An electronic fuse that cuts off the input power when the input power is under electrical overstress; and A DIMM memory module comprising an electronic fuse integrated package in which the register clock driver chip or the power management integrated circuit chip and the electronic fuse are embedded in a single package.

2. In Paragraph 1, The above electronic fuse integrated package comprises a first die constituting the register clock driver chip or the power management integrated circuit chip, and The second die constituting the above electronic fuse, and A package substrate to which the first die and the second die are combined, and A DIMM memory module comprising a molding compound that seals the upper portion of the package substrate.

3. In Paragraph 1, The above DIMM memory module has two or more of the above electronic fuses connected in parallel, and The above DIMM memory module is a DIMM memory module further comprising a redundancy control circuit that controls the two or more electronic fuses connected in parallel.

4. In Paragraph 3, The above-described redundancy control circuit is a DIMM memory module comprising a monitoring unit that detects power output from two or more electronic fuses connected in parallel, and a control logic unit that operates to switch an electronic fuse connected to an input power supply when an electrical transient stress state is detected by the monitoring unit.

5. In Paragraph 3, The above redundancy control circuit is a DIMM memory module configured within the above electronic fuse integrated package.

6. Memory device array composed of DDR SDRAM; A register clock driver chip that distributes signals received from a memory controller to the memory device array; A power management integrated circuit chip that distributes and supplies input power to components including the memory device array and the register clock driver chip; An electronic fuse that cuts off the input power when the input power is under electrical overstress; and A DIMM memory module comprising an electronic fuse integrated package in which the register clock driver chip and the electronic fuse are embedded in a single package.

7. Memory device array composed of DDR SDRAM; A power management integrated circuit chip that distributes and supplies input power to components including the memory device array; An electronic fuse that cuts off the input power when the input power is under electrical overstress; and A DIMM memory module comprising an electronic fuse integrated package in which the above-mentioned power management integrated circuit chip and the above-mentioned electronic fuse are embedded in a single package.

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