Electric circuit

Abstract

This electric circuit, to which radio waves can be input, comprises: a first terminal; a first connection point; a second connection point; a third terminal; a capacitor connected to the first terminal and the first connection point; a first diode; a second diode; and an overvoltage protection element. A cathode of the first diode is connected to the first connection point. An anode of the first diode is connected to the first terminal. A cathode of the second diode is connected to the second connection point. An anode of the second diode is connected to the first connection point. The overvoltage protection element is connected to the second connection point. The overvoltage protection element is connected to the third terminal.

Description

Electric circuit

[0001] This disclosure relates to an electric circuit.

[0002] In recent years, wireless power transfer (WPT) has been used in various fields. By utilizing WPT, problems such as the burden, breakage, and maintenance of wiring can be avoided compared to the case of wired power transfer.

[0003] Patent Document 1 discloses a technique for providing means to prevent the failure of a rectenna.

[0004] Japanese Patent Application Laid-Open No. 2015-192484

[0005] In the electric circuit of a wireless power receiving device, there is a problem that a device connected to a second terminal cannot be protected. Therefore, this disclosure has been made to solve the above problems, and its object is to provide a technique for protecting a device connected to the second terminal of an electric circuit.

[0006] An electrical circuit capable of receiving radio waves, comprising a first terminal, a first connection point, a second connection point, a third terminal, a capacitor connected to the first terminal and the first connection point, a first diode, a second diode, and an overvoltage protection element, wherein the cathode of the first diode is connected to the first connection point, the anode of the first diode is connected to the first terminal, the cathode of the second diode is connected to the second connection point, the anode of the second diode is connected to the first connection point, the overvoltage protection element is connected to the second connection point, and the overvoltage protection element is connected to the third terminal. In an electrical circuit capable of receiving radio waves, the circuit comprises a first terminal, a second terminal, a capacitor connected between the first terminal and the second terminal, and a diode connected in parallel with the capacitor. No overvoltage protection element is connected between the first terminal and the capacitor. This suppresses the adverse effect on the output voltage on the second terminal side due to the parasitic capacitance of the overvoltage protection element (ESD protection element), while also suppressing the output of overvoltages such as ESD (Electrostatic Discharge) and EOS (Electric Over Stress) from the antenna to the second terminal. The device connected to the second terminal can be protected without a complex circuit configuration.

[0007] According to this disclosure, a device connected to a second terminal connected to a second connection point of an electrical circuit can be protected.

[0008] This is a diagram showing the overall configuration of the WPT system. This is a block diagram showing an example configuration of a power transmission device and a power receiving device. This is a block diagram showing the functional configuration of the first information processing device. This is a block diagram showing the functional configuration of the second information processing device. This is a block diagram showing the functional configuration of an electrical circuit (first embodiment). This is a cross-sectional view of an electrical circuit (first embodiment). This is a block diagram showing the functional configuration of an electrical circuit (second embodiment). This is a cross-sectional view of an electrical circuit (second embodiment). This is a block diagram showing the functional configuration of an electrical circuit (third embodiment). This is a first cross-sectional view of an electrical circuit (third embodiment). This is a second cross-sectional view of an electrical circuit (third embodiment). This is a block diagram showing the functional configuration of an electrical circuit (fourth embodiment). This is a circuit diagram showing the functional configuration of an overvoltage protection element. This is a block diagram showing the basic hardware configuration of computer 90.

[0009] The embodiments of this disclosure will be described below with reference to the drawings. In all the drawings illustrating the embodiments, common components are denoted by the same reference numerals, and repeated explanations are omitted. The following embodiments are not intended to unduly limit the content of this disclosure as described in the claims. Not all components shown in the embodiments are necessarily essential components of this disclosure. Also, each drawing is a schematic diagram and is not necessarily a strict illustration.

[0010] <1. Overall System Configuration Diagram> Figure 1 is a diagram showing the overall configuration of the WPT system 1 according to this embodiment.

[0011] The WPT system 1 shown in Figure 1 comprises, for example, a transmitter 100, a receiver 200, a first information processing device 300, and a second information processing device 400. The WPT system 1 shown in Figure 1 is used, for example, in a building or a factory. The connection between the transmitter 100 and the first information processing device 300, and the connection between the first information processing device 300 and the second information processing device 400, may be wired or wireless.

[0012] Figure 1 shows an example where the WPT system 1 includes three transmitters 100, but the number of transmitters 100 included in the WPT system 1 is not limited to three. The WPT system 1 may include two or fewer transmitters 100, or four or more transmitters 100.

[0013] Figure 1 shows an example where the WPT system 1 includes seven receivers 200, but the number of receivers 200 included in the WPT system 1 is not limited to seven. The number of receivers 200 included in the WPT system 1 may be six or fewer, or eight or more.

[0014] In this specification, the transmitter 100 is a (power) transmitter 100 in the sense of transmitting power wirelessly, and similarly, the receiver 200 is a (power) receiver 200 in the sense of receiving power wirelessly. As will be described later, the receiver 200 may transmit information about the state of the receiver 200 or information about measurement results from sensors as a data signal to the transmitter 100, and the transmitter 100 may receive such a data signal. In this case, the transmitter 100 functions as a receiver that receives a data signal, and the receiver 200 functions as a transmitter that transmits a data signal.

[0015] Figure 1 shows an example in which the WPT system 1 includes two first information processing devices 300, but the number of first information processing devices 300 included in the WPT system 1 is not limited to two. The WPT system 1 may include one first information processing device 300, or it may include three or more.

[0016] The transmitter 100 transmits, for example, a power supply signal or a data signal to the receiver 200. The transmitter 100 transmits a power supply signal to the receiver 200 using, for example, radio waves in the 920 MHz band. The transmitter 100 transmits a data signal to the receiver 200 using, for example, radio waves in the 2.4 GHz band. The transmitter 100 may also transmit the data signal using radio waves in the 920 MHz band.

[0017] The transmission signal transmitted from the transmitter 100 may, for example, be a continuous wave (CW) with a predetermined power. The frequency band of the transmission signal is, for example, a 920 MHz band, taking into account the distance between the transmitter 100 and the receiver 200. If the frequency band is higher than the example frequency band, the receiver 200 may not be able to receive the predetermined power necessary for operation unless the distance between the transmitter 100 and the receiver 200 is shortened. Therefore, an appropriate frequency band can be determined by considering a practical range (for example, a distance of a few meters between the transmitter 100 and the receiver 200).

[0018] In this case, the laws of the country where the WPT system 1 is installed may impose restrictions on the intermittent transmission of power signals with a specified power level. For example, if the power signal from transmitter 100 falls under the provisions for radio stations as defined in Japan's Radio Law (regardless of whether a license is in place), it may be necessary to provide a certain pause period for the power signal in accordance with the Radio Law. In this case, considering it over a certain time axis, the power signal cannot be considered a continuous wave. However, it is important to provide a pause period, and since this pause period only needs to be short, the power signal transmitted from transmitter 100 can be considered a nearly continuous wave. The ratio of the power signal duration to the pause period should be such that the power signal transmitted from transmitter 100 can be considered a nearly continuous wave, as described above. For example, the pause period is about 1 / 50 to 1 / 100 of the power signal duration.

[0019] The transmitter 100 may, for example, supply power to one receiver 200, or to multiple receivers 200. The transmitter 100 may, for example, transmit a data signal to one receiver 200, or to multiple receivers 200. The transmitter 100 may, for example, transmit the same data signal as other transmitters 100, or transmit a different data signal from other transmitters 100. The transmitter 100 may, for example, transmit a predetermined command signal as a data signal to the receiver 200, or transmit a pre-set signal as a data signal to the receiver 200.

[0020] The transmitter 100 receives, for example, a data signal transmitted from the receiver 200. The transmitter 100 may receive a data signal transmitted from one receiver 200, or it may receive data signals transmitted from multiple receivers 200. The transmitter 100 transmits the data signal transmitted from the receiver 200 to the first information processing device 300. The transmitter 100 transmits information regarding the state of the transmitter 100 to the first information processing device 300.

[0021] The receiver 200 receives, for example, a power supply signal or a data signal transmitted from the transmitter 100. If the receiver 200 has, for example, a power storage unit, it converts the power supply signal transmitted from the transmitter 100 into power and stores the converted power in the power storage unit. If the receiver 200 has, for example, a predetermined sensor, it converts the power supply signal transmitted from the transmitter 100 into power and drives the sensor with the converted power.

[0022] The receiver 200 transmits, for example, information regarding the status of the receiver 200 or information regarding measurement results from sensors to the transmitter 100 as a data signal.

[0023] The first information processing device 300 is an information processing device that monitors the operation of the transmitter 100 and receiver 200 housed in the WPT system 1. For example, the first information processing device 300 determines whether the transmitter 100 or the receiver 200 is in a preset state based on information about the status of the transmitter 100 and the receiver 200 transmitted from the transmitter 100. If it determines that the transmitter is in a preset state, the first information processing device 300 transmits predetermined information to the second information processing device 400.

[0024] Furthermore, the first information processing device 300 stores information about the transmitter 100 and receiver 200 housed in the WPT system 1. For example, the first information processing device 300 stores information about the status of the transmitter 100 and receiver 200 transmitted from the transmitter 100 in a storage unit provided in the first information processing device 300.

[0025] Furthermore, the first information processing device 300 controls the operation of the transmitter 100, which is housed in the WPT system 1. For example, the first information processing device 300 transmits a predetermined instruction or information to the transmitter 100.

[0026] Furthermore, the first information processing device 300 controls the operation of the second information processing device 400.

[0027] The second information processing device 400 is, for example, an information processing device operated by the administrator of the WPT system 1. When the second information processing device 400 receives a notification from the first information processing device 300 that the transmitter 100, receiver 200, or both thereof, which are connected to the WPT system 1, are in a predetermined state, it informs the user that the transmitter 100, receiver 200, or both thereof are in a predetermined state.

[0028] Furthermore, the second information processing device 400 analyzes the information regarding the status of the transmitter 100 and receiver 200 stored in the first information processing device 300 and presents predetermined information to the user. The predetermined information includes, for example, the following: • Information regarding the placement of the transmitter 100 • Information regarding the placement of the receiver 200 • Information regarding power consumption • Information regarding energy consumption

[0029] <1.1 Transmitter and Receiver Configuration> Figure 2 is a block diagram showing an example configuration of the transmitter 100 and receiver 200 shown in Figure 1. As shown in Figure 2, the transmitter 100 and receiver 200 are separated from each other by a predetermined distance, for example. For example, the transmitter 100 and receiver 200 are installed at a distance of several meters from each other. Specifically, for example, the transmitter 100 is fixed and installed at a predetermined high position indoors, for example, on the ceiling or wall. The receiver 200 is installed in a predetermined device indoors or placed near a device that requires power supply. The receiver 200 may also be carried by the user. The transmitter 100 transmits a power supply signal to the receiver 200 using radio waves at a predetermined frequency, for example, in the 920 MHz band. The receiver 200 converts the power supply signal transmitted from the transmitter 100 into power, and either charges the receiver with the converted power or supplies the converted power to a predetermined device.

[0030] The transmitter 100 includes, for example, an oscillator 101, a transmitting antenna 102, a microcontroller (controller) 103, a data transceiver 104, and a data transceiver antenna 105. The oscillator 101, microcontroller 103, data transceiver 104, data transceiver antenna 105, or at least a combination of these, may be mounted on a PCB (printed circuit board), for example.

[0031] The oscillator 101 generates a signal in a predetermined frequency band, for example, the 920 MHz band. The generated signal may be amplified as needed to remove unwanted frequency components.

[0032] The transmitting antenna 102 is configured to efficiently transmit, for example, radio waves in the 920 MHz band. The transmitting antenna 102 radiates the signal oscillated by the oscillator 101 as a feed signal.

[0033] The microcontroller 103 controls the operation of the transmitter 100. The microcontroller 103 is implemented, for example, by a semiconductor element equipped with an ARM processor. The microcontroller 103 controls, for example, the transmission of radio waves by the transmitting antenna 102.

[0034] The data transceiver 104 performs processing such as converting digital data to analog and modulating analog data. The data transceiver 104 also performs processing such as demodulating the data signal received by the data transmission antenna 105 and digitizing the demodulated data. For example, the data transceiver 104 extracts a predetermined signal from the data signal received by the data transmission antenna 105, converts it to digital data, and transmits it to the microcontroller 103.

[0035] The data transmission antenna 105 is configured to efficiently transmit and receive, for example, radio waves in the 2.4 GHz band. The data transmission antenna 105 radiates data signals supplied from the data transceiver 104. The data transmission antenna 105 also receives data signals transmitted from the receiver 200.

[0036] The receiver 200 includes, for example, a receiving antenna 201, a rectifier circuit 202, a power management unit 203, a power storage unit 204, a microcontroller 205, a data transceiver 206, and a data transmission antenna 207. The receiving antenna 201, the rectifier circuit 202, the power management unit 203, the power storage unit 204, the microcontroller 205, the data transceiver 206, the data transmission antenna 207, or at least a combination of these, may be mounted on, for example, a PCB or FPC (flexible printed circuit board).

[0037] The receiving antenna 201 is configured to efficiently receive, for example, radio waves in the 920 MHz band. The receiving antenna 201 receives the feed signal radiated from the transmitting antenna 102.

[0038] The rectifier circuit 202 rectifies the radio waves received as a power supply signal and converts them into a DC voltage.

[0039] The power management unit 203 manages the DC voltage. For example, the power management unit 203 controls the charging voltage based on the DC voltage. By controlling the charging voltage, the power management unit 203 charges the energy storage unit 204. Also, for example, when the energy storage unit 204 stores more than a predetermined capacity of power, the power management unit 203 supplies the DC voltage to the connected components.

[0040] Furthermore, the power management unit 203 releases the power stored in the energy storage unit 204 in response to control from the microcontroller 205.

[0041] The energy storage unit 204 stores power in response to instructions from the power management unit 203. The energy storage unit 204 is implemented, for example, by a battery or a capacitor. The energy storage unit 204 also releases the stored power in response to instructions from the power management unit 203.

[0042] The microcontroller 205 controls the operation of the receiver 200. The microcontroller 205 is driven by a DC voltage supplied from the power management unit 203 or by power stored in the energy storage unit 204. The microcontroller 205 controls the power management unit 203 to release the power stored in the energy storage unit 204.

[0043] A variety of sensors can be connected to the receiver 200. For example, a thermal sensor, a temperature sensor, a light sensor, a humidity sensor, a vibration sensor, a magnetic sensor, etc. are connected to the receiver 200. Also, a force sensor, a proximity sensor, a gas sensor, an acceleration sensor, a human presence sensor, an infrared sensor, an illuminance sensor, a flow sensor, an electric current sensor, a pressure sensor, etc. may be connected to the receiver 200. The sensors connected to the receiver 200 are driven by, for example, a DC voltage supplied from the power management unit 203 or the power discharged from the power storage unit 204. The microcomputer 205 continuously or intermittently monitors the voltage value at a predetermined part of the receiver 200, the status of the sensors connected to the receiver 200, the information detected by the sensors, etc. The microcomputer 205 transmits the voltage value at a predetermined part of the receiver 200, the status of the sensors connected to the receiver 200, the information detected by the sensors, etc. to the data transceiver 206 as digital data. Note that the sensor may be built in the receiver 200.

[0044] The data transceiver 206 performs processes such as analog conversion of digital data supplied from the microcomputer 205 and modulation of analog data. Also, the data transceiver 206 performs processes such as demodulation of the data signal received by the data transceiver antenna 207 and digitalization of the demodulated data. The data transceiver 206 is driven by, for example, a DC voltage supplied from the power management unit 203 or the power discharged from the power storage unit 204.

[0045] The data transceiver antenna 207 is formed to be able to efficiently transmit and receive radio waves in the 2.4 GHz band, for example. The data transceiver antenna 207 radiates the data signal supplied from the data transceiver 206. Also, the data transceiver antenna 207 receives the data signal transmitted from the transmitter 100. For example, the data transceiver antenna 207 is driven by, for example, a DC voltage supplied from the power management unit 203 or the power discharged from the power storage unit 204.

[0046] <2 Electric Circuit 501> In the present disclosure, the electric circuit 501 that constitutes the rectifier circuit 202, the power management unit 203, and the power storage unit 204 included in the receiver 200 will be described in detail as follows.

[0047] [Electric Circuit 501 (Basic Configuration)] This relates to the electric circuit 501 of a wireless power receiving device (receiver 200). The features of the electric circuit 501 of the wireless power receiving device according to the present disclosure will be described as follows. The electric circuit 501 of the present disclosure is configured as a semiconductor circuit. Specifically, the electric circuit of the present disclosure may be configured as a silicon semiconductor circuit, a compound semiconductor circuit, or a wide bandgap semiconductor circuit. A silicon semiconductor circuit is an integrated circuit fabricated using silicon as a basic material. Specifically, the silicon semiconductor circuit includes two manufacturing processes: bulk CMOS and SOI CMOS. Bulk CMOS is a method of directly forming devices on a single silicon substrate, which has the advantages of a simple manufacturing process and low cost. Also, since heat can be dispersed throughout the entire silicon substrate, it has excellent heat dissipation characteristics. On the other hand, SOI CMOS is a method of forming a thin silicon layer with an insulating layer sandwiched between, which has few parasitic capacitances and excellent high-frequency characteristics. A compound semiconductor circuit is a semiconductor circuit made by combining a plurality of elements other than silicon. Specifically, the compound semiconductor circuit includes GaAs (gallium arsenide) and GaN (gallium nitride). The compound semiconductor circuit is excellent in high-speed operation and high-frequency characteristics compared to a silicon semiconductor. A wide bandgap semiconductor circuit is a circuit using a semiconductor material having a larger bandgap than a conventional silicon semiconductor. Representative materials for the wide bandgap semiconductor circuit include SiC (silicon carbide) and GaN (gallium nitride). Due to the large bandgap, the wide bandgap semiconductor circuit enables high-temperature operation and high-voltage operation. The wide bandgap semiconductor circuit is also excellent in high-frequency characteristics.

[0048] The electric circuit is at least one of a wireless receiving circuit for inputting radio waves, a power conversion circuit for inputting electric waves, an AC-DC conversion circuit for inputting electric waves, and an RF-DC circuit for inputting electric waves. In the present disclosure, mainly, as an example of the electric circuit, an RF-DC circuit capable of inputting electric waves will be described.

[0049] A wireless receiving circuit is a circuit that receives radio waves and processes the radio signals received through the antenna. The wireless receiving circuit consists of elements such as a receiving antenna, a rectifier, and a power management unit. A power conversion circuit is a circuit that converts radio energy received as radio waves into usable power. The power converted by the power conversion circuit is either stored in a power storage unit or supplied to a device. To achieve highly efficient power conversion, it is preferable to design the circuit to minimize the effects of parasitic capacitance. An AC-DC conversion circuit is a circuit that converts high-frequency AC signals into DC signals. The AC-DC conversion circuit uses rectifier diodes and capacitors to convert the input AC signal into DC, enabling a stable power supply. An RF-DC circuit is a circuit that converts radio frequency (RF) signals into DC voltages. The power converted by the RF-DC circuit is either stored in a power storage unit or supplied directly to a device. In this disclosure, the electrical circuit includes the wireless receiving circuit, power conversion circuit, AC-DC conversion circuit, and RF-DC circuit. Furthermore, if an electrical circuit is a wireless receiving circuit, it does not prevent that circuit from being a power conversion circuit, an AC-DC conversion circuit, an RF-DC circuit, etc. In other words, an electrical circuit may include at least two or more of the following circuits: a wireless receiving circuit, a power conversion circuit, an AC-DC conversion circuit, and an RF-DC circuit. For example, it does not prevent an electrical circuit from being both an AC-DC conversion circuit and an RF-DC circuit.

[0050] One embodiment of the electrical circuit according to this disclosure is described below. In an electrical circuit capable of receiving radio waves, the electrical circuit 501 comprises a first terminal (ANTP 511, positive antenna terminal), a second connection point 5011, a third connection point 5012, a third terminal (ANTN 512, negative antenna terminal), a capacitor (C 521) connected to the first terminal (ANTP 511) and the second connection point 5011, a first diode (D_ESD 531, for overvoltage protection), a second diode (D 532B), and a third diode (Voltage Clamp ESD 541, overvoltage protection element), wherein the cathode of the first diode (D_ESD 531) is connected to the second connection point 5011, and the anode of the first diode (D_ESD 531) is connected to the first terminal (ANTP 511), The cathode of the second diode (D532B) is connected to the third connection point 5012, the anode of the second diode (D532B) is connected to the second connection point 5011, the cathode of the third diode (Voltage Clamp ESD541) is connected to the third connection point 5012, and the anode of the third diode (Voltage Clamp ESD541) is connected to the third terminal (ANTN512).

[0051] The first terminal is an antenna input terminal (antenna positive terminal) for inputting radio waves, and the diode is connected in parallel with the capacitor, enabling it to output overvoltage input from the antenna input terminal to the ground output. The second terminal is a circuit output terminal that outputs power to a second circuit different from the electrical circuit, and the capacitor is connected between the antenna input terminal and the circuit output terminal. The third terminal is an antenna input terminal (antenna negative terminal) for inputting radio waves, and the diode is connected in parallel with the capacitor, enabling it to output overvoltage input from the antenna input terminal to the ground output. In this disclosure, for explanatory purposes, the first terminal and the third terminal are described as the antenna positive terminal and the antenna negative terminal, respectively, but the antenna input terminal includes the antenna positive terminal (ANTP, first terminal) and the antenna negative terminal (ANTN, third terminal). Specifically, the electrical circuit 501 includes a capacitor (C521) provided between the first terminal (ANTP 511) and the second terminal (VCC 513) which outputs power received from the first terminal. The electrical circuit 501 includes a diode (D_ESD531) connected in parallel with the capacitor (C521) and capable of outputting an overvoltage input from the first terminal (ANTP511) to the ground output 514. The Voltage Clamp circuit 541 can also protect the circuits connected after VCC513. No overvoltage protection element is connected between the first terminal (ANTP511) and the capacitor (C521). An overvoltage protection element (Voltage Clamp ESD541) is connected between the capacitor (C521) and the second terminal (VCC513).

[0052] The overvoltage protection element (Voltage Clamp ESD541) is directly connected to the transmission path between the capacitor (C521) and the second terminal (VCC513). The overvoltage protection element (Voltage Clamp ESD541) is not directly connected to the transmission path between the first terminal (ANTP511) and the capacitor (C521). The capacitor (C521) is interposed in the transmission path between the first terminal (ANTP511) and the overvoltage protection element (Voltage Clamp ESD541). The diode (D_ESD531) bypasses the capacitor (C521) in the transmission path between the first terminal (ANTP511) and the overvoltage protection element (Voltage Clamp ESD541).

[0053] The overvoltage protection element can output overvoltage to the ground 514 output via the first terminal (ANTP 511), the diode (D_ESD 531), and the overvoltage protection element (Voltage Clamp ESD 541). Specifically, when a positive overvoltage is input to the first terminal (ANTP 511), it becomes forward biased and has the function of releasing current to the ground 514. The overvoltage protection element (Voltage Clamp ESD 541) can protect the device (microcontroller 205, etc.) connected to the second terminal (VCC 513). The overvoltage protection element (Voltage Clamp ESD 541) operates when the input voltage exceeds a predetermined voltage (set voltage), and protects the device (microcontroller 205, etc.) connected to the second terminal (VCC 513) by outputting the input overvoltage to ground 514 without outputting it to the second terminal (VCC 513). The VCC 513 is connected to the power management unit 203, and the power supplied from the ANTP 511 is stored in the energy storage unit 204 via the rectifier circuit 202 (electrical circuit 501 composed of capacitors, diodes, etc.) and the power management unit 203. The power stored in the energy storage unit 204 is supplied to the microcontroller 205, data transceiver 206, data transceiver antenna 207, etc., via the power management unit 203 through a separate path from the one used for storage, to drive the receiver 200. Under normal conditions, the overvoltage protection element (Voltage Clamp ESD 541) maintains a reverse bias state, and in the event of an overvoltage, it becomes forward biased and releases current to ground 514. The overvoltage protection element (Voltage Clamp ESD 541) operates to protect the device (microcontroller 205, etc.) connected to the energy storage unit 204 from overvoltage. Note that the first terminal (ANTP 511) and the third terminal (ANTN 512) may be configured in reverse order if the circuit functions correctly. Specifically, the third terminal (ANTN 512) may be placed in the position of the first terminal (ANTP 511) in this disclosure, and the first terminal (ANTP 511) may be placed in the position of the third terminal (ANTN 512). In this disclosure, overvoltage includes ESD (Electrostatic Discharge), EOS (Electric Over Stress), and the like.Specifically, this includes any electrical signals (voltage, current, radio waves, spatial power) input from antenna 201 that may damage internal circuits and connected devices.

[0054] The overvoltage protection element (Voltage Clamp ESD541) performs substantially the same function as a Zener diode in terms of its operating characteristics. Specifically, the Voltage Clamp ESD541 maintains a reverse bias state and exhibits high impedance during normal operation, but when a certain voltage (clamp voltage) is exceeded, it rapidly transitions to a low impedance state and discharges the excess voltage to ground. Due to these characteristics, it is possible to suppress the voltage of the VCC513 to below a certain value and protect the subsequent circuit. The Voltage Clamp ESD541 has a voltage limiting effect similar to that of a Zener diode circuit and provides equivalent protection. Regardless of the specific circuit configuration, the circuit can be protected from overvoltage due to the sharp characteristic change when the voltage exceeds the clamp level. At the same time, it can also protect the circuit from transient voltage applications such as electrostatic discharge.

[0055] Figure 14 is a block diagram showing the functional configuration of the overvoltage protection element (Voltage Clamp ESD541).

[0056] Figure 14A is a circuit diagram showing a first embodiment of the overvoltage protection element. Figure 14B is a circuit diagram showing a second embodiment of the overvoltage protection element. Figure 14C is a circuit diagram showing a third embodiment of the overvoltage protection element. Each of these is an equivalent circuit diagram of the overvoltage protection element. The overvoltage protection element in Figure 14A comprises a plurality of resistors (5411a, 5411b, 5411c...) connected in series between a second terminal (VCC 513) and ground 514. The overvoltage protection element comprises an NMOS transistor (5411z) whose drain is connected to the second terminal (VCC 513) and whose source is connected to ground 514. The gate of the NMOS transistor (5411z) is connected to a voltage divider point formed by a plurality of resistors connected in series between the second terminal (VCC 513) and ground 514. In this configuration, when the voltage at the second terminal (VCC513) is less than a predetermined voltage value (approximately 3.5V in the diagram), the gate voltage of the NMOS transistor (5411z) falls below the threshold, and the transistor remains in the off state. When the voltage at the second terminal (VCC513) exceeds the predetermined voltage value, the gate voltage exceeds the threshold of the NMOS transistor due to the resistive voltage division, and the transistor turns on. As a result, a low-impedance current path is formed between the second terminal (VCC513) and ground 514, and the excess voltage is discharged to ground. This operation prevents the voltage at the second terminal (VCC513) from rising above a predetermined clamp voltage.

[0057] The overvoltage protection element in Figure 14B includes a Zener diode (5412a) provided in the transmission line connecting the second terminal (VCC 513) and ground 514. The cathode of the Zener diode (5412a) is connected to the second terminal (VCC 513) side, and the anode is connected to ground 514 side. In this configuration, when the voltage at the second terminal (VCC 513) is less than a predetermined breakdown voltage (approximately 3.5V in the figure), the Zener diode maintains a high impedance state, and no current flows between the second terminal (VCC 513) and ground 514. When the voltage at the second terminal (VCC 513) exceeds the predetermined breakdown voltage, the Zener diode (5412a) enters a breakdown state, and current flows from the second terminal (VCC 513) to ground 514. This prevents the voltage at the second terminal (VCC 513) from rising above the breakdown voltage.

[0058] The overvoltage protection element in Figure 14C is provided in the transmission path between the second terminal (VCC 513) and ground 514, and comprises a plurality of capacitors (5413a, 5413b, 5413c, etc.) connected in series. The overvoltage protection element includes an NMOS transistor with its drain connected to the second terminal (VCC 513) and its source connected to ground 514. The gate of the NMOS transistor is connected to a voltage divider point formed by the plurality of capacitors connected in series between the second terminal (VCC 513) and ground 514. In this configuration using a capacitive voltage divider, in the steady state, voltage division is performed according to the capacitance ratio of each capacitor. When the voltage at the second terminal (VCC 513) is less than a predetermined voltage value (approximately 3.5V in the figure), the gate voltage of the NMOS transistor falls below the threshold, and the transistor remains in the off state. When the voltage at the second terminal (VCC 513) exceeds the predetermined voltage value, the gate voltage exceeds the threshold of the NMOS transistor due to the capacitive voltage division, and the transistor turns on. This creates a low-impedance current path between the second terminal (VCC513) and ground 514, and excess voltage is discharged to ground.

[0059] The specific configuration of the electrical circuit 501 of the wireless power receiving device according to this disclosure will be described in the following embodiments.

[0060] [Electrical Circuit 501 (First Embodiment)] Figure 5 is a block diagram showing the functional configuration of the electrical circuit 501 (first embodiment). Figure 6 is a cross-sectional view of the electrical circuit 501 (first embodiment). The electrical circuit 501 (first embodiment) is formed using bulk CMOS. Bulk CMOS is a method of forming a device directly on a single silicon substrate. Compared to SOI CMOS, the manufacturing process is relatively simple and low cost. Compared to SOI CMOS, heat can be dispersed throughout the entire silicon substrate, resulting in superior heat dissipation. Compared to SOI CMOS, there is a large parasitic capacitance between the substrate and the device, which may affect high-frequency characteristics.

[0061] [Basic Configuration of Electrical Circuit 501 (First Embodiment)] The components of the electrical circuit 501 (first embodiment), disclosed in Figures 5 and 6, are described below. ANTP 511 (first terminal) is the positive terminal of the antenna 201 and is the input point for the RF (radio frequency) signal. ANTN 512 (third terminal) is the negative terminal of the antenna 201. VCC 513 is the second terminal (output terminal) and supplies power to the device connected to the circuit. Ground 514 is the ground terminal and is the reference potential point of the circuit. C 521 is a capacitor and is used for rectifying the RF (radio frequency) signal. C_storage 522 is a storage capacitor that stores the rectified power. D_ESD531 is an ESD (Electrostatic Discharge) protection diode that provides protection to C521 from overvoltages such as ESD (Electrostatic Discharge) and EOS (Electric Over Stress). D532A and D532B are rectifier diodes that convert RF (Radio Frequency) signals to DC (Direct Current) voltages and store them in C_storage522. DA_ISO534A and DSub_ISO534B are isolation diodes that electrically isolate D_ESD531 from the PSSUB (Substrate). Voltage Clamp ESD541 is a voltage clamp ESD (Electrostatic Discharge) protection element that protects the circuit from overvoltages. PSUB is a P-type substrate that forms the substrate portion of a semiconductor device. N+ is a highly doped N-type semiconductor region. P+ is a highly doped P-type semiconductor region. P- is a low-doped P-type semiconductor region. STI (Shallow Trench Isolation) is a shallow trench isolation structure that provides electrical isolation between devices.

[0062] [Connection relationship of electrical circuit 501 (first embodiment)] Electrical circuit 501 (first embodiment) includes a second diode (DA_ISO534A) and a third diode (DSub_ISO534B) connected between a first terminal (ANTP511) and a first diode (D_ESD531). Electrical circuit 501 (first embodiment) also includes a fourth diode (D532B) and a fifth diode (D532A). The first, second, and third diodes are formed in a channel region on a silicon substrate. Specifically, ANTP511 (first terminal) is connected to one end of C521. The other end of C521 is connected to the anode of D532B. The anode of D_ESD531 is connected between ANTP511 and one end of C521. The cathode of D_ESD531 is connected between the other end of C521 and the anode of D532B. The anode of D_ESD531 is connected to the first connection point on the transmission line between ANTP511 and C521. The cathode of D_ESD531 is connected to the second connection point on the transmission line between C521 and D532B. The anode of DA_ISO534A is connected between ANTP511 and one end of C521. The cathode of DA_ISO534A is connected between DSub_ISO534B and ANTP511. The cathode of DSub_ISO534B is connected between ANTP511 and one end of C521. The anode of DSub_ISO534B is connected to ANTN512. The anode of D532A is connected to ANTN512. The cathode of D532A is connected between C521 and the anode of D532B. The cathode of D532B is connected to VCC513. One end of C_storage522 is connected to VCC513. The other end of C_storage522 is connected to ground 514. One end of Voltage Clamp ESD541 is connected between the cathode of D532B and VCC513. The other end of Voltage Clamp ESD541 is connected to ground 514.The cathodes of the second diode (DA_ISO534A) and the third diode (DSub_ISO534B) are connected via the first diode (D_ESD531) to a first connection point on the transmission line between ANTP511 and C521.

[0063] [Operation of Electrical Circuit 501 (First Embodiment)] When an RF signal (terminal input signal of ANTP 511, referenced to the terminal voltage of ANTN 512) is input from ANTP 511, this high-frequency signal reaches C 521. Since D_ESD 531 is connected in parallel with C 521, during the positive half-cycle of the RF signal, if C 521 is charged to a value greater than the forward voltage (Vf) of D_ESD 531, it enters a reverse-biased state. As a result, D_ESD 531 does not affect the normal RF signal, and the efficiency of the circuit can be maintained. D532A and D532B function as rectifiers and convert the RF signal to direct current (DC). During the negative half-cycle of the RF signal, D532A conducts and charges C 521. During the positive half-cycle of the RF signal, D532B conducts and charges C_storage 522. When the charging voltage to C521 is less than or equal to the forward voltage (Vf) of D_ESD531, and the ANTP511 voltage rises, current flows through the path of D_ESD531 and D532B, charging C_storage522. This allows for efficient power storage even in low-voltage conditions. The rectified and stored power is supplied to the connected device through the VCC513 terminal. The Voltage Clamp ESD541, connected between VCC513 and ground 514, provides protection in case the output voltage rises excessively.

[0064] The case where a positive overvoltage is input from ANTP 511 will be explained with reference to arrow 51 in Figure 5. When a positive overvoltage is input from ANTP 511, the current is discharged through the path of ANTP 511, D_ESD 531, D532B, Voltage Clamp ESD 541, and ground 514, so the equipment connected to VCC 513 is protected from the overvoltage. This protects the circuit and connected equipment from positive overvoltage. The case where a negative overvoltage is input from ANTP 511 will be explained with reference to arrow 52 in Figure 5. When a negative overvoltage is input from ANTP 511, the current is discharged through the path of ground 514, D532A, and D_ESD 531, so the equipment connected to VCC 513 is protected from the overvoltage. This protects the circuit and connected equipment from negative overvoltage.

[0065] Refer to Figure 6 to explain the operation as a semiconductor circuit. Figure 6 shows a semiconductor device formed on a P-type substrate (PSUB). The N+ region and P+ region are arranged and separated by an STI. DA_ISO534A is a diode that isolates the anode of D_ESD531 from the PSUB in the N+ region. Since the anode (P+) and cathode (N+: N+ region) of DA_ISO534A are short-circuited, no current can flow, and it functions to isolate the anode of D_ESD531 from the PSUB. D_ESD531 is a diode formed between the P+ region and the N+ region. When the RF signal is negative (ANTP is negative), it is reverse-biased and does not affect the rectification function. When the RF signal is positive (ANTP is positive), it is forward biased. However, the cathode voltage of D_ESD531 is normally higher than the anode voltage in circuit operation, so no current flows and it does not affect the rectification function. Also, in situations where the cathode voltage is lower than the anode for some reason, it turns ON when the voltage difference is greater than or equal to the forward bias voltage of D_ESD531, assisting the rectification function. In the event of an overvoltage, it becomes forward biased and performs a protection function. If a negative overvoltage is input from ANTP511, DA_ISO534A becomes forward biased and the excess current is diverted to PSUB. If a positive overvoltage is input from ANTP511, D_ESD531 and D532B become forward biased and the excess current is diverted to VCC513. As a result, the voltage of VCC513 rises, but Voltage Clamp ESD541 performs a protective function by limiting the risen overvoltage to a constant voltage. When a negative overvoltage is input from ANTP511, DA_ISO534A enters a forward-biased voltage limiting state with D532A and reverse-biased (BreakDown) voltage limiting state with D_ESD531, and performs a protective operation by diverting excess current to ANTP511 from ANTN512 or ground 514 (arrow 53 in Figure 5).

[0066] [Electrical Circuit 501 (Second Embodiment)] Figure 7 is a block diagram showing the functional configuration of the electrical circuit 501 (second embodiment). Figure 8 is a cross-sectional view of the electrical circuit 501 (second embodiment). The electrical circuit 501 (second embodiment) is formed using bulk CMOS.

[0067] [Basic Configuration of Electrical Circuit 501 (Second Embodiment)] The components of electrical circuit 501 (second embodiment) differ from those of electrical circuit 501 (first embodiment). Specifically, the difference lies in the fact that the cathodes of DA_ISO534A and DSub_ISO534B are connected to VCC513.

[0068] [Connection relationship of electrical circuit 501 (second embodiment)] Unlike electrical circuit 501 (first embodiment), in electrical circuit 501 (second embodiment), DSub_ISO534B is not connected to the ANTP511 terminal, so it does not become a parasitic capacitance of ANTP511, and the power receiving efficiency is more favorable. ANTP511 (first terminal) is connected to one end of C521. The other end of C521 is connected to the anode of D532B. The anode of D_ESD531 is connected between ANTP511 and one end of C521. The cathode of D_ESD531 is connected between the other end of C521 and the anode of D532B. The anode of DA_ISO534A is connected between ANTP511 and one end of C521. The cathode of DA_ISO534A is connected to VCC513. The cathode of DSub_ISO534B is connected between the cathode of DA_ISO534A and VCC513. The anode of DSub_ISO534B is connected to ANTN512. The anode of D532A is connected to ANTN512. The cathode of D532A is connected between the other end of C521 and the anode of D532B. The cathode of D532B is connected to VCC513. One end of C_storage522 is connected to VCC513. The other end of C_storage522 is connected to ground 514. One end of the Voltage Clamp ESD541 is connected between the cathode of D532B and VCC513. The other end of the Voltage Clamp ESD541 is connected to ground 514.

[0069] [Operation of Electrical Circuit 501 (Second Embodiment)] The operation when a positive or negative overvoltage is input from ANTP 511 is the same as in the first embodiment, and in the electrical circuit 501 (second embodiment), an effective circuit protection function against overvoltage can be realized while achieving efficient RF-DC conversion. The operation when a positive overvoltage is input from ANTP 511 is the same as in the first embodiment, and in the electrical circuit 501 (second embodiment), an effective circuit protection function against overvoltage can be realized while achieving efficient RF-DC conversion. The operation when a negative overvoltage is input from ANTP 511 differs from the first embodiment. In the electrical circuit 501 (second embodiment), when a negative overvoltage is input from ANTP 511, D532A enters a forward bias and D_ESD531 enters a reverse bias (BreakDown) voltage limiting state, and a protection operation is performed to release excess current from ANTN512 or ground 514 to ANTP 511. Unlike the first embodiment, the connection from the ANTP 511 terminal to the cathode of DSub_ISO 534B is eliminated, thus eliminating the parasitic capacitance of DSub_ISO 534B and enabling efficient RF-DC conversion while also providing effective circuit protection against overvoltage. The operation as a semiconductor circuit will be explained with reference to Figure 8. Figure 8 shows a semiconductor device formed on a P-type substrate (PSUB). The operation as a semiconductor circuit differs from that of the electrical circuit 501 (first embodiment). Specifically, when the terminal voltage of ANTP 511 is higher than the forward voltage of D_ESD 531 and DA_ISO 534A than the voltage of VCC 513, the forward bias of D_ESD 531 or DA_ISO 534A is lower, and the device operates to store energy in the capacitor C_storage 522 connected to VCC 513, thereby contributing to improved rectification efficiency. Furthermore, under the condition that the ANTP terminal voltage is negative, the rectification efficiency is greatly improved because, compared to the electrical circuit 501 (first embodiment), the Dsub_ISO534 is a connection that is not visible from the ANTP terminal, thus minimizing the effect of parasitic capacitance.

[0070] [Electrical Circuit 501 (Third Embodiment)] Figure 9 is a block diagram showing the functional configuration of the electrical circuit 501 (third embodiment). Figure 10 is a first cross-sectional view of the electrical circuit 501 (third embodiment). Figure 11 is a second cross-sectional view of the electrical circuit 501 (third embodiment). The electrical circuit 501 (third embodiment) is formed using bulk CMOS.

[0071] [Basic Configuration of Electrical Circuit 501 (Third Embodiment)] Explanation of configurations that overlap with Electrical Circuit 501 (Second Embodiment) will be omitted. Q551A and Q551B are NMOS transistors and provide rectification function in place of diodes D532A and D532B of Electrical Circuit 501 (First Embodiment). Gate Ctrl 552 is a circuit that independently controls the gate voltages of Q551A and Q551B. DBG_ISO 561 is a back gate isolation diode and controls the back gates of Q551A and Q551B. DBG_ISO_Q561A is a back gate isolation diode for Q551A and provides electrical isolation and control between the back gate of Q551A and ground 514. Dsub_ISO_Q561A is a diode between the Isolation N+ of Q551A (DBG_ISO_Q561A cathode) and PSUB, and is a diode for isolating the drain and source of Q551A from PSUB (= ground 513). Dsub_ISO_Q561B is a diode between the Isolation N+ of Q551B (DBG_ISO=Q561C cathode) and PSUB, and is a diode for isolating the drain and source of Q551B from PSUB (= ground 513). DBG_ISO=Q561C is a back gate isolation diode for Q551B, and provides electrical isolation and control between the back gate of Q551B and PSUB (ground 514). Gate565 is the gate electrode of the NMOS transistor and controls the operation of the transistor.

[0072] [Connection relationship of electrical circuit 501 (third embodiment)] The electrical circuit 501 (third embodiment) includes a fourth diode provided between the capacitor and the second terminal, and a fifth diode provided between the capacitor and the output of ground 514. The fourth and fifth diodes are configured as NMOS transistors (Q551B and Q551A). Specifically, ANTP 511 (first terminal) is connected to one end of C521. The other end of C521 is connected to node N1. The anode of D_ESD 531 is connected between ANTP 511 and one end of C521. The cathode of D_ESD 531 is connected to node N1. The anode of DA_ISO 534A is connected between ANTP 511 and one end of C521. The cathode of DA_ISO 534A is connected to VCC 513. The cathode of DSub_ISO534B is connected between the cathode of DA_ISO534A and VCC513. The anode of DSub_ISO534B is connected to ground 514. The anode of DBG_ISO=Q561C is connected to node N1. The cathode of DBG_ISO=Q561C is connected to VCC513. The drain of Q551B (NMOS) is connected to node N1. The source of Q551B is connected to VCC513. The gate of Q551B is connected to Gate Ctrl552. The cathode of DSub_ISO_Q561B is connected between the source of Q551B and VCC513. The anode of DSub_ISO_Q561B is connected to ground 514. The drain of Q551A (NMOS) is connected to ANTN512. The source of Q551A is connected to node N1. The gate of Q551A is connected to Gate Ctrl552. The anode of DSub_ISO_Q561A is connected between the drain of Q551A and ANTN512. The cathode of DSub_ISO_Q561A is connected to the anode of DSub_ISO_Q561A and is connected to ANTN512 and ground 514. Gate Ctrl552 is connected to the gate of Q551A and the gate of Q551B.One end of Voltage Clamp ESD541 is connected to VCC513. The other end of Voltage Clamp ESD541 is connected to ground 514. One end of C_storage522 is connected to VCC513. The other end of C_storage522 is connected to ground 514.

[0073] [Operation of Electrical Circuit 501 (Third Embodiment)] Unlike Electrical Circuit 501 (First Embodiment), Electrical Circuit 501 (Third Embodiment), like Electrical Circuit 501 (Second Embodiment), can suppress the effects of parasitic capacitance while providing overvoltage protection in low-cost bulk processes. When an RF signal is input from ANTP 511, this high-frequency signal reaches C521. Since D_ESD531 is connected in parallel with C521, during the positive half-cycle of the RF signal, if C521 is charged above the forward voltage (Vf) of D_ESD531, it enters a reverse-biased state, which does not affect the normal RF signal and maintains the efficiency of the circuit. Instead of diodes D532A and D532B in Electrical Circuit 501 (First Embodiment), NMOS transistors Q551A and Q551B function as rectifiers, converting the RF signal to direct current (DC). The Gate Ctrl552 circuit independently controls the gate voltages of Q551A and Q551B, setting the Vt voltage at which the MOS turns ON to be lower than the SBD Vf. During the negative half-cycle of the RF signal, Q551A turns ON and charges C521. During the positive half-cycle of the RF signal, Q551B turns ON and charges C_storage522. By controlling the NMOS gate voltage so that IsolationNMOS Vt = approximately 0.1V for SBD Vf = 0.3V, the efficiency gain resulting from the 0.2V difference is improved. DBG_ISO = Q561C causes the back gate potential of Q551B to follow the drain potential. The rectified and stored power is supplied to the connected device through the VCC513 terminal. Voltage Clamp ESD541 is connected between VCC513 and ground 514, providing protection in case the output voltage rises excessively. If a negative overvoltage is input from ANTP511, the current is discharged from ground 514 through the body diode of Q551A and D_ESD531, thus protecting the device connected to VCC513 from overvoltage. If a positive overvoltage is input from ANTP511, the current is discharged from D_ESD531 through the body diode of Q551B, Voltage Clamp ESD541, and ground 514, thus protecting the device connected to VCC513 from overvoltage.

[0074] The operation as a semiconductor circuit will be explained with reference to Figures 10 and 11. Figures 10 and 11 show semiconductor devices formed on a P-type substrate (PSUB). On the P-type substrate (PSUB), N+ and P+ regions separated by STI are formed. Q551B shown in Figure 11 is configured as an NMOS transistor and has an N+ source / drain region in the P-well. Q551A shown in Figure 10 is configured separately as an NMOS transistor. Figure 10 is configured as an NMOS transistor and has an N+ source / drain region in the P-well. DSsub_ISO_Q561B is a diode formed between the N+ region and the PSUB. It isolates the source / drain of Q551B from the PSUB, enabling operation dependent on the VCC513 potential and suppressing parasitic effects. DBG_ISO_Q561A is a diode formed between the P+ region and the N+ region of Q551A. In Figure 11, DBG_ISO = Q561C is a diode formed between the P+ and N+ regions of Q551B, which optimizes the transistor characteristics by making the back gate potential of Q551A follow the drain potential. DSub_ISO_Q561B is a diode formed between the N+ region and PSSUB. It isolates the source / drain of Q551B from PSSUB, enabling operation dependent on the VCC513 potential and suppressing parasitic effects. The gate voltage is controlled by the Gate Ctrl552 circuit and turns on at a Vt voltage lower than the Vf of the SBD. It turns on in the positive half-cycle of the RF signal and charges C_storage522. During normal operation, the RF signal passes through C521, and Q551A and Q551B conduct alternately to perform rectification. If a negative overvoltage is input from ANTP511, the excess current is discharged through the body diode Q551A and D_ESD531. If a positive overvoltage is input from ANTP511, the excess current is discharged through D_ESD531 and the body diode Q551B.

[0075] [Electrical Circuit 501 (Fourth Embodiment)] Figure 12 is a block diagram showing the functional configuration of the electrical circuit 501 (fourth embodiment). Figure 13 is a cross-sectional view of the electrical circuit 501 (fourth embodiment). The electrical circuit 501 (fourth embodiment) is formed using SOI (Silicon-On-Insulator) CMOS. SOI CMOS is a method of forming a thin silicon layer on a silicon substrate with an insulating layer (embedded oxide layer) in between, and then fabricating a device on top of it. The manufacturing process is complex and generally more expensive than bulk CMOS. Because heat conduction is inhibited by the insulating layer, self-heating problems are more likely to occur compared to bulk CMOS. Parasitic capacitance with the substrate is greatly reduced, and even if D532A and D532B are replaced with SOI process CMOS, the structure will basically be ISO2 insulated. As a result, compared to bulk CMOS, parasitic capacitance is eliminated, improving high-frequency characteristics and efficiency.

[0076] [Basic Configuration of Electrical Circuit 501 (Fourth Embodiment)] Electrical circuit 501 (fourth embodiment) is constructed using the SOI (Silicon-On-Insulator) process, is isolated from the PSUB by a BOX (SiO2), and has a process structure that does not have parasitic capacitance between the PSUB substrate and the transistor and diode configuration. Explanation of configurations that overlap with electrical circuit 501 (first embodiment) is omitted. D_ESD531 is an ESD (electrostatic discharge) protection diode added in parallel to C521. Since it is a CAP in parallel with C521 with reverse bias, it has a structure that does not easily affect the circuit operation and efficiency. It provides a function to protect C521 from overvoltages such as ESD (Electrostatic Discharge) and EOS (Electric Over Stress). BOX566 (Buried Oxide) represents the buried oxide layer, a characteristic of the SOI structure. This significantly reduces parasitic capacitance between devices. P- indicates a P-type region within the SOI layer, forming the anode side of D_ESD531. N+ indicates a high-concentration N-type region within the SOI layer, forming the cathode side of D_ESD531. PSUB indicates the P-type substrate at the bottom layer of the SOI structure. It is electrically isolated from the upper device layer by the BOX566 layer. This configuration enables effective overvoltage protection while taking advantage of the benefits of the SOI process. By adding D_ESD531 and modifying Voltage Clamp ESD541, overvoltage protection can be achieved while maintaining the circuit's operating efficiency.

[0077] [Connection Relationship of Electrical Circuit 501 (Fourth Embodiment)] Electrical circuit 501 (fourth embodiment) is formed by a semiconductor process having an insulating layer on a silicon substrate. Specifically, it is formed by an SOI process. For example, electrical circuit 501 (fourth embodiment) is formed by SOI CMOS. In electrical circuit 501 (fourth embodiment), the diode is formed in the silicon layer on the insulating layer. The electrical circuit is formed by a semiconductor process using gallium nitride or silicon carbide, and the diode may be formed in the gallium nitride layer or silicon carbide layer. Even when using gallium nitride or silicon carbide, the basic connection configuration is the same as in the SOI process.

[0078] Specifically, ANTP 511 (first terminal) is connected to one end of C 521. The other end of C 521 is connected to the anode of D 532B. The anode of D_ESD 531 is connected between ANTP 511 and one end of C 521. The cathode of D_ESD 531 is connected between the other end of C 521 and the anode of D 532B. The anode of D 532A is connected to ANTN 512. The cathode of D 532A is connected between the other end of C 521 and the anode of D 532B. The cathode of D 532B is connected to VCC 513. One end of C_storage 522 is connected to VCC 513. The other end of C_storage 522 is connected to ground 514. One end of the Voltage Clamp ESD541 is connected between the cathode of D532B and VCC513. The other end of the Voltage Clamp ESD541 is connected to ground 514. D_ESD531 consists of a P- region (anode side) and an N+ region (cathode side), which are formed on a BOX566 (embedded oxide film) layer. The BOX566 layer electrically isolates the device layer from the PSUB (P-type substrate).

[0079] [Operation of Electrical Circuit 501 (Fourth Embodiment)] When an RF signal is input from ANTP 511, this high-frequency signal reaches C 521 directly. Since D_ESD 531 is connected in parallel with C 521, during the positive half-cycle of the RF signal, if C 521 is charged to a value greater than the forward voltage (Vf) of D_ESD 531, it enters a reverse-biased state. As a result, D_ESD 531 does not affect the normal RF signal, and the efficiency of the circuit can be maintained. D532A and D532B function as rectifiers and convert the RF signal to direct current (DC). During the negative half-cycle of the RF signal, D532A conducts and charges C 521. During the positive half-cycle of the RF signal, D532B conducts and charges C_storage 522. When the charging voltage to C521 is less than or equal to the forward voltage (Vf) of D_ESD531, and the ANTP511 voltage rises, current flows through the path D_ESD531→D532B, charging C_storage522. This allows power to be stored efficiently even in low-voltage conditions (arrow 64 in Figure 12). The rectified and stored power is supplied to the connected device through the VCC513 terminal. Since Voltage Clamp ESD541 is connected between VCC513 and ground 514, it also provides protection in case of excessive voltage rise (overvoltage).

[0080] When a positive overvoltage is input from ANTP 511, refer to arrow 61 in Figure 12 for explanation. When a positive overvoltage (electrostatic discharge, ESD) is input from ANTP 511, the current is discharged through D_ESD 531, D532B, Voltage Clamp ESD 541, and ground 514, thus protecting the equipment connected to VCC 513 from overvoltage. When a negative overvoltage (electrostatic discharge, ESD) is input from ANTP 511, refer to arrow 62 in Figure 12 for explanation. When a negative overvoltage is input from ANTP 511, the current is discharged through ground 514, D532A, and D_ESD 531, thus protecting the equipment connected to VCC 513 from overvoltage. When an overvoltage signal is input between ANTP 511 and ANTN 512, refer to arrow 63 in Figure 12 for explanation. If an excessive signal is input between ANTP 511 and ANTN 512, the current is discharged from D_ESD 531 through D532B, Voltage Clamp ESD 541, and ANTN 512, thus protecting the device connected to VCC 513 from overvoltage. The internal circuitry of electrical circuit 501 is protected.

[0081] The operation as a semiconductor circuit will be explained with reference to Figure 13. Figure 13 shows a semiconductor device in which a BOX566 (embedded oxide layer, SiO2) is formed on a P-type substrate (PSUB). A P- layer (silicon active layer) is formed on the BOX566 layer, and N+ and P+ regions separated by STI (Shallow Trench Isolation) are arranged therein. This structure is called the SOI process. D_ESD531 is a diode formed between the P+ region and the N+ region. It is normally in a reverse bias state with respect to the input signal from ANTP511. In the event of overvoltage, it becomes forward biased and performs a protection function. The SOI structure significantly reduces parasitic capacitance between the device and the substrate. This improves high-frequency characteristics and enhances the efficiency of RF-DC conversion. D532A and D532B function as rectifiers. Depending on the positive and negative half-periods of the RF signal, D532A and D532B alternately conduct, charging C521 and C_storage522. D_ESD531 does not affect normal operation but forms a protection path in case of overvoltage. If a negative overvoltage is input from ANTP511, it is discharged through the path of ground 514, D532A, and D_ESD531, thus protecting the device connected to VCC513 from overvoltage. If a positive overvoltage is input from ANTP511, it is discharged through the path of D_ESD531, D532B, Voltage Clamp ESD541, and ground 514, thus protecting the device connected to VCC513 from overvoltage. Advantages of the SOI structure include improved isolation between devices and reduced parasitic effects. Capacitive coupling with the substrate is reduced, improving high-frequency characteristics.

[0082] <Basic Hardware Configuration of Computer> Figure 15 is a block diagram showing the basic hardware configuration of computer 90. Computer 90 includes at least a processor 901, main memory 902, auxiliary storage 903, and a communication IF 991 (interface). These are electrically connected to each other by a communication bus 921.

[0083] The processor 901 is hardware for executing the instruction set described in the program. The processor 901 consists of an arithmetic unit, registers, peripheral circuits, etc.

[0084] The main memory 902 is for temporarily storing programs and data processed by programs, etc. For example, it is a volatile memory such as DRAM (Dynamic Random Access Memory).

[0085] The auxiliary storage device 903 is a storage device for storing data and programs. Examples include flash memory, HDD (Hard Disc Drive), magneto-optical disk, CD-ROM, DVD-ROM, semiconductor memory, etc.

[0086] A communication interface (IF991) is an interface for inputting and outputting signals for communication with other computers via a network using wired or wireless communication standards. The network consists of various mobile communication systems, such as the Internet, LANs, and wireless base stations. For example, networks include 3G, 4G, and 5G mobile communication systems, LTE (Long Term Evolution), and wireless networks (e.g., Wi-Fi®) that can connect to the Internet via designated access points. When connecting wirelessly, communication protocols include, for example, Z-Wave®, ZigBee®, and Bluetooth®. When connecting via wired connections, the network also includes connections made directly via USB (Universal Serial Bus) cables, etc.

[0087] Furthermore, by distributing all or part of each hardware configuration across multiple computers 90 and connecting them to each other via a network, a computer 90 can be virtually realized. Thus, the concept of computer 90 includes not only a computer 90 housed in a single enclosure or case, but also a virtualized computer system.

[0088] <Basic Functional Configuration of Computer 90> The functional configuration of the computer realized by the basic hardware configuration of computer 90 (Figure 15) is described below. The computer comprises at least one functional unit: a control unit, a memory unit, and a communication unit.

[0089] Furthermore, the functional units of computer 90 can also be realized by distributing all or part of each functional unit across multiple computers 90 interconnected via a network. The concept of computer 90 includes not only a single computer 90 but also a virtualized computer system.

[0090] The control unit is realized when the processor 901 reads various programs stored in the auxiliary storage device 903, loads them into the main memory device 902, and executes processing according to those programs. The control unit can realize various functional units that perform information processing depending on the type of program. In this way, the computer is realized as an information processing device that performs information processing.

[0091] The memory unit is implemented by a main memory 902 and an auxiliary memory 903. The memory unit stores data, various programs, and various databases. The processor 901 can also reserve memory areas corresponding to the memory unit in the main memory 902 or the auxiliary memory 903 according to the program. The control unit can also cause the processor 901 to perform addition, update, and deletion operations on data stored in the memory unit according to the various programs.

[0092] The term "database" refers to a relational database, which is used to manage and associate data sets called tables and masters, which are structured in a tabular format defined by rows and columns. In a database, tables are called tables, masters are called masters, the columns of tables are called columns, and the rows of tables are called records. In a relational database, relationships can be established and linked between tables and masters. Typically, each table and each master has a primary key column to uniquely identify a record, but setting a primary key for a column is not mandatory. The control unit can cause the processor 901 to add, delete, and update records in specific tables and masters stored in the storage unit according to various programs. Furthermore, by storing data, various programs, and various databases in the storage unit, the information processing device and information processing system described in this disclosure can be considered manufactured.

[0093] Furthermore, the databases and masters in this disclosure may include any data structures (lists, dictionaries, associative arrays, objects, etc.) in which information is structurally defined. Data structures also include data that can be considered as data structures by combining data with functions, classes, methods, etc., written in any programming language.

[0094] The communication unit is implemented by the communication IF 991. The communication unit implements the function of communicating with other computers 90 via the network. The communication unit can receive information transmitted from other computers 90 and input it to the control unit. The control unit can cause the processor 901 to perform information processing on the received information according to various programs. The communication unit can also transmit information output from the control unit to other computers 90.

[0095] Furthermore, each of the above-mentioned configurations, functions, processing units, processing means, etc., may be implemented in hardware, in whole or in part, for example, by designing them as integrated circuits. The present invention can also be implemented by software program code that realizes the functions of the embodiment. In this case, a storage medium on which the program code is recorded is provided to a computer, and the processor of that computer reads the program code stored in the storage medium. In this case, the program code read from the storage medium itself realizes the functions of the embodiment described above, and the program code itself and the storage medium on which it is stored constitute the present invention. Examples of storage media used to supply such program code include flexible disks, CD-ROMs, DVD-ROMs, hard disks, SSDs, optical disks, magneto-optical disks, CD-Rs, magnetic tapes, non-volatile memory cards, ROMs, and the like.

[0096] Furthermore, the program code that implements the functions described in this embodiment can be implemented in a wide range of programming or scripting languages, such as assembler, C / C++, Perl, Shell, PHP, and Java®.

[0097] Furthermore, the program code for the software that implements the functions of the embodiment may be distributed via a network and stored in a storage means such as a computer's hard disk or memory, or in a storage medium such as a CD-RW or CD-R, and the computer's processor may read and execute the program code stored in the storage means or storage medium.

[0098] The functions realized by the components described herein may be implemented in a circuit or processing circuitry, including general-purpose processors, application-specific processors, integrated circuits, ASICs (Application Specific Integrated Circuits), CPUs (a Central Processing Unit), conventional circuits, and / or combinations thereof, programmed to realize the described functions. A processor, including transistors and other circuits, is considered a circuit or processing circuitry. A processor may be a programmed processor that executes a program stored in memory. In this specification, circuitry, unit, and means are hardware programmed to realize or perform the described functions. Such hardware may be any hardware disclosed herein, or any hardware known to be programmed to realize or perform the described functions. If such hardware is a processor that is considered a type of circuitry, then such circuitry, means, or unit is a combination of hardware and software used to constitute such hardware and / or processor.

[0099] In this specification, "connection" refers to a relationship in which information, power, signals, or electric and magnetic fields influence each other, regardless of whether or not there is physical contact, and includes not only direct connections but also indirect connections through other elements or materials.

[0100] For example, if circuit element A and circuit element C are connected, and circuit element B is inserted between them, then A and C are considered connected if electrical signal transmission, current flow, or influence via electric and magnetic fields is maintained between A and C. In this specification, “connection” includes the following forms: (1) Conductive connection (“Communicable Connection”) A connection is made if a first connection point and the anode of a diode are conductively connected, and electrical conduction is maintained under certain conditions even if a resistor, capacitor, inductor, switch, or other element is inserted between them. (2) Network connection (“Network Connection”) A connection is made if a first connection point and the anode of a diode belong to the same network, and even if an element is inserted between them, they have an electrical influence on each other. For example, this applies to circuit nodes whose potential is affected, or to circuit paths where impedance matching is considered. (3) Connection as an electrical path ("Electrical Pathway") A connection is defined as a connection when the first connection point and the anode of a diode form an electrical path, regardless of the presence or absence of an intervening element. For example, this includes connections via switching elements in a power supply circuit and path formation within a bridge circuit.

[0101] Furthermore, the definition of connection may differ depending on the type of semiconductor circuit and its operating principle. For example, the concept of connection is applied as follows in bulk CMOS, SOI CMOS, compound semiconductor circuits, and wide-bandgap semiconductor circuits: (1) Connections in CMOS circuits In bulk CMOS, electrical conduction through metal wiring or diffusion regions directly formed on the silicon substrate is defined as a connection. On the other hand, in SOI CMOS, since the silicon layer and the substrate are separated by an embedded oxide layer, coupling due to parasitic capacitance can also be included as a form of connection. (2) Connections in wide-bandgap semiconductor circuits In wide-bandgap semiconductor circuits using SiC or GaN, it is necessary to consider connections via vertical current paths and electron transfer via barrier layers in order to adapt to high voltage and high frequency operation. (3) Connections in high-frequency circuits In high-frequency circuits, not only physical wire connections but also coupling via parasitic inductance and parasitic capacitance, signal transmission by electromagnetic induction, and the effects of resonant circuits may be included. For example, in millimeter-wave circuits, connections via waveguides and antennas are also included.

[0102] In this specification, the definition of "connection" is applied according to the circuit configuration and operating conditions, and is not limited to mere physical conductivity. In a broad sense, coupling via electric and magnetic fields, optical coupling, and electromagnetic coupling can also be included as connections. On the other hand, when defined as a connection in a narrow sense, it may only refer to direct conductivity or specific physical contact. This should be appropriately interpreted according to the embodiments of the present invention.

[0103] In this specification, the phrase "output enabled" is applicable depending on the circuit configuration and operating conditions, and should be interpreted appropriately according to the voltage and current flow and protective actions, as follows:

[0104] In this embodiment, the electrical circuit is configured to appropriately handle the overvoltage input from the first terminal and bypass the current to ground via an overvoltage protection element. (1) Overvoltage bypass function The electrical circuit can clamp the voltage and allow the excess current to flow to ground by operating the overvoltage protection element in response to the overvoltage input from the first terminal. For example, the current generated by the overvoltage is bypassed to ground 514 via the first terminal, diode (D_ESD531), and overvoltage protection element (Voltage Clamp ESD541), thereby suppressing the effect of the overvoltage on the subsequent circuit. (2) Overvoltage clamping function The overvoltage protection element (Voltage Clamp ESD541) protects the device (microcontroller 205, etc.) connected to the second terminal (VCC513) by clamping the input overvoltage to ground 514 without outputting it to the second terminal (VCC513). In this case, if the overvoltage exceeds a certain threshold, the overvoltage protection element turns on and forms a current path to ground. This minimizes the effects of overvoltage and stabilizes the operation of the device. (3) Prevention of effects on downstream circuits The overvoltage protection circuit in this embodiment does not simply output the overvoltage to ground, but prevents the transmission of overvoltage to downstream circuits by limiting the excessive voltage and forming an appropriate current path. This prevents the protected circuit elements from being subjected to high voltage stress and improves the reliability of the entire circuit.

[0105] In this specification, the expression "enable output" should be interpreted appropriately according to the context, depending on the voltage and current flow and protective operation, such as "enable to bypass overvoltage to ground," "enable to clamp overvoltage and release current to ground," "enable to suppress overvoltage and prevent transmission of overvoltage to subsequent circuits," or "enable to channel excess current to ground (in the event of overvoltage)."

[0106] While several embodiments of this disclosure have been described above, these embodiments can be implemented in a variety of other forms, and various omissions, substitutions, and modifications are permitted without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents.

[0107] (Note) The matters described in each of the above embodiments are noted below.

[0108] (Note 1) An electrical circuit capable of receiving radio waves, comprising a first terminal, a first connection point, a second connection point, a third terminal, a capacitor connected to the first terminal and the first connection point, a first diode, a second diode, and an overvoltage protection element, wherein the cathode of the first diode is connected to the first connection point, the anode of the first diode is connected to the first terminal, the cathode of the second diode is connected to the second connection point, the anode of the second diode is connected to the first connection point, the overvoltage protection element is connected to the second connection point, and the overvoltage protection element is connected to the third terminal. This makes it possible to suppress the adverse effect on the output voltage of the second terminal connected to the second connection point due to the parasitic capacitance of the overvoltage protection element (ESD protection element), while also suppressing the output of overvoltages such as ESD (Electrostatic Discharge) and EOS (Electric Over Stress) from the antenna to the second terminal. It is possible to protect the device connected to the second terminal without requiring a complex circuit configuration.

[0109] (Note 2) The electrical circuit is the electrical circuit described in Note 1, which includes at least one of the following: a wireless receiving circuit that receives radio waves, a power conversion circuit that receives radio waves, an AC-DC conversion circuit that receives radio waves, and an RF-DC circuit that receives radio waves.

[0110] (Note 3) The electrical circuit as described in Note 1 or 2, wherein the first terminal is an antenna input terminal for inputting radio waves, and the first diode is connected in parallel with the capacitor, and is capable of outputting an overvoltage input from the antenna input terminal to the ground output.

[0111] (Note 4) The electrical circuit described in Note 3, wherein the second connection point is connected to a circuit output terminal that outputs power to a second circuit different from the electrical circuit, and the capacitor is connected between the antenna input terminal and the circuit output terminal.

[0112] (Note 5) An electrical circuit as described in any of Notes 1 to 4, wherein an overvoltage protection element is connected to the second connection point, and the overvoltage protection element is capable of outputting the overvoltage input from the first terminal to the ground output via the first terminal, the first diode, and the overvoltage protection element. As a result, by placing the overvoltage protection element between the capacitor and the second terminal, the overvoltage from the antenna can be effectively discharged to the ground output. This makes it possible to protect the device connected to the second terminal while suppressing the degradation of the electrical circuit's performance.

[0113] (Note 6) The overvoltage protection element is a Zener diode, as described in any of Notes 1 to 5. This makes it possible to protect the device connected to the second terminal while suppressing a decrease in the performance of the electrical circuit.

[0114] (Note 7) The electrical circuit is an electrical circuit described in any of Notes 1 to 6, configured as a semiconductor circuit. By configuring the electrical circuit as a semiconductor circuit, miniaturization, high integration, and improved mass production are possible. This enables miniaturization and cost reduction of the entire wireless power receiving device.

[0115] (Note 8) The electrical circuit is an electrical circuit described in any of Notes 1 to 7, which is configured as a silicon semiconductor circuit, a compound semiconductor circuit, or a wide-bandgap semiconductor circuit. This makes it possible to realize an electrical circuit with optimal characteristics according to application requirements by selecting various semiconductor materials. Silicon semiconductors offer low cost and high maturity, compound semiconductors offer high-speed operation and high-frequency characteristics, and wide-bandgap semiconductors offer high voltage resistance and high-temperature operation. In particular, by using wide-bandgap semiconductors such as gallium nitride (GaN) and silicon carbide (SiC), excellent performance can be achieved in high-frequency and high-power applications, improving the efficiency and miniaturization of wireless power transmission.

[0116] (Note 9) In an electrical circuit capable of receiving radio waves, the electrical circuit comprises a first terminal, a second terminal, a capacitor connected between the first terminal and the second terminal, and a diode connected in parallel with the capacitor, wherein no overvoltage protection element is connected between the first terminal and the capacitor. This makes it possible to suppress the adverse effect on the output voltage on the second terminal side due to the parasitic capacitance of the overvoltage protection element (ESD protection element), while also suppressing the output of overvoltages such as ESD (Electrostatic Discharge) and EOS (Electric Over Stress) from the antenna to the second terminal. The device connected to the second terminal can be protected without a complex circuit configuration.

[0117] (Note 10) The diode is an electrical circuit as described in Note 9, which is capable of outputting an overvoltage input from the first terminal to the ground output. This allows the overvoltage from the antenna to be effectively discharged to the ground output. This protects the device connected to the second terminal while suppressing a degradation in the performance of the electrical circuit.

[0118] (Note 11) The diode is a first diode, and the electrical circuit includes a second diode and a third diode connected between the first terminal and the first diode, and the electrical circuit is formed using bulk CMOS, with the first diode, the second diode and the third diode formed in a channel region on a silicon substrate, as described in Note 9. This allows for the realization of an electrical circuit at a lower cost compared to the SOI process by using a bulk CMOS process. Furthermore, the addition of the second and third diodes suppresses the adverse effects of parasitic diodes in the bulk process. This makes it possible to provide a low-cost, high-performance electrical circuit.

[0119] (Note 12) The electrical circuit described in Note 11, wherein the outputs of the second and third diodes are connected to an overvoltage protection element and a second terminal. By connecting the outputs of the second and third diodes to an overvoltage protection element and a second terminal, more efficient overvoltage protection is possible while suppressing the effects of parasitic capacitance. This makes it possible to achieve high rectification efficiency in a CMOS structure while suppressing the effects of parasitic elements. The electrical circuit described in Note 10.

[0120] (Note 13) The electrical circuit is as described in Note 11 or 12, comprising a fourth diode provided between the capacitor and the second terminal, and a fifth diode provided between the capacitor and the ground output, wherein the fourth and fifth diodes are configured as NMOS transistors, and the first diode is capable of outputting an overvoltage input from the first terminal to the ground output. By configuring the fourth and fifth diodes as NMOS transistors, the rectification efficiency of the circuit can be improved. NMOS transistors have a lower forward voltage drop compared to conventional diodes, enabling efficient power conversion, especially in low-power wireless power receiving systems. This improves the overall power efficiency of the system, enabling longer-distance wireless power transfer and smaller receiving antennas.

[0121] (Note 14) The electrical circuit is formed by a semiconductor process having an insulating layer on a silicon substrate, and the first diode is an electrical circuit as described in any of Notes 1 to 8, formed on the silicon layer on the insulating layer. By forming the electrical circuit with SOI CMOS, parasitic capacitance can be reduced compared to bulk CMOS. By forming the silicon layer on the insulating layer, capacitive coupling with the substrate is reduced, and high-frequency characteristics are improved. This enables efficient operation in higher frequency bands, improving the performance and miniaturizing wireless power receiving systems.

[0122] (Note 15) The electrical circuit is formed by a semiconductor process using gallium nitride or silicon carbide, and the first diode is an electrical circuit as described in any of Notes 1 to 8, formed in a gallium nitride layer or a silicon carbide layer. This allows for the use of wide-bandgap semiconductor materials such as gallium nitride (GaN) or silicon carbide (SiC), resulting in superior high-frequency characteristics and high breakdown voltage characteristics compared to silicon semiconductors. These materials have high electron mobility and high dielectric breakdown field strength, resulting in low switching losses at high frequencies and high resistance to high voltage and high current. In particular, in wireless power transmission, this leads to improved efficiency during high-frequency operation, miniaturization, and enhanced overvoltage protection. Furthermore, these materials perform well at high temperatures, resulting in less performance degradation due to heat generation and allowing for simplified heat dissipation design. This enables the construction of highly efficient and reliable wireless power receiving systems.

[0123] (Note 16) In the RF-DC circuit of a wireless power receiving device, the RF-DC circuit comprises a capacitor provided between the positive terminal of the antenna and the power supply voltage terminal, and a diode connected in parallel with the capacitor, capable of outputting the overvoltage input from the positive terminal of the antenna to the GND output, and the RF-DC circuit is not connected to an overvoltage protection element between the positive terminal of the antenna and the capacitor. This makes it possible to suppress the adverse effect on the output voltage on the power supply voltage terminal side due to the parasitic capacitance of the overvoltage protection element (ESD protection element), while also suppressing the output of overvoltages such as ESD (Electrostatic Discharge) and EOS (Electric Over Stress) from the antenna to the power supply voltage terminal. The device connected to the power supply voltage terminal can be protected without a complex circuit configuration.

[0124] (Note 17) The RF-DC circuit described in Note 1, wherein an overvoltage protection element is connected between the capacitor and the power supply terminal, and the overvoltage protection element can output the overvoltage to the GND output via the antenna positive terminal, diode, and the overvoltage protection element. As a result, by placing the overvoltage protection element between the capacitor and the power supply terminal, the overvoltage from the antenna can be effectively discharged to the GND output. This makes it possible to protect the device connected to the power supply terminal while suppressing the degradation of the RF-DC circuit's performance.

[0125] (Note 18) The RF-DC circuit is the RF-DC circuit described in Note 1, which is configured as a semiconductor circuit. By configuring the RF-DC circuit as a semiconductor circuit, miniaturization, high integration, and improved mass production capabilities become possible. This enables miniaturization and cost reduction of the entire wireless power receiving device.

[0126] (Note 19) The RF-DC circuit includes a second diode and a third diode connected between the positive terminal of the antenna and the diode, and the RF-DC circuit is formed using bulk CMOS, with the diode, the second diode and the third diode formed in the channel region on the silicon substrate, as described in Note 1. This allows for the realization of an RF-DC circuit at a lower cost compared to the SOI process by using a bulk CMOS process. Furthermore, the addition of the second and third diodes suppresses the adverse effects of parasitic diodes in the bulk process. This makes it possible to provide a low-cost, high-performance RF-DC circuit.

[0127] (Note 20) The RF-DC circuit described in Note 4, wherein the outputs of the second and third diodes are connected to an overvoltage protection element and a power supply voltage terminal. By connecting the outputs of the second and third diodes to the overvoltage protection element and the power supply voltage terminal, more efficient overvoltage protection is possible while suppressing the effects of parasitic capacitance. As a result, high rectification efficiency can be achieved in the CMOS structure while suppressing the effects of parasitic elements.

[0128] (Note 21) The RF-DC circuit is the RF-DC circuit described in Note 4, comprising a fourth diode provided between the capacitor and the power supply voltage terminal, and a fifth diode provided between the capacitor and the GND output, wherein the fourth and fifth diodes are configured as NMOS transistors. By configuring the fourth and fifth diodes as NMOS transistors, the rectification efficiency of the circuit can be improved. Since NMOS transistors have a lower forward voltage drop compared to conventional diodes, efficient power conversion is possible, especially in low-power wireless power receiving systems. This improves the overall power efficiency of the system, enabling longer-distance wireless power transfer and smaller receiving antennas.

[0129] (Note 22) The RF-DC circuit is formed using an SOI process, and the diode is formed in a silicon layer on an insulating layer, as described in Note 1. By forming the RF-DC circuit with SOI CMOS, parasitic capacitance can be further reduced compared to bulk CMOS. By forming the silicon layer on the insulating layer, capacitive coupling with the substrate is reduced, improving high-frequency characteristics. This enables efficient operation in higher frequency bands, leading to improved performance and miniaturization of wireless power receiving systems.

[0130] (Note 23) An electrical circuit capable of receiving radio waves, wherein the electrical circuit comprises a first terminal, a second terminal, a first connection point, a second connection point, a capacitor provided between the first terminal and the second terminal, a first diode connected in parallel with the capacitor, an overvoltage protection element, a second diode, a third diode and a fourth diode, wherein the capacitor is connected to the first connection point and the second connection point, the anode of the first diode is connected to the first connection point, the cathode of the first diode is connected to the second connection point, the overvoltage protection element is not connected between the first terminal and the capacitor, the overvoltage protection element is connected between the capacitor and the second terminal, the cathode of the fourth diode is connected to the second terminal, the anode of the fourth diode is connected to the second connection point, the second diode is connected to the first connection point, the cathode of the third diode is connected to the first connection point, and the anode of the third diode is connected to GND.

[0131] Electrical circuit 501, ANTP 511 (first terminal), ANTN 512 (third terminal), VCC 513 (second terminal), ground 514 (ground terminal), C 521 (capacitor), C_storage 522 (storage capacitor), D_ESD 531 (ESD protection diode), D 532A, D 532B (rectifier diode), DA_ISO 534A, DSub_ISO 534B (isolation diode), Voltage Clamp ESD 541 (voltage clamp ESD protection element), Q 551A, Q 551B (NMOS transistor), Gate Ctrl552 (gate voltage control circuit), DBG_ISO561 (back gate isolation diode), DBG_ISO_Q561A (back gate isolation diode for Q551A), DSub_ISO_Q561B (back gate isolation diode for Q551B), DBG_ISO=Q561C (drain-back gate connection diode for Q551B), Gate565 (gate electrode of NMOS transistor) 565, BOX566 (buried oxide layer) 566

Claims

1. An electrical circuit capable of receiving radio waves, wherein the electrical circuit comprises: a first terminal, a first connection point, a second connection point, a third terminal, a capacitor connected to the first terminal and the first connection point, a first diode, a second diode, and an overvoltage protection element, wherein the cathode of the first diode is connected to the first connection point, the anode of the first diode is connected to the first terminal, the cathode of the second diode is connected to the second connection point, the anode of the second diode is connected to the first connection point, the overvoltage protection element is connected to the second connection point, and the overvoltage protection element is connected to the third terminal.

2. The electrical circuit according to claim 1, wherein the electrical circuit is at least one of the following: a wireless receiving circuit that inputs radio waves; a power conversion circuit that inputs radio waves; an AC-DC conversion circuit that inputs radio waves; and an RF-DC circuit that inputs radio waves.

3. The electrical circuit according to claim 1 or 2, wherein the first terminal is an antenna input terminal for inputting radio waves, and the first diode is connected in parallel with the capacitor and is capable of outputting an overvoltage input from the antenna input terminal to the ground output.

4. The electrical circuit according to claim 3, wherein the second connection point is connected to a circuit output terminal that outputs power to a second circuit different from the electrical circuit, and the capacitor is connected between the antenna input terminal and the circuit output terminal.

5. The electrical circuit according to any one of claims 1 to 4, wherein the overvoltage protection element is connected to the second connection point, and the overvoltage protection element is capable of outputting the overvoltage input from the first terminal to the ground output via the first terminal, the first diode, and the overvoltage protection element.

6. The electrical circuit according to any one of claims 1 to 5, wherein the overvoltage protection element is a Zener diode.

7. The electrical circuit according to any one of claims 1 to 6, wherein the electrical circuit is configured as a semiconductor circuit.

8. The electrical circuit according to any one of claims 1 to 7, wherein the electrical circuit is configured as a silicon semiconductor circuit, a compound semiconductor circuit, or a wide bandgap semiconductor circuit.

9. An electrical circuit capable of receiving radio waves, wherein the electrical circuit comprises: a first terminal; a second terminal; a capacitor connected between the first terminal and the second terminal; and a diode connected in parallel with the capacitor, wherein no overvoltage protection element is connected between the first terminal and the capacitor.

10. The electrical circuit according to claim 9, wherein the diode is capable of outputting an overvoltage input from the first terminal to the ground output.

11. The electrical circuit according to claim 9, wherein the diode is a first diode, the electrical circuit includes a second diode and a third diode connected between the first terminal and the first diode, the electrical circuit is formed of bulk CMOS, and the first diode, the second diode and the third diode are formed in a channel region on a silicon substrate.

12. The electrical circuit according to claim 11, wherein the outputs of the second diode and the third diode are connected to the overvoltage protection element and the second terminal.

13. The electrical circuit according to claim 11 or 12, comprising: a fourth diode provided between the capacitor and the second terminal; and a fifth diode provided between the capacitor and the ground output, wherein the fourth diode and the fifth diode are configured as NMOS transistors; and the first diode is capable of outputting an overvoltage input from the first terminal to the ground output.

14. The electrical circuit is formed by a semiconductor process having an insulating layer on a silicon substrate, and the first diode is formed on a silicon layer on the insulating layer, according to any one of claims 1 to 8.

15. The electrical circuit according to any one of claims 1 to 8, wherein the electrical circuit is formed by a semiconductor process using gallium nitride or silicon carbide, and the first diode is formed in a gallium nitride layer or a silicon carbide layer.

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