PCB structure for improving threading capability of DDR5-dimm

Abstract

The utility model discloses a kind of PCB structure of promoting DDR5-DIMM threading capacity, including PCB board main body, a row of first pin pads is arranged on the PCB board main body, this row first pin pad includes multiple first signal pin pads and multiple first ground pin pads, the inside of one side of each first signal pin pad is opened with a first signal hole tangential to its edge, the outside of one side of the PCB board main body where each first signal pin pad is opened with first signal hole is opened with a first ground hole on the same horizontal line with the first signal hole. The utility model improves threading capacity and signal quality by optimizing the layout of signal hole and ground hole.

Description

Technical Field

[0001] This utility model relates to the field of printed circuit board (PCB) design technology, specifically to a PCB structure that improves the routing capability of DDR5-DIMM. Background Technology

[0002] With the explosive growth of data processing volume and the ever-increasing demands on system operating speed, the performance of the memory subsystem has become one of the key factors affecting the overall performance of a computer system. DDR5-DIMM, as the current mainstream memory module technology, directly relates to whether a computer system can operate efficiently and stably.

[0003] Currently, the common fanout routing method for DDR5-DIMMs involves drilling signal and ground vias on the same side of each signal pin pad and each ground pin pad, with the signal and ground vias in the same row. This routing method significantly impacts the trace throughput of DDR5-DIMMs. Due to the extremely limited space between the two vias, only one signal line can pass through at most, preventing differential lines from being routed according to normal line width and spacing. To achieve connectivity for the differential lines, ground vias are often used. While ground vias provide a physical path for the differential lines to some extent, they disrupt the ideal electromagnetic environment of the differential lines, leading to signal reflections and crosstalk during transmission. These problems cause signal distortion and attenuation, greatly affecting signal quality. Utility Model Content

[0004] In order to overcome the problem that the existing fanout routing method of DDR5-DIMM affects the wiring capability and signal quality, this utility model provides a PCB structure that improves the wiring capability of DDR5-DIMM.

[0005] The technical solution of this utility model is as follows:

[0006] A PCB structure for improving the routing capability of DDR5-DIMMs includes a PCB board body. The PCB board body has a row of first pin pads, which includes multiple first signal pin pads and multiple first ground pin pads. Each first signal pin pad has a first signal hole tangent to its own edge on one side. The PCB board body has a first ground hole on the outside of the side where the first signal hole is located on each first signal pin pad, which is on the same horizontal line as the first signal hole.

[0007] As a preferred embodiment of this utility model, the PCB board body has a first outer layer containment zone on the same layer periphery of each first signal pin pad.

[0008] As a preferred embodiment of this utility model, the edge of each of the first outer layer blackout areas is tangent to the edge of the adjacent first ground pin pad and the adjacent first ground hole.

[0009] As a preferred embodiment of this utility model, the PCB board body is provided with a first inner layer ban zone on the outer periphery of the inner layer of each first signal pin pad.

[0010] As a preferred embodiment of this utility model, the edge of each of the first inner layer blackout areas is spaced 1-3 mil from the edge of the corresponding first signal pin pad.

[0011] As a preferred embodiment of this utility model, the PCB board body is further provided with a row of second pin pads arranged opposite to the first pin pads. The row of second pin pads includes multiple second signal pin pads and multiple second ground pin pads. Each second signal pin pad has a second signal hole tangent to its own edge on the side away from the first signal pin pad. On the outside of the side of each second signal pin pad where the second signal hole is opened, the PCB board body has a second ground hole on the same horizontal line as the second signal hole.

[0012] In a preferred embodiment of this utility model, the ground copper sheet is connected to the first ground hole, the second ground hole, the first ground pin pad, and the second ground pin pad.

[0013] As a preferred embodiment of this utility model, a second outer layer containment zone is provided on the outer periphery of each second signal pin pad on the same layer of the PCB board body.

[0014] As a preferred embodiment of this utility model, the edge of each second outer layer blackout area is tangent to the edge of the adjacent second ground pin pad and the adjacent second ground hole.

[0015] As a preferred embodiment of this utility model, the PCB board body is provided with a second inner layer ban zone on the outer periphery of the inner layer of each second signal pin pad.

[0016] As a preferred embodiment of this utility model, the edge of each second inner layer blackout area is spaced 1-3 mil from the edge of the corresponding second signal pin pad.

[0017] Compared with the prior art, the beneficial effects of this utility model are as follows:

[0018] This invention optimizes the layout of signal holes and ground holes. Signal holes tangent to their own edges are formed inside one side of the signal pin pad, while ground holes are formed outside the side of each signal pin pad where signal holes are located. This hole layout maximizes the spacing between adjacent signal holes and adjacent ground holes, allowing multiple signal lines to pass through and greatly improving cable routing capability. Simultaneously, it enables differential lines to be routed according to normal line width spacing without the need for ground holes, avoiding the disruption of the ideal electromagnetic environment of differential lines caused by ground holes. This effectively reduces signal reflections and crosstalk during transmission, improving signal quality. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this utility model, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of the outer layer structure of a PCB structure that improves the DDR5-DIMM wiring capability in one embodiment of the present invention;

[0021] Figure 2 This is a schematic diagram of the inner layer structure of a PCB structure that improves the routing capability of DDR5-DIMM in one embodiment of this utility model.

[0022] In the diagram,

[0023] 1. PCB board body; 2. First signal pin pad; 3. First ground pin pad; 4. First signal hole; 5. First ground hole; 6. Second signal pin pad; 7. Second ground pin pad; 8. Second signal hole; 9. Second ground hole; 10. Ground copper strip; 11. First outer layer keep-out area; 12. Second outer layer keep-out area; 13. First inner layer keep-out area; 14. Second inner layer keep-out area. Detailed Implementation

[0024] To make the technical problem to be solved, the technical solution, and the beneficial effects of this utility model clearer, the present utility model will be further described in detail below with reference to the accompanying drawings and embodiments. It should be noted that similar reference numerals and letters in the following drawings indicate similar items; therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. It is also declared that the embodiments described below are only for explaining this utility model and are not intended to limit this utility model.

[0025] It should be noted that the terms "installation," "setting," "connection," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise explicitly defined. Indications of orientation or positional relationship are based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used in the application's product, or the orientation or positional relationship commonly understood by those skilled in the art, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. The terms "first" and "second" are used only for descriptive purposes and should not be construed as indicating or implying relative importance or implying a number of technical features. "A plurality" means two or more, unless otherwise explicitly defined. "Several" means one or more, unless otherwise explicitly defined.

[0026] Please see Figure 1 This utility model provides a PCB structure that improves the routing capability of DDR5-DIMMs, including a PCB board body 1. The PCB board body 1 has a row of first pin pads and a row of second pin pads opposite to the first pin pads. The row of first pin pads includes multiple first signal pin pads 2 and multiple first ground pin pads 3. Each first signal pin pad 2 has a first signal hole 4 tangent to its own edge on one side inside. On the outer side of each first signal pin pad 2 with the first signal hole 4, the PCB board body 1 has a first ground hole 5 at the same horizontal line as the first signal hole 4. The row of second pin pads includes multiple second signal pin pads 6 and multiple second ground pin pads 7. Each second signal pin pad 6 has a second signal hole 8 tangent to its own edge on the side away from the first signal pin pad 2 inside. On the outer side of each second signal pin pad 6 with the second signal hole 8, the PCB board body 1 has a second ground hole 9 at the same horizontal line as the second signal hole 8. Meanwhile, a ground copper strip 10 is laid on the PCB board body 1. The ground copper strip 10 is connected to the first ground hole 5, the second ground hole 9, the first ground pin pad 3, and the second ground pin pad 7 to form a complete grounding system. The ground copper strip 10 provides a low-impedance grounding path for the signal, which helps to reduce signal reflection and crosstalk. It also provides a good electromagnetic shielding environment for the differential lines, further improving signal quality.

[0027] The PCB structure in this embodiment optimizes the layout of signal and ground vias. Signal vias tangent to their own edges are made inside one side of the signal pin pads, while ground vias are made outside the side of each signal pin pad where signal vias are made. This via layout maximizes the spacing between two adjacent signal vias and two adjacent ground vias, allowing multiple signal lines to pass through and greatly improving the routing capability. At the same time, it allows differential lines to be routed according to normal line width and spacing without the need for ground vias, avoiding the disruption of the ideal electromagnetic environment of differential lines by ground vias. This effectively reduces phenomena such as reflection and crosstalk during signal transmission and improves signal quality.

[0028] Please see Figure 1 In one embodiment, the PCB board body 1 has a first outer layer hold-out area 11 on the same layer periphery of each first signal pin pad 2, and a second outer layer hold-out area 12 on the same layer periphery of each second signal pin pad 6. The edge of each first outer layer hold-out area 11 is tangent to the edge of the adjacent first ground pin pad 3 and the adjacent first ground via 5, and the edge of each second outer layer hold-out area 12 is tangent to the edge of the adjacent second ground pin pad 7 and the adjacent second ground via 9. The aforementioned outer layer hold-out areas further regulate the spatial layout on the PCB board, rationally plan the spatial relationships between components, provide a more orderly spatial environment for signal transmission, avoid unnecessary wiring around the signal pin pads, and reduce the possibility of signal interference.

[0029] Please see Figure 2 Furthermore, the PCB board body 1 has a first inner layer hold-out region 13 around the inner layer (preferably the second outer layer and the layer below) of each first signal pin pad 2, and a second inner layer hold-out region 14 around the inner layer (preferably the second outer layer and the layer below) of each second signal pin pad 6. The edge of each first inner layer hold-out region 13 is spaced 1-3 mil from the edge of the corresponding first signal pin pad 2, preferably 2 mil; the edge of each second inner layer hold-out region 14 is spaced 1-3 mil from the edge of the corresponding second signal pin pad 6, preferably 2 mil. This set of inner layer hold-out regions ensures that the impedance of each signal pin pad is as close as possible to the impedance requirements of DDR5. Impedance consistency is crucial for signal transmission; when impedance is matched, signals can be transmitted more effectively, reducing signal reflection. Therefore, this setting helps reduce energy loss and distortion during signal transmission, improving signal quality.

[0030] It should be understood that those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.

[0031] The present utility model patent has been described above with reference to the accompanying drawings. Obviously, the implementation of the present utility model patent is not limited to the above-described manner. Any improvements made by adopting the inventive concept and technical solution of the present utility model patent, or the direct application of the inventive concept and technical solution of the present utility model patent to other occasions without modification, are all within the protection scope of the present utility model.

Claims

1. A PCB structure for improving the routing capability of DDR5-DIMMs, characterized in that, The PCB board includes a main body with a row of first pin pads. The row of first pin pads includes multiple first signal pin pads and multiple first ground pin pads. Each first signal pin pad has a first signal hole tangent to its own edge on one side. On the outside of the side of each first signal pin pad with the first signal hole, the PCB board has a first ground hole on the same horizontal line as the first signal hole.

2. The PCB structure for improving DDR5-DIMM traceability according to claim 1, characterized in that, The PCB board body has a first outer layer containment zone on the same layer periphery of each first signal pin pad.

3. The PCB structure for improving DDR5-DIMM traceability according to claim 2, characterized in that, The edge of each of the first outer layer keep-out areas is tangent to the edge of the adjacent first ground pin pad and the adjacent first ground via.

4. The PCB structure for improving DDR5-DIMM traceability according to claim 2, characterized in that, The PCB board body has a first inner layer ban zone on the outer periphery of the inner layer of each first signal pin pad.

5. The PCB structure for improving DDR5-DIMM traceability according to claim 4, characterized in that, The edge of each of the first inner layer keep-out areas is spaced 1-3 mil from the edge of the corresponding first signal pin pad.

6. The PCB structure for improving DDR5-DIMM traceability according to claim 1, characterized in that, The PCB board body is also provided with a row of second pin pads opposite to the first pin pads. The row of second pin pads includes multiple second signal pin pads and multiple second ground pin pads. Each second signal pin pad has a second signal hole tangent to its own edge on the side away from the first signal pin pad. On the outside of the side of each second signal pin pad where the second signal hole is opened, the PCB board body has a second ground hole on the same horizontal line as the second signal hole.

7. The PCB structure for improving DDR5-DIMM traceability according to claim 6, characterized in that, A ground copper strip is laid on the main body of the PCB board, and the ground copper strip is connected to the first ground hole, the second ground hole, the first ground pin pad and the second ground pin pad.

8. The PCB structure for improving DDR5-DIMM traceability according to claim 6, characterized in that, The PCB board body has a second outer layer keep-out zone on the same layer periphery of each second signal pin pad.

9. The PCB structure for improving DDR5-DIMM traceability according to claim 8, characterized in that, The edge of each of the second outer layer keep-out areas is tangent to the edge of the adjacent second ground pin pad and the adjacent second ground via.

10. The PCB structure for improving DDR5-DIMM traceability according to claim 9, characterized in that, The PCB board body has a second inner layer keep-out area on the outer periphery of the inner layer of each second signal pin pad; the edge of each second inner layer keep-out area is spaced 1-3 mil from the edge of the corresponding second signal pin pad.

Images