Low-forming voltage non-volatile memory (NVM)

Abstract

A low formation voltage NVM device is provided by forming a pair of sacrificial conductive pads on an interconnect dielectric material layer that is embedded with a pair of second conductive structures and a patterned material stack. One of the sacrificial conductive pads has a first region and contacts a surface of one of the second conductive structures that contacts a surface of an underlying first conductive structure, and the other of the sacrificial conductive pads has a second region different from the first region and contacts a surface of the other of the second conductive structures that contacts a surface of a top electrode of the patterned material stack. A plasma treatment is performed to induce an antenna effect and convert a dielectric switching material of the patterned material stack into a conductive filament. After the plasma treatment, the pair of sacrificial conductive pads is removed.

Description

Technical Field

[0001] This application relates to non-volatile memory (NVM), and more specifically to low-formation-voltage resistive random access memory (ReRAM or RRAM) devices and methods of forming the same. Background Technology

[0002] Non-volatile memory (NVM) is a type of computer memory that allows the retrieved information to be stored even after it has been power-cycled. In contrast, volatile memory requires constant power to retain data. Resistive random access memory (ReRAM or RRAM) is a type of NVM that operates by changing the resistance of a dielectric material (often called a memristor). The basic idea is that normally insulating dielectric materials can be made conductive by filaments, or conductive paths, formed after a sufficiently high voltage is applied. These conductive paths can be caused by various mechanisms, including the migration of vacancies or metallic defects. Once formed, the filament can be reset (disconnected, resulting in high resistance) or set (reformed, resulting in lower resistance) by another voltage.

[0003] Typical filament formation voltages for dielectric metal oxides (such as hafnium oxide) are 3 to 3.5 volts. This high filament formation voltage is incompatible with existing ReRAM devices. For example, existing 14nm ReRAM devices require formation voltages of approximately 2 volts or less.

[0004] In some ReRAM devices, plasma processing can be used to pre-form filaments in the ReRAM due to the antenna effect. Throughout this application, the term "antenna effect" is used to describe the charge accumulation effect in the isolation mode of electronic circuit components during processing. This charge accumulation often occurs due to charges generated during plasma processing. These charges are then collected via exposed metal surfaces and begin to accumulate in the isolation mode. This accumulation of charge can cause a voltage difference. A voltage can then be applied to the device if it is placed between two different isolation nodes. This voltage difference can ultimately lead to current flow or the application of electrical stress on the device. In such ReRAM devices, top and bottom electrodes are connected to long conductive pads or long wires to collect charge during plasma processing, but the total area is unbalanced and the antenna effect causes soft breakdown across the dielectric metal oxide. Large conductive pads or wires, which are permanent components of such ReRAM devices, penalize the area designed for the device.

[0005] In other ReRAM devices, deoxygenating materials such as rare earth elements can be used to achieve low formation voltage or formation free voltage ReRAM devices. The use of deoxygenating materials within ReRAM devices is generally incompatible with materials present in the back-end process (BEOL).

[0006] Therefore, there is a need to provide a low-formation-voltage ReRAM that solves one or more of the problems mentioned above for conventional low-formation-voltage ReRAM devices. Summary of the Invention

[0007] A low-formation-voltage NVM device is provided by forming a pair of sacrificial conductive pads on an interconnect dielectric material layer, which embeds a pair of second conductive structures and a patterned material stack. One of the sacrificial conductive pads has a first region and contacts a surface of one of the second conductive structures, the surface of which contacts a surface of the underlying first conductive structure. The other sacrificial conductive pad has a second region and contacts a surface of the other of the second conductive structures, the surface of which contacts a surface of the top electrode of the patterned material stack. Plasma treatment is performed to induce an antenna effect and convert the dielectric switching material of the patterned material stack into conductive filaments. After plasma treatment, the pair of sacrificial conductive pads are removed.

[0008] In one aspect of this application, a non-volatile memory (NVM) device is provided. In one embodiment, the NVM device includes a first conductive structure embedded in a first interconnect dielectric layer. A resistive random access memory (ReRAM) device is located on the first conductive structure, wherein the ReRAM device includes a bottom electrode, a conductive filament made of a dielectric conversion material, and a top electrode. A second interconnect dielectric layer is located on the first interconnect dielectric layer and embeds the ReRAM device. According to this application, the second interconnect dielectric layer includes a wavy upper surface in which recesses are present. A pair of second conductive structures are present in the second interconnect dielectric layer, wherein one of the second conductive structures in the pair contacts the surface of the first conductive structure, and another of the second conductive structures in the pair contacts the surface of the top electrode of the ReRAM device.

[0009] In another aspect of this application, a method for forming a non-volatile memory (NVM) device is provided. In one embodiment, the method includes forming a bottom electrode on the surface of a first conductive structure, the first conductive structure being embedded in a first interconnect dielectric material layer. A patterned material stack is then formed on the bottom electrode, the patterned material stack including a dielectric conversion material and a top electrode from bottom to top. A second interconnect dielectric material layer is then formed over the first interconnect dielectric material layer, wherein the patterned material stack is embedded in the second interconnect dielectric material layer. Next, a pair of second conductive structures are formed in the second interconnect dielectric material layer, wherein one of the second conductive structures in the pair contacts the surface of the first conductive structure, and the other of the second conductive structures in the pair contacts the surface of the top electrode of the patterned material stack. Then, a pair of sacrificial conductive pads are formed on the second interconnect dielectric material layer. One of the sacrificial conductive pads has a first region and contacts the surface of the second conductive structure in the pair of second conductive structures, the surface of the second conductive structure contacting the surface of the first conductive structure. The other sacrificial conductive pad has a second region that is different from (i.e., larger or smaller than) the first region and contacts the surface of the second conductive structure in the pair of second conductive structures, the surface of the second conductive structure contacting the surface of the top electrode of the patterned material stack. Next, a plasma treatment is performed to induce an antenna effect and convert the dielectric conversion material into conductive filaments for a ReRAM device, which further includes a bottom electrode and a top electrode. After forming the conductive filaments, the pair of sacrificial conductive pads are removed from the second interconnect dielectric material layer. Attached Figure Description

[0010] Figure 1 This is a cross-sectional view of a BEOL structure that can be used according to an embodiment of this application. The BEOL structure includes a bottom electrode located on the surface of a first conductive structure embedded in a first interconnect dielectric material layer.

[0011] Figure 2 This occurs after the formation of the dielectric switching layer and the top electrode layer. Figure 1 A cross-sectional view of the BEOL structure.

[0012] Figure 3 yes Figure 2 A cross-sectional view of the BEOL structure after a dielectric hard mask layer is formed on the top electrode layer.

[0013] Figure 4 This is done after forming a patterned photoresist mask on the surface of a dielectric hard mask layer. Figure 3A cross-sectional view of the BEOL structure.

[0014] Figure 5 yes Figure 4 The BEOL structure is a cross-sectional view after patterning the dielectric hard mask layer, the top electrode layer and the dielectric switching layer to provide patterned material stacks of the remaining portions of the dielectric hard mask layer, the remaining portions of the top electrode layer and the remaining portions of the dielectric switching layer, and removing the patterned photoresist mask.

[0015] Figure 6 This occurs after dielectric spacers are formed on the sidewalls of a patterned stack of materials. Figure 5 A cross-sectional view of the BEOL structure.

[0016] Figure 7 This occurs after the second interconnect dielectric material layer is formed on top of the first interconnect dielectric material layer. Figure 6 A cross-sectional view of the BEOL structure, wherein dielectric spacers comprising a stack of patterned materials are embedded in a second interconnect dielectric material layer.

[0017] Figure 8 This occurs after a pair of second conductive structures are formed in the second interconnect dielectric material layer. Figure 7 A cross-sectional view of the BEOL structure, wherein one of the second conductive structures in the pair of second conductive structures contacts the surface of the first conductive structure, and the other of the second conductive structures in the pair of second conductive structures contacts the surface of the remaining portion of the top electrode layer of the patterned material stack.

[0018] Figure 9 This occurs after a conductive metal pad layer is formed on both the second interconnect dielectric material layer and the pair of second conductive structures. Figure 8 A cross-sectional view of the BEOL structure.

[0019] Figure 10 yes Figure 9 A cross-sectional view of the BEOL structure after patterning a conductive metal pad layer to provide a pair of sacrificial conductive pads, wherein one of the sacrificial conductive pads in the pair has a first region and contacts the surface of the second conductive structure in the pair of second conductive structures that contacts the surface of the first conductive structure, and the other sacrificial conductive pad in the pair has a second region that is different from (i.e., larger or smaller than) the first region and contacts the surface of the second conductive structure in the pair of second conductive structures, the surface of the second conductive structure contacting the surface of the remaining portion of the top electrode layer of the patterned material stack.

[0020] Figure 11This occurs after performing plasma processing to induce the antenna effect and form the conductive filaments of the ReRAM device. Figure 10 A cross-sectional view of the BEOL structure.

[0021] Figure 12 This is after removing the pair of sacrificial conductive pads. Figure 11 A cross-sectional view of the BEOL structure.

[0022] Figure 13 It occurs after the dielectric capping layer is formed. Figure 12 A cross-sectional view of the BEOL structure. Detailed Implementation

[0023] This application will now be described in more detail with reference to the following discussion and the accompanying drawings. It should be noted that the drawings provided in this application are for illustrative purposes only, and therefore are not drawn to scale. It should also be noted that identical and corresponding elements are referred to by the same reference numerals.

[0024] In the following description, numerous specific details, such as specific structures, components, materials, dimensions, processing steps, and techniques, are set forth in order to provide an understanding of different embodiments of this application. However, those skilled in the art will understand that different embodiments of this application can be practiced without these specific details. In other instances, well-known structures or processing steps have not been described in detail to avoid obscuring the application.

[0025] It will be understood that when a component that is a layer, region, or substrate is referred to as being "on" or "over" another component, it may be directly on the other component, or there may be intermediate components present. Conversely, when a component is referred to as being "directly on" or "directly on" another component, there are no intermediate components present. It should also be understood that when a component is referred to as being "beneath" or "under" another component, it may be directly beneath or under the other component, or there may be intermediate components present. Conversely, when a component is referred to as being "directly below" or "directly under" another component, there are no intermediate components present.

[0026] Note that the accompanying drawings of this application illustrate a memory device region of a BEOL structure in which NVM devices (i.e., low formation voltage ReRAM devices) are present. The non-memory device region of the BEOL structure is located outside the memory device region shown in the drawings. The non-memory device region may include other BEOL devices, such as BEOL resistors or interconnect structures.

[0027] See now Figure 1This illustrates a BEOL structure that can be used according to embodiments of this application. The BEOL structure includes a bottom electrode 16 located on the surface of a first conductive structure 14 embedded in a first interconnect dielectric layer 10. In some embodiments, a diffusion barrier pad 12 may be located on the sidewalls and bottom surface of the first conductive structure 14. The first conductive structure 14, the optional diffusion barrier pad 12, and the first interconnect dielectric layer 10 together provide the interconnect hierarchy L of the BEOL structure. n , where n is an integer starting from a1.

[0028] Although not shown, interconnection level L n It exists on the line front-end (FEOL) level, which includes one or more CMOS devices. In some embodiments (also not shown), the metal level L n-1 It can be located between the interconnect level Ln and the FEOL level. In some embodiments, and when n is 1, the metal level L n-1 It is the middle (MOL) level. In other embodiments, and when n is 2, 3, 4, etc., the metal layer L n-1 It is located at the interconnection layer L n The lower interconnect layer below. In any embodiment, the metal layer L n-1 It includes a dielectric material layer containing at least one metal-level conductive structure embedded therein, which is directly or indirectly connected to a lower-level CMOS device (not shown) existing in the FEOL layer (also not shown).

[0029] When n is 1, the metal layer L n-1 The dielectric material layer can be composed of MOL dielectric materials, such as silicon dioxide, undoped silicate glass (USG), fluorosilicate glass (FSG), borosilicate glass (BPSG), spin-coated low-k dielectric layer, chemical vapor deposition (CVD) low-k dielectric layer, or any combination thereof. As used throughout this application, the term "low-k" refers to a dielectric material having a dielectric constant less than 4.0 (all dielectric constants expressed herein are measured in a vacuum). Furthermore, in such embodiments (i.e., when n is 1), at least one metal-level conductive structure is a contact structure comprising a contact metal or contact metal alloy, such as, for example, tungsten (W), cobalt (Co), platinum (Pt), nickel (Ni), or alloys thereof.

[0030] When n is greater than 1, the metal layer L n-1The dielectric material layer can be composed of interconnecting dielectric materials, such as, for example, silicon dioxide, silsesquioxanes, C-doped oxides including Si, C, O, and H atoms (i.e., organosilicones), thermosetting polyarylene ethers, or multilayers thereof. In this application, the term "polyarylene" is used to refer to aryl moieties or inertly substituted aryl moieties linked together by bonds, fused rings, or inert linking groups (e.g., oxygen, sulfur, sulfone, sulfoxide, carbonyl, and the like). Furthermore, in such embodiments (i.e., when n is greater than 1), at least one metal-level conductive structure is composed of a conductive metal or a conductive metal alloy. Examples of conductive materials that can be used in this application include copper (Cu), aluminum (Al), or tungsten (W), while examples of conductive metal alloys are Cu-Al alloys.

[0031] Interconnection level is L n The first interconnect dielectric material layer 10 may be made of the above-mentioned material used for metal layers of L n-1 The first interconnect dielectric material layer 10 is one component of the interconnect dielectric material layer. It can be formed using conventional deposition processes such as, for example, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), chemical solution deposition, evaporation, or atomic layer deposition (ALD). In one embodiment, the first interconnect dielectric material layer 10 can have a thickness (i.e., vertical height) from 50 nm to 200 nm. Other thicknesses of the first interconnect dielectric material layer 10 are possible and can be used as the thickness of the first interconnect dielectric material layer 10 in this application.

[0032] The first conductive structure 14 embedded in the first interconnect dielectric material layer 10 may be composed of one of the conductive metals or conductive metal alloys described above for at least one metal-level conductive structure. The conductive metal or conductive metal alloy providing the first conductive structure 14 may be formed using conventional deposition processes such as CVD, PECVD, sputtering, chemical solution deposition, or electroplating. In one embodiment, a bottom-up electroplating process is used to form the conductive metal or conductive metal alloy providing the first conductive structure 14.

[0033] As described above, and in some embodiments, the diffusion barrier pad 12 is present along the sidewalls and bottom surface of the first conductive structure 14. In some embodiments (not shown), the diffusion barrier pad is not present. The diffusion barrier pad 12 is composed of a diffusion barrier material (i.e., a material used as a barrier to prevent the diffusion of conductive materials such as copper). Examples of diffusion barrier materials that can be used to provide the diffusion barrier pad 12 include, but are not limited to, Ta, TaN, Ti, TiN, Ru, RuN, RuTa, RuTaN, W, or WN. In some embodiments, the diffusion barrier material may comprise a stack of diffusion barrier materials. In one example, the diffusion barrier material may be composed of a stack of Ta / TaN. The diffusion barrier material may be formed by deposition processes including, for example, CVD, PECVD, ALD, physical vapor deposition (PVD), sputtering, chemical solution deposition, or electroplating.

[0034] Interconnect levels can be formed using any conventional process known to those skilled in the art. n To avoid obscuring the methods of this application, methods for forming interconnection layers L are not provided herein. n The processing. In one embodiment, the damascene process can be used to form an interconnect layer L. n The damascene process may include forming openings in a dielectric material, filling the openings with a material containing a conductive metal, and, if necessary, performing planarization processes, such as chemical mechanical polishing (CMP) and / or grinding.

[0035] In some embodiments, the first conductive structure 14 has a top surface that is coplanar with the top surface of the first interconnect dielectric material layer 10, and, if present, a top surface of the diffusion barrier pad 12.

[0036] In forming interconnection hierarchy L n Subsequently, a bottom electrode 16 is formed on the surface of the first conductive structure 14; the bottom electrode 16 forms an interface with the first conductive structure 14. The bottom electrode 16 has an area smaller than that of the first conductive structure 14, such that a portion of the first conductive structure 14 can be used for subsequent contact formation. The bottom electrode 16 is made of an oxygen-deficient conductive material, such as Cu, Ta, TaN, Ti, TiN, Ru, RuN, RuTa, RuTaN, Co, CoWP, CoN, W, WN, or any combination thereof. The bottom electrode 16 may have a thickness from 2 nm to 80 nm; other thicknesses are possible and may be used as the thickness of the bottom electrode 16 in this application. The bottom electrode 16 may be formed by deposition processes such as sputtering, electroplating, electroless plating, ALD, CVD, PECVD, or PVD. In some embodiments, after depositing the conductive material providing the bottom electrode 16, a deep etching process, a planarization process (e.g., chemical mechanical polishing), or a patterning process (e.g., photolithography and etching) may be performed.

[0037] In some embodiments, such as Figure 1 As shown, the bottom electrode 16 is formed on the topmost surface of the first conductive structure 14, and the bottom electrode 16 is embedded in the dielectric capping layer 18. The dielectric capping layer 18 can be made of any dielectric capping material, including, for example, silicon carbide (SiC), silicon nitride (Si3N4), silicon dioxide (SiO2), carbon-doped oxides, nitrogen and hydrogen-doped silicon carbide (SiC(N,H)), or a multilayer stack of at least one of the above dielectric capping materials. The dielectric capping material providing the dielectric capping layer 18 is compositionally different from the first interconnect dielectric material layer 10. The dielectric capping material providing the dielectric capping layer 18 can be formed using deposition processes such as CVD, PECVD, ALD, chemical solution deposition, or evaporation.

[0038] In one embodiment, a dielectric capping layer 18 is formed over the entire interconnect layer Ln, including a first interconnect dielectric material layer 10, a first conductive structure 14, and a diffusion barrier pad 12 (if present). Openings are then formed in the dielectric capping layer 18 by photolithography and etching. The openings formed in the dielectric capping layer 18 physically expose the surface of the first conductive structure 14. Next, a bottom electrode 16 is formed into the openings present in the dielectric capping layer 18.

[0039] In another embodiment, the bottom electrode 16 is formed by deposition and patterning, and thereafter, a dielectric capping layer 18 is formed laterally adjacent to the bottom electrode 16.

[0040] In some embodiments (not shown), the bottom electrode 16 may be formed on a recessed surface of the first conductive structure 14. The recess in the first conductive structure 14 includes recess etching; if a diffusion barrier pad 12 is present in the structure, the recess etching may also recess the diffusion barrier pad 12. In embodiments where the bottom electrode 16 is formed on a recessed surface of the first conductive structure 14, the dielectric overlay layer 18 may be omitted from the structure, and the bottom electrode 16 may have a top surface coplanar with or below the top surface of the first interconnect dielectric material layer 10.

[0041] See now Figure 2 This illustrates the process after the formation of the dielectric switching layer 20L and the top electrode layer 22L. Figure 1 The BEOL structure is shown. As illustrated, the dielectric switching layer 20L contacts at least one surface of the bottom electrode 16. Thus, the dielectric switching layer 20L forms an interface with the bottom electrode 16.

[0042] The dielectric switching layer 20L is a dielectric material such as a dielectric metal oxide having a dielectric constant greater than 4.0. The dielectric switching layer 20L is electrically insulating at this point in the present application, and during plasma processing, it is converted into a conductive filament. Examples of dielectric metal oxides that can be used as the dielectric switching layer 20L include, but are not limited to, hafnium oxide (HfOx), tantalum oxide (TaOx), titanium oxide (TiOx), aluminum oxide (AlOx), or combinations thereof. The dielectric switching layer 20L can be formed using deposition processes such as CVD, PECVD, ALD, chemical solution deposition, or evaporation. The dielectric switching layer 20L can have a thickness from 1 nm to 50 nm; however, other thicknesses are contemplated for use.

[0043] The top electrode layer 22L (which forms an interface with the dielectric switching layer 20L) may be composed of one of the oxygen-deficient conductive materials mentioned above for the bottom electrode 16. In one embodiment, the top electrode layer 22L is composed of an oxygen-deficient conductive material that is compositionally identical to the oxygen-deficient conductive material providing the bottom electrode 16. In another embodiment, the top electrode layer 22L is composed of an oxygen-deficient conductive material that is compositionally different from the oxygen-deficient conductive material providing the bottom electrode 16. The top electrode layer 22L may have a thickness from 2 nm to 80 nm; other thicknesses are also possible and can be used as the thickness of the top electrode 22L in this application. The top electrode layer 22L may be formed by deposition processes such as sputtering, electroplating, electroless plating, ALD, CVD, PECVD, or PVD.

[0044] Now for reference Figure 3 This shows the process after forming a dielectric hard mask layer 24L on the top electrode layer 22L. Figure 2 The BEOL structure. In some embodiments, the formation of the dielectric hard mask layer 24L may be omitted. When present, the dielectric hard mask layer 24L is a continuous layer covering the entire top electrode layer 22L. The dielectric hard mask layer 24L is made of a dielectric hard mask material such as silicon dioxide, silicon nitride, silicon oxynitride, or any combination thereof. The dielectric hard mask layer 24L can be formed using deposition processes such as CVD, PECVD, ALD, chemical solution deposition, or evaporation. The dielectric hard mask layer 24L can have a thickness from 10 nm to 15 nm; however, other thicknesses can be considered as the thickness of the dielectric hard mask layer 24L.

[0045] Now for reference Figure 4 This illustrates the process after a patterned photoresist mask 26 is formed on the surface of the dielectric hard mask layer 24L. Figure 3The BEOL structure. A patterned photoresist mask 26 is located directly over the region of the structure including the bottom electrode 16 and serves to define a columnar patterned stack of material for the remaining portions of the dielectric hard mask layer 24L, the remaining portions of the top electrode layer 22L, and the remaining portions of the dielectric switching layer 20L. The patterned photoresist mask 26 is composed of positive photoresist, negative photoresist, or a hybrid photoresist. The patterned photoresist mask 26 can be formed by depositing a suitable photoresist material and then patterning the deposited photoresist material by photolithography.

[0046] Now for reference Figure 5 The diagram shows a patterned material stack of a patterned dielectric hard mask layer 24L, a top electrode layer 22L, and a dielectric switching layer 20L to provide the remainder of the dielectric hard mask layer 24L (hereinafter referred to as dielectric hard mask 24), the remainder of the top electrode layer 22L (hereinafter referred to as top electrode 22), and the remainder of the dielectric switching layer 20L (hereinafter referred to as dielectric conversion material 20), and after the patterned photoresist mask 26 has been removed. Figure 4 The BEOL structure.

[0047] The patterning of the dielectric hard mask layer 24L, the top electrode layer 22L, and the dielectric switching layer 20L includes etching processes such as reactive ion etching (RIE) or ion beam etching (IBE). The patterning of the dielectric hard mask layer 24L, the top electrode layer 22L, and the dielectric switching layer 20L utilizes a patterned photoresist mask 26 as an etching mask. The patterned photoresist mask 26 can be removed from the BEOL structure at any time after the pattern has been transferred to at least the dielectric hard mask layer 24L. The patterned photoresist mask 26 can be removed using conventional resist stripping processes (e.g., ashing). In some embodiments, a wet cleaning process follows the formation of the patterned material stack (20 / 22 / 24).

[0048] In some implementations and such Figure 5 As shown, the various elements / components defining the patterned material stack (20 / 22 / 24) have sidewalls that are perpendicularly aligned with each other. In some embodiments, the patterned material stack (20 / 22 / 24) is cylindrical in shape. In some embodiments (and as shown in the figure), the various elements / components defining the patterned material stack (20 / 22 / 24) are cylindrical in shape. Figure 5As shown in the diagram, the width of the patterned material stack (20 / 22 / 24) may be greater than the width of the bottom electrode 16. A wider patterned material stack (20 / 22 / 24) avoids re-sputtering of the bottom electrode metal particles onto the sidewalls of the patterned material stack (20 / 22 / 24), which could cause a short circuit in the device. In other embodiments (not shown), the width of the patterned material stack (20 / 22 / 24) may be the same as the width of the bottom electrode 16; this also avoids re-sputtering of the bottom electrode metal particles onto the sidewalls of the patterned material stack (20 / 22 / 24).

[0049] See now Figure 6 This illustrates the effect after forming dielectric spacers 28 on the sidewalls of a patterned material stack (20 / 22 / 24). Figure 5 The BEOL structure. The dielectric spacer 28 may comprise any dielectric spacer material, including, for example, silicon dioxide, silicon nitride, silicon oxynitride, SiCN, SiCON, or any combination thereof. The dielectric spacer material providing the dielectric spacer 28 may be compositionally the same as or different from the hard mask material providing the dielectric hard mask 24. The dielectric spacer 28 may be formed by depositing the dielectric spacer material followed by spacer etching.

[0050] Now for reference Figure 7 This illustrates the process after the second interconnect dielectric material layer 30 is formed on the first interconnect dielectric material layer 10. Figure 6 The BEOL structure includes a second interconnect dielectric layer 30 in which a dielectric isolator 28 comprising a patterned material stack (20 / 22 / 24) is embedded. The second interconnect dielectric layer 30 may include one of the interconnect dielectric materials mentioned above with respect to the first interconnect dielectric layer 10. In one embodiment, the second interconnect dielectric layer 30 may be composed of an interconnect dielectric material having the same composition as the interconnect dielectric material providing the first interconnect dielectric layer 10. In another embodiment, the second interconnect dielectric layer 30 may be composed of an interconnect dielectric material having a different composition from the interconnect dielectric material providing the first interconnect dielectric layer 10. The second interconnect dielectric layer 30 may be formed using one of the deposition processes described above for forming the first interconnect dielectric layer 10. The second interconnect dielectric layer 30 has a thickness greater than the thickness (20 / 22 / 24) of the patterned material stack. In one embodiment, the second interconnect dielectric layer 30 has a thickness from 50 nm to 500 nm. The second interconnect dielectric layer 30 forms the second interconnect level L of the BEOL structure. n+1 .

[0051] See now Figure 8 This illustrates the effect after a pair of second conductive structures (32L, 32R) are formed in the second interconnect dielectric material layer 30. Figure 7The BEOL structure, wherein one of the second conductive structures (i.e., the second conductive structure 32L) of the pair of second conductive structures (32L, 32R) contacts the surface of the first conductive structure 14, and the other of the second conductive structures (i.e., the second conductive structure 32R) of the pair of second conductive structures (32L, 32R) contacts the surface of the remaining portion of the top electrode layer 22L of the patterned material stack (20 / 22 / 24) (i.e., the top electrode 22).

[0052] Each of the pair of second conductive structures (32L, 32R) is composed of one of the conductive metals or conductive metal alloys described above for the first conductive structure 14. In some embodiments, each of the pair of second conductive structures (32L, 32R) is composed of a conductive metallic material that is compositionally identical to the first conductive structure 14. In other embodiments, each of the pair of second conductive structures (32L, 32R) is composed of a conductive metallic material that is compositionally different from the first conductive structure 14.

[0053] Each of the second conductive structures in the pair of second conductive structures (32L, 32R) can be formed using a dual damascene process or any other process for forming conductive structures in the interconnect dielectric material. Each of the second conductive structures in the pair of second conductive structures (32L, 32R) has a top surface that is coplanar with the top surface of the second interconnect dielectric material layer 30.

[0054] See now Figure 9 This illustrates the formation of a conductive metal pad layer 34 on both the second interconnect dielectric material layer 30 and a pair of second conductive structures (32L, 32R). Figure 8 The BEOL structure. The conductive metal-containing pad layer 34 can be composed of conductive metal nitrides (e.g., TaN, TiN, RuN, RuTaN, CoN, WN, or any combination thereof). Other conductive metal-containing materials besides conductive metal nitrides, or materials other than conductive metal nitrides, can also be used as the conductive metal-containing pad layer 34. The conductive metal-containing pad layer 34 differs in composition from the second conductive structure (32L, 32R). The conductive metal-containing pad layer 34 can be formed using deposition processes such as sputtering, electroplating, electroless plating, ALD, CVD, PECVD, or PVD. The conductive metal-containing pad layer 34 can have a thickness from 5 nm to 50 nm; although other thicknesses are considered and can be used as the thickness of the conductive metal-containing pad layer 34.

[0055] See now Figure 10 This illustrates the process after patterning the conductive metal pad layer 34 to provide a pair of sacrificial conductive pads (34L, 34R). Figure 9The BEOL structure, wherein one of the pair of sacrificial conductive pads (34L, 34R) (i.e., pad 34L) has a first region and contacts the surface of the second conductive structure 32L of the pair of second conductive structures (32L, 32R) that contacts the surface of the first conductive structure 14, and the other of the pair of sacrificial conductive pads (34L, 34R) (i.e., pad 34R) has a second region, the second region being different (i.e., larger or smaller than the first region) and contacting the surface of the second conductive structure 32R of the pair of second conductive structures (32L, 32R), the surface of the second conductive structure 32R contacting the surface of the remaining portion of the top electrode layer (i.e., top electrode 22) of the patterned material stack (20 / 22 / 24). Figure 10 An embodiment is shown in which the sacrificial conductive pad 34R has a second region that is larger than the first region of the sacrificial conductive pad 34L. In some embodiments, the first region of the sacrificial conductive pad 34L may be larger than the second region of the sacrificial conductive pad 34R.

[0056] Patterning of the conductive metal pad layer 34 may include photolithography and etching. As described above, the second region of the sacrificial conductive pad 34R differs from (i.e., is larger or smaller than) the first region of the sacrificial conductive pad 34L. The regional difference between the sacrificial conductive pads (34L, 34R) allows for soft dielectric breakdown across the dielectric conversion material 20 using an antenna effect during subsequent plasma processing. In one embodiment, the ratio of the second region to the first region is greater than 1.2.

[0057] It should be noted that during the patterning of the conductive metal pad layer 34, the recess D1 is formed as a second interconnect dielectric material layer 30 adjacent to and located between the pair of second conductive structures (32L, 32R). Therefore, the second interconnect dielectric material layer 30 now has a wavy upper surface containing the recess D1.

[0058] Now for reference Figure 11 This shows the effect after plasma treatment (PT) to induce the antenna effect and form conductive filament 20F. Figure 10 The BEOL structure; Figure 11The arrows in the diagram indicate the direction of plasma processing. The conductive filament 20F is composed of a switching dielectric material 20, which is now conductive due to dielectric breakdown of the original switching dielectric material 20. The conductivity of the conductive filament 20F is temporary and reversible. The bottom electrode 16, the conductive filament 20F, and the top electrode 22 together form the ReRAM device of this application. Subsequently and during use, the ReRAM device may include the bottom electrode 16, the dielectric conversion material 20, and the top electrode 22. The ReRAM device is located in a BEOL and is embedded with various dielectric materials.

[0059] The conductive filament 20F is a pre-formed filament. In this application, the top electrode 22 and the bottom electrode 16 are connected to long sacrificial conductive pads (34L, 34R) to collect charge during plasma processing; however, the total area is unbalanced and causes soft dielectric breakdown across the switching dielectric material 20 using an antenna effect. The large sacrificial conductive pads (34L, 34R) are subsequently removed from the structure, thereby eliminating the area loss caused by the presence of permanent conductive pads in the final structure. Furthermore, the pre-formed conductive filament 20F of this application reduces the formation voltage to less than 2 volts, compared to 3 volts or more required to form prior art filaments in ReRAM devices.

[0060] In one embodiment of this application, the plasma treatment for inducing the antenna effect and forming the conductive filament 20F may include plasma treatment, wherein Figure 10 The BEOL structure shown undergoes plasma treatment, which includes gases, including but not limited to argon, nitrogen, hydrogen, xenon, ammonia, or mixtures thereof. In some embodiments, the plasma process used in this application may include a pressure range of 1 mTorr to 3 Torr, a plasma power of 0.1 kW to 10 kW, a bias voltage of 0 volts to 50 volts, and a duration of 5 seconds to 15 minutes. The plasma treatment can be performed using inductively coupled plasma (ICP) tools, capacitively coupled plasma (CCP) tools, or microwave-generated plasma tools.

[0061] See now Figure 12 This shows the result after removing the pair of sacrificial conductive pads (34L, 34R). Figure 11The BEOL structure. The pair of sacrificial conductive pads (34L, 34R) can be removed using a material removal process that is selective in removing the conductive metal material providing each sacrificial conductive pad (34L, 34R). Material removal processes that can be used to remove the sacrificial conductive pads (34L, 34R) include chemical mechanical polishing (CMP), reactive ion etching (RIE), or RIE combined with an intermediate wet etching process. Note that after removing the pair of sacrificial conductive pads (34L, 34R), the recess D1 remains in the second interconnect dielectric material layer 30.

[0062] It is worth noting that, Figure 12 This application illustrates an NVM device comprising a first conductive structure 14 embedded in a first interconnect dielectric layer 10. A resistive random access memory (ReRAM) device (16 / 20F / 22) is located on the first conductive structure 14, wherein the ReRAM device (16 / 20F / 22) includes a lower electrode 16, a conductive filament 20F made of a dielectric conversion material, and an upper electrode 22. A second interconnect dielectric layer 30 is located on the first interconnect dielectric layer 10 and embeds the ReRAM device (16 / 20F / 22). According to this application, the second interconnect dielectric layer 30 includes a wavy upper surface having a recess D1 present therein. A pair of second conductive structures (32L, 32R) exist in the second interconnect dielectric material layer 30, wherein one of the second conductive structures (i.e., conductive structure 32L) of the pair of second conductive structures (32L, 32R) contacts the surface of the first conductive structure 14, and the other of the second conductive structures (i.e., conductive structure 34R) of the pair of second conductive structures (32L, 32R) contacts the surface of the top electrode 22 of the ReRAM device (16 / 20F / 22).

[0063] See now Figure 13 This shows the effect after the formation of the dielectric overlay layer 36. Figure 12 The BEOL structure. The dielectric capping layer 36 comprises one of the dielectric capping materials mentioned above for dielectric capping layer 18. In one embodiment, the dielectric capping layer 36 is composed of the same dielectric capping material as dielectric capping layer 18. In another embodiment, the dielectric capping layer 36 is composed of a dielectric capping material different from dielectric capping layer 18. The dielectric capping layer 36 can be formed using one of the deposition processes described above for dielectric capping layer 18. The dielectric capping layer 36 may have a thickness from 10 nm to 150 nm. Other thicknesses of the dielectric capping layer 36 are contemplated and may be used in this application. In some embodiments, a third interconnect dielectric material layer (not shown) providing a third interconnect level is formed over the dielectric capping layer 36. In some embodiments, the dielectric capping layer 36 is omitted.

[0064] While this application has been specifically shown and described with respect to its preferred embodiments, those skilled in the art will understand that foregoing and other changes to form and detail may be made without departing from the scope of this application. Therefore, this application is intended to be limited to the exact form and detail described and shown, but rather to fall within the scope of the appended claims.

Claims

1. A method for forming a non-volatile memory device, the method comprising: A bottom electrode is formed on the surface of a first conductive structure embedded in a first interconnect dielectric material layer; A patterned material stack is formed, the patterned material stack comprising a dielectric conversion material and a top electrode on the bottom electrode from bottom to top; A second interconnect dielectric material layer is formed on top of the first interconnect dielectric material layer, wherein the patterned material stack is embedded in the second interconnect dielectric material layer; A pair of second conductive structures are formed in the second interconnect dielectric material layer, wherein one of the second conductive structures in the pair contacts the surface of the first conductive structure, and the other of the second conductive structures in the pair contacts the surface of the top electrode of the patterned material stack; A pair of sacrificial conductive pads are formed on the second interconnect dielectric material layer, wherein one of the sacrificial conductive pads has a first region and contacts the surface of the second conductive structure in the pair of second conductive structures, the surface of the second conductive structure contacts the surface of the first conductive structure, and the other of the sacrificial conductive pads has a second region, the second region being different from the first region and contacting the surface of the second conductive structure in the pair of second conductive structures, the surface of the second conductive structure contacting the surface of the top electrode of the patterned material stack; Plasma treatment is performed to induce an antenna effect and to convert a dielectric conversion material into a conductive filament for a resistive random access memory device, the resistive random access memory device further comprising a bottom electrode and a top electrode; and Remove the pair of sacrificial conductive pads from the second interconnect dielectric material layer.

2. The method according to claim 1, wherein, During the formation of the pair of sacrificial conductive pads on the second interconnect dielectric material layer, a recess is formed in the second interconnect dielectric material layer.

3. The method according to claim 1, wherein, The process of converting the dielectric conversion material into the conductive filament is performed at a voltage of less than 2 volts.

4. The method of claim 2, further comprising: After removing the pair of sacrificial conductive pads, a dielectric overlay is formed on the upper surface of the second interconnect dielectric material layer, wherein the dielectric overlay exists in the recesses present in the second interconnect dielectric material layer.

5. The method according to claim 1, wherein, Forming the bottom electrode includes embedding the bottom electrode in a dielectric capping layer formed on the first interconnect dielectric material layer.

6. The method according to claim 1, wherein, The patterned material stack further includes a dielectric hard mask located on the top electrode.

7. The method according to claim 6, wherein, The dielectric hard mask has sidewalls that are perpendicularly aligned with the sidewalls of both the top electrode and the dielectric conversion material.

8. The method according to claim 1, wherein, The dielectric conversion material is composed of dielectric metal oxides.

9. The method according to claim 1, wherein, The patterned material stack has a width greater than or equal to the width of the bottom electrode.

10. The method of claim 1, further comprising: Before forming the second interconnect dielectric material layer, dielectric spacers are formed on the sidewalls of the patterned material stack.

11. A non-volatile memory device manufactured by the method according to any one of claims 1 to 10, comprising: The first conductive structure is embedded in the first interconnect dielectric material layer; A resistive random access memory device is located on the first conductive structure, wherein the resistive random access memory device includes a bottom electrode, a conductive filament composed of a dielectric conversion material, and a top electrode; A second interconnect dielectric layer is located on the first interconnect dielectric layer and embedded in the resistive random access memory device, wherein the second interconnect dielectric layer includes a wavy upper surface in which there are recesses; A pair of second conductive structures existing in the second interconnect dielectric material layer, wherein one of the second conductive structures in the pair of second conductive structures contacts the surface of the first conductive structure, and the other of the second conductive structures in the pair of second conductive structures contacts the surface of the top electrode of the resistive random access memory device; A dielectric hard mask located on the top electrode; The dielectric hard mask has sidewalls that are perpendicularly aligned with the sidewalls of both the top electrode and the conductive filament.

12. The non-volatile memory device according to claim 11, wherein, The conductive filament and the top electrode of the resistive random access memory device have a width greater than or equal to the width of the bottom electrode of the resistive random access memory device.

13. The non-volatile memory device according to claim 11, wherein, The bottom electrode of the resistive random access memory device is embedded in a dielectric capping layer located between the first interconnect dielectric layer and the second interconnect dielectric layer.

14. The non-volatile memory device according to claim 11, wherein, The dielectric conversion material is composed of dielectric metal oxides.

15. The non-volatile memory device of claim 11, further comprising a dielectric capping layer located on the second interconnect dielectric material layer.

16. The non-volatile memory device of claim 11, further comprising a dielectric spacer located on the sidewall of the conductive filament and the sidewall of the top electrode of the resistive random access memory device.

17. The non-volatile memory device according to claim 11, wherein, The conductive filaments are pre-formed using a voltage of less than 2 volts.

18. The non-volatile memory device according to claim 11, wherein, The conductive filament and the top electrode of the resistive random access memory device have a cylindrical shape.

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