Pixel, display device including the pixel, and method of manufacturing the display device

Abstract

The present application relates to a pixel, a display device including the pixel, and a method of manufacturing the display device. The pixel includes: a first sub-pixel region and a second sub-pixel region, which are arranged adjacent to each other in a first direction; a first electrode and a second electrode, which are disposed in each of the first sub-pixel region and the second sub-pixel region and are spaced apart from each other; a plurality of light-emitting elements, which are disposed between the first electrode and the second electrode in each of the first sub-pixel region and the second sub-pixel region; a first driving transistor, which is disposed in the first sub-pixel region and is connected to the first electrode of the first sub-pixel region; and a second driving transistor, which is disposed in the second sub-pixel region and is connected to the first electrode of the second sub-pixel region. The first electrode of the first sub-pixel region and the first electrode of the second sub-pixel region are electrically disconnected from each other, and the second electrode of the first sub-pixel region and the second electrode of the second sub-pixel region are electrically connected to each other.

Description

Technical Field

[0001] The present disclosure relates to a pixel, a display device including the pixel, and a method of manufacturing the display device. Background Art

[0002] As the interest in information display increases and the demand for using portable information media increases, the demand for display devices has increased significantly, and the commercialization of display devices is underway. Summary of the Invention

[0003] Technical Problem

[0004] An object of the present disclosure is to provide a pixel having enhanced reliability, a display device including the pixel, and a method of manufacturing the display device.

[0005] Technical Solution

[0006] A pixel according to an embodiment of the present disclosure may include: a first sub-pixel region and a second sub-pixel region, disposed adjacent to each other in a first direction; a first electrode and a second electrode, disposed in each of the first sub-pixel region and the second sub-pixel region and spaced apart from each other; a plurality of light-emitting elements, disposed between the first electrode and the second electrode in each of the first sub-pixel region and the second sub-pixel region; a first driving transistor, disposed in the first sub-pixel region and connected to the first electrode of the first sub-pixel region; and a second driving transistor, disposed in the second sub-pixel region and connected to the first electrode of the second sub-pixel region.

[0007] The first electrode of the first sub-pixel region and the first electrode of the second sub-pixel region may be electrically disconnected from each other, and the second electrode of the first sub-pixel region and the second electrode of the second sub-pixel region may be electrically connected to each other.

[0008] In an embodiment, each of the first sub-pixel region and the second sub-pixel region may include a first sub-region and a second sub-region spaced apart from each other in a second direction intersecting the first direction. The first electrode disposed in each of the first sub-pixel region and the second sub-pixel region may include a 1-1 sub-electrode disposed in the first sub-region and a 1-2 sub-electrode disposed in the second sub-region. The second electrode disposed in each of the first sub-pixel region and the second sub-pixel region may include a 2-1 sub-electrode disposed in the first sub-region and a 2-2 sub-electrode disposed in the second sub-region.

[0009] In an embodiment of the present disclosure, the light-emitting elements in each of the first sub-pixel region and the second sub-pixel region may include: a first light-emitting element disposed between the 1-1 sub-electrode and the 2-1 sub-electrode; and a second light-emitting element disposed between the 1-2 sub-electrode and the 2-2 sub-electrode.

[0010] In an embodiment of the present disclosure, the first sub-electrode and the second sub-electrode of each of the first sub-pixel region and the second sub-pixel region, together with the first light-emitting element connected in parallel therebetween, may form a first group, and the first sub-electrode and the second sub-electrode of each of the first sub-pixel region and the second sub-pixel region, together with the second light-emitting element connected in parallel therebetween, may form a second group.

[0011] In an embodiment of the present disclosure, the pixel may further include a first contact electrode disposed in each of the first sub-pixel region and the second sub-pixel region and disposed on each of the first sub-electrode and the second sub-electrode and the first sub-electrode and the second sub-electrode.

[0012] In an embodiment of the present disclosure, the pixel may further include a first intermediate electrode disposed in a region between the first sub-region and the second sub-region in each of the first sub-pixel region and the second sub-pixel region.

[0013] In an embodiment of the present disclosure, the first intermediate electrode and the first contact electrode may be integrally formed with each other on the second sub-electrode disposed in the first sub-region of each of the first sub-pixel region and the second sub-pixel region.

[0014] In an embodiment of the present disclosure, the first group and the second group of each of the first sub-pixel region and the second sub-pixel region may be electrically connected to each other through the first intermediate electrode.

[0015] In an embodiment of the present disclosure, the first intermediate electrode may connect the first contact electrode on the second sub-electrode of the first group to the first contact electrode on the first sub-electrode of the second group in each of the first sub-pixel region and the second sub-pixel region.

[0016] In an embodiment of the present disclosure, the pixel may further include a third electrode disposed in each of the first sub-pixel region and the second sub-pixel region and spaced apart from the first electrode and the second electrode. The third electrode may include a third sub-electrode disposed in the first sub-region and a third sub-electrode disposed in the second sub-region. The first sub-electrode and the third sub-electrode may be connected to each other through a connection line in each of the first sub-pixel region and the second sub-pixel region.

[0017] In an embodiment of the present disclosure, each of the first sub-pixel region and the second sub-pixel region may further include a third sub-region disposed below the second sub-region in the second direction.

[0018] Here, the first electrode of each of the first sub-pixel region and the second sub-pixel region may further include a 1-3 sub-electrode disposed in the third sub-region. The second electrode of each of the first sub-pixel region and the second sub-pixel region may further include a 2-3 sub-electrode disposed in the third sub-region. The light-emitting element of each of the first sub-pixel region and the second sub-pixel region may further include a third light-emitting element disposed between the 1-3 sub-electrode and the 2-3 sub-electrode.

[0019] In an embodiment of the present disclosure, the 1-3 sub-electrode and the 2-3 sub-electrode together with the third light-emitting element connected in parallel therebetween may form a third group in each of the first sub-pixel region and the second sub-pixel region.

[0020] In an embodiment of the present disclosure, the pixel may further include: a second contact electrode disposed on each of the 1-3 sub-electrode and the 2-3 sub-electrode in each of the first sub-pixel region and the second sub-pixel region, and the second contact electrode and the first contact electrode are disposed on the same layer; and a second intermediate electrode disposed in the region between the second sub-region and the third sub-region in each of the first sub-pixel region and the second sub-pixel region, and the second intermediate electrode and the first contact electrode are integrally disposed with each other on the 2-2 sub-electrode. The second intermediate electrode may connect the first contact electrode on the 2-2 sub-electrode of the second group to the second contact electrode on the 1-3 sub-electrode of the third group in each of the first sub-pixel region and the second sub-pixel region.

[0021] In an embodiment of the present disclosure, each of the first sub-pixel region and the second sub-pixel region may further include a fourth sub-region disposed below the third sub-region in the second direction.

[0022] Here, the first electrode of each of the first sub-pixel region and the second sub-pixel region may further include a 1-4 sub-electrode disposed in the fourth sub-region. The second electrode of each of the first sub-pixel region and the second sub-pixel region may further include a 2-4 sub-electrode disposed in the fourth sub-region. The light-emitting element of each of the first sub-pixel region and the second sub-pixel region may further include a fourth light-emitting element disposed between the 1-4 sub-electrode and the 2-4 sub-electrode.

[0023] In an embodiment of the present disclosure, the 1-4 sub-electrode and the 2-4 sub-electrode together with the fourth light-emitting element connected in parallel therebetween may form a fourth group in each of the first sub-pixel region and the second sub-pixel region.

[0024] In an embodiment of the present disclosure, the pixel may further include: a third contact electrode disposed on each of the 1-4th sub-electrode and the 2-4th sub-electrode in each of the first sub-pixel region and the second sub-pixel region, and the third contact electrode and the second contact electrode are disposed on the same layer; and a third intermediate electrode disposed in the region between the third sub-region and the fourth sub-region in each of the first sub-pixel region and the second sub-pixel region, and the third intermediate electrode and the second contact electrode are integrally disposed with each other on the 2-3rd sub-electrode. The third intermediate electrode may connect the second contact electrode on the 2-3rd sub-electrode of the third group to the third contact electrode on the 1-4th sub-electrode of the fourth group in each of the first sub-pixel region and the second sub-pixel region.

[0025] In an embodiment of the present disclosure, the pixel may further include a third sub-pixel region, which is disposed adjacent to the second sub-pixel region in a first direction and includes a first sub-region, a second sub-region, and a third sub-region spaced apart from each other in a second direction. Here, the third sub-pixel region may include: a first electrode including a 1-1st sub-electrode disposed in the first sub-region, a 1-2nd sub-electrode disposed in the second sub-region and spaced apart from the 1-1st sub-electrode, and a 1-3rd sub-electrode disposed in the third sub-region and spaced apart from the 1-2nd sub-electrode; a second electrode including a 2-1st sub-electrode disposed in the first sub-region, a 2-2nd sub-electrode disposed in the second sub-region and spaced apart from the 2-1st sub-electrode, and a 2-3rd sub-electrode disposed in the third sub-region and spaced apart from the 2-2nd sub-electrode; a light-emitting element disposed between the first electrode and the second electrode; a third driving transistor electrically connected to the 1-1st sub-electrode; a contact electrode disposed on each of the 1-1st sub-electrode and the 2-2nd sub-electrode and the 2-1st sub-electrode and the 2-2nd sub-electrode, and the contact electrode and the first contact electrode are disposed on the same layer; and an intermediate electrode disposed in each of the region between the first sub-region and the second sub-region and the region between the second sub-region and the third sub-region.

[0026] In an embodiment of the present disclosure, the intermediate electrode may include a first sub-intermediate electrode integrated with the contact electrode in the third sub-pixel region on the 2-1st sub-electrode, and a second sub-intermediate electrode integrated with the contact electrode on the 2-2nd sub-electrode. The first sub-intermediate electrode may electrically connect the 2-1st sub-electrode to the 1-2nd sub-electrode. The second sub-intermediate electrode may electrically connect the 2-2nd sub-electrode to the 1-3rd sub-electrode.

[0027] A display device according to an embodiment of the present disclosure may include: a substrate including a display region and a non-display region, wherein the display region includes a plurality of pixel regions; and pixels disposed in each of the pixel regions.

[0028] In an embodiment of the present disclosure, a pixel may include: a first sub-pixel region and a second sub-pixel region, which are adjacent to each other in a first direction, and each includes a first sub-region, a second sub-region, and a third sub-region that are spaced apart from each other in a second direction intersecting the first direction; a first electrode disposed in each of the first sub-pixel region and the second sub-pixel region, and including a 1-1 sub-electrode disposed in the first sub-region, a 1-2 sub-electrode disposed in the second sub-region, and a 1-3 sub-electrode disposed in the third sub-region; a second electrode disposed in each of the first sub-pixel region and the second sub-pixel region, and including a 2-1 sub-electrode disposed in the first sub-region and spaced apart from the 1-1 sub-electrode, a 2-2 sub-electrode disposed in the second sub-region and spaced apart from the 1-2 sub-electrode, and a 2-3 sub-electrode disposed in the third sub-region and spaced apart from the 1-3 sub-electrode; a plurality of light-emitting elements disposed between the first electrode and the second electrode in each of the first sub-pixel region and the second sub-pixel region; a first driving transistor and a second driving transistor, the first driving transistor being connected to the 1-1 sub-electrode of the first sub-pixel region, and the second driving transistor being connected to the 1-1 sub-electrode of the second sub-pixel region; a contact electrode disposed on each of the 1-1 sub-electrode to the 1-3 sub-electrode and the 2-1 sub-electrode to the 2-3 sub-electrode; and a first intermediate electrode and a second intermediate electrode disposed in each of the first sub-pixel region and the second sub-pixel region, the first intermediate electrode being disposed in a region between the first sub-region and the second sub-region, and the second intermediate electrode being disposed in a region between the second sub-region and the third sub-region.

[0029] In an embodiment of the present disclosure, the first intermediate electrode and the contact electrode may be integrated with each other on the 2-1 sub-electrode and electrically connect the 2-1 sub-electrode to the 1-2 sub-electrode. The second intermediate electrode and the contact electrode may be integrated with each other on the 2-2 sub-electrode and electrically connect the 2-2 sub-electrode to the 1-3 sub-electrode.

[0030] A method of manufacturing a display device according to an embodiment may include: disposing a pixel in a pixel region, where the pixel region includes a first sub-pixel region and a second sub-pixel region, the first sub-pixel region and the second sub-pixel region being adjacent to each other in a first direction, and each including a first sub-region, a second sub-region, and a third sub-region that are spaced apart from each other in a second direction intersecting the first direction. Here, disposing the pixel may include forming a first driving transistor and a second driving transistor, and forming a display element layer on the first driving transistor and the second driving transistor.

[0031] In an embodiment of the present disclosure, forming the display element layer may include: forming first and second wires spaced apart from each other in each of a first sub-pixel region and a second sub-pixel region; supplying a plurality of light-emitting elements to each of the first sub-pixel region and the second sub-pixel region, and aligning the light-emitting elements by supplying respective alignment voltages to the first and second wires; forming contact electrodes on each of the first and second wires, and forming intermediate electrodes integrated with the contact electrodes in each of a region between the first sub-region and the second sub-region and a region between the second sub-region and the third sub-region; and forming a first-1 sub-electrode, a first-2 sub-electrode, and a first-3 sub-electrode sequentially arranged in a second direction in each of the first sub-pixel region and the second sub-pixel region by removing a part of the first wire, and forming a second-1 sub-electrode, a second-2 sub-electrode, and a second-3 sub-electrode sequentially arranged in the second direction in each of the first sub-pixel region and the second sub-pixel region by removing a part of the second wire.

[0032] In an embodiment of the present disclosure, the intermediate electrode disposed in the region between the first sub-region and the second sub-region may extend from the contact electrode on the second-1 sub-electrode to the contact electrode on the first-2 sub-electrode in a row disposed after the second-1 sub-electrode in a plan view, and electrically connect the second-1 sub-electrode to the first-2 sub-electrode.

[0033] In addition, the intermediate electrode disposed in the region between the second sub-region and the third sub-region may extend from the contact electrode on the second-2 sub-electrode to the contact electrode on the first-3 sub-electrode in a row disposed after the second-2 sub-electrode in a plan view, and electrically connect the second-2 sub-electrode to the first-3 sub-electrode.

[0034] Advantageous Effects

[0035] In a pixel according to an embodiment of the present disclosure, a display device including the pixel, and a method of manufacturing the display device, the light-emitting elements distributed to each of a plurality of sub-emission regions forming each pixel may be connected in a series / parallel combination structure, so that the light output efficiency of the light-emitting elements can be improved, and the light output distribution of the light-emitting elements in the sub-emission regions may be uniform. Description of the Drawings

[0036] Figure 1a is a schematic perspective view showing a light-emitting element according to an embodiment of the present disclosure.

[0037] Figure 1b is a cross-sectional view showing Figure 1a the light-emitting element.

[0038] Figure 2ais a perspective view schematically showing a light-emitting element according to an embodiment of the present disclosure.

[0039] Figure 2b shows Figure 2a a cross-sectional view of the light-emitting element.

[0040] Figure 3a is a perspective view schematically showing a light-emitting element according to an embodiment of the present disclosure.

[0041] Figure 3b shows Figure 3a a cross-sectional view of the light-emitting element.

[0042] Figure 4a is a schematic perspective view showing a light-emitting element according to an embodiment of the present disclosure.

[0043] Figure 4b shows Figure 4a a cross-sectional view of the light-emitting element.

[0044] Figure 5 shows a display device according to an embodiment of the present disclosure, and in particular, is a schematic plan view of a display device using any one of the light-emitting elements shown in Figure 1a , Figure 1b , Figure 2a , Figure 2b , Figure 3a , Figure 3b , Figure 4a and Figure 4b as a light source.

[0045] Figures 6a to 6e is a circuit diagram showing various embodiments of the electrical connection relationships of the components included in one pixel shown in Figure 5 .

[0046] Figures 7a to 7c is a circuit diagram showing different embodiments of the electrical connection relationships of the components included in one pixel shown in Figure 5 .

[0047] Figure 8 shows Figure 5 a schematic plan view of one pixel in the pixel shown.

[0048] Figure 9 is a cross-sectional view taken along line I-I' of Figure 8 .

[0049] Figure 10 is a cross-sectional view taken along line II-II' of Figure 8 .

[0050] Figure 11 is a cross-sectional view taken along line Figure 8A cross-sectional view taken along line III-III'.

[0051] Figure 12 shows Figure 11 another embodiment of the first embankment pattern shown in Figure 8 and is a cross-sectional view corresponding to line III-III' of

[0052] Figure 13 shows Figure 11 another embodiment of the display element layer shown in Figure 8 and is a cross-sectional view corresponding to line III-III' of

[0053] Figure 14 is a plan view showing the drive current flowing through a pixel according to an embodiment of the present disclosure, and for example, shows the flow of the drive current through the pixel of Figure 8

[0054] Figures 15a to 15f is a schematic plan view sequentially showing a method of manufacturing the pixel shown in Figure 8

[0055] Figures 16a to 16f is a cross-sectional view sequentially showing a method of manufacturing the pixel shown in Figure 10

[0056] Figure 17 shows Figure 8 another embodiment of the first connection line to the third connection line shown in

[0057] Figures 18 to 21 is a schematic plan view showing another example of a pixel according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0058] Since the present disclosure allows for various variations and multiple embodiments, specific embodiments will be shown in the drawings and described in detail in the written description. However, this is not intended to limit the present disclosure to a particular mode of practice, and it should be understood that all changes, equivalents, and substitutions that do not depart from the technical scope of the present disclosure are encompassed by the present disclosure.

[0059] ​​​Throughout the disclosure, the same reference numerals are used throughout the various figures and embodiments of the disclosure to denote the same components. For clarity of illustration, the dimensions of the elements in the figures may be exaggerated. It should be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the teachings of the disclosure, the first element discussed below may be referred to as the second element. Similarly, the second element may also be referred to as the first element. In the disclosure, unless the context clearly indicates otherwise, the singular form is also intended to include the plural meaning.

[0060] It should also be understood that when used in this specification, the terms "comprise", "include", "have", etc. indicate the presence of the recited features, wholes, steps, operations, elements, components, and / or combinations thereof, but do not preclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or combinations thereof. Further, in a case where a first portion such as a layer, film, region, or plate is disposed on a second portion, the first portion may not only be directly disposed on the second portion, but also a third portion may be interposed between the first portion and the second portion. Further, in a case where it is indicated that a first portion such as a layer, film, region, or plate is formed on a second portion, the surface of the second portion on which the first portion is formed is not limited to the upper surface of the second portion, but may include other surfaces such as the side surface or the lower surface of the second portion. Conversely, in a case where a first portion such as a layer, film, region, or plate is directly under a second portion, the first portion may be directly under the second portion, and a third portion is not interposed between the first portion and the second portion.

[0061] To describe the disclosure in detail, embodiments of the disclosure and the required details are described with reference to the accompanying drawings so that those of ordinary skill in the art to which the disclosure pertains can easily practice the disclosure. Further, as long as not specifically mentioned in the sentence, the singular form may include the plural form.

[0062] Figure 1a is a perspective view schematically showing a light-emitting element according to an embodiment of the disclosure. Figure 1b shows Figure 1a a cross-sectional view of the light-emitting element. Figure 2a is a perspective view schematically showing a light-emitting element according to an embodiment of the disclosure. Figure 2b shows Figure 2a a cross-sectional view of the light-emitting element. Figure 3a is a perspective view schematically showing a light-emitting element according to an embodiment of the disclosure. Figure 3b shows Figure 3a a cross-sectional view of the light-emitting element. Figure 4ais a schematic perspective view showing a light-emitting element according to an embodiment of the present disclosure. Figure 4b is a cross-sectional view showing Figure 4a the light-emitting element.

[0063] For illustration, reference will be made to Figure 1a 、 Figure 1b 、 Figure 2a 、 Figure 2b 、 Figure 3a and Figure 3b to describe a light-emitting element LD manufactured by an etching method, and then reference will be made to Figure 4a and Figure 4b to describe a light-emitting element LD manufactured by a growth method. In an embodiment of the present disclosure, the type and / or shape of the light-emitting element LD are not limited to Figure 1a 、 Figure 1b 、 Figure 2a 、 Figure 2b 、 Figure 3a 、 Figure 3b 、 Figure 4a and Figure 4b the embodiments shown in.

[0064] Referring to Figure 1a 、 Figure 1b 、 Figure 2a 、 Figure 2b 、 Figure 3a and Figure 3b , the light-emitting element LD may include a first semiconductor layer 11, a second semiconductor layer 13, and an active layer 12 interposed between the first semiconductor layer 11 and the second semiconductor layer 13. For example, the light-emitting element LD may be implemented as an emission stack formed by sequentially stacking the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13.

[0065] In an embodiment of the present disclosure, the light-emitting element LD may be formed in a shape extending in one direction. If the direction in which the light-emitting element LD extends is defined as the longitudinal direction, the light-emitting element LD may have one end and the other end in the extending direction. Either the first semiconductor layer 11 or the second semiconductor layer 13 may be disposed at one end of the light-emitting element LD, and the other of the first semiconductor layer 11 and the second semiconductor layer 13 may be disposed at the other end of the light-emitting element LD.

[0066] The light-emitting element LD may have various shapes. For example, the light-emitting element LD may have a rod-like shape or a bar-like shape extending in the longitudinal direction (i.e., having an aspect ratio greater than 1). In an embodiment of the present disclosure, the length L of the light-emitting element LD in the longitudinal direction may be greater than its diameter (D, or the width of the cross-section). The light-emitting element LD may include a light-emitting diode manufactured to have a small size. For example, it has a length L and / or a diameter D corresponding to the micron scale or the nanometer scale. In an embodiment of the present disclosure, the size of the light-emitting element LD may be changed to meet the requirements (or design conditions) of the lighting device or the self-emitting display device to which the light-emitting element LD will be applied.

[0067] The first semiconductor layer 11 may include, for example, at least one N-type semiconductor layer. For example, the first semiconductor layer 11 may include an N-type semiconductor layer, which may include any one of semiconductor materials such as InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and is doped with a first conductive dopant such as Si, Ge, or Sn. However, the constituent material of the first semiconductor layer 11 is not limited thereto, and various other materials may be used to form the first semiconductor layer 11.

[0068] The active layer 12 may be disposed on the first semiconductor layer 11 and have a single quantum well structure or a multi-quantum well structure. The position of the active layer 12 may be changed in various ways according to the type of the light-emitting element LD. The active layer 12 may emit light having a wavelength ranging from 400 nm to 900 nm and uses a double heterostructure. In an embodiment of the present disclosure, a cladding layer (not shown) doped with a conductive dopant may be formed above and / or below the active layer 12. For example, the cladding layer may be formed of an AlGaN layer or an InAlGaN layer. In an embodiment, materials such as AlGaN or AlInGaN may be used to form the active layer 12, and various other materials may be used to form the active layer 12.

[0069] If an electric field of a predetermined voltage or higher is applied to opposite ends of the light-emitting element LD, the light-emitting element LD emits light by the coupling of electron-hole pairs in the active layer 12. Since the light emission of the light-emitting element LD can be controlled based on the foregoing principle, the light-emitting element LD can be used as a light source for various light-emitting devices and pixels of display devices.

[0070] The second semiconductor layer 13 may be disposed on the active layer 12 and include a semiconductor layer having a type different from that of the first semiconductor layer 11. For example, the second semiconductor layer 13 may include at least one P-type semiconductor layer. For example, the second semiconductor layer 13 may include a P-type semiconductor layer, which may include at least one semiconductor material among InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and is doped with a second conductive dopant such as Mg. However, the material for forming the second semiconductor layer 13 is not limited thereto, and various other materials may be used to form the second semiconductor layer 13.

[0071] In an embodiment of the present disclosure, the first semiconductor layer 11 and the second semiconductor layer 13 may have different widths (or thicknesses) in the longitudinal direction of the light-emitting element LD. For example, the first semiconductor layer 11 may have a width (or thickness) greater than the width (or thickness) of the second semiconductor layer 13 in the longitudinal direction of the light-emitting element LD. Thus, as Figures 1a to 3b shown, the active layer 12 of the light-emitting element LD may be disposed at a position closer to the upper surface of the second semiconductor layer 13 than to the lower surface of the first semiconductor layer 11.

[0072] In an embodiment of the present disclosure, in addition to the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13, the light-emitting element LD may further include an additional electrode 15 disposed on the second semiconductor layer 13. In an embodiment, as Figure 3a and Figure 3b shown, the light-emitting element LD may further include an additional electrode 16 disposed on one end of the first semiconductor layer 11.

[0073] Although each of the additional electrode 15 and the additional electrode 16 may be an ohmic contact electrode, the present disclosure is not limited thereto, and according to an embodiment, each of the additional electrode 15 and the additional electrode 16 may be a Schottky contact electrode. In addition, each of the additional electrode 15 and the additional electrode 16 may include a metal or a metal oxide. For example, chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni), and their oxides (such as ITO) or alloys may be used alone or in combination with each other. However, the present disclosure is not limited thereto.

[0074] The materials included in the corresponding additional electrodes 15 and 16 may be the same as or different from each other. The additional electrodes 15 and 16 may be transparent or translucent. Thus, the light generated from the light-emitting element LD can pass through the additional electrodes 15 and 16 and be emitted outside the light-emitting element LD. In some embodiments, when the light generated from the light-emitting element LD is emitted outside the light-emitting element LD through an area other than the opposite ends of the light-emitting element LD instead of passing through the additional electrodes 15 and 16, the additional electrodes 15 and 16 may include opaque metals.

[0075] In an embodiment of the present disclosure, the light-emitting element LD may further include an insulating layer 14. However, in some embodiments, the insulating layer 14 may be omitted or may be provided to cover only some of the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13.

[0076] The insulating layer 14 can prevent the active layer 12 from short-circuiting due to contact with a conductive material other than the first semiconductor layer 11 and the second semiconductor layer 13. In addition, due to the insulating layer 14, the occurrence of defects on the surface of the light-emitting element LD can be minimized, thereby improving the lifespan and efficiency of the light-emitting element LD. In the case where a plurality of light-emitting elements LD are arranged in close contact with each other, the insulating layer 14 can prevent an undesired short circuit from occurring between the light-emitting elements LD. As long as the short circuit between the active layer 12 and an external conductive material can be prevented, the provision of the insulating layer 14 is not limited.

[0077] As Figure 1a and Figure 1b shown, the insulating layer 14 can be provided in a shape surrounding the outer peripheral surface of the emission stack including the first semiconductor layer 11, the active layer 12, the second semiconductor layer 13, and the additional electrode 15. For illustration, Figure 1a the insulating layer 14 with a part of it removed is shown. The first semiconductor layer 11, the active layer 12, the second semiconductor layer 13, and the additional electrode 15 included in the light-emitting element LD can be surrounded by the insulating layer 14.

[0078] Although in the above-mentioned embodiments, the insulating layer 14 is described as surrounding the entire outer peripheral surface of the first semiconductor layer 11, the active layer 12, the second semiconductor layer 13, and the additional electrode 15, the present disclosure is not limited thereto.

[0079] In some embodiments, as Figure 2a and Figure 2bAs shown, the insulating layer 14 may surround the respective outer peripheral surfaces of the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13, and may not surround the entire outer peripheral surface of the additional electrode 15 provided on the second semiconductor layer 13, or may only surround a part of the outer peripheral surface of the additional electrode 15 and not surround the other part of the outer peripheral surface of the additional electrode 15. Here, the insulating layer 14 may allow at least the opposite ends of the light-emitting element LD to be exposed to the outside. For example, the insulating layer 14 may allow not only the additional electrode 15 provided at one end of the second semiconductor layer 13 to be exposed to the outside, but also one end of the first semiconductor layer 11 to be exposed to the outside. In an embodiment, as Figure 3a and Figure 3b shown, when the additional electrode 15 and the additional electrode 16 are respectively provided at the opposite ends of the light-emitting element LD, the insulating layer 14 may allow at least a part of each of the additional electrode 15 and the additional electrode 16 to be exposed to the outside. Optionally, in an embodiment, the insulating layer 14 may not be provided.

[0080] In an embodiment of the present disclosure, the insulating layer 14 may include a transparent insulating material. For example, the insulating layer 14 may include at least one insulating material selected from the group consisting of SiO2, Si3N4, Al2O3, and TiO2, but is not limited thereto. In other words, various materials having insulating properties may be employed.

[0081] If the insulating layer 14 is provided on the surface of the light-emitting element LD, a short circuit between the active layer 12 and a first electrode and / or a second electrode (not shown) can be prevented. In addition, due to the insulating layer 14, the occurrence of defects on the surface of the light-emitting element LD can be minimized, thereby improving the lifetime and efficiency of the light-emitting element LD. When a plurality of light-emitting elements LD are provided in close contact with each other, the insulating layer 14 can prevent an undesired short circuit from occurring between the light-emitting elements LD.

[0082] The light-emitting element LD can be used as a light source for various display devices. The light-emitting element LD can be manufactured by a surface treatment process. For example, the light-emitting element LD can be surface-treated such that when a plurality of light-emitting elements LD are mixed with a fluid solution (or solvent) and supplied to each emission region (for example, the emission region of each pixel or the emission region of each sub-pixel), the light-emitting elements LD can be uniformly distributed in the solution instead of being unevenly aggregated.

[0083] The light-emitting device including the above-mentioned light-emitting element LD can be used not only in a display device but also in various devices that require a light source. For example, in the case where a plurality of light-emitting elements LD are provided in the emission region of each pixel of a display panel, the light-emitting element LD can be used as a light source of the pixel. However, the application fields of the light-emitting element LD are not limited to the above-mentioned examples. For example, the light-emitting element LD can also be used in other types of devices that require a light source, such as a lighting device.

[0084] Next, with reference to Figure 4a and Figure 4b a light-emitting element LD manufactured by a growth method will be described.

[0085] The following description of the light-emitting element LD manufactured by a growth method will focus on the differences from the above-mentioned embodiments, and the components of the light-emitting element LD that are not separately explained in the following description may be consistent with the components of the foregoing embodiments. The same reference numerals will be used to denote the same components, and similar reference numerals will be used to denote similar components.

[0086] With reference to Figure 4a and Figure 4b , a light-emitting element LD according to an embodiment of the present disclosure may include a first semiconductor layer 11, a second semiconductor layer 13, and an active layer 12 interposed between the first semiconductor layer 11 and the second semiconductor layer 13. In some embodiments, the light-emitting element LD may include an emission pattern 10 having a core-shell structure. The emission pattern 10 may include a first semiconductor layer 11 provided in a central portion of the light-emitting element LD, an active layer 12 surrounding at least one side of the first semiconductor layer 11, a second semiconductor layer 13 surrounding at least one side of the active layer 12, and an additional electrode 15 surrounding at least one side of the second semiconductor layer 13.

[0087] The light-emitting element LD can be formed in a shape of a multi-pyramid extending in one direction. For example, the light-emitting element LD can have a shape of a hexagonal pyramid. If the extending direction of the light-emitting element LD is defined as the longitudinal direction, the light-emitting element LD can have one end portion (or lower end portion) and the other end portion (or upper end portion) in the longitudinal direction. A part of either the first semiconductor layer 11 or the second semiconductor layer 13 on one end portion (or lower end portion) of the light-emitting element LD can be exposed to the outside. A part of the other of the first semiconductor layer 11 and the second semiconductor layer 13 on the other end portion (or upper end portion) of the light-emitting element LD can be exposed to the outside. For example, a part of the first semiconductor layer 11 on one end portion (or lower end portion) of the light-emitting element LD can be exposed, and a part of the second semiconductor layer 13 on the other end portion (or upper end portion) of the light-emitting element LD can be exposed. In an embodiment, in the case where the light-emitting element LD can include the additional electrode 15, a part of the additional electrode 15 surrounding at least one side of the second semiconductor layer 13 on the other end portion (or upper end portion) of the light-emitting element LD can be exposed.

[0088] In an embodiment of the present disclosure, the first semiconductor layer 11 can be disposed in the core (i.e., the central (or middle) portion) of the light-emitting element LD. The light-emitting element LD can have a shape corresponding to the shape of the first semiconductor layer 11. For example, if the first semiconductor layer 11 has a shape of a hexagonal pyramid, the light-emitting element LD and the emission pattern 10 can each also have a shape of a hexagonal pyramid.

[0089] The active layer 12 can be disposed and / or formed in a shape surrounding the outer peripheral surface of the first semiconductor layer 11 in the longitudinal direction of the light-emitting element LD. Specifically, the active layer 12 can be disposed and / or formed in a shape surrounding the region of the first semiconductor layer 11 except for the lower end portion among the opposite end portions of the first semiconductor layer 11 in the longitudinal direction of the light-emitting element LD.

[0090] The second semiconductor layer 13 can be disposed and / or formed in a shape surrounding the active layer 12 in the longitudinal direction of the light-emitting element LD, and can include a semiconductor layer having a type different from the type of the first semiconductor layer 11. For example, the second semiconductor layer 13 can include at least one P-type semiconductor layer.

[0091] In an embodiment of the present disclosure, the light-emitting element LD can include the additional electrode 15 surrounding at least one side of the second semiconductor layer 13. The additional electrode 15 can be an ohmic contact electrode electrically connected to the second semiconductor layer 13, but the present disclosure is not limited thereto.

[0092] As described above, the light-emitting element LD may have a hexagonal pyramid shape having opposite ends protruding outward, and the light-emitting element LD may be implemented as an emission pattern 10 having a core-shell structure including a first semiconductor layer 11 disposed in its central portion, an active layer 12 surrounding the first semiconductor layer 11, a second semiconductor layer 13 surrounding the active layer 12, and an additional electrode 15 surrounding the second semiconductor layer 13. The first semiconductor layer 11 may be disposed in one end (or lower end) of the light-emitting element LD having a hexagonal pyramid shape, and the additional electrode 15 may be disposed in the other end (or upper end) of the light-emitting element LD.

[0093] In an embodiment, the light-emitting element LD may further include an insulating layer 14 disposed on the outer peripheral surface of the emission pattern 10 having a core-shell structure. The insulating layer 14 may include a transparent insulating material.

[0094] Figure 5 A display device according to an embodiment of the present disclosure is shown, and for example, is a schematic plan view of a display device using any one of the light-emitting elements shown in Figure 1a 、 Figure 1b 、 Figure 2a 、 Figure 2b 、 Figure 3a 、 Figure 3b 、 Figure 4a and Figure 4b as a light source.

[0095] For illustration, Figure 5 the structure of the display device is schematically shown, which focuses on the display area for displaying an image. In some embodiments, although not shown, at least one driving circuit (e.g., a scan driver and a data driver) and / or a plurality of lines may also be provided in the display device.

[0096] Referring to Figure 1a 、 Figure 1b 、 Figure 2a 、 Figure 2b 、 Figure 3a 、 Figure 3b 、 Figure 4a 、 Figure 4b and Figure 5 , a display device according to an embodiment of the present disclosure may include a substrate SUB, a plurality of pixels PXL disposed on the substrate SUB and each including at least one light-emitting element LD, a driver (not shown) disposed on the substrate SUB and driving the pixels PXL, and a line assembly (not shown) disposed to connect the pixels PXL to the driver.

[0097] According to the method of driving the light-emitting element LD, the display device can be divided into a passive matrix display device and an active matrix display device. For example, when the display device is implemented as an active matrix type, each of the pixels PXL may include a driving transistor that controls the amount of current to be supplied to the light-emitting element LD, and a switching transistor that transmits a data signal to the driving transistor.

[0098] Recently, considering resolution, contrast, and operating speed, active matrix display devices that selectively turn on each pixel PXL have become mainstream. However, the present disclosure is not limited thereto. For example, passive matrix display devices in which pixels PXL can be turned on in groups can also employ components (e.g., a first electrode and a second electrode) for driving the light-emitting element LD.

[0099] The substrate SUB may include a display area DA and a non-display area NDA.

[0100] In an embodiment, the display area DA may be disposed in the central portion of the display device, and the non-display area NDA may be disposed in the peripheral portion of the display device to surround the display area DA. The positions of the display area DA and the non-display area NDA are not limited thereto, and the positions of the display area DA and the non-display area NDA may be changed.

[0101] The display area DA may be an area in which pixels PXL for displaying an image are disposed. The non-display area NDA may be an area in which drivers for driving the pixels PXL and some line components for connecting the pixels PXL to the drivers are disposed.

[0102] The display area DA may have various shapes. For example, the display area DA may be set to a closed polygon shape including linear sides. As a further example, the display area DA may be set to a circular shape and / or an elliptical shape including curved sides. Alternatively, the display area DA may be set to various shapes such as a semi-circular shape and a semi-elliptical shape including linear sides and curved sides.

[0103] The non-display area NDA may be disposed on at least one side of the display area DA. In an embodiment of the present disclosure, the non-display area NDA may surround the perimeter (or edge) of the display area DA.

[0104] The substrate SUB may include a transparent insulating material that allows light to pass through.

[0105] The substrate SUB may be a rigid substrate. For example, the rigid substrate may be one of a glass substrate, a quartz substrate, a glass-ceramic substrate, and a crystalline glass substrate. The substrate SUB may be a flexible substrate.

[0106] A region of the substrate SUB may be set as a display area DA in which pixels PXL are provided, and another region of the substrate SUB may be set as a non-display area NDA. For example, the substrate SUB may include a display area DA and a non-display area NDA provided around the display area DA, and the display area DA includes a plurality of pixel areas in which corresponding pixels PXL are formed.

[0107] The pixels PXL may be provided in the display area DA on the substrate SUB. In an embodiment of the present disclosure, the pixels PXL may be arranged in a stripe or PenTile arrangement structure in the display area DA, but the present disclosure is not limited thereto.

[0108] Each of the pixels PXL may include at least one light-emitting element LD that is driven in response to a corresponding scan signal and a corresponding data signal. The light-emitting element LD may have a small size corresponding to the micron or nanometer level and is connected in parallel to the light-emitting element LD provided adjacent thereto, but the present disclosure is not limited thereto. The light-emitting element LD may form a light source for each pixel PXL.

[0109] Each of the pixels PXL may include at least one light source driven by a predetermined signal (e.g., a scan signal and a data signal) and / or a predetermined power supply (e.g., a first driving power supply and a second driving power supply). For example, each of the pixels PXL may include the light-emitting element LD shown in each of the Figures 1a to 4b embodiments, for example, at least one ultra-small light-emitting element LD having a small size corresponding to the nanometer or micron level. However, in an embodiment of the present disclosure, the type of the light-emitting element LD that can be used as a light source for each of the pixels PXL is not limited thereto.

[0110] In an embodiment of the present disclosure, the color, type, and / or number of the pixels PXL are not particularly limited. For example, the color of the light emitted from each pixel PXL can be changed in various ways.

[0111] The driver may provide a predetermined signal and a predetermined power voltage to each of the pixels PXL through a line assembly, and thus control the operation of the pixels PXL. For illustration, in Figure 5 the line assembly is omitted.

[0112] The driver may include a scan driver, an emission driver, a data driver, and a timing controller. Among them, the scan driver provides a scan signal to the pixels PXL through scan lines, the emission driver provides an emission control signal to the pixels PXL through emission control lines, and the data driver provides a data signal to the pixels PXL through data lines. The timing controller may control the scan driver, the emission driver, and the data driver.

[0113] Figures 6a to 6e is a diagram showing the components included in Figure 5Circuit diagrams of various embodiments of the electrical connection relationships of components in a pixel shown therein.

[0114] For example, Figures 6a to 6e Different embodiments of the electrical connection relationships of the components included in pixel PXL that can be used in an active display device are shown. However, the types of components included in pixel PXL to which the embodiments of the present disclosure can be applied are not limited thereto.

[0115] In Figures 6a to 6e not only the components in each of the pixels PXL shown in Figure 5 are included, but also the regions where the components are provided are covered in the definition of the term "pixel PXL". In an embodiment, each pixel PXL shown in Figures 6a to 6e can be any one of the pixels PXL provided in the display device of Figure 5 . The pixels PXL can have substantially the same or similar structures to each other.

[0116] Referring to Figures 1a to 4b , Figure 5 and Figures 6a to 6e , each pixel PXL (hereinafter referred to as "pixel") can include an emission unit EMU that generates light having a luminance corresponding to a data signal. The pixel PXL can also selectively include a pixel circuit 144 that drives the emission unit EMU.

[0117] In an embodiment, the emission unit EMU can include a plurality of light-emitting elements LD connected in parallel between a first power line PL1 to which a first driving power supply VDD is applied and a second power line PL2 to which a second driving power supply VSS is applied. For example, the emission unit EMU can include a first electrode EL1 (or "first alignment electrode") connected to the first driving power supply VDD via the pixel circuit 144 and the first power line PL1, a second electrode EL2 (or "second alignment electrode") connected to the second driving power supply VSS through the second power line PL2, and a plurality of light-emitting elements LD connected in parallel to each other in the same direction between the first electrode EL1 and the second electrode EL2. In an embodiment of the present disclosure, the first electrode EL1 can be an anode electrode, and the second electrode EL2 can be a cathode electrode.

[0118] In an embodiment of the present disclosure, each of the light-emitting elements LD included in the emission unit EMU may include a first end connected to a first driving power supply VDD through a first electrode EL1, and a second end connected to a second driving power supply VSS through a second electrode EL2. The first driving power supply VDD and the second driving power supply VSS may have different potentials. For example, the first driving power supply VDD may be set as a high-potential power supply, and the second driving power supply VSS may be set as a low-potential power supply. Here, during the emission period of the pixel PXL, the potential difference between the first driving power supply VDD and the second driving power supply VSS may be set to a value equal to or greater than the threshold voltage of the light-emitting element LD.

[0119] As described above, the light-emitting elements LD connected in parallel to each other in the same direction (e.g., in the forward direction) between the first electrode EL1 and the second electrode EL2 may form corresponding effective light sources, where voltages having different potentials are respectively supplied to the first electrode EL1 and the second electrode EL2. The effective light sources may be grouped to form the emission unit EMU of the pixel PXL.

[0120] The light-emitting elements LD of the emission unit EMU may emit light having a brightness corresponding to the driving current supplied thereto through the pixel circuit 144. For example, during each frame period, the pixel circuit 144 may supply a driving current corresponding to the gray level of the corresponding frame data to the emission unit EMU. The driving current supplied to the emission unit EMU may be divided among the light-emitting elements LD connected to each other in the same direction. Therefore, each of the light-emitting elements LD may emit light having a brightness corresponding to the current applied thereto, such that the emission unit EMU may emit light having a brightness corresponding to the driving current.

[0121] Although Figures 6a to 6e an embodiment in which the light-emitting elements LD are connected to each other in the same direction between the first driving power supply VDD and the second driving power supply VSS is shown, the present disclosure is not limited thereto. In an embodiment, the emission unit EMU may further include at least one ineffective light source in addition to the light-emitting elements LD forming the corresponding effective light sources. For example, as Figure 6d and Figure 6eAs shown, at least one reverse light-emitting element LDr may also be connected between the first electrode EL1 and the second electrode EL2 of the emission unit EMU. The reverse light-emitting element LDr and the light-emitting element LD forming an effective light source may be connected in parallel with each other between the first electrode EL1 and the second electrode EL2. Here, the reverse light-emitting element LDr may be connected between the first electrode EL1 and the second electrode EL2 in a direction opposite to that of the light-emitting element LD. Even when a predetermined driving voltage (e.g., a forward-direction driving voltage) is applied between the first electrode EL1 and the second electrode EL2, the reverse light-emitting element LDr remains disabled. Therefore, current basically does not flow through the reverse light-emitting element LDr.

[0122] The pixel circuit 144 may be connected to the scan line Si and the data line Dj of the corresponding pixel PXL. For example, if the pixel PXL is provided in the i-th row (i is a positive integer) and the j-th column (j is a positive integer) of the display area DA, the pixel circuit 144 of the pixel PXL may be connected to the i-th scan line Si and the j-th data line Dj of the display area DA. In an embodiment, as Figure 6a and Figure 6b shown, the pixel circuit 144 may include a first transistor T1, a second transistor T2, and a storage capacitor Cst. The structure of the pixel circuit 144 is not limited to Figure 6a and Figure 6b the embodiment shown.

[0123] First, referring to Figure 6a , the pixel circuit 144 may include a first transistor T1, a second transistor T2, and a storage capacitor Cst.

[0124] A first terminal of the first transistor T1 (switching transistor) may be connected to the j-th data line Dj, and a second terminal of the first transistor T1 may be connected to the first node N1. Here, the first terminal and the second terminal of the first transistor T1 are different terminals, and for example, if the first terminal is the source electrode, the second terminal may be the drain electrode. The gate electrode of the first transistor T1 may be connected to the i-th scan line Si.

[0125] When a scan signal having a voltage (e.g., a low-level voltage) capable of turning on the first transistor T1 is supplied from the i-th scan line Si, the first transistor T1 turns on to electrically connect the j-th data line Dj and the first node N1. Here, the data signal of the corresponding frame is supplied to the j-th data line Dj, so that the data signal is transmitted to the first node N1. The data signal transmitted to the first node N1 may be stored in the storage capacitor Cst.

[0126] The first terminal of the second transistor T2 (driving transistor) may be connected to the first driving power supply VDD, and the second terminal of the second transistor T2 may be electrically connected to the first electrode EL1 of the light-emitting element LD. The gate electrode of the second transistor T2 may be connected to the first node N1. In this way, the second transistor T2 can control the amount of driving current to be supplied to the light-emitting element LD in response to the voltage of the first node N1.

[0127] One electrode of the storage capacitor Cst may be connected to the first driving power supply VDD, and the other electrode of the storage capacitor Cst may be connected to the first node N1. The storage capacitor Cst is charged with a voltage corresponding to the data signal supplied to the first node N1, and holds the charged voltage until a data signal for a subsequent frame is supplied.

[0128] Figure 6a and Figure 6b Each shows a pixel circuit 144 including a first transistor T1, a storage capacitor Cst, and a second transistor T2, where the first transistor T1 transmits a data signal to the pixel PXL, the storage capacitor Cst stores the data signal, and the second transistor T2 supplies a driving current corresponding to the data signal to the light-emitting element LD.

[0129] However, the present disclosure is not limited thereto, and the structure of the pixel circuit 144 can be changed in various ways. For example, the pixel circuit 144 may further include at least one transistor element (such as a transistor element for compensating the threshold voltage of the second transistor T2, a transistor element for initializing the first node N1, and / or a transistor element for controlling the emission time of the light-emitting element LD) or other circuit elements (such as a boosting capacitor for boosting the voltage of the first node N1).

[0130] In addition, although in Figure 6a , the transistors (for example, the first transistor T1 and the second transistor T2) included in the pixel circuit 144 are shown to be formed of P-type transistors, the present disclosure is not limited thereto. In other words, at least one of the first transistor T1 and the second transistor T2 included in the pixel circuit 144 can be changed to an N-type transistor.

[0131] Referring to Figures 1a to 4b , Figure 5 and Figure 6b , the first transistor T1 and the second transistor T2 according to an embodiment of the present disclosure can be formed of N-type transistors. Except for changes in the connection positions of some components due to the change in transistor type, Figure 6b the configuration and operation of the pixel circuit 144 shown in Figure 6a are similar to the configuration and operation of the pixel circuit 144 in

[0132] In an embodiment of the present disclosure, Figure 6b the pixel circuit 144 shown in may include a first transistor T1 and a second transistor T2 formed of N-type transistors, and a storage capacitor Cst. When the first transistor T1 and the second transistor T2 are formed of N-type transistors, an emission unit EMU may be connected between a first driving power supply VDD and the pixel circuit 144 to ensure the stability of the storage capacitor Cst, where the storage capacitor Cst is charged with a voltage corresponding to a data signal supplied to a first node N1. Here, the present disclosure is not limited thereto. In an embodiment, Figure 6b the emission unit EMU shown in may be connected between the pixel circuit 144 and a second driving power supply VSS. In an embodiment of the present disclosure, the configuration of the pixel circuit 144 is not limited to Figure 6a and Figure 6b the embodiments shown in. For example, the pixel circuit 144 may be formed in the same manner as the embodiments shown in Figure 6c and Figure 6d .

[0133] As Figure 6c and Figure 6d shown, the pixel circuit 144 may also be connected to at least another scan line. For example, the pixel PXL disposed in the i-th row of the display area DA may also be connected to the (i - 1)-th scan line Si-1 and / or the (i + 1)-th scan line Si+1. In an embodiment, the pixel circuit 144 may be connected not only to the first driving power supply VDD and the second driving power supply VSS, but also to a third power supply. For example, the pixel circuit 144 may also be connected to an initialization power supply Vint.

[0134] The pixel circuit 144 may include a first transistor T1 to a seventh transistor T7 and a storage capacitor Cst.

[0135] One electrode (e.g., a source electrode) of the first transistor T1 (a driving transistor) may be connected to the first driving power supply VDD via a fifth transistor T5, and the other electrode (e.g., a drain electrode) of the first transistor T1 may be connected to one end of a light-emitting element LD via a sixth transistor T6. The gate electrode of the first transistor T1 may be connected to the first node N1. The first transistor T1 may control a driving current flowing between the first driving power supply VDD and the second driving power supply VSS via the light-emitting element LD in response to the voltage of the first node N1. The aforementioned first transistor T1 may have the same configuration as that of the second transistor T2 described with reference to Figure 6a .

[0136] The second transistor T2 (switching transistor) may be connected between the j-th data line Dj connected to the pixel PXL and the source electrode of the first transistor T1. The gate electrode of the second transistor T2 may be connected to the i-th scan line Si, and the i-th scan line Si is connected to the pixel PXL. In the case where a scan signal having a gate-on voltage (e.g., a low-level voltage) is supplied from the i-th scan line Si, the second transistor T2 may be turned on to electrically connect the j-th data line Dj to the source electrode of the first transistor T1. Therefore, if the second transistor T2 is turned on, the data signal supplied from the j-th data line Dj may be transmitted to the first transistor T1. The aforementioned second transistor T2 may have the same configuration as that of the first transistor T1 described with reference to Figure 6a the configuration described above.

[0137] The third transistor T3 may be connected between the drain electrode of the first transistor T1 and the first node N1. The gate electrode of the third transistor T3 may be connected to the i-th scan line Si. In the case where a scan signal having a gate-on voltage is supplied from the i-th scan line Si, the third transistor T3 may be turned on to electrically connect the drain electrode of the first transistor T1 to the first node N1.

[0138] The fourth transistor T4 may be connected between the first node N1 and the initialization power line to which the initialization power supply Vint is to be applied. The gate electrode of the fourth transistor T4 may be connected to the previous scan line, e.g., the (i - 1)-th scan line Si-1. In the case where a scan signal having a gate-on voltage is supplied to the (i - 1)-th scan line Si-1, the fourth transistor T4 may be turned on so that the voltage of the initialization power supply Vint may be transmitted to the first node N1. Here, the initialization power supply Vint may have a voltage equal to or less than the minimum voltage of the data signal.

[0139] The fifth transistor T5 may be connected between the first driving power supply VDD and the first transistor T1. The gate electrode of the fifth transistor T5 may be connected to the corresponding emission control line, e.g., the i-th emission control line Ei. In the case where an emission control signal having a gate-off voltage is supplied to the i-th emission control line Ei, the fifth transistor T5 may be turned off, and in other cases, it may be turned on.

[0140] The sixth transistor T6 may be connected between the first transistor T1 and the first end portion (i.e., the second node N2) of the light-emitting element LD. The gate electrode of the sixth transistor T6 may be connected to the i-th emission control line Ei. In the case where an emission control signal having a gate-off voltage is supplied to the i-th emission control line Ei, the sixth transistor T6 may be turned off, and in other cases, it may be turned on.

[0141] The seventh transistor T7 can be connected between the initialization power line and the first end of the light-emitting element LD. The gate electrode of the seventh transistor T7 can be connected to any one of the scan lines in the subsequent group, for example, connected to the (i + 1)-th scan line Si+1. When a scan signal with a gate-on voltage is provided to the (i + 1)-th scan line Si+1, the seventh transistor T7 can be turned on, so that the voltage of the initialization power supply Vint can be supplied to the first end of the light-emitting element LD.

[0142] The storage capacitor Cst can be connected between the first driving power supply VDD and the first node N1. The storage capacitor Cst can store a voltage corresponding to both the data signal applied to the first node N1 and the threshold voltage of the first transistor T1 during each frame period.

[0143] Although in Figure 6a and Figure 6d the transistors included in the pixel circuit 144 (e.g., the first transistor T1 to the seventh transistor T7) are shown to be formed of P-type transistors, the present disclosure is not limited thereto. For example, at least one of the first transistor T1 to the seventh transistor T7 can be changed to an N-type transistor.

[0144] In an embodiment of the present disclosure, the configuration of the pixel circuit 144 is not limited to the Figures 6a to 6d embodiment shown in Figure 6e For example, the pixel circuit 144 can be formed in the same manner as the embodiment shown in

[0145] As Figure 6e shown, the pixel circuit 144 can also be connected to the control line CLi and the sense line SENj. For example, the pixel circuit 144 of the pixel PXL disposed in the i-th row and the j-th column of the display area DA can be connected to the i-th control line CLi and the j-th sense line SENj of the display area DA. The above-described pixel circuit 144, in addition to including Figure 6a and Figure 6b the first transistor T1 and the second transistor T2 shown in

[0146] The third transistor T3 is connected between the second transistor T2 and the j-th sense line SENj. For example, one electrode of the third transistor T3 can be connected to a terminal (e.g., the source electrode) of the second transistor T2 connected to the first electrode EL1, and the other electrode of the third transistor T3 can be connected to the j-th sense line SENj. In the case where the sense line is omitted, the gate electrode of the third transistor T3 can be connected to the j-th data line Dj.

[0147] In an embodiment, the gate electrode of the third transistor T3 is connected to the i-th control line CLi. In the case where the i-th control line CLi is omitted, the gate electrode of the third transistor T3 may be connected to the i-th scan line Si. The third transistor T3 may be turned on by a control signal having a gate turn-on voltage (e.g., a high-level voltage) and supplied to the i-th control line CLi during a predetermined sensing period, so that the j-th sensing line SENj and the second transistor T2 can be electrically connected to each other.

[0148] In an embodiment, the sensing period may be a period for extracting characteristic information (e.g., the threshold voltage of the second transistor T2, etc.) of each of the pixels PXL provided in the display area DA. During the above-mentioned sensing period, the second transistor T2 may be turned on by supplying a predetermined reference voltage capable of turning on the second transistor T2 to the first node N1 via the j-th data line Dj and the first transistor T1, or by connecting each pixel PXL to a current source, etc. In addition, the second transistor T2 may turn on the third transistor T3 by supplying a control signal having a gate turn-on voltage to connect to the j-th sensing line SENj. Therefore, the characteristic information including the threshold voltage of the second transistor T2, etc. of each pixel PXL can be extracted through the j-th sensing line SENj. The extracted characteristic information can be used to convert image data to compensate for the characteristic deviation between the pixels PXL.

[0149] Although Figure 6e An embodiment is shown in which all of the first transistor T1 to the third transistor T3 are N-type transistors, but the present disclosure is not limited thereto. For example, at least one of the first transistor T1 to the third transistor T3 may be changed to a P-type transistor. In addition, although Figure 6e An embodiment is shown in which the emission unit EMU is connected between the pixel circuit 144 and the second driving power supply VSS, but the emission unit EMU may be connected between the first driving power supply VDD and the pixel circuit 144.

[0150] Although Figures 6a to 6e An embodiment is shown in which all the light-emitting elements LD of each emission unit EMU are connected in parallel with each other, but the present disclosure is not limited thereto. In an embodiment, the emission unit EMU may include at least one series group including a plurality of light-emitting elements LD connected in parallel with each other. In other words, the emission unit EMU may be formed of a series / parallel combination structure. The foregoing configuration will be described below with reference to Figures 7a to 7c Description of the foregoing configuration.

[0151] The structure of the pixel PXL applicable to the present disclosure is not limited to Figures 6a to 6eThe embodiment shown in, and the corresponding pixel PXL may have various structures. In an embodiment of the present disclosure, each pixel PXL may be formed as a passive light-emitting display device or the like. In this case, the pixel circuit 144 may be omitted, and opposite ends of the light-emitting element LD included in the emission unit EMU may be directly connected to the scan lines Si-1, Si, and Si+1, the j-th data line Dj, the first power line PL1 to which the first driving power supply VDD is to be applied, the second power line PL2 to which the second driving power supply VSS is to be applied, and / or a predetermined control line.

[0152] Figures 7a to 7c is a circuit diagram showing different embodiments of the electrical connection relationship of the components included in Figure 5 one pixel PXL shown in. As Figures 7a to 7c shown in, the emission unit EMU of each pixel PXL may include a plurality of series groups connected to each other in sequence. In the following description of the Figures 7a to 7c embodiment of, the detailed description of the components similar or identical to the components of the Figures 6a to 6e embodiment, such as the detailed description of the pixel circuit 144, will be omitted to avoid redundant description.

[0153] Although Figures 7a to 7c shows that the i-th scan line Si connected to the pixel circuit 144 intersects the first power line PL1, the i-th scan line Si and the first power line PL1 are insulated from each other and electrically disconnected from each other.

[0154] First, referring to Figure 7a , the emission unit EMU may include a plurality of light-emitting elements connected in series to each other. For example, the emission unit EMU may include a first light-emitting element LD1, a second light-emitting element LD2, a third light-emitting element LD3, and a fourth light-emitting element LD4 connected in series in the forward direction between the first driving power supply VDD and the second driving power supply VSS, and thus form an effective light source. In the following embodiments, the term "light-emitting element LD" or "plurality of light-emitting elements LD" will be used to arbitrarily specify one of the first light-emitting element LD1 to the fourth light-emitting element LD4, or to commonly specify the first light-emitting element LD1 to the fourth light-emitting element LD4.

[0155] The first end portion (e.g., the second semiconductor layer) of the first light-emitting element LD1 can be connected to the first driving power supply VDD through the first electrode EL1, and the second end portion (e.g., the first semiconductor layer) of the first light-emitting element LD1 can be connected to the first end portion (e.g., the second semiconductor layer) of the second light-emitting element LD2 through the first conductive pattern CP1 connected between the first series group and the second series group. The first end portion of the second light-emitting element LD2 can be connected to the first conductive pattern CP1, and the second end portion (e.g., the first semiconductor layer) of the second light-emitting element LD2 can be connected to the first end portion (e.g., the second semiconductor layer) of the third light-emitting element LD3 through the second conductive pattern CP2 connected between the second series group and the third series group. The first end portion of the third light-emitting element LD3 can be connected to the second conductive pattern CP2, and the second end portion (e.g., the first semiconductor layer) of the third light-emitting element LD3 can be connected to the first end portion (e.g., the second semiconductor layer) of the fourth light-emitting element LD4 through the third conductive pattern CP3 connected between the third series group and the fourth series group. The first end portion of the fourth light-emitting element LD4 can be connected to the third conductive pattern CP3, and the second end portion (e.g., the first semiconductor layer) of the fourth light-emitting element LD4 can be connected to the second driving power supply VSS through the second electrode EL2.

[0156] As described above, the first light-emitting element LD1 to the fourth light-emitting element LD4 can be connected in series between the first electrode EL1 and the second electrode EL2 of the emission unit EMU.

[0157] In the case where the emission unit EMU has a structure in which the light-emitting elements LD are connected in series with each other, compared with the case of the emission unit EMU having a structure in which the light-emitting elements LD are connected in parallel with each other, the voltage applied between the first electrode EL1 and the second electrode EL2 can be increased, and the amount of driving current flowing through the emission unit EMU can be reduced. Therefore, in the case where the emission unit EMU of each pixel PXL has a series structure, the power consumption of the display device can be reduced.

[0158] In an embodiment, at least one series group can be provided in a form including a plurality of light-emitting elements LD connected in parallel with each other. In this case, the emission unit EMU of each pixel PXL can be formed of a series / parallel combination structure. For example, the emission unit EMU can be as Figure 7b shown.

[0159] Next, referring to Figure 7b , the emission unit EMU of the pixel PXL can include a plurality of series groups connected in sequence to each other between the first driving power supply VDD and the second driving power supply VSS. Each of the series groups can include one or more light-emitting elements LD connected in the forward direction between two sub-electrodes of the corresponding series group.

[0160] The emission unit EMU may include a first series group SET1 to a third series group SET3 connected in sequence between a first driving power supply VDD and a second driving power supply VSS.

[0161] The first series group SET1 may include at least one first light-emitting element LD1 connected between a 1-1 sub-electrode SEL1_1 and a 2-1 sub-electrode SEL2_1. For example, the first series group SET1 may include a 1-1 sub-electrode SEL1_1 connected to the first driving power supply VDD via a pixel circuit 144, a 2-1 sub-electrode SEL2_1 connected to the second driving power supply VSS, and a plurality of first light-emitting elements LD1 connected between the 1-1 sub-electrode SEL1_1 and the 2-1 sub-electrode SEL2_1. A first end portion (e.g., a second semiconductor layer) of each first light-emitting element LD1 may be electrically connected to the 1-1 sub-electrode SEL1_1 of the first series group SET1, and a second end portion (e.g., a first semiconductor layer) of each first light-emitting element LD1 may be electrically connected to the 2-1 sub-electrode SEL2_1 of the first series group SET1. The first light-emitting elements LD1 may be connected in parallel between the 1-1 sub-electrode SEL1_1 and the 2-1 sub-electrode SEL2_1 of the first series group SET1, and are connected between the first driving power supply VDD and the second driving power supply VSS in the same direction (e.g., in the forward direction) through the 1-1 sub-electrode SEL1_1 and the 2-1 sub-electrode SEL2_1.

[0162] The second series group SET2 may include at least one second light-emitting element LD2 connected between a 1-2 sub-electrode SEL1_2 and a 2-2 sub-electrode SEL2_2. For example, the second series group SET2 may include a 1-2 sub-electrode SEL1_2 connected to the first driving power supply VDD via a pixel circuit 144 and the first series group SET1, a 2-2 sub-electrode SEL2_2 connected to the second driving power supply VSS, and a plurality of second light-emitting elements LD2 connected between the 1-2 sub-electrode SEL1_2 and the 2-2 sub-electrode SEL2_2. A first end portion (e.g., a second semiconductor layer) of each second light-emitting element LD2 may be electrically connected to the 1-2 sub-electrode SEL1_2 of the second series group SET2, and a second end portion (e.g., a first semiconductor layer) of each second light-emitting element LD2 may be electrically connected to the 2-2 sub-electrode SEL2_2 of the second series group SET2. The second light-emitting elements LD2 may be connected in parallel between the 1-2 sub-electrode SEL1_2 and the 2-2 sub-electrode SEL2_2 of the second series group SET2, and are connected between the first driving power supply VDD and the second driving power supply VSS in the same direction (e.g., in the forward direction) through the 1-2 sub-electrode SEL1_2 and the 2-2 sub-electrode SEL2_2.

[0163] The third series group SET3 may include at least one third light-emitting element LD3 connected between the 1-3rd sub-electrode SEL1_3 and the 2-3rd sub-electrode SEL2_3. For example, the third series group SET3 may include the 1-3rd sub-electrode SEL1_3 connected to the first driving power supply VDD via the pixel circuit 144 and a previous series group (e.g., the first series group SET1 and the second series group SET2), the 2-3rd sub-electrode SEL2_3 connected to the second driving power supply VSS, and a plurality of third light-emitting elements LD3 connected between the 1-3rd sub-electrode SEL1_3 and the 2-3rd sub-electrode SEL2_3. The first end portion (e.g., the second semiconductor layer) of each third light-emitting element LD3 may be electrically connected to the 1-3rd sub-electrode SEL1_3 of the third series group SET3, and the second end portion (e.g., the first semiconductor layer) of each third light-emitting element LD3 may be electrically connected to the 2-3rd sub-electrode SEL2_3 of the third series group SET3. The third light-emitting elements LD3 may be connected in parallel between the 1-3rd sub-electrode SEL1_3 and the 2-3rd sub-electrode SEL2_3 of the third series group SET3, and are connected in the same direction (e.g., in the forward direction) between the first driving power supply VDD and the second driving power supply VSS through the 1-3rd sub-electrode SEL1_3 and the 2-3rd sub-electrode SEL2_3.

[0164] In the foregoing embodiment, the 1-1st sub-electrode SEL1_1 of the first series group SET1 may be the anode electrode of the emission unit EMU of each pixel PXL. The 2-3rd sub-electrode SEL2_3 of the third series group SET3 may be the cathode electrode of the emission unit EMU.

[0165] In addition, the emission unit EMU may include a plurality of intermediate electrodes, wherein the plurality of intermediate electrodes electrically connect successive series groups among the first series group SET1 to the third series group SET3. For example, the emission unit EMU may include a first intermediate electrode CTE1 disposed between the first series group SET1 and the second series group SET2 and a second intermediate electrode CTE2 disposed between the second series group SET2 and the third series group SET3.

[0166] The first series group SET1 and the second series group SET2 can be connected to each other through the first intermediate electrode CTE1. For example, the 2-1 sub-electrode SEL2_1 of the first series group SET1 can be connected to the first intermediate electrode CTE1, and the 1-2 sub-electrode SEL1_2 of the second series group SET2 can be connected to the first intermediate electrode CTE1. The second series group SET2 and the third series group SET3 can be connected to each other through the second intermediate electrode CTE2. For example, the 2-2 sub-electrode SEL2_2 of the second series group SET2 can be connected to the second intermediate electrode CTE2, and the 1-3 sub-electrode SEL1_3 of the third series group SET3 can be connected to the second intermediate electrode CTE2.

[0167] As described above, in the case where the emission unit EMU includes light-emitting elements LD connected to each other in a series / parallel combined structure, the drive current / voltage conditions can be easily adjusted according to the specifications of the product to which the emission unit EMU is applied.

[0168] In particular, in the emission unit EMU of the pixel PXL including light-emitting elements LD connected to each other in a series / parallel combined structure, the drive current can be reduced compared to the drive current of the emission unit EMU including light-emitting elements LD connected in parallel with each other. In addition, in the emission unit EMU of the pixel PXL including light-emitting elements LD connected to each other in a series / parallel combined structure, the drive voltage to be applied to the opposite ends of the emission unit EMU can be reduced compared to the drive voltage of the emission unit EMU including all light-emitting elements LD connected in series with each other. In the case where all the light-emitting elements LD are only connected in series, if at least one of the light-emitting elements LD connected in series is not completely oriented in the forward direction, the drive current can be blocked along the path through which it flows in the pixel PXL, thereby possibly causing a dark spot defect. On the other hand, in the case where the light-emitting elements LD are connected to each other in a series / parallel hybrid structure, even if some of the light-emitting elements LD in each series group are not correctly connected in the forward direction or defects occur in some of the light-emitting elements LD, the drive current is allowed to flow through the other light-emitting elements LD in the corresponding series group. Therefore, defects of the pixel PXL can be prevented or reduced.

[0169] In an embodiment, each pixel PXL may include a plurality of sub-regions. The sub-emission units EMU1 and EMU2 provided in the sub-regions can be combined to form the emission unit EMU of the pixel PXL. Here, each of the sub-emission units EMU1 and EMU2 may include at least one series group formed by a plurality of light-emitting elements LD connected in parallel with each other.

[0170] Reference Figure 7c, the emission unit EMU of the pixel PXL may include a first sub - emission unit EMU1 and a second sub - emission unit EMU2 connected between a first driving power supply VDD and a second driving power supply VSS. Each of the first sub - emission unit EMU1 and the second sub - emission unit EMU2 may include a first series group SET1 to a third series group SET3 connected in sequence between the first driving power supply VDD and the second driving power supply VSS. Each of the first series group SET1 to the third series group SET3 may include one or more light - emitting elements LD connected in the forward direction between two sub - electrodes of the corresponding series group.

[0171] The pixel PXL may include a first sub - region in which the first sub - emission unit EMU1 is disposed, and a second sub - region in which the second sub - emission unit EMU2 is disposed.

[0172] In the first sub - region, a first pixel circuit 144_a connected to the first sub - emission unit EMU1 may be disposed. In the second sub - region, a second pixel circuit 144_b connected to the second sub - emission unit EMU2 may be disposed. In addition, the pixel PXL may include a common circuit 145 connected to the first pixel circuit 144_a and the second pixel circuit 144_b.

[0173] The common circuit 145 may store or record a data signal applied from the j - th data line Dj in response to a scan signal provided from the i - th scan line Si, and supply the data signal to the first pixel circuit 144_a and the second pixel circuit 144_b. The common circuit 145 may include a first transistor T1 connected to the i - th scan line Si and the j - th data line Dj. The first transistor T1 is substantially the same as the first transistor T1 (switching transistor) described with reference to Figure 6a and thus a repeated description thereof will be omitted.

[0174] The first pixel circuit 144_a and the second pixel circuit 144_b may supply a driving current corresponding to the data signal stored in the common circuit 145 to the corresponding light - emitting elements LD disposed in the corresponding sub - emission units.

[0175] In an embodiment, each of the first pixel circuit 144_a and the second pixel circuit 144_b may include what has been referred to with reference to Figure 6aThe described second transistor T2 (driving transistor) and storage capacitor Cst. For example, the first pixel circuit 144_a may include the second transistor T2 and the storage capacitor Cst, and supply a driving current corresponding to a data signal (e.g., the data signal stored in the storage capacitor Cst) to the light-emitting element LD of the first sub-emission unit EMU1. Similarly, the second pixel circuit 144_b may include the second transistor T2 and the storage capacitor Cst, and supply a driving current corresponding to a data signal (e.g., the data signal stored in the storage capacitor Cst) to the light-emitting element LD of the second sub-emission unit EMU2. Here, the second transistor T2 and the storage capacitor Cst are substantially the same as the second transistor T2 and the storage capacitor Cst already described with reference to Figure 6a the described second transistor T2 and storage capacitor Cst, and thus a detailed description thereof will be omitted.

[0176] As described above, the first pixel circuit 144_a and the second pixel circuit 144_b may have the same circuit structure, and respectively supply a driving current corresponding to the data signal transmitted from the common circuit 145 and stored in the associated storage capacitor Cst to the light-emitting elements LD of the corresponding sub-emission units uniformly. For example, the driving current corresponding to the data signal may be transmitted to the first node N1, and then the total driving current is distributed to the first pixel circuit 144_a and the second pixel circuit 144_b at the first node N1, so that the distributed driving currents are respectively supplied to the light-emitting elements LD of the first sub-emission unit EMU1 and the second sub-emission unit EMU2. Here, the driving current flowing to the light-emitting element LD in each of the first sub-emission unit EMU1 and the second sub-emission unit EMU2 may be controlled by the second transistor T2 of the corresponding one of the first pixel circuit 144_a and the second pixel circuit 144_b, regardless of the characteristics of each of the light-emitting elements LD. Therefore, a uniform driving current can be supplied to the light-emitting element LD in each of the first sub-emission unit EMU1 and the second sub-emission unit EMU2.

[0177] In other words, since the driving current is independently supplied to the light-emitting element LD in each of the first sub-emission unit EMU1 and the second sub-emission unit EMU2, even if the light-emitting elements LD have deviations in characteristics (e.g., voltage drop deviations), the same or similar driving currents can be respectively supplied to the light-emitting elements LD, so that the light-emitting elements LD can emit light substantially uniformly.

[0178] As described above, in the case where each of the first sub-emission unit EMU1 and the second sub-emission unit EMU2 includes a light-emitting element LD connected in a series / parallel combination structure to form the emission unit EMU of the pixel PXL, defects of the pixel PXL can be prevented, and the light-emitting elements LD provided to the pixel PXL can emit light substantially uniformly.

[0179] Figure 8 is a schematic plan view showing Figure 5 one pixel among the pixels shown in Figure 9 is a cross-sectional view taken along line I-I' of Figure 8 Figure 10 is a cross-sectional view taken along line II-II' of Figure 8 Figure 11 is a cross-sectional view taken along line III-III' of Figure 8 Figure 12 shows Figure 11 another embodiment of the first bank pattern shown in Figure 8 and is a cross-sectional view corresponding to line III-III' of Figure 13 shows Figure 11 another embodiment of the display element layer shown in Figure 8 and is a cross-sectional view corresponding to line III-III' of

[0180] Figure 8 The pixel shown in Figures 6a to 6e and Figures 7a to 7c can be any one of the pixels shown in Figure 8 For example, the pixel shown in Figure 7c can be the pixel shown in

[0181] For illustration, the illustration of the transistor connected to the light-emitting element and the signal line connected to the transistor is omitted in Figure 8

[0182] Although Figures 8 to 13 the structure of the pixel PXL is simply shown, for example, showing that each electrode is formed of a single electrode layer and each insulating layer is formed of a single insulating layer, the present disclosure is not limited thereto.

[0183] In addition, in the description of the embodiments of the present disclosure, "components are provided and / or formed on the same layer" may mean that the components are formed by the same process, and "components are provided and / or formed on different layers" may mean that the components are formed by different processes.

[0184] Referring to Figures 1a to 4b , Figure 5 , Figure 7c and Figures 8 to 13 , a display device according to an embodiment of the present disclosure may include a substrate SUB, a line component, and at least one pixel PXL.

[0185] The substrate SUB may include a transparent insulating material that allows light to pass through. The substrate SUB may be a rigid substrate or a flexible substrate.

[0186] ​​​​For example, the rigid substrate may be one of a glass substrate, a quartz substrate, a glass-ceramic substrate, and a vitreous glass substrate.

[0187] The flexible substrate may be a plastic substrate or a film substrate that may include an organic polymer material. For example, the flexible substrate may include at least one of the following: polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, triacetate cellulose, and cellulose acetate propionate.

[0188] However, the material constituting the substrate SUB may vary and include, for example, fiber-reinforced plastic (FRP).

[0189] During the process of manufacturing the display device, the material applied to the substrate SUB may have an impedance (thermal resistance) to high processing temperatures. The substrate SUB may include a display area DA and a non-display area NDA provided around the display area DA, where the display area DA includes at least one pixel area in which pixels PXL are provided.

[0190] In an embodiment, the pixels PXL may be arranged in a matrix shape and / or a stripe shape along a plurality of pixel rows extending in a first direction DR1 and a plurality of pixel columns extending in a second direction DR2 intersecting the first direction DR1 in the display area DA, but the present disclosure is not limited thereto. In an embodiment, the pixels PXL may be provided in the display area DA on the substrate SUB in various arrangements.

[0191] The pixel area in which each pixel PXL is provided may include an emission area EMA and a peripheral area, where light is emitted from the emission area EMA, and the peripheral area surrounds the periphery of the emission area EMA. Here, the term "peripheral area" may include a non-emission area from which light is not emitted.

[0192] In an embodiment of the present disclosure, each pixel PXL may include a first sub-pixel SPXL1 and a second sub-pixel SPXL2.

[0193] The first sub-pixel SPXL1 may be provided in a first sub-area SPXA1, and the second sub-pixel SPXL2 may be provided in a second sub-area SPXA2. The first sub-area SPXA1 may include a first sub-emission area SEMA1 that emits light. The second sub-area SPXA2 may include a second sub-emission area SEMA2 that emits light. The first sub-emission area SEMA1 and the second sub-emission area SEMA2 may form the emission area EMA of each pixel PXL. In an embodiment of the present disclosure, the peripheral area (or non-emission area) of each pixel PXL may surround the first sub-emission area SEMA1 and the second sub-emission area SEMA2.

[0194] The first sub-pixel SPXL1 and the second sub-pixel SPXL2 may be bilaterally symmetric with respect to the dashed line VL, wherein the dashed line VL extends in the second direction DR2.

[0195] Each of the first sub-pixel SPXL1 and the second sub-pixel SPXL2 may include a substrate SUB, a pixel circuit layer PCL, and a display element layer DPL. For example, the first sub-pixel SPXL1 may include a substrate SUB, a pixel circuit layer PCL having a first pixel circuit 144_a, and a display element layer DPL including a light-emitting element LD. The second sub-pixel SPXL2 may include a substrate SUB, a pixel circuit layer PCL having a second pixel circuit 144_b, and a display element layer DPL including a light-emitting element LD.

[0196] In an embodiment of the present disclosure, each pixel PXL including the first sub-pixel SPXL1 and the second sub-pixel SPXL2 may include a common circuit 145. The common circuit 145 may be electrically connected to each of the first pixel circuit 144_a and the second pixel circuit 144_b.

[0197] The pixel circuit layer PCL of each of the first sub-pixel SPXL1 and the second sub-pixel SPXL2 may include a buffer layer BFL, a pixel circuit including at least one transistor T and signal lines (not shown) connected to the transistor T, and a passivation layer PSV covering the pixel circuit.

[0198] The buffer layer BFL may prevent impurities from diffusing into the transistor T. Although the buffer layer BFL may be provided as a single-layer structure, the buffer layer BFL may be provided as a multi-layer structure having two or more layers. In the case where the buffer layer BFL has a multi-layer structure, the corresponding layers may be formed of the same material or different materials. Depending on the material or process conditions of the substrate SUB, the buffer layer BFL may be omitted.

[0199] The transistor T included in each of the first sub-pixel SPXL1 and the second sub-pixel SPXL2 may include a driving transistor that controls the amount of driving current to be supplied to the light-emitting element LD. For example, the first sub-pixel SPXL1 may include a first driving transistor T (Tdr1) that controls the amount of driving current to be supplied to the light-emitting element LD provided in the first sub-emission region SEMA1. The second sub-pixel SPXL2 may include a second driving transistor T (Tdr2) that controls the amount of driving current to be supplied to the light-emitting element LD provided in the second sub-emission region SEMA2. In an embodiment of the present disclosure, the first driving transistor T (Tdr1) may be the second transistor T2 of the first pixel circuit 144_a described with reference to Figure 7c described. The second driving transistor T (Tdr2) may be the referenceFigure 7c The second transistor T2 of the described second pixel circuit 144_b.

[0200] Each of the first driving transistor T (Tdr1) and the second driving transistor T (Tdr2) may include a transistor semiconductor pattern SCL, a gate electrode GE, a first terminal SE, and a second terminal DE. The first terminal SE may be a source electrode or a drain electrode, and the second terminal DE may be the other electrode of the source electrode and the drain electrode. For example, when the first terminal SE is a source electrode, the second terminal DE may be a drain electrode.

[0201] The transistor semiconductor pattern SCL may be provided and / or formed on the buffer layer BFL. The transistor semiconductor pattern SCL may include a first contact region contacting the first terminal SE and a second contact region contacting the second terminal DE. The region between the first contact region and the second contact region may be a channel region. The transistor semiconductor pattern SCL may be a semiconductor panel formed of polysilicon, amorphous silicon, an oxide semiconductor, etc. The channel region may be an intrinsic semiconductor as an undoped semiconductor pattern. Each of the first contact region and the second contact region may be a semiconductor pattern doped with impurities.

[0202] The gate electrode GE may be provided and / or formed on the transistor semiconductor pattern SCL, and a gate insulating layer GI is interposed between the gate electrode GE and the transistor semiconductor pattern SCL.

[0203] The first terminal SE and the second terminal DE may respectively contact the first contact region and the second contact region of the transistor semiconductor pattern SCL through corresponding contact holes penetrating through the interlayer insulating layer ILD and the gate insulating layer GI.

[0204] Although in the foregoing embodiments, the first terminal SE and the second terminal DE of each of the first driving transistor T (Tdr1) and the second driving transistor T (Tdr2) are independent electrodes electrically connected to the transistor semiconductor pattern SCL, the present disclosure is not limited thereto. In an embodiment, the first terminal SE of each of the first driving transistor T (Tdr1) and the second driving transistor T (Tdr2) may be one of a first contact region and a second contact region adjacent to the channel region of the corresponding transistor semiconductor pattern SCL. The second terminal DE of each of the first driving transistor T (Tdr1) and the second driving transistor T (Tdr2) may be the other of the first contact region and the second contact region adjacent to the channel region of the corresponding transistor semiconductor pattern SCL. In this case, the second terminal DE of each of the first driving transistor T (Tdr1) and the second driving transistor T (Tdr2) may be electrically connected to the light-emitting element LD of the corresponding sub-pixel through a bridging electrode, a contact electrode, etc. For example, the second terminal DE of the first driving transistor T (Tdr1) may be electrically connected to the light-emitting element LD of the first sub-pixel SPXL1 through a bridging electrode or a contact electrode. In addition, the second terminal DE of the second driving transistor T (Tdr2) may be electrically connected to the light-emitting element LD of the second sub-pixel SPXL2 through a bridging electrode or a contact electrode.

[0205] In an embodiment of the present disclosure, the common circuit 145 included in each pixel PXL may include a switching transistor T1, which is connected to each of the first driving transistor T (Tdr1) and the second driving transistor T (Tdr2) and transmits a data signal thereto. In the same manner as the first driving transistor T (Tdr1) and the second driving transistor T (Tdr2), the switching transistor T1 included in the common circuit 145 may also include a transistor semiconductor pattern SCL, a gate electrode GE, a first terminal SE, and a second terminal DE. In the following embodiments, the term "transistor T" or "a plurality of transistors T" will be used to arbitrarily specify at least one of the first driving transistor T (Tdr1), the second driving transistor T (Tdr2), and the switching transistor T1, or to commonly specify the first driving transistor T (Tdr1), the second driving transistor T (Tdr2), and the switching transistor T1.

[0206] In an embodiment of the present disclosure, the transistor T in the pixel circuit layer PCL included in each of the first sub-pixel SPXL1 and the second sub-pixel SPXL2 may be formed of an LTPS thin-film transistor, but the present disclosure is not limited thereto. In some embodiments, the transistor T may be formed of an oxide semiconductor thin-film transistor. Further, a case where the transistor T is a thin-film transistor having a top-gate structure has been shown, but the present disclosure is not limited thereto. In an embodiment, the transistor T may be a thin-film transistor having a bottom-gate structure.

[0207] The passivation layer PSV may be provided and / or formed on the transistor T and the signal line and cover the transistor T and the signal line. The passivation layer PSV may be in the form of an organic insulating layer, an inorganic insulating layer, or a structure including an organic insulating layer provided on an inorganic insulating layer. The inorganic insulating layer may include at least one of silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiON), and metal oxides such as AlO x . The organic insulating layer may include an organic insulating material that allows light to pass through. The organic insulating layer may include at least one of, for example, polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, and benzocyclobutene resin.

[0208] Hereinafter, the display element layer DPL will be described.

[0209] The display element layer DPL included in each of the first sub-pixel SPXL1 and the second sub-pixel SPXL2 may include a first bank pattern BNK1, first electrodes EL1 to third electrodes EL3, a contact electrode CNE, a first intermediate electrode CTE1 and a second intermediate electrode CTE2, and a light-emitting element LD.

[0210] The first bank pattern BNK1 may be a support component that supports each of the first electrodes EL1 to third electrodes EL3 so as to change the surface profile of each of the first electrodes EL1 to third electrodes EL3, such that light emitted from the light-emitting element LD can travel more effectively in the image display direction of the display device.

[0211] The first bank pattern BNK1 can be disposed and / or formed in the emission regions of each of the first sub-pixel SPXL1 and the second sub-pixel SPXL2, and between the passivation layer PSV and the first electrode EL1 to the third electrode EL3. For example, each first bank pattern BNK1 can be disposed and / or formed between the passivation layer PSV and the first electrode EL1, between the passivation layer PSV and the second electrode EL2, and between the passivation layer PSV and the third electrode EL3. The first bank pattern BNK1 can include an inorganic insulating layer formed of an inorganic material or an organic insulating layer formed of an organic material. In an embodiment, the first bank pattern BNK1 can include an organic insulating layer having a single-layer structure and / or an inorganic insulating layer having a single-layer structure, but the present disclosure is not limited thereto. In an embodiment, the first bank pattern BNK1 can be arranged in the form of a multi-layer structure formed by stacking at least one organic insulating layer and at least one inorganic insulating layer.

[0212] The first bank pattern BNK1 can have a trapezoidal cross-section with a decreasing width upward from one surface of the passivation layer PSV, but the present disclosure is not limited thereto. In an embodiment, as Figure 12 shown, the first bank pattern BNK1 can include a curved surface having a cross-section with a semi-elliptical shape, a semi-circular shape, etc., and the cross-section has a decreasing width upward from one surface of the passivation layer PSV. In a cross-sectional view, the shape of the first bank pattern BNK1 is not limited to the foregoing embodiments, and can be changed in various ways within a range that can improve the efficiency of light emitted from each of the light-emitting elements LD. The first bank patterns BNK1 adjacent to each other can be disposed on the same plane on the passivation layer PSV and have the same height.

[0213] Each pixel PXL can include a second bank pattern BNK2 that surrounds at least one side of each of the first sub-emission region SEMA1 and the second sub-emission region SEMA2. For example, the second bank pattern BNK2 included in each pixel PXL can surround at least one side of the first sub-emission region SEMA1 of the first sub-pixel SPXL1 and surround at least one side of the second sub-emission region SEMA2 of the second sub-pixel SPXL2.

[0214] The second bank pattern BNK2 may be a structure that defines (or demarcates) the respective emission areas EMA of each pixel PXL and the pixels PXL adjacent thereto, and may be, for example, a pixel defining layer. The second bank pattern BNK2 may include at least one light blocking material and / or reflective material, thereby preventing light leakage defects where light (or rays) leak between each pixel PXL and the pixels PXL adjacent thereto. In an embodiment, a reflective material layer may be formed on the second bank pattern BNK2 to further improve the efficiency of the light emitted from each pixel PXL. Although the second bank pattern BNK2 may be formed and / or disposed on a layer different from the layer on which the first bank pattern BNK1 is disposed, the present disclosure is not limited thereto. In an embodiment, the second bank pattern BNK2 may be formed and / or disposed on the same layer as the layer on which the first bank pattern BNK1 is disposed. In an embodiment of the present disclosure, the second bank pattern BNK2 may be formed on a layer different from the layer of the first bank pattern BNK1 and disposed on the first insulating layer INS1.

[0215] The first electrode EL1, the second electrode EL2, and the third electrode EL3 included in each of the first sub-pixel SPXL1 and the second sub-pixel SPXL2 may be spaced apart from each other. The second electrode EL2 may be disposed between the first electrode EL1 and the third electrode EL3. In an embodiment of the present disclosure, the first electrode EL1 and the second electrode EL2 may be spaced apart from each other by a predetermined distance. The second electrode EL2 and the third electrode EL3 may be spaced apart from each other by a predetermined distance.

[0216] In each of the first sub-emission area SEMA1 and the second sub-emission area SEMA2, the distance between the first electrode EL1 and the second electrode EL2 may be the same as the distance between the second electrode EL2 and the third electrode EL3. Thus, the light emitting elements LD may be more regularly aligned in the first sub-emission area SEMA1 and the second sub-emission area SEMA2. However, the present disclosure is not limited thereto. In an embodiment, the distance between the first electrode EL1 and the second electrode EL2 may be different from the distance between the second electrode EL2 and the third electrode EL3.

[0217] In an embodiment of the present disclosure, the third electrode EL3 of the first sub-pixel SPXL1 and the first electrode EL1 of the second sub-pixel SPXL2 may be disposed adjacent to each other and spaced apart from each other by a predetermined distance. The distance between the third electrode EL3 of the first sub-pixel SPXL1 and the first electrode EL1 of the second sub-pixel SPXL2 may be different from the distance between two adjacent electrodes in each of the first sub-pixel SPXL1 and the second sub-pixel SPXL2. For example, the distance between the third electrode EL3 of the first sub-pixel SPXL1 and the first electrode EL1 of the second sub-pixel SPXL2 may be less than the distance between the first electrode EL1 and the second electrode EL2 of the first sub-pixel SPXL1.

[0218] Each of the first electrode EL1, the second electrode EL2, and the third electrode EL3 may be provided and / or formed on the first bank pattern BNK1 and have a surface profile corresponding to the shape of the first bank pattern BNK1. For example, each of the first electrode EL1, the second electrode EL2, and the third electrode EL3 may include a protrusion corresponding to the first bank pattern BNK1 and a planar portion corresponding to the passivation layer PSV. The first electrode EL1, the second electrode EL2, and the third electrode EL3 may be formed of a material having a predetermined reflectivity to allow the light emitted from each of the light-emitting elements LD to travel in the image display direction of the display device. <{

[0219] Each of the first electrode EL1, the second electrode EL2, and the third electrode EL3 may be made of a conductive material having a predetermined reflectivity. The conductive material may include an opaque metal, which has the advantage of reflecting the light emitted from the light-emitting element LD in the image display direction of the display device. The opaque metal may include metals such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Ti, and their alloys. In an embodiment, each of the first electrode EL1, the second electrode EL2, and the third electrode EL3 may include a transparent conductive material. The transparent conductive material may include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium tin zinc oxide (ITZO) or a conductive polymer such as PEDOT. In the case where each of the first electrode EL1, the second electrode EL2, and the third electrode EL3 may include a transparent conductive material, a separate conductive layer formed of an opaque metal for reflecting the light emitted from the light-emitting element LD in the image display direction of the display device may also be included. However, the material of each of the first electrode EL1, the second electrode EL2, and the third electrode EL3 is not limited to the foregoing materials.

[0220] Although each of the first electrode EL1, the second electrode EL2, and the third electrode EL3 may be provided and / or formed as a single-layer structure, the present disclosure is not limited thereto. In an embodiment, each of the first electrode EL1, the second electrode EL2, and the third electrode EL3 may be provided and / or formed as a multi-layer structure formed by stacking at least two materials among metals, alloys, conductive oxides, and conductive polymers. Each of the first electrode EL1, the second electrode EL2, and the third electrode EL3 may have a multi-layer structure including at least two layers to minimize distortion caused by signal delay in the case where a signal (or voltage) is transmitted to opposite ends of each of the light-emitting elements LD. For example, each of the first electrode EL1, the second electrode EL2, and the third electrode EL3 may be formed of a multi-layer structure in which layers are stacked in the order of ITO / Ag / ITO.

[0221] As described above, since each of the first electrode EL1, the second electrode EL2, and the third electrode EL3 has a surface profile corresponding to the shape of the first bank pattern BNK1 disposed thereunder, the light emitted from each of the light-emitting elements LD can be reflected by each of the first electrode EL1, the second electrode EL2, and the third electrode EL3, and travel more reliably in the image display direction of the display device. Therefore, the efficiency of the light emitted from each of the light-emitting elements LD can be further improved.

[0222] The first bank pattern BNK1 and each of the first electrode EL1, the second electrode EL2, and the third electrode EL3 can each be used as a reflection component that guides the light emitted from the light-emitting element LD in a desired direction, and thus improve the optical efficiency of the display device. In other words, the first bank pattern BNK1 and each of the first electrode EL1, the second electrode EL2, and the third electrode EL3 can each be used as a reflection component that enables the light emitted from the light-emitting element LD to travel in the image display direction of the display device, thereby improving the light output efficiency of the light-emitting element LD.

[0223] In an embodiment of the present disclosure, each of the first electrode EL1, the second electrode EL2, and the third electrode EL3 included in each of the first sub-pixel SPXL1 and the second sub-pixel SPXL2 may include a plurality of sub-electrodes disposed in the same column. For example, the first electrode EL1 may include a 1-1 sub-electrode SEL1_1, a 1-2 sub-electrode SEL1_2, and a 1-3 sub-electrode SEL1_3 that are disposed in the same column in the second direction DR2 and spaced apart from each other. The second electrode EL2 may include a 2-1 sub-electrode SEL2_1, a 2-2 sub-electrode SEL2_2, and a 2-3 sub-electrode SEL2_3 that are disposed in the same column in the second direction DR2 and spaced apart from each other. The third electrode EL3 may include a 3-1 sub-electrode SEL3_1, a 3-2 sub-electrode SEL3_2, and a 3-3 sub-electrode SEL3_3 that are disposed in the same column in the second direction DR2 and spaced apart from each other.

[0224] The 1-1 sub-electrode SEL1_1, the 2-1 sub-electrode SEL2_1, and the 3-1 sub-electrode SEL3_1 may be disposed in the same row in the corresponding sub-emission regions of each of the first sub-pixel SPXL1 and the second sub-pixel SPXL2, and spaced apart from each other. For example, the 1-1 sub-electrode SEL1_1 may be spaced apart from the 2-1 sub-electrode SEL2_1 by a predetermined distance. The 2-1 sub-electrode SEL2_1 may be spaced apart from the 3-1 sub-electrode SEL3_1 by a predetermined distance.

[0225] In an embodiment of the present disclosure, the first sub-electrode SEL1_1 and the third sub-electrode SEL3_1 of the first sub-pixel SPXL1 may be connected to each other through a first connection line CNL1. For example, the first connection line CNL1 may be integrated with the first sub-electrode SEL1_1 and the third sub-electrode SEL3_1, and be electrically and / or physically connected to the first sub-electrode SEL1_1 and the third sub-electrode SEL3_1. Therefore, the first connection line CNL1 may be regarded as a region of the first sub-electrode SEL1_1 or a region of the third sub-electrode SEL3_1. The first sub-electrode SEL1_1, the first connection line CNL1, and the third sub-electrode SEL3_1 may be integrated with each other and form an independent conductive pattern.

[0226] The first sub-electrode SEL1_1 and the third sub-electrode SEL3_1 of the second sub-pixel SPXL2 may be connected to each other through a third connection line CNL3. The third connection line CNL3 may be integrated with the first sub-electrode SEL1_1 and the third sub-electrode SEL3_1, and be electrically and / or physically connected to the first sub-electrode SEL1_1 and the third sub-electrode SEL3_1. Therefore, the first connection line CNL1 may be regarded as a region of the first sub-electrode SEL1_1 or a region of the third sub-electrode SEL3_1. The first sub-electrode SEL1_1, the third connection line CNL3, and the third sub-electrode SEL3_1 may be integrated with each other and form an independent conductive pattern.

[0227] The first sub-electrode SEL1_2, the second sub-electrode SEL2_2, and the third sub-electrode SEL3_2 may be arranged in the same row in the corresponding sub-emission regions of each of the first sub-pixel SPXL1 and the second sub-pixel SPXL2, and be spaced apart from each other. For example, the first sub-electrode SEL1_2 may be spaced apart from the second sub-electrode SEL2_2 by a predetermined distance. The second sub-electrode SEL2_2 may be spaced apart from the third sub-electrode SEL3_2 by a predetermined distance.

[0228] The first sub-electrode SEL1_3, the second sub-electrode SEL2_3, and the third sub-electrode SEL3_3 may be arranged in the same row in the corresponding sub-emission regions of each of the first sub-pixel SPXL1 and the second sub-pixel SPXL2, and be spaced apart from each other. For example, the first sub-electrode SEL1_3 may be spaced apart from the second sub-electrode SEL2_3 by a predetermined distance. The second sub-electrode SEL2_3 may be spaced apart from the third sub-electrode SEL3_3 by a predetermined distance.

[0229] The second-third sub-electrodes SEL2_3 of the first sub-pixel SPXL1 and the second-third sub-electrodes SEL2_3 of the second sub-pixel SPXL2 can be electrically connected and / or physically connected to each other through the second connection line CNL2. The second connection line CNL2 can be integrally provided and / or formed with the second-third sub-electrodes SEL2_3 of the first sub-pixel SPXL1 and the second sub-pixel SPXL2, and thus is connected to the second-third sub-electrodes SEL2_3 of each of the first sub-pixel SPXL1 and the second sub-pixel SPXL2. Since the second connection line CNL2 can be integrally provided and / or formed with the second-third sub-electrodes SEL2_3 of each of the first sub-pixel SPXL1 and the second sub-pixel SPXL2, the second connection line CNL2 can be a region of the second-third sub-electrodes SEL2_3 of each of the first sub-pixel SPXL1 and the second sub-pixel SPXL2. In other words, the second connection line CNL2 can be a region of the second-third sub-electrodes SEL2_3 of the first sub-pixel SPXL1 or a region of the second-third sub-electrodes SEL2_3 of the second sub-pixel SPXL2.

[0230] In an embodiment of the present disclosure, the second connection line CNL2 can be commonly provided to the first sub-pixel SPXL1 and the second sub-pixel SPXL2, and is connected to the driving voltage line (e.g., Figure 7c the second power line PL2) to which the second driving power supply VSS is to be applied through the second contact hole CH2. The first connection line CNL1 and the third connection line CNL3 can be provided only in the corresponding sub-pixels. For example, the first connection line CNL1 can be provided only in the first sub-pixel SPXL1. The third connection line CNL3 can be provided only in the second sub-pixel SPXL2.

[0231] In an embodiment of the present disclosure, a sub-emission region of each of the first sub-pixel SPXL1 and the second sub-pixel SPXL2 in a second direction DR2 may include a first region A1 to a third region A3 that are separated from each other in the second direction DR2. In addition, the sub-emission region of each of the first sub-pixel SPXL1 and the second sub-pixel SPXL2 may be divided into the first region A1 to the third region A3 according to the positions of sub-electrodes. For example, a first sub-emission region SEMA1 of the first sub-pixel SPXL1 may be divided into a first region A1, a second region A2, and a third region A3, where a 1-1 sub-electrode SEL1_1, a 2-1 sub-electrode SEL2_1, and a 3-1 sub-electrode SEL3_1 are located in the first region A1, a 1-2 sub-electrode SEL1_2, a 2-2 sub-electrode SEL2_2, and a 3-2 sub-electrode SEL3_2 are located in the second region A2, and a 1-3 sub-electrode SEL1_3, a 2-3 sub-electrode SEL2_3, and a 3-3 sub-electrode SEL3_3 are located in the third region A3. Similarly, a second sub-emission region SEMA2 of the second sub-pixel SPXL2 may be divided into a first region A1, a second region A2, and a third region A3, where the 1-1 sub-electrode SEL1_1, the 2-1 sub-electrode SEL2_1, and the 3-1 sub-electrode SEL3_1 are located in the first region A1, the 1-2 sub-electrode SEL1_2, the 2-2 sub-electrode SEL2_2, and the 3-2 sub-electrode SEL3_2 are located in the second region A2, and the 1-3 sub-electrode SEL1_3, the 2-3 sub-electrode SEL2_3, and the 3-3 sub-electrode SEL3_3 are located in the third region A3.

[0232] In the first region A1 of each of the first sub-pixel SPXL1 and the second sub-pixel SPXL2, the 1-1 sub-electrode SEL1_1, the 2-1 sub-electrode SEL2_1, and the 3-1 sub-electrode SEL3_1 together with a plurality of light-emitting elements LD connected in parallel therebetween may form a first series group SET1. In the second region A2 of each of the first sub-pixel SPXL1 and the second sub-pixel SPXL2, the 1-2 sub-electrode SEL1_2, the 2-2 sub-electrode SEL2_2, and the 3-2 sub-electrode SEL3_2 together with a plurality of light-emitting elements LD connected in parallel therebetween may form a second series group SET2. In the third region A3 of each of the first sub-pixel SPXL1 and the second sub-pixel SPXL2, the 1-3 sub-electrode SEL1_3, the 2-3 sub-electrode SEL2_3, and the 3-3 sub-electrode SEL3_3 together with a plurality of light-emitting elements LD connected in parallel therebetween may form a third series group SET3.

[0233] In the sub-emission regions of each of the first sub-pixel SPXL1 and the second sub-pixel SPXL2, the first series group SET1 to the third series group SET3 may be provided. The first series group SET1 to the third series group SET3 may form the sub-emission units of the corresponding sub-pixels. For example, in the first sub-emission region SEMA1 of the first sub-pixel SPXL1, the first series group SET1 to the third series group SET3 may be provided. The first series group SET1 to the third series group SET3 may form the first sub-emission unit EMU1. In the second sub-emission region SEMA2 of the second sub-pixel SPXL2, the first series group SET1 to the third series group SET3 may be provided. The first series group SET1 to the third series group SET3 may form the second sub-emission unit EMU2. The first sub-emission unit EMU1 and the second sub-emission unit EMU2 may be combined to form the emission unit EMU of each pixel PXL.

[0234] The 1-1 sub-electrode SEL1_1 and the 3-1 sub-electrode SEL3_1 included in the first series group SET1 of each of the first sub-pixel SPXL1 and the second sub-pixel SPXL2 may correspond to the anode electrode of the sub-emission unit of the corresponding sub-pixel. The 2-3 sub-electrode SEL2_3 included in the third series group SET3 may correspond to the cathode electrode of the sub-emission unit of the corresponding sub-pixel. For example, the 1-1 sub-electrode SEL1_1 and the 3-1 sub-electrode SEL3_1 of the first sub-pixel SPXL1 may correspond to the anode electrode of the first sub-emission unit EMU1 of the first sub-pixel SPXL1. The 2-3 sub-electrode SEL2_3 of the first sub-pixel SPXL1 may correspond to the cathode electrode of the first sub-emission unit EMU1. In addition, the 1-1 sub-electrode SEL1_1 and the 3-1 sub-electrode SEL3_1 of the second sub-pixel SPXL2 may correspond to the anode electrode of the second sub-emission unit EMU2 of the second sub-pixel SPXL2. The 2-3 sub-electrode SEL2_3 of the second sub-pixel SPXL2 may correspond to the cathode electrode of the second sub-emission unit EMU2.

[0235] In an embodiment of the present disclosure, the 1-1 sub-electrode SEL1_1 and the 3-1 sub-electrode SEL3_1 of the first sub-pixel SPXL1 may be electrically connected to the first pixel circuit 144_a included in the pixel circuit layer PCL of the first sub-pixel SPXL1 through the first contact hole CH1. For example, the 1-1 sub-electrode SEL1_1 and the 3-1 sub-electrode SEL3_1 of the first sub-pixel SPXL1 may be electrically connected to the first driving transistor T (Tdr1) through the first contact hole CH1.

[0236] The first sub-electrode SEL1_1 and the third sub-electrode SEL3_1 of the second sub-pixel SPXL2 can be electrically connected through the third contact hole CH3 to the second pixel circuit 144_b included in the pixel circuit layer PCL of the second sub-pixel SPXL2. For example, the first sub-electrode SEL1_1 and the third sub-electrode SEL3_1 of the second sub-pixel SPXL2 can be electrically connected through the third contact hole CH3 to the second driving transistor T (Tdr2).

[0237] In the foregoing embodiment, each of the light-emitting elements LD can be formed of such a light-emitting element made of a material having an inorganic crystal structure and having an ultra-small size, for example, in the range from nanoscale to micron scale. For example, each of the light-emitting elements LD can be an ultra-small light-emitting element manufactured by an etching method or an ultra-small light-emitting element manufactured by a growth method. The type, size, shape, etc. of the light-emitting element LD can be changed in various ways. Although at least two to dozens of light-emitting elements LD can be aligned and / or arranged in the emission area EMA of each pixel PXL, the number of the light-emitting elements LD is not limited thereto. In an embodiment, the number of the light-emitting elements LD aligned and / or arranged in the emission area EMA of each pixel PXL can be changed in various ways.

[0238] Although Figure 8 has described an example in which the corresponding light-emitting element LD is arranged (or aligned) between two adjacent sub-electrodes in the horizontal direction (e.g., in the first direction DR1) along the second direction DR2 in the corresponding series group, the present disclosure is not limited thereto. In an embodiment, at least one of the light-emitting elements LD can be arranged and / or connected between two adjacent sub-electrodes in the corresponding series group in the third direction DR3 (e.g., a direction inclined to the first direction DR1 or the second direction DR2) or in the vertical direction. In addition, in an embodiment, at least one reverse light-emitting element LDr connected in the opposite direction between two adjacent sub-electrodes in each series group can be provided, or at least one defective light-emitting element not connected to two adjacent sub-electrodes in each series group can be provided between two sub-electrodes, for example, an invalid light source (not shown).

[0239] The light-emitting element LD can be diffused in a solution and supplied to the emission area EMA of each pixel PXL.

[0240] In an embodiment of the present disclosure, the light-emitting element LD can be supplied to the emission region EMA of each pixel PXL by an inkjet printing method, a slot coating method, or various other methods. For example, the light-emitting element LD can be mixed with a volatile solvent and supplied to the emission region EMA of each pixel PXL by an inkjet printing method or a slot coating method. Here, if corresponding alignment signals (or alignment voltages) are supplied to the first electrode EL1, the second electrode EL2, and the third electrode EL3 provided in the emission region EMA of each pixel PXL, an electric field is formed between two adjacent electrodes among the first electrode EL1, the second electrode EL2, and the third electrode EL3, so that the light-emitting element LD can be aligned between the two adjacent electrodes. After the light-emitting element LD is aligned, the solvent can be removed by a volatilization method or other methods. In this way, the light-emitting element LD can be disposed between the first electrode EL1, the second electrode EL2, and the third electrode EL3.

[0241] Before the light-emitting element LD is aligned in the emission region EMA of each pixel PXL, the first electrode EL1 and the third electrode EL3 can be electrically connected and / or physically connected. For example, the first electrode EL1 and the third electrode EL3 can be integrally provided and / or formed, and thus are electrically connected and / or physically connected to each other. In the case where the first electrode EL1 and the third electrode EL3 are integrally provided and / or formed, the third electrode EL3 can be a region of the first electrode EL1.

[0242] After the light-emitting element LD is aligned in the emission region EMA of each pixel PXL, each of the first electrode EL1, the second electrode EL2, and the third electrode EL3 can include a plurality of sub-electrodes provided in the same column and spaced apart from each other. For example, by removing or disconnecting a part of the first electrode EL1 after the light-emitting element LD is aligned, the first electrode EL1 can include the 1-1 sub-electrode SEL1_1, the 1-2 sub-electrode SEL1_2, and the 1-3 sub-electrode SEL1_3 provided in the same column and spaced apart from each other. By removing or disconnecting a part of the second electrode EL2 after the light-emitting element LD is aligned, the second electrode EL2 can include the 2-1 sub-electrode SEL2_1, the 2-2 sub-electrode SEL2_2, and the 2-3 sub-electrode SEL2_3 provided in the same column and spaced apart from each other. Similarly, by removing or disconnecting a part of the third electrode EL3 after the light-emitting element LD is aligned, the third electrode EL3 can include the 3-1 sub-electrode SEL3_1, the 3-2 sub-electrode SEL3_2, and the 3-3 sub-electrode SEL3_3 provided in the same column and spaced apart from each other.

[0243] In an embodiment of the present disclosure, before the light-emitting element LD is aligned in the emission region EMA of each pixel PXL, the first connection line CNL1 and the third connection line CNL3 may be kept electrically connected and / or physically connected to each other, and then electrically separated and / or physically separated from each other after the light-emitting element LD is aligned. After the light-emitting element LD is aligned in the emission region EMA of each pixel PXL, the first connection line CNL1 and the third connection line CNL3 may be separated from each other, so that the pixel PXL may be set in a form including a first sub-pixel SPXL1 and a second sub-pixel SPXL2. Here, the pixel region in which each pixel PXL is provided may include a first sub-region SPXA1 in which the first sub-pixel SPXL1 is provided and a second sub-region SPXA2 in which the second sub-pixel SPXL2 is provided.

[0244] As described above, in the case where the light-emitting element LD is aligned in the emission region EMA of each pixel PXL, the first electrode EL1, the second electrode EL2, and the third electrode EL3 may be used as alignment electrodes (or alignment lines) for aligning the light-emitting element LD. For example, the first electrode EL1 and the third electrode EL3 may be first alignment electrodes to which the same first alignment signal (or the same first alignment voltage) is to be applied. The second electrode EL2 may be a second alignment electrode to which a second alignment signal (or a second alignment voltage) is to be applied. The first alignment signal and the second alignment signal may have different voltage levels. If the first electrode EL1, the second electrode EL2, and the third electrode EL3 are supplied with corresponding alignment signals, respective electric fields may be formed between the first electrode EL1 and the second electrode EL2 and between the second electrode EL2 and the third electrode EL3. The light-emitting element LD may be aligned in the emission region EMA of the pixel PXL by the electric fields formed between the first electrode EL1 to the third electrode EL3.

[0245] After the light-emitting element LD is aligned in the emission region EMA of the pixel PXL, by removing a part of each of the first electrode EL1 to the third electrode EL3, each of the first electrode EL1 to the third electrode EL3 may be set in a form including three sub-electrodes provided in the same column and spaced apart from each other. The sub-electrodes may be used as drive electrodes for driving the light-emitting element LD.

[0246] Although an example has been described in the foregoing embodiment in which each of the first electrode EL1 to the third electrode EL3 is formed to include three sub-electrodes arranged in the same column and spaced apart from each other by removing a part of each of the first electrode EL1 to the third electrode EL3 after alignment of the light-emitting element LD, the present disclosure is not limited thereto. In an embodiment, each of the first electrode EL1 to the third electrode EL3 is formed to include two sub-electrodes arranged in the same column and spaced apart from each other or four sub-electrodes arranged in the same column and spaced apart from each other by removing a part of each of the first electrode EL1 to the third electrode EL3 after alignment of the light-emitting element LD. In a case where each of the first electrode EL1 to the third electrode EL3 may include two sub-electrodes arranged in the same column and spaced apart from each other, the sub-emission regions of each of the first sub-pixel SPXL1 and the second sub-pixel SPXL2 may be divided into two regions according to the respective positions of the two sub-electrodes. In a case where each of the first electrode EL1 to the third electrode EL3 may include four sub-electrodes arranged in the same column and spaced apart from each other, the sub-emission regions of each of the first sub-pixel SPXL1 and the second sub-pixel SPXL2 may be divided into four regions according to the respective positions of the four sub-electrodes.

[0247] In an embodiment of the present disclosure, in the step of aligning the light-emitting element LD in the emission region EMA of each pixel PXL, the relative bias and alignment of the light-emitting element LD to be supplied to the emission region EMA may be controlled by controlling the alignment signals (or alignment voltages) respectively applied to the first electrode EL1, the second electrode EL2, and the third electrode EL3 or by forming a magnetic field. For example, in the step of aligning the light-emitting element LD, when adjusting the waveform of the alignment signal or forming a magnetic field in the emission region EMA, the number of the light-emitting elements LD oriented in the forward direction may be controlled to be greater than the number of the reverse light-emitting elements LDr oriented in the opposite direction, where the light-emitting element LD is oriented in the forward direction such that one of the opposite ends EP1 and EP2 of the light-emitting element LD faces the first alignment electrode and the other end faces the second alignment electrode.

[0248] Each of the light-emitting elements LD may include a light-emitting element manufactured by an etching method or a core-shell light-emitting element manufactured by a growth method. In the case where each of the light-emitting elements LD is a light-emitting element manufactured by an etching method, each light-emitting element LD may include an emission stack (or stacked pattern) formed by sequentially stacking a first semiconductor layer 11, an active layer 12, a second semiconductor layer 13, and an additional electrode 15 in the longitudinal direction of each light-emitting element LD. In the case where each of the light-emitting elements LD is a light-emitting element having a core-shell structure and manufactured by a growth method, each light-emitting element LD may include an emission pattern 10 having a first semiconductor layer 11 disposed in the central portion of the light-emitting element LD, an active layer 12 surrounding at least one side of the first semiconductor layer 11, a second semiconductor layer 13 surrounding at least one side of the active layer 12, and an additional electrode 15 surrounding at least one side of the second semiconductor layer 13.

[0249] Each of the light-emitting elements LD may include a first end portion EP1 and a second end portion EP2, wherein the first end portion EP1 is electrically connected to one of two adjacent sub-electrodes in a first direction DR1, and the second end portion EP2 is electrically connected to the other of the two sub-electrodes. In an embodiment of the present disclosure, the first end portion EP1 of each light-emitting element LD may be the second semiconductor layer 13 including a P-type semiconductor layer, and the second end portion EP2 of each light-emitting element LD may be the first semiconductor layer 11 including an N-type semiconductor layer. In other words, in the emission region EMA of the pixel PXL, each light-emitting element LD may be connected in the forward direction between two adjacent sub-electrodes in the first direction DR1. As described above, the light-emitting elements LD connected in the forward direction between two adjacent sub-electrodes may form an effective light source for each of the first to third series groups SET1 to SET3.

[0250] The first end portion EP1 of each of the light-emitting elements LD may be directly connected to one of two adjacent sub-electrodes in the first direction DR1 or may be connected to the one sub-electrode through a contact electrode CNE. In addition, the second end portion EP2 of each of the light-emitting elements LD may be directly connected to the other of the two adjacent sub-electrodes or may be connected to the other sub-electrode through a contact electrode CNE.

[0251] The light-emitting elements LD may be disposed and / or formed on the first insulating layer INS1 in the emission region EMA of each pixel PXL.

[0252] The first insulating layer INS1 may be formed and / or disposed under each of the light-emitting elements LD, wherein the light-emitting elements LD are aligned (or arranged) between two adjacent sub-electrodes in each series group of sub-electrodes in the emission region EMA forming each pixel PXL. The first insulating layer INS1 may be filled into the space between each of the light-emitting elements LD and the passivation layer PSV to stably support the light-emitting elements LD and prevent the light-emitting elements LD from being removed from the passivation layer PSV.

[0253] In addition, in the emission region EMA of each pixel PXL, the first insulating layer INS1 may expose an area of each of the sub-electrodes forming each series group and cover other areas except for that one area. Here, the contact electrode CNE may be disposed and / or formed in an area of each of the exposed sub-electrodes such that each of the sub-electrodes and the contact electrode CNE may be electrically connected and / or physically connected to each other.

[0254] The first insulating layer INS1 may be formed of an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material. Although in an embodiment of the present disclosure, the first insulating layer INS1 may be formed of an inorganic insulating layer that has an advantage in protecting the light-emitting elements LD from the pixel circuit layer PCL in each of the first sub-pixel PXL1 and the second sub-pixel PXL2, the present disclosure is not limited thereto. In an embodiment, the first insulating layer INS1 may be formed of an organic insulating layer that has an advantage in planarizing the support surface of the light-emitting elements LD.

[0255] The second insulating layer INS2 may be disposed and / or formed on the light-emitting elements LD. The second insulating layer INS2 may be disposed and / or formed on each of the light-emitting elements LD to cover a part of the upper surface of each of the light-emitting elements LD and expose the opposite ends EP1 and EP2 of each of the light-emitting elements LD to the outside. The second insulating layer INS2 may be formed in an independent pattern in the emission region EMA of each pixel PXL, but the present disclosure is not limited thereto.

[0256] The second insulating layer INS2 may have a single-layer structure or a multi-layer structure and include an inorganic insulating layer or an organic insulating layer, wherein the inorganic insulating layer includes at least one inorganic material and the organic insulating layer includes at least one organic material. The second insulating layer INS2 may be fixed to each of the light-emitting elements LD aligned in the emission region EMA of each pixel PXL. In an embodiment of the present disclosure, the second insulating layer INS2 may include an inorganic insulating layer that has an advantage in protecting the active layer 12 of each of the light-emitting elements LD from the influence of external oxygen, water, etc. However, the present disclosure is not limited thereto. The second insulating layer INS2 may be formed of an organic insulating layer including an organic material according to the design conditions of the display device to which the light-emitting elements LD are applied.

[0257] In an embodiment of the present disclosure, after the alignment of the light-emitting element LD in the emission area EMA of each pixel PXL has been completed, a second insulating layer INS2 is formed on the light-emitting element LD, so that the light-emitting element LD can be prevented from being removed from the alignment position. As Figure 13 shown, when there is a gap (or space) between the first insulating layer INS1 and the light-emitting element LD before the formation of the second insulating layer INS2, the gap can be filled with the second insulating layer INS2 during the process of forming the second insulating layer INS2. Therefore, the light-emitting element LD can be supported more stably. Thus, the second insulating layer INS2 can be formed of an organic insulating layer that has an advantage in filling the gap between the first insulating layer INS1 and the light-emitting element LD with the second insulating layer INS2.

[0258] In an embodiment of the present disclosure, the second insulating layer INS2 can be formed on each of the light-emitting elements LD, so that the active layer 12 of each of the light-emitting elements LD can be prevented from contacting an external conductive material. The second insulating layer INS2 can cover only a part of the surface of each of the light-emitting elements LD, so that the opposite ends EP1 and EP2 of each of the light-emitting elements LD can be exposed to the outside.

[0259] The light-emitting element LD of each of the first sub-pixel SPXL1 and the second sub-pixel SPXL2 can include at least one first light-emitting element LD1, at least one second light-emitting element LD2, and at least one third light-emitting element LD3, wherein at least one first light-emitting element LD1 is included in the first series group SET1, at least one second light-emitting element LD2 is included in the second series group SET2, and at least one third light-emitting element LD3 is included in the third series group SET3.

[0260] The first light-emitting element LD1 can include a 1-1 light-emitting element LD1_1 connected in the forward direction between the 1-1 sub-electrode SEL1_1 and the 2-1 sub-electrode SEL2_1, and a 1-2 light-emitting element LD1_2 connected in the forward direction between the 3-1 sub-electrode SEL3_1 and the 2-1 sub-electrode SEL2_1.

[0261] The second light-emitting element LD2 can include a 2-1 light-emitting element LD2_1 connected in the forward direction between the 1-2 sub-electrode SEL1_2 and the 2-2 sub-electrode SEL2_2, and a 2-2 light-emitting element LD2_2 connected in the forward direction between the 3-2 sub-electrode SEL3_2 and the 2-2 sub-electrode SEL2_2.

[0262] The third light-emitting element LD3 may include a 3-1 light-emitting element LD3_1 connected in the forward direction between the 1-3 sub-electrode SEL1_3 and the 2-3 sub-electrode SEL2_3, and a 3-2 light-emitting element LD3_2 connected in the forward direction between the 3-3 sub-electrode SEL3_3 and the 2-3 sub-electrode SEL2_3.

[0263] In an embodiment, the light-emitting element LD aligned (or disposed) in the sub-emission region of each of the first sub-pixel SPXL1 and the second sub-pixel SPXL2 may include at least one reverse light-emitting element LDr that is connected between two adjacent sub-electrodes in a direction opposite to the forward direction (e.g., the reverse direction).

[0264] Contact electrodes CNE may be respectively provided on the 1-1 sub-electrode SEL1_1, the 1-2 sub-electrode SEL1_2, and the 1-3 sub-electrode SEL1_3, the 2-1 sub-electrode SEL2_1, the 2-2 sub-electrode SEL2_2, and the 2-3 sub-electrode SEL2_3, and the 3-1 sub-electrode SEL3_1, the 3-2 sub-electrode SEL3_2, and the 3-3 sub-electrode SEL3_3.

[0265] The contact electrode CNE may be formed of various transparent conductive materials. For example, each contact electrode CNE may include at least one of various conductive materials such as ITO, IZO, and ITZO, and may be substantially transparent or semi-transparent to meet a predetermined transmittance. However, the material of the contact electrode CNE is not limited to those of the foregoing embodiments. In some embodiments, the contact electrode CNE may be formed of various opaque conductive materials.

[0266] In an embodiment of the present disclosure, the contact electrode CNE may include a first contact electrode CNE1 to a ninth contact electrode CNE9.

[0267] The first contact electrode CNE1 may be provided on the 1-1 sub-electrode SEL1_1 and connect one end of each of the opposite ends EP1 and EP2 of the 1-1 sub-electrode SEL1_1 to the 1-1 light-emitting element LD1_1. In a plan view, the first contact electrode CNE1 may overlap one end of each of the 1-1 light-emitting element LD1_1 and the 1-1 sub-electrode SEL1_1.

[0268] The second contact electrode CNE2 may be disposed on the 2-1st sub-electrode SEL2_1, and connect one of the opposite ends EP1 and EP2 of each of the 2-1st sub-electrodes SEL2_1 to the other end of each of the 1-1st light-emitting elements LD1_1. In addition, the second contact electrode CNE2 may connect the other side of the 2-1st sub-electrode SEL2_1 to one of the opposite ends EP1 and EP2 of each of the 1-2nd light-emitting elements LD1_2. In a plan view, the second contact electrode CNE2 may overlap with the other end of each of the 1-1st light-emitting elements LD1_1, overlap with the 2-1st sub-electrode SEL2_1, and overlap with one end of each of the 1-2nd light-emitting elements LD1_2.

[0269] The third contact electrode CNE3 may be disposed on the 3-1st sub-electrode SEL3_1, and connect the 3-1st sub-electrode SEL3_1 to the other end of each of the opposite ends EP1 and EP2 of the 1-2nd light-emitting elements LD1_2. In a plan view, the third contact electrode CNE3 may overlap with the other end of each of the 1-2nd light-emitting elements LD1_2 and the 3-1st sub-electrode SEL3_1.

[0270] The first contact electrode CNE1, the second contact electrode CNE2, and the third contact electrode CNE3 may be disposed in the first region A1, and the first series group SET1 of each of the first sub-pixel SPXL1 and the second sub-pixel SPXL2 is located in the first region A1.

[0271] The fourth contact electrode CNE4 may be disposed on the 1-2nd sub-electrode SEL1_2, and connect the 1-2nd sub-electrode SEL1_2 to one of the opposite ends EP1 and EP2 of each of the 2-1st light-emitting elements LD2_1. In a plan view, the fourth contact electrode CNE4 may overlap with one end of each of the 2-1st light-emitting elements LD2_1 and the 1-2nd sub-electrode SEL1_2.

[0272] The fifth contact electrode CNE5 may be disposed on the 2-2nd sub-electrode SEL2_2, and connect one of the opposite ends EP1 and EP2 of each of the 2-2nd sub-electrodes SEL2_2 to the other end of each of the 2-1st light-emitting elements LD2_1. In addition, the fifth contact electrode CNE5 may connect the other side of the 2-2nd sub-electrode SEL2_2 to one of the opposite ends EP1 and EP2 of each of the 2-2nd light-emitting elements LD2_2. In a plan view, the fifth contact electrode CNE5 may overlap with the other end of each of the 2-1st light-emitting elements LD2_1, the 2-2nd sub-electrode SEL2_2, and one end of each of the 2-2nd light-emitting elements LD2_2.

[0273] The sixth contact electrode CNE6 may be disposed on the 3-2nd sub-electrode SEL3_2 and connect the 3-2nd sub-electrode SEL3_2 to the other end portion among the opposite end portions EP1 and EP2 of each 2-2nd light-emitting element LD2_2. In a plan view, the sixth contact electrode CNE6 may overlap with the other end portion of each 2-2nd light-emitting element LD2_2 and the 3-2nd sub-electrode SEL3_2.

[0274] The fourth contact electrode CNE4, the fifth contact electrode CNE5, and the sixth contact electrode CNE6 may be disposed in the second region A2, and the second series group SET2 of each of the first sub-pixel SPXL1 and the second sub-pixel SPXL2 is located in the second region A2.

[0275] The second contact electrode CNE2 disposed in the first series group SET1 may be electrically and / or physically connected to the fourth contact electrode CNE4 and the sixth contact electrode CNE6 disposed in the second series group SET2 through the first intermediate electrode CTE1.

[0276] In a plan view, the first intermediate electrode CTE1 of each of the first sub-pixel SPXL1 and the second sub-pixel SPXL2 may be located in the boundary between the first region A1 where the first series group SET1 is located and the second region A2 where the second series group SET2 is located. The first intermediate electrode CTE1 may include a 1-1st intermediate electrode CTE1_1 connecting the second contact electrode CNE2 and the fourth contact electrode CNE4, and a 1-2nd intermediate electrode CTE1_2 connecting the second contact electrode CNE2 and the sixth contact electrode CNE6.

[0277] The 1-1st intermediate electrode CTE1_1 may extend in a direction (e.g., the third direction DR3) inclined to the first direction DR1 or the second direction DR2 in the region between the first region A1 and the second region A2, and electrically and / or physically connect the second contact electrode CNE2 in the first region A1 and the fourth contact electrode CNE4 in the second region A2. Therefore, the 1-1st intermediate electrode CTE1_1 may be used as a connection electrode (or a bridging electrode) connecting the second contact electrode CNE2 in the first region A1 and the fourth contact electrode CNE4 in the second region A2.

[0278] In addition, the 1-2nd intermediate electrode CTE1_2 may extend in the third direction DR3 in the region between the first region A1 and the second region A2, and electrically and / or physically connect the second contact electrode CNE2 in the first region A1 and the sixth contact electrode CNE6 in the second region A2. Therefore, the 1-2nd intermediate electrode CTE1_2 may be used as a connection electrode (or a bridging electrode) connecting the second contact electrode CNE2 in the first region A1 and the sixth contact electrode CNE6 in the second region A2.

[0279] The first intermediate electrode CTE1 may be disposed on each of the sub-electrodes on the same layer as the layer on which the contact electrode CNE is disposed, and includes the same material as the material of the contact electrode CNE, and is formed by the same process as the process of the contact electrode CNE.

[0280] In an embodiment of the present disclosure, the 1-1 intermediate electrode CTE1_1 may be integrally formed with the second contact electrode CNE2 and / or the fourth contact electrode CNE4. In the case where the 1-1 intermediate electrode CTE1_1 is integrally formed with the second contact electrode CNE2 and / or the fourth contact electrode CNE4, the 1-1 intermediate electrode CTE1_1 may be regarded as a region of the second contact electrode CNE2 and / or a region of the fourth contact electrode CNE4. The 1-2 intermediate electrode CTE1_2 may be integrally formed with the second contact electrode CNE2 and / or the sixth contact electrode CNE6. In the case where the 1-2 intermediate electrode CTE1_2 is integrally formed with the second contact electrode CNE2 and / or the sixth contact electrode CNE6, the 1-2 intermediate electrode CTE1_2 may be regarded as a region of the second contact electrode CNE2 and / or a region of the sixth contact electrode CNE6. The 1-2 intermediate electrode CTE1_2 may be integrally formed with the 1-1 intermediate electrode CTE1_1.

[0281] As described above, the first intermediate electrode CTE1, the second contact electrode CNE2, the fourth contact electrode CNE4, and the sixth contact electrode CNE6 may be integrally formed and thus electrically connected and / or physically connected to each other. Therefore, the first series group SET1 and the second series group SET2 of each of the first sub-pixel SPXL1 and the second sub-pixel SPXL2 may be electrically connected and / or physically connected to each other.

[0282] The seventh contact electrode CNE7 may be disposed on the 1-3 sub-electrode SEL1_3 and connect the 1-3 sub-electrode SEL1_3 to one of the opposite end portions EP1 and EP2 of each 3-1 light-emitting element LD3_1. In a plan view, the seventh contact electrode CNE7 may overlap with one end portion of each 3-1 light-emitting element LD3_1 and the 1-3 sub-electrode SEL1_3.

[0283] The eighth contact electrode CNE8 may be disposed on the 2-3rd sub-electrode SEL2_3, and connect one of the opposite ends EP1 and EP2 of each 2-3rd sub-electrode SEL2_3 to the other end of each 3-1st light-emitting element LD3_1. In addition, the eighth contact electrode CNE8 may connect the other side of the 2-3rd sub-electrode SEL2_3 to one of the opposite ends EP1 and EP2 of each 3-2nd light-emitting element LD3_2. In a plan view, the eighth contact electrode CNE8 may overlap with the other end of each 3-1st light-emitting element LD3_1, one end of each 3-2nd light-emitting element LD3_2, and the 2-3rd sub-electrode SEL2_3.

[0284] The ninth contact electrode CNE9 may be disposed on the 3-3rd sub-electrode SEL3_3, and connect one of the opposite ends EP1 and EP2 of each 3-3rd sub-electrode SEL3_3 to the other end of each 3-2nd light-emitting element LD3_2. In a plan view, the ninth contact electrode CNE9 may overlap with the other end of each 3-2nd light-emitting element LD3_2 and the 3-3rd sub-electrode SEL3_3.

[0285] The seventh contact electrode CNE7, the eighth contact electrode CNE8, and the ninth contact electrode CNE9 may be disposed in the third region A3, and the third series group SET3 of each of the first sub-pixel SPXL1 and the second sub-pixel SPXL2 is located in the third region A3.

[0286] The fifth contact electrode CNE5 disposed in the second series group SET2 may be electrically and / or physically connected to the seventh contact electrode CNE7 and the ninth contact electrode CNE9 disposed in the third series group SET3 through the second intermediate electrode CTE2.

[0287] The second intermediate electrode CTE2 may be disposed on each of the sub-electrodes on the same layer as the layer on which the contact electrode CNE is disposed, include the same material as the material of the contact electrode CNE, and be formed by the same process as the process of the contact electrode CNE.

[0288] The second intermediate electrode CTE2 of each of the first sub-pixel SPXL1 and the second sub-pixel SPXL2 may be located in the boundary region between the second region A2 where the second series group SET2 is located and the third region A3 where the third series group SET3 is located. The second intermediate electrode CTE2 may include a 2-1st intermediate electrode CTE2_1 connecting the fifth contact electrode CNE5 and the seventh contact electrode CNE7, and a 2-2nd intermediate electrode CTE2_2 connecting the fifth contact electrode CNE5 and the ninth contact electrode CNE9.

[0289] The 2-1 intermediate electrode CTE2_1 can extend in a direction perpendicular to the third direction DR3 in the region between the second region A2 and the third region A3, and electrically connect and / or physically connect the fifth contact electrode CNE5 in the second region A2 and the seventh contact electrode CNE7 in the third region A3. Therefore, the 2-1 intermediate electrode CTE2_1 can be used as a connection electrode (or bridging electrode) for connecting the fifth contact electrode CNE5 in the second region A2 and the seventh contact electrode CNE7 in the third region A3.

[0290] The 2-2 intermediate electrode CTE2_2 can extend in the third direction DR3 in the region between the second region A2 and the third region A3, and electrically connect and / or physically connect the fifth contact electrode CNE5 in the second region A2 and the ninth contact electrode CNE9 in the third region A3. Therefore, the 2-2 intermediate electrode CTE2_2 can be used as a connection electrode (or bridging electrode) for connecting the fifth contact electrode CNE5 in the second region A2 and the ninth contact electrode CNE9 in the third region A3.

[0291] The 2-1 intermediate electrode CTE2_1 can be integrally formed with the fifth contact electrode CNE5 and / or the seventh contact electrode CNE7. In the case where the 2-1 intermediate electrode CTE2_1 is integrally formed with the fifth contact electrode CNE5 and / or the seventh contact electrode CNE7, the 2-1 intermediate electrode CTE2_1 can be regarded as a region of the fifth contact electrode CNE5 and / or a region of the seventh contact electrode CNE7. The 2-2 intermediate electrode CTE2_2 can be integrally formed with the fifth contact electrode CNE5 and / or the ninth contact electrode CNE9. In the case where the 2-2 intermediate electrode CTE2_2 is integrally formed with the fifth contact electrode CNE5 and / or the ninth contact electrode CNE9, the 2-2 intermediate electrode CTE2_2 can be regarded as a region of the fifth contact electrode CNE5 and / or a region of the ninth contact electrode CNE9.

[0292] As described above, the second intermediate electrode CTE2, the fifth contact electrode CNE5, the seventh contact electrode CNE7, and the ninth contact electrode CNE9 can be integrally formed, and thus are electrically connected and / or physically connected to each other. Therefore, the second series group SET2 and the third series group SET3 in each of the first sub-pixel SPXL1 and the second sub-pixel SPXL2 can be electrically connected and / or physically connected to each other.

[0293] In an embodiment of the present disclosure, in the step of forming the second contact electrode CNE2 of the first series group SET1 and the fourth contact electrode CNE4 and the sixth contact electrode CNE6 of the second series group SET2, the first intermediate electrode CTE1 that serially connects the first light-emitting element LD1 of the first series group SET1 and the second light-emitting element LD2 of the second series group SET2 can be formed simultaneously. In addition, in the step of forming the fifth contact electrode CNE5 of the second series group SET2 and the seventh contact electrode CNE7 and the ninth contact electrode CNE9 of the third series group SET3, the second intermediate electrode CTE2 that serially connects the second light-emitting element LD2 of the second series group SET2 and the third light-emitting element LD3 of the third series group SET3 can be formed simultaneously. Therefore, the process of manufacturing each pixel PXL including the first sub-pixel SPXL1 and the second sub-pixel SPXL2 and the display device including the pixel PXL can be facilitated, thereby improving the product yield.

[0294] Each of the first contact electrode CNE1 to the ninth contact electrode CNE9 may have a rod-shaped shape extending in the second direction DR2, but the present disclosure is not limited thereto, and for example, it can be changed into various shapes as long as it can reliably electrically connect and / or physically connect one of the sub-electrodes provided thereunder to one of the opposite end portions EP1 and EP2 of each of the light-emitting elements LD.

[0295] The third insulating layer INS3(ENC) may be provided and / or formed on the first contact electrode CNE1 to the ninth contact electrode CNE9. The third insulating layer INS3(ENC) may be a packaging layer covering the pixel circuit layer PCL and the display element layer DPL provided in each pixel PXL. The third insulating layer INS3(ENC) may be an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material. For example, the third insulating layer INS3(ENC) may have a structure formed by alternately stacking at least one inorganic layer and at least one organic layer.

[0296] According to the foregoing embodiment, the emission area EMA of each pixel PXL may be divided into a first sub-emission area SEMA1 and a second sub-emission area SEMA2 in a first direction DR1. A pixel circuit layer PCL including a pixel circuit provided with a driving transistor and a display element layer DPL including a light-emitting element LD may be formed in each of the first sub-emission area SEMA1 and the second sub-emission area SEMA2. Further, each of the first sub-emission area SEMA1 and the second sub-emission area SEMA2 is divided into a first area A1, a second area A2, and a third area A3 in a second direction DR2. In each of the first area A1, the second area A2, and the third area A3, at least two light-emitting elements LD connected in parallel with each other between sub-electrodes may be provided. Further, a first intermediate electrode CTE1 and / or a second intermediate electrode CTE2 provided in a boundary between the first area A1, the second area A2, and the third area A3 may connect one contact electrode CNE of a previous area in two successive areas to at least one contact electrode CNE of a subsequent area. Thus, the light-emitting elements LD provided (or supplied) to the first sub-emission area SEMA1 and the second sub-emission area SEMA2 may be connected in a series / parallel combination structure, and thus sub-emission units of each of the first sub-emission area SEMA1 and the second sub-emission area SEMA2 are formed. A first sub-emission unit EMU1 of the first sub-emission area SEMA1 and a second sub-emission unit EMU2 of the second sub-emission area SEMA2 may be combined to form an emission unit EMU of one pixel PXL.

[0297] According to the foregoing embodiments, the first sub-emission unit EMU1 and the second sub-emission unit EMU2 each having a series / parallel combination structure may be provided, so that each of the first sub-pixel SPXL1 and the second sub-pixel SPXL2 can be reliably driven, and the driving current to be supplied to the panel of the display device can be reduced. Accordingly, power consumption efficiency can be improved. In addition, the driving current may be supplied to the light-emitting element LD of the first sub-pixel SPXL1 through the first driving transistor T (Tdr1) included in the first pixel circuit 144_a, and the driving current may be supplied to the light-emitting element LD of the second sub-pixel SPXL2 through the second driving transistor T (Tdr2) included in the second pixel circuit 144_b. Accordingly, the driving current may be independently supplied to the light-emitting elements LD of the first sub-emission unit EMU1 and the second sub-emission unit EMU2, respectively. Therefore, driving currents that are equal or similar to each other may be respectively supplied to the light-emitting elements LD of the first sub-emission unit EMU1 and the second sub-emission unit EMU2, so that the light-emitting elements LD can emit light substantially uniformly. As a result, the first sub-emission unit EMU1 and the second sub-emission unit EMU2 may be combined to form the emission unit EMU of each pixel PXL, so that a plurality of pixels PXL provided in the display area DA of the display device may form a uniform light output distribution.

[0298] Figure 14 is a plan view showing a driving current flowing through a pixel according to an embodiment of the present disclosure, and, for example, shows the flow of the driving current flowing through Figure 8 the pixel. Specifically, in Figure 14 when the pixel PXL is driven to emit light in response to a data signal having a predetermined gray level, the flow of the driving current flowing through Figure 8 the pixel PXL is indicated by a dotted arrow.

[0299] Referring to Figures 1a to 5 、 Figure 7c 、and Figures 8 to 14 , if the driving current flows from the first power line PL1 to the second power line PL2 through the driving transistors of each of the first sub-pixel SPXL1 and the second sub-pixel SPXL2 included in each pixel PXL and via the first sub-pixel SPXL1 and the second sub-pixel SPXL2, the driving current may travel to the corresponding sub-emission unit through the first contact hole CH1 and the third contact hole CH3. For example, the driving current may be supplied to the 1-1 sub-electrode SEL1_1 and the 3-1 sub-electrode SEL3_1 of the first sub-emission unit EMU1 of the first sub-pixel SPXL1 through the first contact hole CH1, and supplied to the 1-1 sub-electrode SEL1_1 and the 3-1 sub-electrode SEL3_1 of the second sub-emission unit EMU2 of the second sub-pixel SPXL2 through the third contact hole CH3.

[0300] The drive currents supplied to the 1-1st sub-electrode SEL1_1 and the 3-1st sub-electrode SEL3_1 in each of the first sub-emission unit EMU1 and the second sub-emission unit EMU2 can flow to the 2-1st sub-electrode SEL2_1 via the 1-1st light-emitting element LD1_1 and the 1-2nd light-emitting element LD1_2 of the first series group SET1. Accordingly, each of the 1-1st light-emitting element LD1_1 and the 1-2nd light-emitting element LD1_2 can emit light with a brightness corresponding to the associated distributed current.

[0301] The drive current flowing through the 2-1st sub-electrode SEL2_1 of the first series group SET1 in each of the first sub-emission unit EMU1 and the second sub-emission unit EMU2 can travel through the first intermediate electrode CTE1 to the 1-2nd sub-electrode SEL1_2 and the 3-2nd sub-electrode SEL3_2 of the second series group SET2. The drive current flows to the 2-2nd sub-electrode SEL2_2 of the second series group SET2 via the 2-1st light-emitting element LD2_1 connected in the forward direction between the 1-2nd sub-electrode SEL1_2 and the 2-2nd sub-electrode SEL2_2 and the 2-2nd light-emitting element LD2_2 connected in the forward direction between the 3-2nd sub-electrode SEL3_2 and the 2-2nd sub-electrode SEL2_2. Accordingly, each of the 2-1st light-emitting element LD2_1 and the 2-2nd light-emitting element LD2_2 can emit light with a brightness corresponding to the associated distributed current.

[0302] The drive current flowing through the 2-2nd sub-electrode SEL2_2 of the second series group SET2 in each of the first sub-emission unit EMU1 and the second sub-emission unit EMU2 can travel through the second intermediate electrode CTE2 to the 1-3rd sub-electrode SEL1_3 and the 3-3rd sub-electrode SEL3_3 of the third series group SET3. The drive current flows to the 2-3rd sub-electrode SEL2_3 of the third series group SET3 via the 3-1st light-emitting element LD3_1 connected in the forward direction between the 1-3rd sub-electrode SEL1_3 and the 2-3rd sub-electrode SEL2_3 and the 3-2nd light-emitting element LD3_2 connected in the forward direction between the 3-3rd sub-electrode SEL3_3 and the 2-3rd sub-electrode SEL2_3. Accordingly, each of the 3-1st light-emitting element LD3_1 and the 3-2nd light-emitting element LD3_2 can emit light with a brightness corresponding to the associated distributed current.

[0303] The drive current flowing through the 2-3rd sub-electrode SEL2_3 of the third series group SET3 in each of the first sub-emission unit EMU1 and the second sub-emission unit EMU2 can travel to the drive voltage line (e.g., the second power line PL2) via the second contact hole CH2 and the second connection line CNL2. In this way, the drive current of each pixel PXL including the first sub-pixel SPXL1 and the second sub-pixel SPXL2 can sequentially flow through the first light-emitting element LD1 of the first series group SET1, the second light-emitting element LD2 of the second series group SET2, and the third light-emitting element LD3 of the third series group SET3. Therefore, each pixel PXL can emit light with a brightness corresponding to the data signal supplied during each frame period. In addition, since the same or similar drive current is separately supplied to the light-emitting element LD included in the first sub-emission unit EMU1 and the light-emitting element LD included in the second sub-emission unit EMU2 of the second sub-pixel SPXL2, each pixel PXL can have a light output distribution similar to or the same as that of the adjacent pixel PXL.

[0304] Figures 15a to 15f are schematic plan views sequentially showing the manufacturing Figure 8 of the pixel shown in Figures 1a to 16f are schematic plan views sequentially showing the manufacturing Figure 10 of the pixel shown in

[0305] Hereinafter, reference will be made to Figures 1a to 15f and Figures 1a to 16f to describe the manufacturing Figure 8 and Figure 10 of the pixel shown in according to an embodiment of the present disclosure.

[0306] Referring to Figures 1a to 5 , Figure 7c , Figures 8 to 10 , Figure 15a and Figure 16a , the pixel circuit layer PCL of the pixel PXL is formed on the substrate SUB. The pixel PXL may include an emission area EMA and a peripheral area provided around the emission area EMA.

[0307] The pixel circuit layer PCL may include a first pixel circuit 144_a and a second pixel circuit 144_b each including at least one transistor T, signal lines connected to each of the first pixel circuit 144_a and the second pixel circuit 144_b, and a passivation layer PSV. Here, the signal lines may include the second power line PL2 to which the second drive power supply VSS is to be applied.

[0308] The passivation layer PSV may include a first contact hole CH1 exposing the transistor T (e.g., the first driving transistor T (Tdr1) included in the first pixel circuit 144_a), a second contact hole CH2 exposing the second power line PL2, and a third contact hole CH3 exposing the second driving transistor T (Tdr2) included in the second pixel circuit 144_b.

[0309] Subsequently, a first bank pattern BNK1 is formed on the passivation layer PSV. Each first bank pattern BNK1 may be spaced apart from an adjacent first bank pattern BNK1 on the passivation layer PSV by a predetermined distance. In a plan view, the first bank pattern BNK1 may have a rod-like shape extending in the second direction DR2, but the present disclosure is not limited thereto. The first bank pattern BNK1 may include an inorganic insulating layer formed of an inorganic material, or an organic insulating layer formed of an organic material.

[0310] refer to Figures 1a to 5 、 Figure 7c 、 Figures 8 to 10 、 Figure 15b 、 Figure 16a and Figure 16b First to sixth conductive lines CL1 to CL6 , a bridge pattern BRP, and a second connection line CNL2 including a conductive material (or substance) having high reflectivity are formed on the passivation layer PSV including the first bank pattern BNK1 .

[0311] Each of the first to sixth conductive lines CL1 to CL6 may be formed on a corresponding first bank pattern BNK1 in the emission area EMA of the pixel PXL and spaced apart from adjacent conductive lines. Here, the distance between the third conductive line CL3 and the fourth conductive line CL4 may be less than the distance between two other adjacent conductive lines. Accordingly, considering the degree of integration of the components included in the emission area EMA of each pixel PXL, during subsequent processes, the light-emitting element LD input to the emission area EMA may be aligned only in a desired area. However, the present disclosure is not limited thereto. In an embodiment, the distance between the third conductive line CL3 and the fourth conductive line CL4 may be the same as the distance between two other adjacent conductive lines.

[0312] In an embodiment of the present disclosure, the first conductive line CL1 may be connected to the first driving transistor T (Tdr1) of the first pixel circuit 144_a through the first contact hole CH1, and the sixth conductive line CL6 may be connected to the second driving transistor T (Tdr2) of the second pixel circuit 144_b through the third contact hole CH3.

[0313] The bridging pattern BRP may extend in a first direction DR1 and be connected to the first wire CL1, the third wire CL3, the fourth wire CL4, and the sixth wire CL6 among the first wire CL1 to the sixth wire CL6. In an embodiment of the present disclosure, the bridging pattern BRP, the first wire CL1, the third wire CL3, the fourth wire CL4, and the sixth wire CL6 may be integrally formed and electrically connected and / or physically connected to each other. In an embodiment of the present disclosure, the bridging pattern BRP may be commonly disposed between each pixel PXL and the pixel PXL adjacent thereto. The pixels PXL disposed in the same row in the first direction DR1 may be commonly connected to the bridging pattern BRP.

[0314] The second connection line CNL2 may extend in the first direction DR1 and be connected to the second wire CL2 and the fifth wire CL5 among the first wire CL1 to the sixth wire CL6. In an embodiment of the present disclosure, the second connection line CNL2, the second wire CL2, and the fifth wire CL5 may be integrally formed and electrically connected and / or physically connected to each other. The second connection line CNL2 may be electrically connected to the second power line PL2 through the second contact hole CH2. In an embodiment of the present disclosure, the second connection line CNL2 may be commonly disposed between each pixel PXL and the pixel PXL adjacent thereto. The pixels PXL disposed in the same row in the first direction DR1 may be commonly connected to the second connection line CNL2.

[0315] In a plan view, the first wire CL1 to the sixth wire CL6 may be sequentially disposed and / or formed in the emission area EMA of the pixel PXL in the first direction DR1. In addition, each of the first wire CL1 to the sixth wire CL6 may extend in a second direction DR2 in the emission area EMA of the pixel PXL.

[0316] Subsequently, an insulating material layer INSM is formed on the passivation layer PSV including the first wire CL1 to the sixth wire CL6, the bridging pattern BRP, the second connection line CNL2, etc. The insulating material layer INSM may include an inorganic insulating layer or an organic insulating layer, where the inorganic insulating layer includes an inorganic material and the organic insulating layer includes an organic material.

[0317] Reference Figures 1a to 5 、 Figure 7c 、 Figures 8 to 10 、 Figure 、 ​ and ​, a second bank pattern BNK2 is formed in a peripheral region disposed around an emission region EMA of a pixel PXL. Here, the second bank pattern BNK2 may be formed on an insulating material layer INSM. The second bank pattern BNK2 may be a pixel defining layer that defines (or divides) the emission region EMA between the pixel PXL and an adjacent pixel to the pixel PXL. The second bank pattern BNK2 may include an inorganic insulating layer and / or an organic insulating layer, the inorganic insulating layer includes an inorganic material, and the organic insulating layer includes an organic material. In an embodiment, the second bank pattern BNK2 may be formed by the same process as the process of forming the first bank pattern BNK1 in the emission region EMA of the pixel PXL.

[0318] Reference ​ , ​ , ​ , ​ and ​ , first wires CL1 to sixth wires CL6 are respectively supplied with corresponding alignment signals (or alignment voltages) through a bridging pattern BRP and a second connection line CNL2, so that an electric field can be formed between two adjacent wires. Here, a first alignment signal (or a first alignment voltage) may be applied to each of the first wire CL1, the third wire CL3, the fourth wire CL4, and the sixth wire CL6 connected to the bridging pattern BRP. A second alignment signal (or a second alignment voltage) having a voltage level different from that of the first alignment signal may be applied to each of the second wire CL2 and the fifth wire CL5 connected to the second connection line CNL2.

[0319] For example, in a case where AC power or DC power having a predetermined voltage and period is repeatedly applied to each of the first wire CL1 to the sixth wire CL6 several times, an electric field can be formed between two adjacent wires among the first wire CL1 to the sixth wire CL6, and the electric field corresponds to a difference between corresponding potentials of the two adjacent wires. Here, since the same alignment signal is applied to the third wire CL3 and the fourth wire CL4, no potential difference may occur between the two wires CL3 and CL4.

[0320] While an electric field is formed between the first through sixth wires CL1 to CL6 formed in the emission area EMA of the pixel PXL, a mixed solution including the light-emitting element LD is supplied to the emission area EMA by an inkjet printing method or the like. For example, an inkjet nozzle is disposed on the insulating material layer INSM, and a solvent mixed with a plurality of light-emitting elements LD can be supplied to the emission area EMA of the pixel PXL by removing the inkjet nozzle. Here, the solvent can be any one of acetone, water, alcohol, and toluene, but the present disclosure is not limited thereto. For example, the solvent can have the form of ink or paste. The method of supplying the light-emitting element LD to the emission area EMA of the pixel PXL is not limited to the method of the foregoing embodiment. The method of supplying the light-emitting element LD can be changed in various ways.

[0321] After the light-emitting element LD is supplied to the emission area EMA of the pixel PXL, the solvent can be removed.

[0322] In the case where the light-emitting element LD is supplied to the emission area EMA of the pixel PXL, self-alignment of the light-emitting element LD can be caused by the electric field formed between the first through sixth wires CL1 to CL6. Accordingly, the light-emitting element LD can be aligned between the first wire CL1 and the second wire CL2, between the second wire CL2 and the third wire CL3, between the fourth wire CL4 and the fifth wire CL5, and between the fifth wire CL5 and the sixth wire CL6. Each of the light-emitting elements LD can be aligned on the insulating material layer INSM in the emission area EMA of the pixel PXL.

[0323] The light-emitting elements LD can be connected in the forward direction between two wires adjacent to each other in the first direction DR1. For example, the first end EP1 of each of the light-emitting elements LD aligned between the first wire CL1 and the second wire CL2 can be connected to the first wire CL1, and the second end EP2 of each of the light-emitting elements LD aligned between the first wire CL1 and the second wire CL2 can be connected to the second wire CL2. In addition, the first end EP1 of each of the light-emitting elements LD aligned between the second wire CL2 and the third wire CL3 can be connected to the third wire CL3, and the second end EP2 of each of the light-emitting elements LD aligned between the second wire CL2 and the third wire CL3 can be connected to the second wire CL2. The first end EP1 of each of the light-emitting elements LD aligned between the fourth wire CL4 and the fifth wire CL5 can be connected to the fourth wire CL4, and the second end EP2 of each of the light-emitting elements LD aligned between the fourth wire CL4 and the fifth wire CL5 can be connected to the fifth wire CL5. In addition, the first end EP1 of each of the light-emitting elements LD aligned between the fifth wire CL5 and the sixth wire CL6 can be connected to the sixth wire CL6, and the second end EP2 of each of the light-emitting elements LD aligned between the fifth wire CL5 and the sixth wire CL6 can be connected to the fifth wire CL5.

[0324] In an embodiment, the light-emitting element LD can include at least one reverse light-emitting element LDr, which is connected in a direction opposite to the forward direction according to the wavelength of the alignment signal applied to each of two adjacent wires.

[0325] In the step of aligning the light-emitting elements LD, for example, by adjusting the alignment signal to be applied to two adjacent wires to control the direction and magnitude of the electric field formed between the two adjacent wires, the ratio of the number of light-emitting elements LD arranged in the forward direction to the number of light-emitting elements connected in a direction opposite to the forward direction (e.g., the number of reverse light-emitting elements LDr) in the emission area EMA of the pixel PXL can be adjusted, or the light-emitting elements LD aligned in the forward direction can be concentratedly arranged at a specific position in the emission area EMA.

[0326] Reference ​ 、 ​ 、 ​ and ​ , after the light-emitting elements LD are aligned in the emission area EMA of the pixel PXL, a second insulating layer INS2 is formed on each of the light-emitting elements LD. The second insulating layer INS2 can cover at least a part of the upper surface of each of the light-emitting elements LD, so that the opposite ends EP1 and EP2 of each of the light-emitting elements LD can be exposed to the outside.

[0327] The first insulating layer INS1 can be formed by etching an insulating material layer INSM through a process for forming the second insulating layer INS2 or an etching process to be performed before or after this process, such that a part of each of the first to sixth conductive lines CL1 to CL6 is exposed.

[0328] Reference ​ , ​ , ​ , ​ and ​ , first contact electrodes CNE1 to CNE9 are formed on the first to sixth conductive lines CL1 to CL6, and two first intermediate electrodes CTE1 and two second intermediate electrodes CTE2 are formed that are connected to some of the first contact electrodes CNE1 to CNE9.

[0329] The first contact electrode CNE1, the fourth contact electrode CNE4, and the seventh contact electrode CNE7 can be formed on the first conductive line CL1. The first contact electrode CNE1, the fourth contact electrode CNE4, and the seventh contact electrode CNE7 can be directly formed on the first conductive line CL1 and are electrically and / or physically connected to the first conductive line CL1. The second contact electrode CNE2, the fifth contact electrode CNE5, and the eighth contact electrode CNE8 can be formed on the second conductive line CL2. The second contact electrode CNE2, the fifth contact electrode CNE5, and the eighth contact electrode CNE8 can be directly formed on the second conductive line CL2 and are electrically and / or physically connected to the second conductive line CL2. The third contact electrode CNE3, the sixth contact electrode CNE6, and the ninth contact electrode CNE9 can be formed on the third conductive line CL3. The third contact electrode CNE3, the sixth contact electrode CNE6, and the ninth contact electrode CNE9 can be directly formed on the third conductive line CL3 and are electrically and / or physically connected to the third conductive line CL3.

[0330] The first contact electrode CNE1, the fourth contact electrode CNE4, and the seventh contact electrode CNE7 can be formed on the fourth wire CL4. The first contact electrode CNE1, the fourth contact electrode CNE4, and the seventh contact electrode CNE7 can be directly formed on the fourth wire CL4 and be electrically connected and / or physically connected to the fourth wire CL4. The second contact electrode CNE2, the fifth contact electrode CNE5, and the eighth contact electrode CNE8 can be formed on the fifth wire CL5. The second contact electrode CNE2, the fifth contact electrode CNE5, and the eighth contact electrode CNE8 can be directly formed on the fifth wire CL5 and be electrically connected and / or physically connected to the fifth wire CL5. The third contact electrode CNE3, the sixth contact electrode CNE6, and the ninth contact electrode CNE9 can be formed on the sixth wire CL6. The third contact electrode CNE3, the sixth contact electrode CNE6, and the ninth contact electrode CNE9 can be directly formed on the sixth wire CL6 and be electrically connected and / or physically connected to the sixth wire CL6.

[0331] One of the two first intermediate electrodes CTE1 can include a 1-1 intermediate electrode CTE1_1 connecting the second contact electrode CNE2 on the second wire CL2 to the fourth contact electrode CNE4 on the first wire CL1, and a 1-2 intermediate electrode CTE1_2 connecting the second contact electrode CNE2 to the sixth contact electrode CNE6 on the third wire CL3.

[0332] The other of the two first intermediate electrodes CTE1 can include a 1-1 intermediate electrode CTE1_1 connecting the second contact electrode CNE2 on the fifth wire CL5 to the fourth contact electrode CNE4 on the fourth wire CL4, and a 1-2 intermediate electrode CTE1_2 connecting the second contact electrode CNE2 to the sixth contact electrode CNE6 on the sixth wire CL6.

[0333] One of the two second intermediate electrodes CTE2 can include a second intermediate electrode CTE2_1 connecting the fifth contact electrode CNE5 on the second wire CL2 to the seventh contact electrode CNE7 on the first wire CL1, and a 2-2 intermediate electrode CTE2_2 connecting the fifth contact electrode CNE5 to the ninth contact electrode CNE9 on the third wire CL3.

[0334] The other of the two second intermediate electrodes CTE2 can include a second intermediate electrode CTE2_1 connecting the fifth contact electrode CNE5 on the fifth wire CL5 to the seventh contact electrode CNE7 on the fourth wire CL4, and a 2-2 intermediate electrode CTE2_2 connecting the fifth contact electrode CNE5 to the ninth contact electrode CNE9 on the sixth wire CL6.

[0335] Reference ​ 、 ​ 、 ​ and ​ ,In order to allow each pixel PXL to be driven independently (or individually) from its adjacent pixels PXL, a mask is used to remove a part of the bridging pattern BRP between the pixel PXL and the adjacent pixels PXL by an etching method or the like, thereby forming a first connection line CNL1 and a third connection line CNL3. In an embodiment of the present disclosure, in the case of performing the process of removing a part of the bridging pattern BRP, the second connection line CNL2 may be commonly provided to each pixel PXL and the pixel PXL adjacent thereto, rather than being separated between the pixel PXL and the adjacent pixels PXL, but the present disclosure is not limited thereto. In an embodiment, during the process of removing a part of the bridging pattern BRP, a part of the second connection line CNL2 may also be removed between each pixel PXL and the pixel PXL adjacent thereto, so that the pixel PXL and the adjacent pixel PXL can be separated from each other.

[0336] The first connection line CNL1 and the third connection line CNL3 formed by the process of removing a part of the bridging pattern BRP may be electrically separated and / or physically separated from each other. In other words, the first connection line CNL1 and the third connection line CNL3 may be independent conductive patterns (or wires) that are separated from each other rather than connected to each other. The first connection line CNL1 may be electrically connected and / or physically connected to the first wire CL1 and the third wire CL3. The third connection line CNL3 may be electrically connected and / or physically connected to the fourth wire CL4 and the sixth wire CL6.

[0337] Each pixel PXL may be divided into a first sub-pixel SPXL1 including the first connection line CNL1 and a second sub-pixel SPXL2 including the third connection line CNL3. Thus, the pixel region in which each pixel PXL is disposed may include a first sub-region SPXA1 in which the first sub-pixel SPXL1 is disposed, and a second sub-region SPXA2 in which the second sub-pixel SPXL2 is disposed. In an embodiment of the present disclosure, the first sub-region SPXA1 may include a first sub-emission region SEMA1 that emits light. The second sub-region SPXA2 may include a second sub-emission region SEMA2 that emits light. The first wire CL1, the second wire CL2, and the third wire CL3 may correspond to (or be disposed in) the first sub-emission region SEMA1. The fourth wire CL4, the fifth wire CL5, and the sixth wire CL6 may correspond to (or be disposed in) the second sub-emission region SEMA2.

[0338] During the process of separating the first connection line CNL1 and the third connection line CNL3 from each other by removing a part of the bridging pattern BRP, each of the first through sixth conductive lines CL1 to CL6 may be partially removed or disconnected, and thus is configured in the form of an electrode including three sub-electrodes spaced apart from each other in the second direction DR2.

[0339] During the process of separating the first connection line CNL1 and the third connection line CNL3 from each other, the first conductive line CL1 of the first sub-emission region SEMA1 may be partially removed or disconnected, and thus the first electrode EL1 is formed, which includes the 1-1 sub-electrode SEL1_1, the 1-2 sub-electrode SEL1_2, and the 1-3 sub-electrode SEL1_3 that are arranged in the same column and spaced apart from each other in the second direction DR2. During the process of separating the first connection line CNL1 and the third connection line CNL3 from each other, the second conductive line CL2 of the first sub-emission region SEMA1 may be partially removed or disconnected, and thus the second electrode EL2 is formed, which includes the 2-1 sub-electrode SEL2_1, the 2-2 sub-electrode SEL2_2, and the 2-3 sub-electrode SEL2_3 that are arranged in the same column and spaced apart from each other in the second direction DR2. During the process of separating the first connection line CNL1 and the third connection line CNL3 from each other, the third conductive line CL3 of the first sub-emission region SEMA1 may be partially removed or disconnected, and thus the third electrode EL3 is formed, which includes the 3-1 sub-electrode SEL3_1, the 3-2 sub-electrode SEL3_2, and the 3-3 sub-electrode SEL3_3 that are arranged in the same column and spaced apart from each other in the second direction DR2.

[0340] During the process of separating the first connection line CNL1 and the third connection line CNL3 from each other, the fourth wire CL4 of the second sub-emission region SEMA2 may be partially removed or disconnected, and thus the first electrode EL1 is formed, which includes the 1-1 sub-electrode SEL1_1, the 1-2 sub-electrode SEL1_2, and the 1-3 sub-electrode SEL1_3 that are arranged in the same column and spaced apart from each other in the second direction DR2. During the process of separating the first connection line CNL1 and the third connection line CNL3 from each other, the fifth wire CL5 of the second sub-emission region SEMA2 may be partially removed or disconnected, and thus the second electrode EL2 is formed, which includes the 2-1 sub-electrode SEL2_1, the 2-2 sub-electrode SEL2_2, and the 2-3 sub-electrode SEL2_3 that are arranged in the same column and spaced apart from each other in the second direction DR2. During the process of separating the first connection line CNL1 and the third connection line CNL3 from each other, the sixth wire CL6 of the second sub-emission region SEMA2 may be partially removed or disconnected, and thus the third electrode EL3 is formed, which includes the 3-1 sub-electrode SEL3_1, the 3-2 sub-electrode SEL3_2, and the 3-3 sub-electrode SEL3_3 that are arranged in the same column and spaced apart from each other in the second direction DR2.

[0341] Each of the first sub-emission region SEMA1 and the second sub-emission region SEMA2 may be divided (or partitioned) into a first region A1, a second region A2, and a third region A3 according to the positions of the sub-electrodes. In the first region A1 of each of the first sub-emission region SEMA1 and the second sub-emission region SEMA2, the 1-1 sub-electrode SEL1_1, the 2-1 sub-electrode SEL2_1, and the 3-1 sub-electrode SEL3_1 may be provided. In the second region A2 of each of the first sub-emission region SEMA1 and the second sub-emission region SEMA2, the 1-2 sub-electrode SEL1_2, the 2-2 sub-electrode SEL2_2, and the 3-2 sub-electrode SEL3_2 may be provided. In the third region A3 of each of the first sub-emission region SEMA1 and the second sub-emission region SEMA2, the 1-3 sub-electrode SEL1_3, the 2-3 sub-electrode SEL2_3, and the 3-3 sub-electrode SEL3_3 may be provided.

[0342] In a plan view, the light-emitting element LD may include a first light-emitting element LD1 aligned (or disposed) in a first region A1 of each of a first sub-emission region SEMA1 and a second sub-emission region SEMA2, a second light-emitting element LD2 aligned (or disposed) in a second region A2 of each of the first sub-emission region SEMA1 and the second sub-emission region SEMA2, and a third light-emitting element LD3 aligned (or disposed) in a third region A3 of each of the first sub-emission region SEMA1 and the second sub-emission region SEMA2.

[0343] The first light-emitting element LD1 may include at least one first 1-1 light-emitting element LD1_1 aligned (or disposed) between a first 1-1 sub-electrode SEL1_1 and a second 1-1 sub-electrode SEL2_1 in each of the first sub-emission region SEMA1 and the second sub-emission region SEMA2, and at least one first 1-2 light-emitting element LD1_2 aligned (or disposed) between the second 1-1 sub-electrode SEL2_1 and a third 1-1 sub-electrode SEL3_1. The first light-emitting element LD1, together with two adjacent sub-electrodes interposed therebetween in each of the first light-emitting elements LD1, may form a first series group SET1 of sub-emission units in each of the first sub-emission region SEMA1 and the second sub-emission region SEMA2. In other words, the first light-emitting element LD1 of the first sub-emission region SEMA1, together with two adjacent sub-electrodes interposed therebetween in each of the first light-emitting elements LD1, may form a first series group SET1 of the first sub-emission unit EMU1. The first light-emitting element LD1 of the second sub-emission region SEMA2, together with two adjacent sub-electrodes interposed therebetween in each of the first light-emitting elements LD1, may form a first series group SET1 of the second sub-emission unit EMU2.

[0344] One end EP1 of the opposite ends EP1 and EP2 of the first 1-1 light-emitting element LD1_1 may be more reliably connected to the first 1-1 sub-electrode SEL1_1 through a first contact electrode CNE1 on the first 1-1 sub-electrode SEL1_1, and the other end EP2 of the opposite ends EP1 and EP2 of the first 1-1 light-emitting element LD1_1 may be more reliably connected to the second 1-1 sub-electrode SEL2_1 through a second contact electrode CNE2 on the second 1-1 sub-electrode SEL2_1.

[0345] One end EP1 of the opposite ends EP1 and EP2 of the first 1-2 light-emitting element LD1_2 may be more reliably connected to the third 1-1 sub-electrode SEL3_1 through a third contact electrode CNE3 on the third 1-1 sub-electrode SEL3_1, and the other end EP2 of the opposite ends EP1 and EP2 of the first 1-2 light-emitting element LD1_2 may be more reliably connected to the second 1-1 sub-electrode SEL2_1 through a second contact electrode CNE2 on the second 1-1 sub-electrode SEL2_1.

[0346] The second light-emitting element LD2 may include at least one 2-1 light-emitting element LD2_1 aligned (or disposed) between the 1-2 sub-electrode SEL1_2 and the 2-2 sub-electrode SEL2_2 and at least one 2-2 light-emitting element LD2_2 aligned (or disposed) between the 2-2 sub-electrode SEL2_2 and the 3-2 sub-electrode SEL3_2 in each of the first sub-emission region SEMA1 and the second sub-emission region SEMA2. The second light-emitting element LD2, together with two adjacent sub-electrodes interposed therebetween in each of the second light-emitting elements LD2, may form a second series group SET2 of sub-emission units in each of the first sub-emission region SEMA1 and the second sub-emission region SEMA2. In other words, the second light-emitting element LD2 of the first sub-emission region SEMA1, together with two adjacent sub-electrodes interposed therebetween in each of the second light-emitting elements LD2, may form a second series group SET2 of the first sub-emission unit EMU1. The second light-emitting element LD2 of the second sub-emission region SEMA2, together with two adjacent sub-electrodes interposed therebetween in each of the second light-emitting elements LD2, may form a second series group SET2 of the second sub-emission unit EMU2.

[0347] One end EP1 of the opposite ends EP1 and EP2 of the 2-1 light-emitting element LD2_1 may be more reliably connected to the 1-2 sub-electrode SEL1_2 through the fourth contact electrode CNE4 on the 1-2 sub-electrode SEL1_2, and the other end EP2 of the opposite ends EP1 and EP2 of the 2-1 light-emitting element LD2_1 may be more reliably connected to the 2-2 sub-electrode SEL2_2 through the fifth contact electrode CNE5 on the 2-2 sub-electrode SEL2_2.

[0348] One end EP1 of the opposite ends EP1 and EP2 of the 2-2 light-emitting element LD2_2 may be more reliably connected to the 3-2 sub-electrode SEL3_2 through the sixth contact electrode CNE6 on the 3-2 sub-electrode SEL3_2, and the other end EP2 of the opposite ends EP1 and EP2 of the 2-2 light-emitting element LD2_2 may be more reliably connected to the 2-2 sub-electrode SEL2_2 through the fifth contact electrode CNE5 on the 2-2 sub-electrode SEL2_2.

[0349] In an embodiment of the present disclosure, the second contact electrode CNE2 on the 2-1 sub-electrode SEL2_1 of the first series group SET1 of each of the first sub-emission region SEMA1 and the second sub-emission region SEMA2 can be electrically and / or physically connected to the fourth contact electrode CNE4 on the 1-2 sub-electrode SEL1_2 of the second series group SET2 of the corresponding sub-emission region through the 1-1 intermediate electrode CTE1_1. In addition, the second contact electrode CNE2 on the 2-1 sub-electrode SEL2_1 of the first series group SET1 of each of the first sub-emission region SEMA1 and the second sub-emission region SEMA2 can be electrically and / or physically connected to the sixth contact electrode CNE6 on the 3-2 sub-electrode SEL3_2 of the second series group SET2 of the corresponding sub-emission region through the 1-2 intermediate electrode CTE1_2.

[0350] The third light-emitting element LD3 may include at least one 3-1 light-emitting element LD3_1 aligned (or arranged) between the 1-3 sub-electrode SEL1_3 and the 2-3 sub-electrode SEL2_3 and at least one 3-2 light-emitting element LD3_2 aligned (or arranged) between the 2-3 sub-electrode SEL2_3 and the 3-3 sub-electrode SEL3_3 in each of the first sub-emission region SEMA1 and the second sub-emission region SEMA2. The third light-emitting element LD3 together with the two adjacent sub-electrodes interposed therebetween in each of the third light-emitting elements LD3 can form the third series group SET3 of the sub-emission unit of each of the first sub-emission region SEMA1 and the second sub-emission region SEMA2. In other words, the third light-emitting element LD3 of the first sub-emission region SEMA1 together with the two adjacent sub-electrodes interposed therebetween in each of the third light-emitting elements LD3 can form the third series group SET3 of the first sub-emission unit EMU1. The third light-emitting element LD3 of the second sub-emission region SEMA2 together with the two adjacent sub-electrodes interposed therebetween in each of the third light-emitting elements LD3 can form the third series group SET3 of the second sub-emission unit EMU2.

[0351] One end EP1 of the opposite ends EP1 and EP2 of the 3-1 light-emitting element LD3_1 can be more reliably connected to the 1-3 sub-electrode SEL1_3 through the seventh contact electrode CNE7 on the 1-3 sub-electrode SEL1_3, and the other end EP2 of the opposite ends EP1 and EP2 of the 3-1 light-emitting element LD3_1 can be more reliably connected to the 2-3 sub-electrode SEL2_3 through the eighth contact electrode CNE8 on the 2-3 sub-electrode SEL2_3.

[0352] One of the opposite ends EP1 and EP2 of the 3-2 light-emitting element LD3_2, i.e., EP1, can be more reliably connected to the 3-3 sub-electrode SEL3_3 through the ninth contact electrode CNE9 on the 3-3 sub-electrode SEL3_3, and the other end EP2 of the opposite ends EP1 and EP2 of the 3-2 light-emitting element LD3_2 can be more reliably connected to the 2-3 sub-electrode SEL2_3 through the eighth contact electrode CNE8 on the 2-3 sub-electrode SEL2_3.

[0353] In an embodiment of the present disclosure, the fifth contact electrode CNE5 on the 2-2 sub-electrode SEL2_2 of the second series group SET2 of each of the first sub-emission region SEMA1 and the second sub-emission region SEMA2 can be electrically connected and / or physically connected to the seventh contact electrode CNE7 on the 1-3 sub-electrode SEL1_3 of the third series group SET3 of the corresponding sub-emission region through the 2-1 intermediate electrode CTE2_1. In addition, the fifth contact electrode CNE5 on the 2-2 sub-electrode SEL2_2 of the second series group SET2 of each of the first sub-emission region SEMA1 and the second sub-emission region SEMA2 can be electrically connected and / or physically connected to the ninth contact electrode CNE9 on the 3-3 sub-electrode SEL3_3 of the third series group SET3 of the corresponding sub-emission region through the 2-2 intermediate electrode CTE2_2.

[0354] In each of the first sub-pixel SPXL1 and the second sub-pixel SPXL2, the 1-1 sub-electrode SEL1_1, the 2-1 sub-electrode SEL2_1, and the 3-1 sub-electrode SEL3_1, and the first light-emitting element LD1 connected in the forward direction therebetween can form a first series group SET1. The 1-2 sub-electrode SEL1_2, the 2-2 sub-electrode SEL2_2, and the 3-2 sub-electrode SEL3_2, and the second light-emitting element LD2 connected in the forward direction therebetween can form a second series group SET2. The 1-3 sub-electrode SEL1_3, the 2-3 sub-electrode SEL2_3, and the 3-3 sub-electrode SEL3_3, and the third light-emitting element LD3 connected in the forward direction therebetween can form a third series group SET3.

[0355] The first series group SET1 and the second series group SET2 can be electrically connected to each other through the first intermediate electrode CTE1. The second series group SET2 and the third series group SET3 can be electrically connected to each other through the second intermediate electrode CTE2.

[0356] The first to third series groups SET1 to SET3 of the first sub-pixel SPXL1 can form a first sub-emission unit EMU1 of a first sub-emission region SEMA1. The first to third series groups SET1 to SET3 of the second sub-pixel SPXL2 can form a second sub-emission unit EMU2 of a second sub-emission region SEMA2. In an embodiment of the present disclosure, the first sub-emission unit EMU1 and the second sub-emission unit EMU2 can be combined to form an emission unit EMU of each pixel PXL.

[0357] Reference ​ 、 ​ and ​ , after forming a first electrode EL1, a second electrode EL2, and a third electrode EL3 in each of the first sub-emission region SEMA1 and the second sub-emission region SEMA2, a third insulating layer INS3 (ENC) is formed to cover first to ninth contact electrodes CNE1 to CNE9 on the first electrode EL1, the second electrode EL2, and the third electrode EL3.

[0358] ​ is a plan view showing another embodiment of the first to third connection lines shown in ​ .

[0359] Except for the fact that the first connection line CNL1 of the first sub-pixel SPXL1 and the third connection line CNL3 of the second sub-pixel SPXL2 are provided in the peripheral region of the pixel PXL, ​ the pixel PXL shown in ​ can have a configuration that is substantially the same as or similar to the configuration of the pixel PXL in

[0360] In ​ , a detailed description of configurations that are the same as or similar to the configurations of the above ​ embodiments will be omitted.

[0361] Reference ​ 、 ​ and Figure 17 , the pixel PXL can include an emission region EMA that can emit light, and a peripheral region provided around the emission region EMA. The emission region EMA can include a first sub-emission region SEMA1 and a second sub-emission region SEMA2.

[0362] In the peripheral region of the pixel PXL, a second bank pattern BNK2 can be provided and / or formed to define (or divide) the corresponding emission region EMA of the pixel PXL. In addition, a first connection line CNL1 connecting the 1-1 sub-electrode SEL1_1 and the 3-1 sub-electrode SEL3_1 connected to the first sub-emission region SEMA1, and a third connection line CNL3 connecting the 1-1 sub-electrode SEL1_1 and the 3-1 sub-electrode SEL3_1 connected to the second sub-emission region SEMA2 can be provided in the peripheral region of the pixel PXL.

[0363] In reference Figure 15f In the step of removing a part of the bridging pattern BRP described, the bridging pattern BRP can be divided into the first connection line CNL1 and the third connection line CNL3. Here, the bridging pattern BRP can be provided in the peripheral region of the pixel PXL. The pixel PXL and an adjacent pixel PXL thereto (e.g., a pixel provided in the same row as the pixel PXL) can share the bridging pattern BRP. In other words, the bridging pattern BRP provided in the peripheral region of the pixel PXL can be provided not only to the peripheral region of the pixel PXL but also to the peripheral region of an adjacent pixel PXL to the pixel PXL.

[0364] In this case, if a part of the bridging pattern BRP is removed from the peripheral regions of the pixel PXL and an adjacent pixel PXL thereto, the first connection line CNL1 and the third connection line CNL3 that are electrically separated and / or physically separated from each other can be formed in the peripheral region of the pixel PXL. Accordingly, each of the first connection line CNL1 and the third connection line CNL3 can be electrically connected and / or physically connected to the 1-1 sub-electrode SEL1_1 and the 3-1 sub-electrode SEL3_1 of the corresponding sub-pixel in the peripheral region of the corresponding pixel PXL. For example, the first connection line CNL1 can be electrically connected and / or physically connected to the 1-1 sub-electrode SEL1_1 and the 3-1 sub-electrode SEL3_1 included in the first sub-pixel SPXL1 of the pixel PXL. The third connection line CNL3 can be electrically connected and / or physically connected to the 1-1 sub-electrode SEL1_1 and the 3-1 sub-electrode SEL3_1 included in the second sub-pixel SPXL2 of the pixel PXL.

[0365] Figures 18 to 21 is a schematic plan view showing another example of a pixel according to an embodiment of the present disclosure.

[0366] In Figures 18 to 21 will omit the detailed description of configurations that are the same as or similar to the configurations of the embodiment of Figure 8 For the sake of brevity, detailed descriptions of configurations identical or similar to those of the embodiments of

[0367] Reference Figures 1a to 5 and Figure 18, the pixel PXL may include a first sub-pixel SPXL1 and a second sub-pixel SPXL2. The first sub-pixel SPXL1 may include a first sub-emission region SEMA1. The second sub-pixel SPXL2 may include a second sub-emission region SEMA2. The first sub-emission region SEMA1 and the second sub-emission region SEMA2 may be combined to form an emission region EMA of the pixel PXL.

[0368] The first electrode EL1, the second electrode EL2, and the third electrode EL3 may be disposed in each of the first sub-emission region SEMA1 and the second sub-emission region SEMA2. The first contact electrode CNE1 may be disposed on the first electrode EL1. The second contact electrode CNE2 may be disposed on the second electrode EL2. The third contact electrode CNE3 may be disposed on the third electrode EL3. In addition, a first light-emitting element LD1 disposed between two adjacent electrodes may be disposed in each of the first sub-emission region SEMA1 and the second sub-emission region SEMA2.

[0369] The first light-emitting element LD1 may include a 1-1 light-emitting element LD1_1 disposed between the first electrode EL1 and the second electrode EL2 and a 1-2 light-emitting element LD1_2 disposed between the second electrode EL2 and the third electrode EL3 in each of the first sub-emission region SEMA1 and the second sub-emission region SEMA2. The first electrode EL1, the second electrode EL2, the third electrode EL3, and the first light-emitting element LD1 in the first sub-emission region SEMA1 may form a first sub-emission unit. The first electrode EL1, the second electrode EL2, the third electrode EL3, and the second light-emitting element LD2 in the second sub-emission region SEMA2 may form a second sub-emission unit.

[0370] The first electrode EL1 of the first sub-emission unit may be connected to a driving transistor (hereinafter referred to as "first driving transistor") of a pixel circuit included in the first sub-pixel SPXL1 through a first contact hole CH1. The third electrode EL3 of the second sub-emission unit may be connected to a driving transistor (hereinafter referred to as "second driving transistor") of a pixel circuit included in the second sub-pixel SPXL2 through a third contact hole CH3. The current flowing through each of the light-emitting elements LD in the first sub-emission unit may be controlled by the first driving transistor. The current flowing through each of the light-emitting elements LD in the second sub-emission unit may be controlled by the second driving transistor. Therefore, a uniform driving current may be provided to the light-emitting elements LD of the first sub-emission unit and the second sub-emission unit, respectively, such that the light-emitting elements LD may emit light substantially uniformly.

[0371] Next, refer to Figures 1a to 5 and Figure 19, a pixel PXL may include a first sub - pixel SPXL1 and a second sub - pixel SPXL2. The first sub - pixel SPXL1 may include a first sub - emission area SEMA1. The second sub - pixel SPXL2 may include a second sub - emission area SEMA2. A first electrode EL1, a second electrode EL2, and a third electrode EL3 may be disposed in each of the first sub - emission area SEMA1 and the second sub - emission area SEMA2. A contact electrode CNE may be disposed on the first electrode EL1, the second electrode EL2, and the third electrode EL3 respectively.

[0372] Each of the first electrode EL1, the second electrode EL2, and the third electrode EL3 may include two sub - electrodes disposed in the same column and spaced apart from each other in a second direction DR2. For example, the first electrode EL1 may include a 1 - 1 sub - electrode SEL1_1 and a 1 - 2 sub - electrode SEL1_2.

[0373] The second electrode EL2 may include a 2 - 1 sub - electrode SEL2_1 and a 2 - 2 sub - electrode SEL2_2.

[0374] The third electrode EL3 may include a 3 - 1 sub - electrode SEL3_1 and a 3 - 2 sub - electrode SEL3_2.

[0375] The contact electrode CNE may include a first contact electrode CNE1 disposed on the 1 - 1 sub - electrode SEL1_1, a second contact electrode CNE2 disposed on the 1 - 2 sub - electrode SEL1_2, a third contact electrode CNE3 disposed on the 2 - 1 sub - electrode SEL2_1, a fourth contact electrode CNE4 disposed on the 2 - 2 sub - electrode SEL2_2, a fifth contact electrode CNE5 disposed on the 3 - 1 sub - electrode SEL3_1, and a sixth contact electrode CNE6 disposed on the 3 - 2 sub - electrode SEL3_2.

[0376] Each of the first sub - emission area SEMA1 and the second sub - emission area SEMA2 may be divided into a first area A1 and a second area A2. In the first area A1, the 1 - 1 sub - electrode SEL1_1, the 2 - 1 sub - electrode SEL2_1, and the 3 - 1 sub - electrode SEL3_1 disposed in the same row are arranged. In the second area A2, the 1 - 2 sub - electrode SEL1_2, the 2 - 2 sub - electrode SEL2_2, and the 3 - 2 sub - electrode SEL3_2 disposed in the same row are arranged.

[0377] In a first region A1 of each of a first sub-emission region SEMA1 and a second sub-emission region SEMA2, a first series group may be formed by a 1-1 sub-electrode SEL1_1, a 2-1 sub-electrode SEL2_1, and a 3-1 sub-electrode SEL3_1 together with a first light-emitting element LD1 connected in parallel therebetween. Further, in a second region A2 of each of the first sub-emission region SEMA1 and the second sub-emission region SEMA2, a second series group may be formed by a 1-2 sub-electrode SEL1_2, a 2-2 sub-electrode SEL2_2, and a 3-2 sub-electrode SEL3_2 together with a second light-emitting element LD2 connected in parallel therebetween. The first series group and the second series group of the first sub-emission region SEMA1 may form a first sub-emission unit. The first series group and the second series group of the second sub-emission region SEMA2 may form a second sub-emission unit.

[0378] In an embodiment of the present disclosure, the first series group and the second series group of each of the first sub-emission unit and the second sub-emission unit may be electrically connected to each other through a first intermediate electrode CTE1. The first intermediate electrode CTE1 may be disposed in a boundary between the first region A1 and the second region A2 of each of the first sub-emission region SEMA1 and the second sub-emission region SEMA2, and includes a 1-1 intermediate electrode CTE1_1 and a 1-2 intermediate electrode CTE1_2. The 1-1 intermediate electrode CTE1_1 may electrically connect a second contact electrode CNE2 provided on the 2-1 sub-electrode SEL2_1 disposed in the first series group to a fourth contact electrode CNE4 provided on the 1-2 sub-electrode SEL1_2 disposed in the second series group. The 1-1 intermediate electrode CTE1_1, the second contact electrode CNE2, and the fourth contact electrode CNE4 may be integrally provided. The 1-2 intermediate electrode CTE1_2 may electrically connect the second contact electrode CNE2 provided on the 2-1 sub-electrode SEL2_1 disposed in the first series group to a sixth contact electrode CNE6 provided on the 3-2 sub-electrode SEL3_2 disposed in the second series group. The 1-2 intermediate electrode CTE1_2, the second contact electrode CNE2, and the sixth contact electrode CNE6 may be integrally provided.

[0379] According to the foregoing embodiment, a first sub-emission unit and a second sub-emission unit each having a series / parallel combination structure may be provided, so that a pixel PXL including a first sub-pixel SPXL1 and a second sub-pixel SPXL2 can be reliably driven. Further, the same or similar drive current may be respectively supplied to the light-emitting elements LD included in each of the first sub-emission unit and the second sub-emission unit, so that the light-emitting elements LD can generally emit light having a uniform intensity.

[0380] Next, referring to Figures 1a to 5 and Figure 20, the pixel PXL may include a first sub-pixel SPXL1 and a second sub-pixel SPXL2. The first sub-pixel SPXL1 may include a first sub-emission region SEMA1. The second sub-pixel SPXL2 may include a second sub-emission region SEMA2. The first electrode EL1, the second electrode EL2, and the third electrode EL3 may be disposed in each of the first sub-emission region SEMA1 and the second sub-emission region SEMA2. The contact electrode CNE may be respectively disposed on the first electrode EL1, the second electrode EL2, and the third electrode EL3.

[0381] Each of the first electrode EL1, the second electrode EL2, and the third electrode EL3 may include four sub-electrodes disposed in the same column and spaced apart from each other in the second direction DR2. For example, the first electrode EL1 may include a 1-1 sub-electrode SEL1_1, a 1-2 sub-electrode SEL1_2, a 1-3 sub-electrode SEL1_3, and a 1-4 sub-electrode SEL1_4. The second electrode EL2 may include a 2-1 sub-electrode SEL2_1, a 2-2 sub-electrode SEL2_2, a 2-3 sub-electrode SEL2_3, and a 2-4 sub-electrode SEL2_4. The third electrode EL3 may include a 3-1 sub-electrode SEL3_1, a 3-2 sub-electrode SEL3_2, a 3-3 sub-electrode SEL3_3, and a 3-4 sub-electrode SEL3_4.

[0382] The contact electrode CNE may include a first contact electrode CNE1 to a twelfth contact electrode CNE12. The first contact electrode CNE1 may be disposed on the 1-1 sub-electrode SEL1_1. The second contact electrode CNE2 may be disposed on the 2-1 sub-electrode SEL2_1. The third contact electrode CNE3 may be disposed on the 3-1 sub-electrode SEL3_1. The fourth contact electrode CNE4 may be disposed on the 1-2 sub-electrode SEL1_2. The fifth contact electrode CNE5 may be disposed on the 2-2 sub-electrode SEL2_2. The sixth contact electrode CNE6 may be disposed on the 3-2 sub-electrode SEL3_2. The seventh contact electrode CNE7 may be disposed on the 1-3 sub-electrode SEL1_3. The eighth contact electrode CNE8 may be disposed on the 2-3 sub-electrode SEL2_3. The ninth contact electrode CNE9 may be disposed on the 3-3 sub-electrode SEL3_3. The tenth contact electrode CNE10 may be disposed on the 1-4 sub-electrode SEL1_4. The eleventh contact electrode CNE11 may be disposed on the 2-4 sub-electrode SEL2_4. The twelfth contact electrode CNE12 may be disposed on the 3-4 sub-electrode SEL3_4.

[0383] Each of the first sub-emission region SEMA1 and the second sub-emission region SEMA2 can be divided into a first region A1, a second region A2, a third region A3, and a fourth region A4. In the first region A1, the 1-1 sub-electrode SEL1_1, the 2-1 sub-electrode SEL2_1, and the 3-1 sub-electrode SEL3_1 arranged in the same row are disposed. In the second region A2, the 1-2 sub-electrode SEL1_2, the 2-2 sub-electrode SEL2_2, and the 3-2 sub-electrode SEL3_2 arranged in the same row are disposed. In the third region A3, the 1-3 sub-electrode SEL1_3, the 2-3 sub-electrode SEL2_3, and the 3-3 sub-electrode SEL3_3 arranged in the same row are disposed. And in the fourth region A4, the 1-4 sub-electrode SEL1_4, the 2-4 sub-electrode SEL2_4, and the 3-4 sub-electrode SEL3_4 arranged in the same row are disposed.

[0384] In the first region A1 of each of the first sub-emission region SEMA1 and the second sub-emission region SEMA2, the 1-1 sub-electrode SEL1_1, the 2-1 sub-electrode SEL2_1, and the 3-1 sub-electrode SEL3_1, together with the first light-emitting element LD1 connected in parallel therebetween, can form a first series group. The first light-emitting element LD1 can include the 1-1 light-emitting element LD1_1 and the 1-2 light-emitting element LD1_2.

[0385] In the second region A2 of each of the first sub-emission region SEMA1 and the second sub-emission region SEMA2, the 1-2 sub-electrode SEL1_2, the 2-2 sub-electrode SEL2_2, and the 3-2 sub-electrode SEL3_2, together with the second light-emitting element LD2 connected in parallel therebetween, can form a second series group. The second light-emitting element LD2 can include the 2-1 light-emitting element LD2_1 and the 2-2 light-emitting element LD2_2.

[0386] In the third region A3 of each of the first sub-emission region SEMA1 and the second sub-emission region SEMA2, the 1-3 sub-electrode SEL1_3, the 2-3 sub-electrode SEL2_3, and the 3-3 sub-electrode SEL3_3, together with the third light-emitting element LD3 connected in parallel therebetween, can form a third series group. The third light-emitting element LD3 can include the 3-1 light-emitting element LD3_1 and the 3-2 light-emitting element LD3_2.

[0387] In a fourth region A4 of each of a first sub-emission region SEMA1 and a second sub-emission region SEMA2, a first-to-fourth sub-electrode SEL1_4, a second-to-fourth sub-electrode SEL2_4, and a third-to-fourth sub-electrode SEL3_4, together with a fourth light-emitting element LD4 connected in parallel therebetween, may form a fourth series group. The fourth light-emitting element LD4 may include at least one fourth-first light-emitting element LD4_1 and at least one fourth-second light-emitting element LD4_2, where the fourth-first light-emitting element LD4_1 is connected in the forward direction between the first-to-fourth sub-electrode SEL1_4 and the second-to-fourth sub-electrode SEL2_4, and the fourth-second light-emitting element LD4_2 is connected in the forward direction between the third-to-fourth sub-electrode SEL3_4 and the second-to-fourth sub-electrode SEL2_4.

[0388] The first to fourth series groups of the first sub-emission region SEMA1 may form a first sub-emission unit. The first to fourth series groups of the second sub-emission region SEMA2 may form a second sub-emission unit.

[0389] In an embodiment of the present disclosure, the first series group and the second series group of each of the first sub-emission unit and the second sub-emission unit may be electrically connected to each other through a first intermediate electrode CTE1. The second series group and the third series group of each of the first sub-emission unit and the second sub-emission unit may be electrically connected to each other through a second intermediate electrode CTE2.

[0390] The third series group and the fourth series group of each of the first sub-emission unit and the second sub-emission unit may be electrically connected to each other through a third intermediate electrode CTE3. The third intermediate electrode CTE3 may be disposed at a boundary between a third region A3 and a fourth region A4 of each of the first sub-emission region SEMA1 and the second sub-emission region SEMA2, and includes a third-first intermediate electrode CTE3_1 and a third-second intermediate electrode CTE3_2.

[0391] In an embodiment of the present disclosure, the third-first intermediate electrode CTE3_1 may electrically connect and / or physically connect an eighth contact electrode CNE8 on a second-to-third sub-electrode SEL2_3 of each of the first sub-emission region SEMA1 and the second sub-emission region SEMA2 to a tenth contact electrode CNE10 on a first-to-fourth sub-electrode SEL1_4 of each of the first sub-emission region SEMA1 and the second sub-emission region SEMA2. The third-second intermediate electrode CTE3_2 may electrically connect and / or physically connect an eighth contact electrode CNE8 on a second-to-third sub-electrode SEL2_3 of each of the first sub-emission region SEMA1 and the second sub-emission region SEMA2 to a twelfth contact electrode CNE12 on a third-to-fourth sub-electrode SEL3_4 of each of the first sub-emission region SEMA1 and the second sub-emission region SEMA2.

[0392] According to the foregoing embodiments, a first sub-emission unit and a second sub-emission unit each having a series / parallel combination structure may be provided such that a pixel PXL including a first sub-pixel SPXL1 and a second sub-pixel SPXL2 can be reliably driven. In addition, the same or similar drive current may be respectively provided to the light-emitting elements LD included in each of the first sub-emission unit and the second sub-emission unit, such that the light-emitting elements LD can generally emit light with uniform intensity.

[0393] Next, with reference to Figures 1a to 5 and Figure 21 , the pixel PXL may include a first sub-pixel SPXL1, a second sub-pixel SPXL2, and a third sub-pixel SPXL3. The first sub-pixel SPXL1 may include a first sub-emission region SEMA1. The second sub-pixel SPXL2 may include a second sub-emission region SEMA2. The third sub-pixel SPXL3 may include a third sub-emission region SEMA3. The first sub-emission region SEMA1, the second sub-emission region SEMA2, and the third sub-emission region SEMA3 may be combined to form an emission region EMA of the pixel PXL.

[0394] A first electrode EL1, a second electrode EL2, and a third electrode EL3 may be provided in each of the first sub-emission region SEMA1, the second sub-emission region SEMA2, and the third sub-emission region SEMA3. Contact electrodes CNE may be respectively provided on the first electrode EL1, the second electrode EL2, and the third electrode EL3.

[0395] Each of the first electrode EL1, the second electrode EL2, and the third electrode EL3 may include three sub-electrodes provided in the same column and spaced apart from each other in a second direction DR2. For example, the first electrode EL1 may include a 1-1 sub-electrode SEL1_1, a 1-2 sub-electrode SEL1_2, and a 1-3 sub-electrode SEL1_3. The second electrode EL2 may include a 2-1 sub-electrode SEL2_1, a 2-2 sub-electrode SEL2_2, and a 2-3 sub-electrode SEL2_3. The third electrode EL3 may include a 3-1 sub-electrode SEL3_1, a 3-2 sub-electrode SEL3_2, and a 3-3 sub-electrode SEL3_3.

[0396] The contact electrodes CNE may include a first contact electrode CNE1 to a ninth contact electrode CNE9. The first contact electrode CNE1 may be disposed on the 1-1 sub-electrode SEL1_1. The second contact electrode CNE2 may be disposed on the 2-1 sub-electrode SEL2_1. The third contact electrode CNE3 may be disposed on the 3-1 sub-electrode SEL3_1. The fourth contact electrode CNE4 may be disposed on the 1-2 sub-electrode SEL1_2. The fifth contact electrode CNE5 may be disposed on the 2-2 sub-electrode SEL2_2. The sixth contact electrode CNE6 may be disposed on the 3-2 sub-electrode SEL3_2. The seventh contact electrode CNE7 may be disposed on the 1-3 sub-electrode SEL1_3. The eighth contact electrode CNE8 may be disposed on the 2-3 sub-electrode SEL2_3. The ninth contact electrode CNE9 may be disposed on the 3-3 sub-electrode SEL3_3.

[0397] Each of the first sub-emission region SEMA1, the second sub-emission region SEMA2, and the third sub-emission region SEMA3 may be divided into a first region A1, a second region A2, and a third region A3, wherein in the first region A1, the 1-1 sub-electrode SEL1_1, the 2-1 sub-electrode SEL2_1, and the 3-1 sub-electrode SEL3_1 arranged in the same row are disposed, in the second region A2, the 1-2 sub-electrode SEL1_2, the 2-2 sub-electrode SEL2_2, and the 3-2 sub-electrode SEL3_2 arranged in the same row are disposed, and in the third region A3, the 1-3 sub-electrode SEL1_3, the 2-3 sub-electrode SEL2_3, and the 3-3 sub-electrode SEL3_3 arranged in the same row are disposed.

[0398] In a first region A1 of each of a first sub-emission region SEMA1, a second sub-emission region SEMA2, and a third sub-emission region SEMA3, a first sub-electrode SEL1_1, a second sub-electrode SEL2_1, and a third sub-electrode SEL3_1 together with a first light-emitting element LD1 connected in parallel therebetween may form a first series group. Further, in a second region A2 of each of the first sub-emission region SEMA1, the second sub-emission region SEMA2, and the third sub-emission region SEMA3, a first sub-electrode SEL1_2, a second sub-electrode SEL2_2, and a third sub-electrode SEL3_2 together with a second light-emitting element LD2 connected in parallel therebetween may form a second series group. Further, in a third region A3 of each of the first sub-emission region SEMA1, the second sub-emission region SEMA2, and the third sub-emission region SEMA3, a first sub-electrode SEL1_3, a second sub-electrode SEL2_3, and a third sub-electrode SEL3_3 together with a third light-emitting element LD3 connected in parallel therebetween may form a third series group. The first series group to the third series group of the first sub-emission region SEMA1 may form a first sub-emission unit. The first series group to the third series group of the second sub-emission region SEMA2 may form a second sub-emission unit. The first series group to the third series group of the third sub-emission region SEMA3 may form a third sub-emission unit.

[0399] In an embodiment of the present disclosure, the first series group and the second series group of each of the first sub-emission unit to the third sub-emission unit may be electrically connected to each other through a first intermediate electrode CTE1. The second series group and the third series group of each of the first sub-emission unit to the third sub-emission unit may be electrically connected to each other through a second intermediate electrode CTE2. The first intermediate electrode CTE1 may be disposed at a boundary between the first region A1 and the second region A2 of each of the first sub-emission region SEMA1, the second sub-emission region SEMA2, and the third sub-emission region SEMA3. The second intermediate electrode CTE2 may be disposed at a boundary between the second region A2 and the third region A3 of each of the first sub-emission region SEMA1, the second sub-emission region SEMA2, and the third sub-emission region SEMA3.

[0400] The 1-1 sub-electrode SEL1_1 and the 3-1 sub-electrode SEL3_1 of the first sub-emission unit may be integrally formed with the first connection line CNL1 and are connected to a driving transistor (hereinafter referred to as "the first driving transistor") of a pixel circuit connected to the first sub-emission unit through the first contact hole CH1. The 1-1 sub-electrode SEL1_1 and the 3-1 sub-electrode SEL3_1 of the second sub-emission unit may be integrally formed with the third connection line CNL3 and are connected to a driving transistor (hereinafter referred to as "the second driving transistor") of a pixel circuit connected to the second sub-emission unit through the third contact hole CH3. The 1-1 sub-electrode SEL1_1 and the 3-1 sub-electrode SEL3_1 of the third sub-emission unit may be integrally formed with the fourth connection line CNL4 and are connected to a driving transistor (hereinafter referred to as "the third driving transistor") of a pixel circuit connected to the third sub-emission unit through the fourth contact hole CH4. Here, the pixel circuit connected to the first sub-emission unit, the pixel circuit connected to the second sub-emission unit, and the pixel circuit connected to the third sub-emission unit may be independent pixel circuits and have the same circuit structure.

[0401] The current flowing through each of the light-emitting elements LD in the first sub-emission unit may be controlled by the first driving transistor. The current flowing through each of the light-emitting elements LD in the second sub-emission unit may be controlled by the second driving transistor. The current flowing through each of the light-emitting elements LD in the third sub-emission unit may be controlled by the third driving transistor. Accordingly, uniform driving currents may be respectively provided to the light-emitting elements LD of the first to third sub-emission units, such that the light-emitting elements LD may emit light substantially uniformly.

[0402] In addition, the first to third sub-emission units each having a series / parallel combination structure may be provided, such that a pixel PXL including a first sub-pixel SPXL1, a second sub-pixel SPXL2, and a third sub-pixel SPXL3 may be reliably driven.

[0403] Although examples in which the pixel PXL may include two sub-pixels SPXL1 and SPXL2 or three sub-pixels SPXL1, SPXL2, and SPXL3 and each sub-pixel may include two series groups, three series groups, or four series groups have been described in the foregoing embodiments, the present disclosure is not limited thereto. In an embodiment, the pixel PXL may include n sub-pixels (n is a natural number of 2 or greater), and each sub-pixel may include two or more series groups.

[0404] Although various embodiments have been described above, those skilled in the art will understand that various modifications, additions, and substitutions are possible without departing from the scope of the present disclosure.

[0405] Accordingly, the embodiments disclosed in this specification are for illustrative purposes only and are not intended to limit the technical scope of the present disclosure. The scope of the present disclosure may be defined by the appended claims.

Claims

1. A pixel, comprising: A first sub-pixel region and a second sub-pixel region, which are arranged adjacent to each other in a first direction; A first electrode and a second electrode, which are arranged in each of the first sub-pixel region and the second sub-pixel region and are spaced apart from each other; A plurality of light-emitting elements, which are arranged between the first electrode and the second electrode in each of the first sub-pixel region and the second sub-pixel region; A first driving transistor, which is arranged in the first sub-pixel region and is electrically connected to the first electrode of the first sub-pixel region; And A second driving transistor, which is arranged in the second sub-pixel region and is electrically connected to the first electrode of the second sub-pixel region, Wherein, the first electrode of the first sub-pixel region and the first electrode of the second sub-pixel region are electrically disconnected from each other, and the second electrode of the first sub-pixel region and the second electrode of the second sub-pixel region are electrically connected to each other. Each of the first sub-pixel region and the second sub-pixel region includes a first sub-region and a second sub-region, which are spaced apart from each other in a second direction intersecting the first direction. The first electrode arranged in each of the first sub-pixel region and the second sub-pixel region includes a 1-1 sub-electrode arranged in the first sub-region and a 1-2 sub-electrode arranged in the second sub-region. The second electrode arranged in each of the first sub-pixel region and the second sub-pixel region includes a 2-1 sub-electrode arranged in the first sub-region and a 2-2 sub-electrode arranged in the second sub-region. The plurality of light-emitting elements in each of the first sub-pixel region and the second sub-pixel region include: a first light-emitting element, which is arranged between the 1-1 sub-electrode and the 2-1 sub-electrode; and a second light-emitting element, which is arranged between the 1-2 sub-electrode and the 2-2 sub-electrode. The 1-1 sub-electrode and the 2-1 sub-electrode in each of the first sub-pixel region and the second sub-pixel region, together with the first light-emitting element electrically connected in parallel therebetween, form a first group, and the 1-2 sub-electrode and the 2-2 sub-electrode in each of the first sub-pixel region and the second sub-pixel region, together with the second light-emitting element electrically connected in parallel therebetween, form a second group, and The first group and the second group are electrically connected in series with each other.

2. The pixel according to claim 1, further comprising a first contact electrode, which is arranged in each of the first sub-pixel region and the second sub-pixel region and is arranged on each of the 1-1 sub-electrode, the 1-2 sub-electrode, the 2-1 sub-electrode, and the 2-2 sub-electrode.

3. The pixel according to claim 2, further comprising a first intermediate electrode, which is arranged in the region between the first sub-region and the second sub-region in each of the first sub-pixel region and the second sub-pixel region.

4. The pixel according to claim 3, wherein, The first intermediate electrode and the first contact electrode are integrally formed with each other on the 2-1st sub-electrode in the first sub-region provided in each of the first sub-pixel region and the second sub-pixel region.

5. The pixel according to claim 4, wherein The first group and the second group in each of the first sub-pixel region and the second sub-pixel region are electrically connected to each other through the first intermediate electrode.

6. The pixel according to claim 5, wherein, The first intermediate electrode electrically connects the first contact electrode on the 2-1st sub-electrode of the first group to the first contact electrode on the 1-2nd sub-electrode of the second group in each of the first sub-pixel region and the second sub-pixel region.

7. The pixel according to claim 6, further comprising a third electrode, the third electrode being provided in each of the first sub-pixel region and the second sub-pixel region and spaced apart from the first electrode and the second electrode, The third electrode includes a 3-1st sub-electrode provided in the first sub-region and a 3-2nd sub-electrode provided in the second sub-region, and The 1-1st sub-electrode and the 3-1st sub-electrode are electrically connected to each other through a connection line in each of the first sub-pixel region and the second sub-pixel region.

8. The pixel according to claim 7, wherein, Each of the first sub-pixel region and the second sub-pixel region further includes a third sub-region provided below the second sub-region in the second direction, The first electrode in each of the first sub-pixel region and the second sub-pixel region further includes a 1-3rd sub-electrode provided in the third sub-region, The second electrode in each of the first sub-pixel region and the second sub-pixel region further includes a 2-3rd sub-electrode provided in the third sub-region, and The plurality of light-emitting elements in each of the first sub-pixel region and the second sub-pixel region further includes a third light-emitting element provided between the 1-3rd sub-electrode and the 2-3rd sub-electrode.

9. The pixel according to claim 8, wherein The 1-3rd sub-electrode and the 2-3rd sub-electrode together with the third light-emitting element electrically connected in parallel therebetween form a third group in each of the first sub-pixel region and the second sub-pixel region.

10. The pixel according to claim 9, further comprising: A second contact electrode provided on each of the 1-3rd sub-electrode and the 2-3rd sub-electrode in each of the first sub-pixel region and the second sub-pixel region, and the second contact electrode and the first contact electrode are provided on the same layer; And A second intermediate electrode provided in the region between the second sub-region and the third sub-region in each of the first sub-pixel region and the second sub-pixel region, and the second intermediate electrode and the first contact electrode are integrally formed with each other on the 2-2nd sub-electrode. Among them, in each of the first sub-pixel region and the second sub-pixel region, the second intermediate electrode electrically connects the first contact electrode on the 2-2nd sub-electrode of the second group to the second contact electrode on the 1-3rd sub-electrode of the third group.

11. The pixel according to claim 10, wherein each of the first sub-pixel region and the second sub-pixel region further includes a fourth sub-region disposed below the third sub-region in the second direction, the first electrode of each of the first sub-pixel region and the second sub-pixel region further includes a 1-4th sub-electrode disposed in the fourth sub-region, the second electrode of each of the first sub-pixel region and the second sub-pixel region further includes a 2-4th sub-electrode disposed in the fourth sub-region, and the plurality of light-emitting elements of each of the first sub-pixel region and the second sub-pixel region further includes a fourth light-emitting element disposed between the 1-4th sub-electrode and the 2-4th sub-electrode.

12. The pixel according to claim 11, wherein, The 1-4th sub-electrode, the 2-4th sub-electrode, and the fourth light-emitting element electrically connected in parallel therebetween form a fourth group in each of the first sub-pixel region and the second sub-pixel region.

13. The pixel according to claim 12, further comprising: a third contact electrode disposed on each of the 1-4th sub-electrode and the 2-4th sub-electrode in each of the first sub-pixel region and the second sub-pixel region, and the third contact electrode and the second contact electrode are disposed on the same layer; and a third intermediate electrode disposed in the region between the third sub-region and the fourth sub-region in each of the first sub-pixel region and the second sub-pixel region, and the third intermediate electrode and the second contact electrode are integrated with each other on the 2-3rd sub-electrode, wherein, in each of the first sub-pixel region and the second sub-pixel region, the third intermediate electrode electrically connects the second contact electrode on the 2-3rd sub-electrode of the third group to the third contact electrode on the 1-4th sub-electrode of the fourth group.

14. The pixel according to claim 8, further comprising a third sub-pixel region, the third sub-pixel region is disposed adjacent to the second sub-pixel region in the first direction and includes a first sub-region, a second sub-region, and a third sub-region spaced apart from each other in the second direction, Among them, the third sub-pixel region includes: a first electrode including a 1-1st sub-electrode disposed in the first sub-region, a 1-2nd sub-electrode disposed in the second sub-region and spaced apart from the 1-1st sub-electrode, and a 1-3rd sub-electrode disposed in the third sub-region and spaced apart from the 1-2nd sub-electrode; The second electrode includes a 2-1 sub-electrode disposed in the first sub-region, a 2-2 sub-electrode disposed in the second sub-region and spaced apart from the 2-1 sub-electrode, and a 2-3 sub-electrode disposed in the third sub-region and spaced apart from the 2-2 sub-electrode; The light-emitting element is disposed between the first electrode and the second electrode in the third sub-pixel region; The third driving transistor is electrically connected to the 1-1 sub-electrode in the third sub-pixel region; The contact electrode is disposed on each of the 1-1 sub-electrode and the 1-2 sub-electrode in the third sub-pixel region and the 2-1 sub-electrode and the 2-2 sub-electrode in the third sub-pixel region, and the contact electrode is disposed on the same layer as the first contact electrode; and The intermediate electrode is disposed in each of the region between the first sub-region and the second sub-region in the third sub-pixel region and the region between the second sub-region and the third sub-region in the third sub-pixel region.

15. The pixel according to claim 14, wherein The intermediate electrode includes a first sub-intermediate electrode integrated with the contact electrode on the 2-1 sub-electrode in the third sub-pixel region, and a second sub-intermediate electrode integrated with the contact electrode on the 2-2 sub-electrode in the third sub-pixel region, The first sub-intermediate electrode electrically connects the 2-1 sub-electrode in the third sub-pixel region to the 1-2 sub-electrode in the third sub-pixel region, and The second sub-intermediate electrode electrically connects the 2-2 sub-electrode in the third sub-pixel region to the 1-3 sub-electrode in the third sub-pixel region.

16. A display device, comprising: A substrate including a display region and a non-display region, the display region including a plurality of pixel regions; And Pixels disposed in each of the plurality of pixel regions, wherein The pixel includes: A first sub-pixel region and a second sub-pixel region, which are adjacent to each other in a first direction and each include a first sub-region, a second sub-region, and a third sub-region spaced apart from each other in a second direction intersecting the first direction; A first electrode disposed in each of the first sub-pixel region and the second sub-pixel region, and including a 1-1 sub-electrode disposed in the first sub-region, a 1-2 sub-electrode disposed in the second sub-region, and a 1-3 sub-electrode disposed in the third sub-region; A second electrode is disposed in each of the first sub-pixel region and the second sub-pixel region, and includes a 2-1 sub-electrode disposed in the first sub-region and spaced apart from the 1-1 sub-electrode, a 2-2 sub-electrode disposed in the second sub-region and spaced apart from the 1-2 sub-electrode, and a 2-3 sub-electrode disposed in the third sub-region and spaced apart from the 1-3 sub-electrode; A plurality of light-emitting elements are disposed between the first electrode and the second electrode in each of the first sub-pixel region and the second sub-pixel region; A first driving transistor and a second driving transistor, the first driving transistor being electrically connected to the 1-1 sub-electrode of the first sub-pixel region, and the second driving transistor being electrically connected to the 1-1 sub-electrode of the second sub-pixel region; Contact electrodes are disposed on each of the 1-1 sub-electrode to the 1-3 sub-electrode and the 2-1 sub-electrode to the 2-3 sub-electrode; and A first intermediate electrode and a second intermediate electrode are disposed in each of the first sub-pixel region and the second sub-pixel region, the first intermediate electrode being disposed in a region between the first sub-region and the second sub-region, and the second intermediate electrode being disposed in a region between the second sub-region and the third sub-region, The first intermediate electrode and the contact electrode are integrally formed with each other on the 2-1 sub-electrode and electrically connect the 2-1 sub-electrode to the 1-2 sub-electrode, and The second intermediate electrode and the contact electrode are integrally formed with each other on the 2-2 sub-electrode and electrically connect the 2-2 sub-electrode to the 1-3 sub-electrode.

17. A method of manufacturing a display device, comprising Disposing pixels in a pixel region, the pixel region including a first sub-pixel region and a second sub-pixel region, the first sub-pixel region and the second sub-pixel region being adjacent to each other in a first direction and each including a first sub-region, a second sub-region, and a third sub-region spaced apart from each other in a second direction intersecting the first direction, wherein Disposing the pixels includes: forming a first driving transistor and a second driving transistor, and forming a display element layer on the first driving transistor and the second driving transistor, Forming the display element layer includes: Forming a first wire and a second wire spaced apart from each other in each of the first sub-pixel region and the second sub-pixel region; Supplying a plurality of light-emitting elements to each of the first sub-pixel region and the second sub-pixel region, and aligning the plurality of light-emitting elements by supplying corresponding alignment voltages to the first wire and the second wire; Forming contact electrodes on each of the first wire and the second wire, and forming intermediate electrodes integrally formed with the contact electrodes in each of a region between the first sub-region and the second sub-region and a region between the second sub-region and the third sub-region; and By removing a portion of the first wire, a 1-1 sub-electrode, a 1-2 sub-electrode, and a 1-3 sub-electrode are formed in each of the first sub-pixel region and the second sub-pixel region and arranged in sequence in the second direction. And by removing a portion of the second wire, a 2-1 sub-electrode, a 2-2 sub-electrode, and a 2-3 sub-electrode are formed in each of the first sub-pixel region and the second sub-pixel region and arranged in sequence in the second direction. The intermediate electrode disposed in the region between the first sub-region and the second sub-region extends from the contact electrode on the 2-1 sub-electrode to the contact electrode on the 1-2 sub-electrode in a row disposed after the 2-1 sub-electrode in a plan view, and electrically connects the 2-1 sub-electrode to the 1-2 sub-electrode. The intermediate electrode disposed in the region between the second sub-region and the third sub-region extends from the contact electrode on the 2-2 sub-electrode to the contact electrode on the 1-3 sub-electrode in a row disposed after the 2-2 sub-electrode in a plan view, and electrically connects the 2-2 sub-electrode to the 1-3 sub-electrode.

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