Silicon carbide semiconductor device and manufacturing method thereof

Abstract

The electric field relaxation layer (3) includes a first region (3a) of the second conductivity type and a second region (3b) of the second conductivity type, wherein the first region (3a) is formed at a position deeper than the trench (7), and the second region (3b) is arranged with the same longitudinal direction as the longitudinal direction of the trench and is separated from the side surfaces of the trench between the plurality of trenches, and connects the first region and the base region. In addition, the structure is as follows: the first region and the second region are formed by ion implantation, and a double implantation region (3c) is formed by overlapping the first region and the second region, and the double implantation region has a peak of the second impurity concentration.

Description

[0001] Cross-references between related applications

[0002] This application is based on Japanese Patent Application No. 2019-197841 filed on October 30, 2019, the contents of which are incorporated herein by reference. Technical Field

[0003] The present invention relates to a silicon carbide (SiC) semiconductor device having a trench gate structure and comprising SiC, and a method for manufacturing the same. Background Art

[0004] In the past, SiC semiconductor devices with trench gate structures were used as a structure that increased the channel density to allow high current to flow. In such trench gate SiC semiconductor devices, the breakdown electric field strength of SiC is high, and there is a possibility that electric field stress acts on the bottom of the trench and causes insulation breakdown. Therefore, as shown in Patent Document 1, the following treatment is performed: a p-type electric field relaxation layer is formed on both sides of the trench gate to suppress the high electric field from acting on the bottom of the trench and prevent insulation breakdown. The electric field relaxation layer is set as a two-layer structure with a high-concentration region located below and a low-concentration region located above, and these are formed by ion implantation or the like.

[0005] Prior art literature

[0006] Patent Literature

[0007] Patent Document 1: Japanese Patent No. 6428489 Summary of the Invention

[0008] The inventors investigated forming each layer of a two-layer p-type electric field relaxation layer using ion implantation, as described in Patent Document 1. Specifically, ion implantation was performed after forming a portion of the drift layer to form the first region located at the bottom of the electric field relaxation layer. Subsequently, ion implantation was performed again after forming the remaining portion of the drift layer to form the second region located at the top of the electric field relaxation layer. This enabled the electric field relaxation layer to be formed using a two-step ion implantation process. The term "ion implantation" refers to a process combining multiple implantation conditions with varying acceleration energies and implantation doses, not just ion implantation under a single condition.

[0009] However, the inventors discovered that adopting such a process can lead to the following technical issues. Specifically, when forming the remaining portion of the drift layer, film thickness deviations may occur during epitaxial growth. Furthermore, to ensure optimal epitaxial growth in SiC, an off-substrate is used as the semiconductor substrate, so the drift layer formed thereon also has an off angle. Furthermore, when ion implantation is performed on the drift layer with an off angle to form the second region, channeling occurs due to injection swing, causing variations in the implantation depth. If film thickness deviations in the remaining portion of the drift layer and implantation depth deviations due to channeling occur in this manner, the second region may not reach the first region, and the first and second regions may be electrically disconnected. In this case, the first region becomes floating and is no longer fixed to the source potential, so the electric field relaxation effect of the electric field relaxation layer cannot be fully achieved. Furthermore, the increased resistance within the p-layer may lead to a decrease in tolerance.

[0010] The object of the present invention is to provide a SiC semiconductor device and a method for manufacturing the same, wherein a first region and a second region constituting an electric field relaxation layer are reliably connected in potential, thereby ensuring tolerance while utilizing the electric field relaxation layer to relax the electric field stress toward the bottom of the trench.

[0011] In a first aspect of the present invention, a SiC semiconductor device comprises: a substrate of a first conductivity type or a second conductivity type composed of SiC; a drift layer formed on the substrate and composed of SiC of the first conductivity type having a lower impurity concentration than that of the substrate; a base region formed on the drift layer and composed of SiC of the second conductivity type; a source region formed in an upper portion of the base region and composed of SiC of the first conductivity type having a higher concentration than that of the drift layer; a contact region formed in an upper portion of the base region at a position different from that of the source region and composed of SiC of the second conductivity type having a higher concentration than that of the base region; a trench gate structure formed by extending a portion of the substrate from the surface of the source region to the substrate; The trench gate structure comprises a gate electrode formed through a gate insulating film within a plurality of trenches arranged along a longitudinal direction extending deeper than the base region. A source electrode is electrically connected to the source region and the contact region. A drain electrode is formed on the back side of the substrate. Furthermore, an electric field relaxation layer is disposed within the drift layer and includes a first region of the second conductivity type and a second region of the second conductivity type. The first region is formed deeper than the trench. The second region is disposed between the plurality of trenches, separated from the side surfaces of the trenches, and connected to the base region. In this structure, both the first and second regions are formed of ion-implanted layers. The first and second regions overlap to form a double-implanted region, and the peak second impurity concentration is present in the double-implanted region.

[0012] This structure creates an electric field relaxation layer deeper than the trench, with the electric field relaxation layer formed by the first and second regions, each composed of an ion-implanted layer. Furthermore, a double-implanted region is formed, where the first and second regions overlap, and the second impurity concentration peaks in the double-implanted region. This connects the first and second regions and fixes them to the source potential, preventing the first region from floating. Consequently, the electric field relaxation effect and tolerance of the electric field relaxation layer can be fully achieved.

[0013] In the SiC semiconductor device according to the second aspect of the present invention, the second conductivity type impurity concentration is higher in at least the portion of the second region located below the first region than in the first region.

[0014] Thus, at least the portion of the second region below the first region has a higher second conductivity type impurity concentration than the first region. This prevents the depletion layer from contacting the doubly injected region, thereby suppressing leakage.

[0015] In the SiC semiconductor device according to the third aspect of the present invention, the upper portion of the first region on the second region side has a higher second conductivity type impurity concentration than the lower portion below the upper portion.

[0016] By increasing the second conductivity-type impurity concentration in the upper portion of the first region, it is possible to suppress contact between the depletion layer and the doubly implanted region when a high voltage is applied as the drain voltage. This achieves the same effects as those of the SiC semiconductor device according to another aspect of the present invention described above.

[0017] In the fourth aspect of the present invention, the manufacturing method of the SiC semiconductor device includes the following step of forming the second region: after forming the first region, forming the remaining portion of the drift layer, and then ion-implanting the second conductive type impurity into the remaining portion of the drift layer to form the remaining electric field relaxation layer, thereby forming a second region having a length direction that is the same as the length direction of the trench and connected to the first region. In the step of forming the second region, the second conductive type impurity ions are implanted to a position deeper than the above-mentioned remaining portion of the drift layer, thereby forming a double implantation region consisting of the second region and the first region overlapping.

[0018] In this way, an electric field relaxation layer is formed that is deeper than the trench, and the electric field relaxation layer is composed of the first region and the second region. Furthermore, the ion implantation depth is adjusted to form a double implantation region where the first and second regions overlap. This ensures that the first and second regions are reliably connected and fixed to the source potential, preventing the first region from floating. Consequently, the electric field relaxation effect and tolerance of the electric field relaxation layer can be fully achieved.

[0019] In the method for manufacturing a SiC semiconductor device according to a fifth aspect of the present invention, in the step of forming the second region, the second conductivity type impurity concentration in at least a portion of the second region on the first region side is made higher than that in the first region.

[0020] Thus, at least the portion of the second region below the first region has a higher second conductivity type impurity concentration than the first region. This prevents the depletion layer from contacting the doubly injected region, thus suppressing leakage.

[0021] In the method for manufacturing a SiC semiconductor device according to a sixth aspect of the present invention, in the step of forming the first region, the second conductivity type impurity concentration in the upper portion of the first region is made higher than that in the lower portion.

[0022] Thus, the upper portion of the first region, which is on the second region side, has a higher second conductivity type impurity concentration than the lower portion. This prevents the depletion layer from contacting the double-implanted region, thus suppressing leakage.

[0023] In addition, the parenthesized reference numerals assigned to each component etc. show an example of the correspondence relationship between the component etc. and the specific component etc. described in the embodiment to be described later. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is a diagram showing the cross-sectional structure of the SiC semiconductor device according to the first embodiment.

[0025] Figure 2 It is a diagram schematically showing the relationship between the position of each portion of the electric field relaxation layer 3 and the implantation distribution of the p-type impurity.

[0026] Figure 3A It shows Figure 1 A cross-sectional view showing a manufacturing process of a SiC semiconductor device is shown.

[0027] Figure 3B It shows the next Figure 3A Cross-sectional view of the manufacturing process of the SiC semiconductor device.

[0028] Figure 3C It shows the next Figure 3B Cross-sectional view of the manufacturing process of the SiC semiconductor device.

[0029] Figure 3D It shows the next Figure 3C Cross-sectional view of the manufacturing process of the SiC semiconductor device.

[0030] Figure 3E It shows the next Figure 3D Cross-sectional view of the manufacturing process of the SiC semiconductor device.

[0031] Figure 3F It shows the next Figure 3E Cross-sectional view of the manufacturing process of the SiC semiconductor device.

[0032] Figure 3G It shows the next Figure 3F Cross-sectional view of the manufacturing process of the SiC semiconductor device.

[0033] Figure 4 This is a diagram showing the results of measuring the p-type impurity concentration of the electric field relaxation layer when the film thickness of the remaining portion of the n-type drift layer deviates from a target value.

[0034] Figure 5A This is a cross-sectional view showing the equipotential distribution and the state of the depletion layer in a comparative example.

[0035] Figure 5B This is a cross-sectional view showing the equipotential distribution and the depletion layer state of the SiC semiconductor device according to the second embodiment.

[0036] Figure 6 It is a diagram showing the cross-sectional structure of a SiC semiconductor device according to a third embodiment.

[0037] Figure 7 This is a cross-sectional view showing the equipotential distribution and the state of the depletion layer in the SiC semiconductor device according to the third embodiment.

[0038] Figure 8 This is a cross-sectional view showing the equipotential distribution and the state of the depletion layer in the SiC semiconductor device according to the fourth embodiment.

[0039] Figure 9 It is a perspective cross-sectional view of a SiC semiconductor device according to a fifth embodiment.

[0040] Figure 10 yes Figure 9 A top-down layout diagram of a SiC semiconductor device is shown. Summary of the Invention

[0042] Hereinafter, embodiments of the present invention will be described based on the drawings. In the following embodiments, identical or equivalent parts will be denoted by the same reference numerals.

[0043] (First embodiment)

[0044] The first embodiment of the present invention will be described. First, regarding the SiC semiconductor device of the present embodiment having a vertical MOSFET with an inversion-type trench gate structure, refer to Figure 1 In addition, Figure 1 In the paper, only one unit of vertical MOSFET is described, but Figure 1 The vertical MOSFET shown has the same structure as that shown in FIG. 1 , and a plurality of cells are arranged adjacent to each other.

[0045] like Figure 1 As shown, use n + The vertical MOSFET is formed on the semiconductor substrate 1. + The semiconductor substrate 1 is made of a high concentration of, for example, 1×10 19 ~1×10 20 cm －3 The impurity concentration of n-type impurities such as phosphorus or nitrogen is doped with a SiC single crystal with a thickness of about 300μm. + On the semiconductor substrate 1, n-type impurities are formed, for example, 1×10 15 ~5×10 16 cm －3 Such a ratio + The n-type semiconductor substrate 1 has an n-type drift layer 2 made of SiC doped with a low impurity concentration and having a thickness of about 5 to 15 μm.

[0046] An electric field relaxation layer 3 doped with p-type impurities such as boron or aluminum is formed within the n-type drift layer 2. In this embodiment, the electric field relaxation layer 3 is arranged in a strip-like structure, extending in one direction. The electric field relaxation layer 3 is positioned on both sides of the trench gate structure (described later), with its bottom extending deeper than the bottom of the trench gate structure.

[0047] More specifically, the electric field relaxation layer 3 is formed from the n + The electric field relaxation layer 3 is formed from a position at a predetermined distance from the n-type semiconductor substrate 1 to the surface of the n-type drift layer 2. + The semiconductor substrate 1 includes a first region 3a and a second region 3b located above the first region 3a.

[0048] The widths of the first region 3a and the second region 3b, i.e., the dimensions in the direction perpendicular to the length of the trench gate structure in a plane direction parallel to the substrate plane, can be the same, or one can be wider than the other. In this embodiment, the first region 3a is wider than the second region 3b, and the first region 3a extends from both sides of the second region 3b. For example, the width of the first region 3a is set to 1.3 μm, the width of the second region 3b is set to 0.7 μm, and the amount of extension of the first region 3a from one side of the second region 3b is set to 0.3 μm. By setting such a structure, the expansion of the JFET region can be prevented between adjacent electric field relaxation layers 3, and the shortest current path can be ensured between the trench gate structure and the drain electrode 12 described later, thereby suppressing the increase in on-resistance.

[0049] The first region 3a is formed at a position about 0.5 to 2.0 μm away from the surface of the n-type drift layer 2, and the p-type impurity concentration is, for example, 1×10 16 ~1×10 19 cm －3 On the other hand, the second region 3b is formed to a depth of about 0.5 to 2.0 μm relative to the surface of the n-type drift layer 2, and the p-type impurity concentration is set higher than that of the first region 3a. For example, the p-type impurity concentration of the second region 3b is 1×10 17 ~1×10 20 cm －3 The depth is about 1.0 to 2.0 μm.

[0050] Furthermore, as described later, both the first region 3a and the second region 3b are composed of ion-implanted layers formed by implanting p-type impurity ions. The first region 3a and the second region 3b partially overlap, forming a double-implanted region 3c. The presence of this double-implanted region 3c ensures a secure connection between the first region 3a and the second region 3b. While electrical connection between the first region 3a and the second region 3b requires contact, variations in the thickness of the n-type drift layer 2 may cause the first region 3a and the second region 3b to separate. Therefore, the double-implanted region 3c is formed to a certain thickness even if variations in the thickness of the n-type drift layer 2 exist.

[0051] Figure 2 The relationship between the position of each part of the electric field relaxation layer 3 and the injection distribution of the p-type impurity is schematically shown. As shown in the figure, the p-type impurity concentration in the double injection region 3c is higher than that in the first region 3a and the second region 3b. In addition, the double injection region 3c is formed so as to have a peak of the p-type impurity in the depth direction. Here, the double injection region 3c has a thickness of more than 0.1μm. In addition, as a concentration distribution of the p-type impurity, there is a peak of the p-type impurity in the depth direction at about 0.05 to 0.2μm, and the p-type impurity concentration at this peak is 1×10 17 ~1×10 20 cm －3 about.

[0052] In addition, the first region 3 a and the second region 3 b are each formed uniformly throughout the entire region at the above-mentioned impurity concentration in portions other than the double-implanted region 3 c .

[0053] And, as Figure 1 As shown, a p-type base region 4 is formed on the surface of the n-type drift layer 2 and the electric field relaxation layer 3. The p-type base region 4 is a layer constituting the channel of the vertical MOSFET and is formed on both sides of a trench 7 constituting a trench gate structure described later so as to be in contact with the side surfaces of the trench 7.

[0054] In the surface layer portion of the p-type base region 4, an n-type layer doped with n-type impurities at a high concentration is formed on the trench gate structure side relative to the position corresponding to the electric field relaxation layer 3 so as to be in contact with the trench gate structure. + Type source region 5. In the case of this embodiment, for example, n + The type source region 5 is formed to have an impurity concentration of 1×10 20 cm －3 The thickness is about 0.3 μm. + A p-type source region 5 is formed at a position different from the electric field relaxation layer 3, specifically, at a position corresponding to the electric field relaxation layer 3.+ Type contact region 6. In the case of this embodiment, for example, p + The type contact region 6 is formed to have an impurity concentration of 1×10 20 cm －3 The thickness is about 0.3 μm.

[0055] Furthermore, in Figure 1 In the cross section, a p-type base region 4 and an n-type base region 5 are formed at the center of the adjacent electric field relaxation layer 3. + A trench 7 is formed in the n-type source region 5, extending through the n-type drift layer 2 and shallower than the bottom of the electric field relaxation layer 3. The trench 7 can be formed to any depth as long as it is deeper than the bottom of the p-type base region 4 and shallower than the electric field relaxation layer 3. For example, the trench 7 is set to a depth that protrudes from the bottom of the p-type base region 4 by about 0.3 μm and is shallower than the double-implantation region 3 c.

[0056] The p-type base region 4 and the n-type base region 5 are arranged in contact with the side surface of the trench 7. + The inner wall surface of the trench 7 is covered with a gate insulating film 8 composed of an oxide film or the like, and a gate electrode 9 composed of doped polysilicon formed on the surface of the gate insulating film 8 fills the trench 7. In this way, the structure with the gate insulating film 8 and the gate electrode 9 in the trench 7 forms a trench gate structure.

[0057] In addition, although Figure 1 Although not shown, the trench gate structure is formed into, for example, a rectangular shape with its longitudinal direction being perpendicular to the paper, i.e., the same direction as the longitudinal direction of the electric field relaxation layer 3. Furthermore, the structure is formed such that a plurality of trench gate structures are arranged in a stripe shape at equal intervals in the horizontal direction of the paper, thereby configuring a plurality of units.

[0058] And, in n + Type source region 5 and p + The source electrode 10 is formed on the surface of the n-type contact region 6. The source electrode 10 is made of various metals such as Ni / Al. + The portion connected to the n-type source region 5 is made of a metal capable of making ohmic contact with the n-type SiC. + The portion connected to the p-type base region 4 through the p-type contact region 6 is made of a metal capable of making ohmic contact with the p-type SiC. In addition, the source electrode 10 is electrically isolated from the gate wiring (not shown) electrically connected to the gate electrode 9 via the interlayer insulating film 11. In addition, the source electrode 10 is electrically isolated from the n-type base region 4 through the contact hole formed in the interlayer insulating film 11. + Type source region 5 and p + The type contact area 6 is electrically contacted.

[0059] Furthermore, in n +The back side of the semiconductor substrate 1 is formed with n + The drain electrode 12 is electrically connected to the semiconductor substrate 1. With this structure, an n-channel inversion type trench gate vertical MOSFET is formed.

[0060] In the vertical MOSFET thus constructed, when a gate voltage is applied to the gate electrode 9 with the source voltage set to 0 and the drain voltage set to, for example, 10 V, the portion of the p-type base region 4 that contacts the side surface of the trench 7 becomes an inversion-type channel region. Furthermore, current flows between the source electrode 10 and the drain electrode 12 through the channel region.

[0061] On the other hand, when no gate voltage is applied, with the gate voltage and source voltage at zero, a high voltage, such as 1400 V, is applied as the drain voltage. In SiC, which has an electric field breakdown strength approximately 10 times that of silicon devices, this voltage also applies an electric field approximately 10 times that of silicon devices to the gate insulating film 8, potentially causing electric field concentration in the gate insulating film 8, particularly at the bottom of the trench 7 in the gate insulating film 8.

[0062] However, in this embodiment, an electric field relaxation layer 3 is provided that is deeper than the trench 7. Therefore, the electric field relaxation layer 3 pushes the equipotential lines downward toward the drift side, thereby preventing the electric field from concentrating on the gate insulating film 8 at the bottom of the trench gate. This effect is particularly enhanced by increasing the width and depth of the electric field relaxation layer 3.

[0063] Therefore, electric field concentration in gate insulating film 8, particularly electric field concentration at the bottom of trench 7 in gate insulating film 8, can be alleviated. This provides a highly reliable SiC semiconductor device capable of preventing gate insulating film 8 from being broken down.

[0064] Furthermore, in this embodiment, a double-implanted region 3c is provided to reliably connect the first region 3a and the second region 3b. If the first region 3a and the second region 3b were not connected, the first region 3a could not be fixed to the source potential and would be in a floating state. However, by connecting the first region 3a and the second region 3b as in this embodiment, the first region 3a can be reliably fixed to the source potential. This ensures the aforementioned effect.

[0065] Next, about Figure 1 The manufacturing method of the trench gate vertical MOSFET shown in FIG. Figure 3A to Figure 3G Provide explanation.

[0066] 〔 Figure 3A The process shown]

[0067] First, prepare +An epitaxial substrate on which an n-type drift layer 2 is epitaxially grown on the surface of an n-type semiconductor substrate 1. + The n-type semiconductor substrate 1 is a substrate made of SiC single crystal doped with n-type impurities at a high concentration and having an off angle. However, at this time, the n-type drift layer 2 is not entirely formed, but a portion of the surface side of the n-type drift layer 2 is not yet formed.

[0068] 〔 Figure 3B The process shown]

[0069] An ion implantation mask (not shown) is placed on the n-type drift layer 2 , and p-type impurities are ion-implanted into the surface portion of the n-type drift layer 2 using the mask to form the first region 3 a .

[0070] 〔 Figure 3C The process shown]

[0071] After removing the ion implantation mask, epitaxial growth is again performed on the remaining portion of the n-type drift layer 2. Furthermore, an ion implantation mask (not shown) is positioned and used to implant p-type impurities into the newly formed portion of the n-type drift layer 2. The implanted impurities are then activated by heat treatment, for example, to form the second region 3b. The ion implantation mask is then removed. This results in an electric field relaxation layer 3 in which the first region 3a and the second region 3b are connected, and the overlapping portion serves as the double-implanted region 3c. While it is possible to form both the first region 3a and the second region 3b simultaneously through ion implantation after forming the n-type drift layer 2, a high ion implantation energy is required to implant ions at a deeper level. Therefore, the first region 3a is formed after forming a portion of the n-type drift layer 2, followed by the remaining portion of the n-type drift layer 2, and finally the second region 3b. This ensures a deep electric field relaxation layer 3 by making the electric field relaxation layer 3 a two-layer structure.

[0072] Here, after forming the first region 3a, when the remaining portion of the n-type drift layer 2 is epitaxially grown, film thickness variations may occur. For example, when forming a film with a target thickness of 0.7 μm, a variation of ±0.07 μm may occur. In order to perform epitaxial growth well in SiC, an offset substrate is used as the n-type drift layer. + n-type semiconductor substrate 1, however, in this case, the n-type drift layer 2 also inherits the off angle and grows epitaxially. When ion implantation is performed on an n-type drift layer 2 with such an off angle, the ion implantation depth varies due to the channeling effect. Specifically, when the n-type drift layer 2 has an off angle of 4°, the depth varies by approximately 0.1 μm due to the channeling effect caused by the ±2° ion implantation deviation.

[0073] Therefore, considering the maximum thickness variation of 0.07 μm in the remaining portion of the n-type drift layer 2 and the maximum depth variation of 0.1 μm due to the channeling effect, it is necessary to form a double-implanted region 3c to connect the first region 3a and the second region 3b. For example, if the double-implanted region 3c is formed with a thickness of at least 0.17 μm, for example, approximately 0.2 μm, which is the sum of the maximum thickness variation and the maximum depth variation, then the first region 3a and the second region 3b can be reliably connected. Accordingly, when ion implanting the second region 3b, the p-type impurity is implanted to a depth of approximately 0.2 μm, corresponding to the target film thickness of the remaining portion of the n-type drift layer 2.

[0074] This ensures that the first region 3a and the second region 3b are reliably connected. Furthermore, when such ion implantation is performed, the double-implanted region 3c is formed to have a higher p-type impurity concentration than the first region 3a and the second region 3b, and to have a peak in the p-type impurity concentration in the depth direction. This will be explained using an example.

[0075] As an example, when the target value of the film thickness of the remaining part of the n-type drift layer 2 is set to 0.7 μm, the p-type impurity concentration of the electric field relaxation layer 3 is measured for the case where the target value is obtained and the case where a film thickness deviation of ±0.1 μm, which is larger than the maximum film thickness deviation, occurs. Figure 4 The results are shown in FIG. 2. In this measurement, the depth of the ion implantation was set to 0.7 μm, which is the target value of the film thickness of the remaining portion of the n-type drift layer 2 .

[0076] As described above, variations in the film thickness of the remaining portion of the n-type drift layer 2 and variations in the maximum depth due to the channeling effect may occur. Therefore, when ion implantation is performed according to the target film thickness, the first region 3a and the second region 3b may be connected or disconnected.

[0077] Figure 4 In the example shown, when the remaining portion of the n-type drift layer 2 is formed with a film thickness thinner than the target value of 0.6 μm or with a film thickness equal to the target value of 0.7 μm, the p-type impurity concentration has a peak.

[0078] When the film thickness is thinner than the target value, the ion implantation depth is deeper than the target film thickness. Therefore, as long as the variation in the ion implantation depth due to the channeling effect does not shift toward the shallowest depth, the first region 3a and the second region 3b can be reliably connected. On the other hand, when the film thickness is the target value, the film thickness and the ion implantation depth are the same. Therefore, if the variation in the ion implantation depth due to the channeling effect shifts toward the shallower depth, the first region 3a and the second region 3b may not be connected.

[0079] Furthermore, when the film thickness is thicker than the target value, if the ion implantation depth does not shift to the deeper side due to the channel effect, the first region 3a and the second region 3b are not connected or the connection becomes insufficient. Figure 4 In the example shown, when the film thickness is 0.8 μm, the connection between the first region 3 a and the second region 3 b is insufficient, resulting in a portion where the impurity concentration is reduced.

[0080] Therefore, even if the remaining portion of the n-type drift layer 2 is formed thicker than the target value, or the ion implantation is shifted toward the shallower side due to the channeling effect, an ion implantation depth that takes this into account is required to ensure reliable connection between the first region 3a and the second region 3b. Specifically, as described above, a thickness of 0.17 μm or greater, for example, approximately 0.2 μm, calculated by adding the maximum film thickness deviation and the maximum depth deviation, can be estimated to form the double-implanted region 3c. This allows the double-implanted region 3c to be formed, ensuring reliable connection between the first region 3a and the second region 3b. Furthermore, if the double-implanted region 3c is formed, the p-type impurity concentration in this portion is higher than that in the portions of the first region 3a and the second region 3b other than the double-implanted region 3c. Consequently, the electric field relaxation layer 3 is in a state where the peak p-type impurity concentration is in the double-implanted region 3c.

[0081] 〔 Figure 3D The process shown]

[0082] A p-type base region 4 is epitaxially grown on the surfaces of the n-type drift layer 2 and the electric field relaxation layer 3 .

[0083] 〔 Figure 3E The process shown]

[0084] An etching mask (not shown) is disposed to cover the surface of the p-type base region 4 and to open the region where the trench 7 is to be formed. Furthermore, after performing anisotropic etching using the etching mask, isotropic etching and sacrificial oxidation steps are performed as needed to form the trench 7. This allows the formation of a trench 7 that penetrates the p-type base region 4 and reaches the n-type drift layer 2, is shallower than the electric field relaxation layer 3, and is disposed between the adjacent second regions 3 b and separated from the second regions 3 b.

[0085] Next, after removing the etching mask, a gate oxidation step is performed to form a gate insulating film 8. Furthermore, a polysilicon layer is formed by doping impurities on the surface of the gate insulating film 8 and then patterned to form a gate electrode 9. Thus, a trench gate structure is formed.

[0086] 〔 Figure 3F The process shown]

[0087] The surface of the p-type base region 4 forms an n + After a mask (not shown) is formed to open the planned formation area of ​​the n-type source region 5, n-type impurities are ion-implanted at a high concentration to form an n-type source region 5. + Similarly, a p-type source region 5 is formed on the surface of the p-type base region 4. + After a mask (not shown) is formed to open the planned formation area of ​​the p-type contact region 6, p-type impurities are ion-implanted at a high concentration to form a p-type contact region 6. + Type contact area 6.

[0088] 〔 Figure 3G The process shown]

[0089] After forming the interlayer insulating film 11, the interlayer insulating film 11 is patterned to form a + A contact hole is formed to expose the p-type source region 5 and the p-type base region 4, and a contact hole is formed in a cross section different from the cross section shown in the figure to expose the gate electrode 9. In addition, after forming a film of electrode material so as to fill the contact hole, it is patterned to form the source electrode 10 and the gate wiring (not shown).

[0090] Afterwards, by + A drain electrode 12 is formed on the back side of the semiconductor substrate 1. Figure 1 The vertical MOSFET shown is completed.

[0091] As described above, in this embodiment, the p-type impurity ion implantation depth during formation of the second region 3b is set deeper than the film thickness of the portion of the n-type drift layer 2 located above the first region 3a, ensuring reliable overlap between the first and second regions 3a, 3b. Furthermore, the doubly implanted region 3c has a higher p-type impurity concentration than the portion of the first and second regions 3a, 3b that is not doubly implanted, and exhibits a peak in the depth direction. This ensures that the first region 3a is connected to the second region 3b and fixed to the source potential, preventing the first region 3a from floating. Consequently, the electric field relaxation effect of the electric field relaxation layer 3 can be fully achieved.

[0092] (Second embodiment)

[0093] The second embodiment is described below. This embodiment differs from the first embodiment in that the p-type impurity concentration of the electric field relaxation layer 3 is changed. The rest of the embodiment is the same as the first embodiment, so only the differences from the first embodiment will be described.

[0094] As described in the first embodiment, when both the first region 3a and the second region 3b are formed by ion implantation and overlapped, a double-implanted region 3c is formed. Due to the high impurity concentration in this double-implanted region 3c, a large number of extra-lattice atoms are present, potentially leading to injection defects. These injection defects create new energy levels, generating carriers when the depletion layer reaches the double-implanted region 3c when a drain voltage is applied, potentially becoming a leakage source. To prevent the depletion layer from reaching the double-implanted region 3c, the electric field relaxation layer 3 can be made high-concentration to prevent the depletion layer from expanding within the electric field relaxation layer 3. However, when the electric field relaxation layer 3 is made high-concentration, particularly when the entire first region 3a located below the electric field relaxation layer 3 is made high-concentration, the extension of the depletion layer toward the n-type drift layer 2 increases, potentially leading to a problem of not achieving a withstand voltage.

[0095] Therefore, in this embodiment, the p-type impurity concentration in the first region 3a is made relatively low, and the p-type impurity concentration in the second region 3b is made higher than that in the first region 3a. For example, the p-type impurity concentration in the first region 3a is set to 1×10 16 ~1×10 18 cm －3 About the second region 3b, the p-type impurity concentration is set to 1×10 17 ~1×10 20 cm －3 about.

[0096] Thus, in this embodiment, since the p-type impurity concentration in the second region 3b is higher than that in the first region 3a, when a high voltage is applied as the drain voltage, the depletion layer extending within the electric field relaxation layer 3 can be prevented from contacting the double-injection region 3c. When the depletion layer contacts the double-injection region 3c, injection defects generated in the double-injection region 3c become a major cause of carrier generation and a leakage source. Therefore, by preventing the depletion layer extending within the electric field relaxation layer 3 from contacting the double-injection region 3c, leakage can be suppressed. This is explained in detail with reference to simulation results.

[0097] Figure 5A The simulation results of the comparative example show the equipotential distribution and the depletion layer extending within the electric field relaxation layer 3 when the first region 3a and the second region 3b have the same concentration. The equipotential distribution is represented by a thin line, and the depletion layer is represented by a dotted line. Since excessively high p-type impurity concentrations in the first region 3a can lead to a decrease in breakdown voltage, a simulation was performed in which the p-type impurity concentration in the first region 3a was equal to that in the second region 3b rather than increasing it. Here, the p-type impurity concentration in the entire first region 3a and the second region 3b was set to 5×1017 cm －3 Assuming the drain voltage is 1400 V. As shown in the figure, since the p-type impurity concentrations in the first region 3a and the second region 3b are low, the depletion layer extends further inward across the entire area of ​​the electric field relaxation layer 3. Consequently, the depletion layer contacts the doubly injected region 3c, which becomes a leakage source.

[0098] Figure 5B The simulation results of this embodiment show the equipotential distribution and the depletion layer extending in the electric field relaxation layer 3 when the p-type impurity concentration of the second region 3b is higher than that of the first region 3a. Figure 5A The depletion layer of the case is indicated by a thin dotted line, and the depletion layer of the simulation result of this embodiment is indicated by a thick dotted line. Here, the p-type impurity concentration in the entire first region 3a is 5×10 17 cm －3 The p-type impurity concentration in the entire second region 3b is set to 1×10 18 cm －3 Assuming the drain voltage is 1400 V, as shown in the figure, since the p-type impurity concentration in the second region 3b is increased, the depletion layer is less likely to enter the electric field relaxation layer 3. Therefore, the depletion layer is almost not in contact with the double-injection region 3c, and the double-injection region 3c can be prevented from becoming a leakage source.

[0099] Here, in the case of this embodiment, although the second region 3b is made to have a high concentration, the first region 3a is made to have the same concentration as Figure 5A Basically, the extension of the depletion layer into the first region 3a depends on the relationship between the n-type impurity concentration of the n-type drift layer 2 and the p-type impurity concentration of the first region 3a. However, when the p-type impurity concentration of the second region 3b is high, the intrusion of the depletion layer is suppressed near the second region 3b in the first region 3a due to the influence of the second region 3b. Therefore, Figure 5B As shown, the depletion layer can be made to be almost out of contact with the double-injection region 3 c.

[0100] By making the p-type impurity concentration in the second region 3b higher than that in the first region 3a, the depletion layer can be prevented from contacting the double-injected region 3c, thereby suppressing leakage. While the p-type impurity concentration throughout the second region 3b is uniform here, it is sufficient to make the p-type impurity concentration higher than that in the first region 3a at least in the portion adjacent to the first region 3a, i.e., the lower portion of the second region 3b. In this case, the second region 3b can be divided into an upper portion and a lower portion, each having a uniform concentration, with the p-type impurity concentration in the lower portion being higher than that in the upper portion. Alternatively, a concentration gradient can be provided, with the p-type impurity concentration gradually increasing from the upper portion to the lower portion.

[0101] Thus, a high breakdown voltage can be obtained by the electric field relaxation layer 3, leakage can be suppressed, and a decrease in the reliability of the trench gate can be suppressed. Thus, a SiC semiconductor device having a trench gate structure with high breakdown voltage and high reliability can be obtained.

[0102] The method for manufacturing the trench gate vertical MOSFET thus constructed is substantially the same as that of the first embodiment. Figure 3B 、 Figure 3C In the steps shown, only the dosage of the p-type impurity when forming the first region 3 a and the second region 3 b needs to be changed.

[0103] (Third embodiment)

[0104] The third embodiment will be described. This embodiment is similar to the second embodiment except that the p-type impurity concentration of the electric field relaxation layer 3 is changed. Therefore, only the differences from the second embodiment will be described.

[0105] In this embodiment, if Figure 6 As shown in FIG. 1 , the p-type impurity concentration of the upper portion 3d of the first region 3a, i.e., the portion on the second region 3b side including the double-implanted region 3c, is made higher than that of the lower portion 3e below the upper portion 3d. Specifically, the p-type impurity concentration of the upper portion 3d is set to 1×10 17 ~1×10 20 cm －3 The p-type impurity concentration of the lower layer portion 3e is set to 1×10 16 ~1×10 18 cm －3 Furthermore, the p-type impurity concentration of the second region 3b is set to be equal to that of the lower portion 3e, that is, 1×10 16 ~1×10 19 cm －3 about.

[0106] In this way, by increasing the p-type impurity concentration in the upper portion 3d of the first region 3a, the depletion layer can be kept from nearly contacting the double-injected region 3c when a high voltage is applied as the drain voltage, similar to the first embodiment. This achieves the same effects as the first embodiment. Furthermore, while the p-type impurity concentration in the first region 3a is locally high, the p-type impurity concentration in at least the lower portion 3e is lower than that in the upper portion 3d, thereby suppressing a decrease in the breakdown voltage.

[0107] As a reference, a simulation was performed on a SiC semiconductor device having the structure of this embodiment. Figure 7 is a simulation result, showing the equipotential distribution and the state of the depletion layer extending in the electric field relaxation layer 3. In addition, as a reference, the thin dotted line shows Figure 5A The depletion layer of the case is shown by the thick dashed line. In the simulation, the drain voltage is set to 1400 V. In addition, the p-type impurity concentration of the lower portion 3e and the second region 3b is set to 5×10 17 cm －3 The p-type impurity concentration of the upper layer 3d is set to 1×10 18 cm －3 As shown in the figure, the second region 3b is designed to be equal to the lower portion 3e. Therefore, while the depletion layer extends further inward compared to the first embodiment, the increased p-type impurity concentration in the upper portion 3d reduces the intrusion of the depletion layer into the upper portion 3d. This confirms that the depletion layer can be prevented from contacting the double-implanted region 3c.

[0108] (Fourth embodiment)

[0109] This embodiment is similar to the second and third embodiments except that the p-type impurity concentration of the electric field relaxation layer 3 is changed. Therefore, only the differences from the second and third embodiments will be described.

[0110] In this embodiment, as in the third embodiment, the p-type impurity concentration in the upper portion 3d of the first region 3a is higher than that in the lower portion 3e. Furthermore, the p-type impurity concentration in the second region 3b is also increased to the same level as in the upper portion 3d. This high concentration in the second region 3b further suppresses the depletion layer from extending into the electric field relaxation layer 3, preventing the depletion layer from contacting the double-injection region 3c, and further suppressing leakage.

[0111] For reference, a simulation was performed on a SiC semiconductor device having the structure of this embodiment. Figure 8The simulation results show the equipotential distribution and the depletion layer extending in the electric field relaxation layer 3. In the simulation, the drain voltage is set to 1400 V. The p-type impurity concentration of the lower layer 3e is set to 5×10 17 cm －3 The p-type impurity concentration of the upper portion 3d and the second region 3b is set to 1×10 18 cm －3 As shown in the figure, the depletion layer also penetrates less into the second region 3b than in the second embodiment. In this way, it was confirmed that the depletion layer can be prevented from contacting the double-injection region 3c.

[0112] (Fifth embodiment)

[0113] The fifth embodiment will now be described. This embodiment differs from the second to fourth embodiments in that the p-type impurity concentration of the electric field relaxation layer 3 is modified. Otherwise, the structure is the same as the second to fourth embodiments, so only the differences will be described. While this example illustrates the application of the structure of this embodiment to the second embodiment, it is also applicable to the third and fourth embodiments.

[0114] In this embodiment, if Figure 9 and Figure 10 As shown, the second region 3b has the same direction as the trench gate structure as its longitudinal direction, whereas the first region 3a has its longitudinal direction as its longitudinal direction, which is a direction intersecting the second region 3b, orthogonal to the direction in this case.

[0115] Even if the length directions of the first region 3a and the second region 3b are different, a double-implanted region 3c is formed at the intersection. Therefore, as in the first embodiment, by making the p-type impurity concentration of the second region 3b higher than that of the first region 3a, the same effects as those of the first embodiment can be achieved. Similarly, by making the p-type impurity concentration of the upper portion 3d of the first region 3a higher than that of the lower portion 3e, as in the third and fourth embodiments, the same effects as those of the third and fourth embodiments can be achieved.

[0116] In addition, here, as Figure 10 As shown, the first region 3a and the second region 3b are perpendicular to each other when viewed from the substrate normal direction, but it is sufficient that they at least intersect. Furthermore, the first region 3a may not be in a strip shape, but may be in a grid shape having, for example, a portion extending in the same direction as the longitudinal direction of the trench gate structure as in the first to third embodiments, and a portion extending in a direction intersecting therewith as in this embodiment.

[0117] (Other embodiments)

[0118] The present invention has been described based on the above-mentioned embodiment, but is not limited to the embodiment and includes various modifications and variations within the scope of equivalents. In addition, various combinations and forms, and further combinations and forms including only one element, more than or less than the above elements, also fall within the scope and scope of the present invention.

[0119] For example, in the first embodiment described above, the target thickness of the portion of the n-type drift layer 2 above the first region 3a is set to 0.7 μm. However, this is merely an example and can be modified as appropriate. In this case, as long as ion implantation is performed at a depth greater than the sum of the maximum thickness variation during epitaxial growth and the maximum depth variation due to the channeling effect, the same effects as those of the first embodiment can be achieved.

[0120] Furthermore, in each of the above embodiments, the side surface of the second region 3b is made perpendicular to the n + The direction of the surface of the semiconductor substrate 1 is shown in the figure, but it does not necessarily need to be set to a vertical direction. Figure 5B As shown in the simulation results of , etc., the upper portion of the second region 3b is made narrower than the lower portion, thereby forming a tapered shape in which the side surface of the second region 3b is inclined. Conversely, the lower portion of the second region 3b may be made narrower than the upper portion.

[0121] Furthermore, regarding the shape of the first region 3a, in the above embodiments, the cross section taken along a direction perpendicular to the longitudinal direction of the trench gate structure is shown as a quadrilateral with rounded corners, but the cross-sectional shape may also be an oval shape or the like.

[0122] Furthermore, the portion of the n-type drift layer 2 above the first region 3a, i.e., the portion where the second region 3b is formed, may have an n-type impurity concentration higher than that of the other portions of the n-type drift layer 2. This allows the portion of the n-type drift layer 2 between the second regions 3b to function as a current spreading layer having a higher n-type impurity concentration than the portion below it, thereby spreading the current flowing from the channel over a wider area and contributing to lower on-resistance.

[0123] Furthermore, while the above embodiments illustrate an n-channel MOSFET with n-type as the first conductivity type and p-type as the second conductivity type, the present invention is also applicable to a p-channel MOSFET in which the conductivity types of the components are reversed. Furthermore, the above description illustrates a trench gate MOSFET as an example, but the present invention is also applicable to an IGBT with the same trench gate structure. The IGBT differs from the above embodiments in that only the conductivity type of substrate 1 is changed from n-type to p-type; the remaining structure and manufacturing method are the same as those of the above embodiments.

Claims

1. A silicon carbide semiconductor device, characterized in that: have: a substrate of the first conductivity type or the second conductivity type composed of silicon carbide; a drift layer formed on the substrate and composed of silicon carbide of the first conductivity type having a lower impurity concentration than that of the substrate; a base region formed on the drift layer and composed of second conductivity type silicon carbide; a source region formed in an upper portion of the base region and composed of silicon carbide of the first conductivity type having a higher concentration than that of the drift layer; a contact region formed in an upper portion of the base region at a position different from that of the source region and composed of silicon carbide of the second conductivity type having a higher concentration than that of the base region; a trench gate structure formed by forming a gate electrode via a gate insulating film in a plurality of trenches arranged with one direction as the longitudinal direction and formed from the surface of the source region to a position deeper than the base region; a source electrode electrically connected to the source region and the contact region; a drain electrode formed on the back side of the substrate; as well as an electric field relaxation layer disposed in the drift layer and including a first region of the second conductivity type and a second region of the second conductivity type, wherein the first region is formed at a position deeper than the trench, the second region is disposed between the plurality of trenches with its longitudinal direction being the same as the longitudinal direction of the trench and spaced apart from the side surfaces of the trench, and the second region connects the first region and the base region. The first region and the second region are both composed of ion implantation layers. The first region and the second region overlap to form a double implantation region. The second impurity concentration has a peak in the double implantation region.

2. The silicon carbide semiconductor device according to claim 1, wherein At least a portion of the second region located below the first region has a higher second conductivity type impurity concentration than the first region.

3. The silicon carbide semiconductor device according to claim 1, wherein The second conductive type impurity concentration in the entire second region is higher than that in the first region.

4. The silicon carbide semiconductor device according to claim 2, wherein The second conductivity type impurity concentration in the first region is 1×10 16 ~1×10 19 cm －3 , The second conductivity type impurity concentration in the second region is higher than that in the first region, and the second conductivity type impurity concentration is 1×10 17 ~1×10 20 cm －3 .

5. The silicon carbide semiconductor device according to claim 1, wherein An upper portion of the first region, which is on the second region side, has a higher second conductivity type impurity concentration than a lower portion below the upper portion.

6. The silicon carbide semiconductor device according to claim 5, wherein The second conductive type impurity concentration is higher in at least a portion of the second region located below the first region than in the lower portion.

7. The silicon carbide semiconductor device according to claim 5, wherein The second conductive type impurity concentration in the entire second region is higher than that in the lower portion.

8. The silicon carbide semiconductor device according to claim 5, wherein The second conductivity type impurity concentration of the lower layer is 1×10 16 ~1×10 19 cm －3 , The second conductivity type impurity concentration in the upper layer is 1×10 17 ~1×10 20 cm －3 .

9. The silicon carbide semiconductor device according to any one of claims 1 to 8, wherein The first region is formed with the same longitudinal direction as the longitudinal direction of the groove. The first region is wider than the second region.

10. The silicon carbide semiconductor device according to any one of claims 1 to 8, wherein The first region is formed with a longitudinal direction intersecting with a longitudinal direction of the groove.

11. A method for manufacturing a silicon carbide semiconductor device, characterized in that: The process includes the following steps: forming a drift layer on a substrate of the first conductivity type or the second conductivity type composed of silicon carbide, the drift layer being composed of silicon carbide of the first conductivity type having a lower impurity concentration than that of the substrate; forming an electric field relaxation layer of a second conductivity type on the drift layer; forming a base region composed of second conductivity type silicon carbide on the electric field relaxation layer and the drift layer; forming a source region composed of first conductivity type silicon carbide having a higher impurity concentration than that of the drift layer in an upper portion of the base region within the base region; forming a contact region composed of second conductivity type silicon carbide having a higher impurity concentration than that of the base region at a position different from the source region in an upper portion of the base region; forming a trench that penetrates the base region from the surface of the source region to the drift layer and is shallower than the electric field relaxation layer, the trench being arranged with one direction as its length direction and separated from the electric field relaxation layer; forming a gate insulating film on the surface of the trench; forming a gate electrode on the gate insulating film in the trench; forming a source electrode electrically connected to the source region and the contact region; and A drain electrode is formed on the back side of the substrate. The steps of forming the drift layer and the electric field relaxation layer include the following steps: After forming a portion of the drift layer, ion implanting a second conductive type impurity into a surface portion of the portion of the drift layer to form a first region as a portion of the electric field relaxation layer; and After forming the first region, the remaining portion of the drift layer is formed, and the remaining portion of the drift layer is ion-implanted with second conductive type impurities to form the remaining electric field relaxation layer, thereby forming a second region having a longitudinal direction that is the same as the longitudinal direction of the trench and connected to the first region. In the step of forming the second region, the second conductive type impurity ions are implanted to a position deeper than the remaining portion of the drift layer, thereby forming a double implantation region consisting of the second region and the first region overlapping and having a peak second conductive type impurity concentration.

12. The method for manufacturing a silicon carbide semiconductor device according to claim 11, wherein: In the step of forming the second region, the second conductivity type impurity concentration in at least a portion of the second region on the first region side is made higher than that in the first region.

13. The method for manufacturing a silicon carbide semiconductor device according to claim 11, wherein: In the step of forming the first region, the second conductivity type impurity concentration in the upper portion of the first region is made higher than that in the lower portion.

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