A hardware Trojan detection method based on machine learning and hybrid sampling

Abstract

The application belongs to the technical field of integrated circuit hardware security, and discloses a hardware Trojan detection method based on machine learning and mixed sampling. First, the interconnection structure of all gates in the netlist is matched through the inducted low-flip-rate structure; all gates in the netlist are mixed sampled, if the gate does not belong to the low-flip-rate structure, the n-level circuit around the gate is searched and a subgraph is established; if the gate belongs to the low-flip-rate structure, the logic cone where the gate is located is wholly sampled; all connection structures in the feature subgraph are one-hot code encoded, and then accumulated to obtain a fixed-length feature vector; finally, all feature vectors are input to the trained machine learning classifier for node classification, and the hardware Trojan node is detected. The application retains part of the high-dimensional features of the graph, and adopts the mixed sampling mode to expand the feature difference between the hardware Trojan and the normal node, so that the machine learning model can better train and distinguish the hardware Trojan and the normal node, and the detection precision of the detection model is improved.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of integrated circuit hardware security, and particularly relates to a hardware Trojan detection method and system based on machine learning and hybrid sampling, a computer device and a data processing terminal. BACKGROUND

[0002] At present, with the continuous development of the modern integrated circuit (IC) industry, the cost of design and manufacturing is increasing, and the supply chain of each stage may come from all over the world. In the IC process: system level, development environment, register transfer level, gate level, transistor level and physical level all have the possibility of being implanted with malicious logic, and the process of IC industry globalization greatly increases the risk of untrusted third-party supply chain inserting hardware Trojan in the design and manufacturing process. These intentionally or maliciously implanted logic in the original IC design are called hardware Trojans (HT), which can cause serious consequences such as information leakage, function change, performance reduction, denial of service and even chip destruction, become a major hidden danger in the information security neighborhood, and seriously affect national security and the consumer electronics field. Third-party intellectual property cores (IP cores) are widely used in IC design to reduce design cycle and improve design efficiency. However, the provider of the third-party IP core is not transparent, and hardware design engineers often do not have the right to access the IP core, or can only access the gate-level netlist after compilation and synthesis through high-level access, and the readability of the gate-level netlist is very poor, which provides a natural shelter for the implantation of hardware Trojans. The gate-level netlist is a disaster area for hardware Trojan implantation, so how to detect hardware Trojans in the gate-level netlist of the IP core is a very meaningful and challenging work.

[0003] Traditional hardware Trojan detection methods mainly include logic testing, code analysis and formal verification. Although these schemes are theoretically available, they may have state explosion problems with increasingly large integrated circuits, and it is difficult to cover all cases using logic verification, resulting in low hardware Trojan detection efficiency. Machine learning methods have also been applied to hardware Trojan detection. Through modeling of hardware Trojan features and training of machine learning models, the above hardware Trojan detection efficiency problems can be greatly solved, but there are still some problems: the machine learning method based on multiple hardware Trojan features will spend a huge amount of time on feature extraction, and this time will increase exponentially in the case of very large circuit size; the traditional machine learning method does not make good use of the features of the netlist graph, resulting in low detection efficiency of the model; the feature of the edge node of the hardware Trojan is not obvious, which is also a common problem in machine learning methods.

[0004] Through the above analysis, the problems and defects of the prior art are: the machine learning method based on multiple hardware Trojan features of the prior art will spend a huge amount of time on feature extraction, and this time increases exponentially in the case of very large circuit scale; the traditional machine learning method does not make good use of the features of the netlist diagram, resulting in low detection efficiency of the model.

[0005] The difficulty of solving the above problems and defects is:

[0006] 1. Since multi-dimensional feature extraction is very time-consuming, exploring a feature that can aggregate multi-dimensional features in the circuit netlist is the biggest improvement direction and difficulty at present;

[0007] 2. The feature needs to aggregate the graph-related high-order characteristics in the netlist, such as the degree centrality of the node and the neighbor node in the netlist, the number of interconnection relationships, etc.

[0008] 3. How to handle the boundary node information of the hardware Trojan is the key to recognition.

[0009] The significance of solving the above problems and defects is: using an aggregated feature to represent hardware nodes can speed up hardware feature extraction, and introducing high-order features of the graph can improve the detection efficiency of the detection model and speed up the iteration of the detection model. A feasible solution for handling boundary nodes is provided to improve the detection accuracy of hardware Trojans. SUMMARY

[0010] In view of the problems existing in the prior art, the present application provides a hardware Trojan detection method, system, computer device and data processing terminal.

[0011] The present application is implemented as follows: a hardware Trojan detection method, the hardware Trojan detection method builds a detection model; all gates in the netlist are matched with the low-flip-rate structure; all gates in the netlist are mixed sampled, if the gate does not belong to the low-flip-rate structure, the surrounding n-level circuit is searched and a subgraph is established; if the gate belongs to the low-flip-rate structure, the logic cone where the gate is located is sampled as a whole; all connection structures in the feature subgraph are one-hot coded, and then accumulated to obtain a fixed-length feature vector; finally, all feature vectors are input into the trained machine learning classifier for node classification to detect the hardware Trojan nodes.

[0012] Further, the netlist to be tested is text parsed and graph structure modeled using python language, and the graph is represented in the form of an adjacency matrix. Then, all nodes in the netlist are matched with the low-flip-rate structure.

[0013] Further, the feature vector of fixed length is obtained by accumulation, and then the feature vector is put into a machine learning model for training. After continuously adjusting the parameters for model training, the model with the highest detection accuracy is selected for subsequent hardware Trojan detection. The same operation is performed on the to-be-tested netlist, and the feature vector obtained in the fifth step is put into the detection model generated in S106 for hardware Trojan detection. The detection model outputs the hardware Trojan detection result of the entire netlist. If there is a suspected hardware Trojan node in the output result, it means that the circuit is not safe, and more detailed analysis needs to be performed on the suspected node.

[0014] Further, the hardware Trojan detection method comprises the following steps:

[0015] In the first step, the netlist with the embedded Trojan in the test set is mapped into a directed graph, and the structure is G=(N, E), G is the adjacency matrix of the entire netlist, N is all the gates in the net, and E is the connection relationship between the gates. This step mainly extracts the graph information of the netlist to speed up the extraction of subsequent features.

[0016] In the second step, the low-flip-probability connection structure existing in the hardware Trojan is summarized and used for structure matching in the third step. This step guides different sampling strategies.

[0017] In the third step, structure matching is performed on all nodes. If the low-flip-rate structure exists in the front and rear connection relationship, the node is marked as a matched node. If not, it is marked as an unmatched node. This step is used to screen the nodes suspected of being hardware Trojans.

[0018] In the fourth step, different sampling strategies are used for different marked gates to increase the feature gap between the hardware Trojan and the normal node.

[0019] In the fifth step, the adjacency matrix obtained by the node is represented by a feature vector. All connection relationships in the adjacency matrix are counted in the form of one-hot code. This step aggregates the neighbor information of the hardware Trojan and the node features.

[0020] In the sixth step, the obtained feature vector is put into a machine learning classification model for training to obtain the final detection model.

[0021] In the seventh step, the to-be-tested netlist is subjected to the first step to the fifth step, and the feature vector obtained in the fifth step is put into the detection model generated in S106 for hardware Trojan detection. The detection model outputs the hardware Trojan detection result of the entire netlist. If there is a suspected hardware Trojan node in the output result, it means that the circuit is not safe, and more detailed analysis needs to be performed on the suspected node.

[0022] Further, in the first step of modeling the netlist, a script is used to traverse the netlist, and the gates and wires in the netlist are recorded to obtain the preliminary graph structure. The gates are N in the graph structure, and the wires are E in the graph structure. Then, the adjacency matrix is represented by the collected information. The established adjacency matrix is a directed graph, which means that the gates have fan-in and fan-out relationships.

[0023] Further, the fourth step of the unmatching node: the node is suspected to be a hardware Trojan drive circuit, the information around the node is aggregated in the form of aggregation in the graph neural network, the node and connection information in the neighborhood of the node are obtained by forward and backward n-level breadth-first search, the node information is added, and a total of 2n+1 levels are stored in an adjacency matrix;

[0024] The matched node: a complete judgment is performed on the logical cone; the logical cone is generated as follows:

[0025] 1) searching n levels from the target node to the fan-out direction to find the root node of the logical cone;

[0026] 2) performing forward breadth-first search for 2n+1 levels from the root node of the logical cone to obtain a fixed-length logical cone;

[0027] 3) finally, the logical cone is stored in an adjacency matrix.

[0028] Further, the sampling strategy for the node in the fourth step is to sample and aggregate the information in the neighborhood of the node for node embedding; the biased sampling method is used to completely represent the logical cone where the matched node is located, and the connection relationship of the entire logical cone is used to judge whether the node is a hardware Trojan;

[0029] If there are n types of gates in the netlist, then the one-hot code needs n 2 dimension. For example, if there are two types of gates, AND gates and OR gates, and there are connection relationships between AND-OR, OR-OR, AND-AND, and OR-AND, the one-hot code of these connection relationships is represented as [0, 1, 0, 0], [0, 0, 1, 0], [1, 0, 0, 0], [0, 0, 0, 1], and finally the one-hot code is accumulated to obtain the feature vector of the node [1, 1, 1, 2];

[0030] The training parameters of the sixth step are defined as follows: TP is the number of correctly identified Trojans, TN is the number of correctly identified normal nodes, FP is the number of incorrectly identified Trojans, TN is the number of incorrectly identified normal nodes, TPR is defined as TP / (TP+TN), and TNR is defined as TN / (TN+FP).

[0031] Another object of the present application is to provide a computer device comprising a memory and a processor, wherein the memory stores a computer program, and the computer program is executed by the processor to make the processor execute the steps of the hardware Trojan detection method.

[0032] Another object of the present application is to provide an information data processing terminal for implementing the hardware Trojan detection method.

[0033] Another object of the present application is to provide a hardware Trojan detection system for implementing the hardware Trojan detection method, comprising:

[0034] A directed graph mapping module is configured to map the netlist embedded with the Trojan in the test set into a directed graph.

[0035] A connection structure induction module is configured to induce the low-flip-probability connection structure existing in the hardware Trojan.

[0036] A structure matching module is configured to perform one-time structure matching on all nodes, and if a low-flip-rate structure exists in the front and rear connection relationship, the node is marked as a matched node, and if not, the node is marked as an unmatched node.

[0037] A sampling strategy module is configured to perform different sampling strategies on different marked gates.

[0038] A formal statistics module is configured to represent the adjacency matrix obtained by the node as a feature vector, and to statistically represent all connection relationships in the adjacency matrix in the form of one-hot code.

[0039] A detection module acquisition module is configured to put the obtained feature vector into a supervised neural network for training to obtain a final detection model.

[0040] A hardware Trojan detection module is configured to perform hardware Trojan detection, and the detection model outputs the hardware Trojan detection result of the entire netlist. If the output result contains suspected hardware Trojan nodes, it means that the circuit is not safe, and the suspected nodes need to be analyzed in more detail.

[0041] In combination with all the technical solutions described above, the present application has the advantages and positive effects that: the present application only needs to perform one-time feature extraction to retain the high-order characteristics of the graph and the node characteristics, and uses a hybrid sampling technology to amplify the Trojan features of the hardware Trojan edge nodes, thereby effectively identifying whether there is a hardware Trojan inside the chip on the poor readability gate-level netlist, and greatly improving the hardware Trojan detection efficiency.

[0042] Compared with the prior art, the present application has the following advantages: compared with the existing hardware Trojan detection method based on traditional machine learning, the algorithm complexity of the present application for feature extraction is O(N), which can complete feature extraction in a short time when dealing with large-scale integrated circuit netlist, and is much faster than the scheme based on multiple hardware Trojan features in algorithm. The present application retains part of the high-dimensional features of the graph, and uses a mixed sampling method to expand the feature difference between the hardware Trojan and the normal node, so that the machine learning model can better train and distinguish the hardware Trojan and the normal node, and improve the detection accuracy of the detection model.

[0043] Compared with the hardware Trojan detection technology based on logic verification, the present application does not need to generate test vectors, and can effectively avoid the state explosion. DETAILED DESCRIPTION

[0044] Figure 1 is a hardware Trojan detection method flowchart provided by an embodiment of the present application.

[0045] Figure 2 is a structural schematic diagram of a hardware Trojan detection system provided by an embodiment of the present application.

[0046] Figure 3 is a flow schematic diagram of a hardware Trojan detection method provided by an embodiment of the present application.

[0047] Figure 4 is a feature extraction and feature vector representation schematic diagram based on mixed sampling provided by an embodiment of the present application.

[0048] Figure 5 is a detection result diagram of a reference circuit provided by an embodiment of the present application.

[0049] In the figure: 1, a directed graph mapping module; 2, a connection structure induction module; 3, a structure matching module; 4, a sampling strategy module; 5, a formal statistics module; 6, a detection module acquisition module; 7, a hardware Trojan detection module. DETAILED DESCRIPTION

[0050] In order to make the purpose, technical scheme and advantages of the present application more clear, the present application is further described in detail below in combination with embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application, and are not used to limit the present application.

[0051] In view of the problems existing in the prior art, the present application provides a hardware Trojan detection method, system, computer device and data processing terminal, which are described in detail below in combination with the drawings.

[0052] As shown in Figure 1 The hardware Trojan detection method provided by the present application includes the following steps:

[0053] S101: The netlist embedded with the Trojan in the test set is mapped into a directed graph, and the structure is G=(N, E), G is the adjacency matrix of the entire netlist, N is all the gates in the net, and E is the connection relationship between the gates, which is the most classic expression of the graph, and this method makes the graph structure simple and clear.

[0054] S102: The low-flip-probability connection structure existing in the hardware Trojan is summarized, and is used for structure matching in S103.

[0055] S103: Structure matching is performed on all nodes, and if the low-flip-rate structure shown in Table 1 exists in the front and rear connection relationship, the node is marked as a matched node, and if not, it is marked as an unmatched node.

[0056] S104: Different sampling strategies are performed for different marked gates, assuming that the sampling depth is 2n+1, and n is the depth of a single direction of neighborhood sampling:

[0057] S105: The adjacency matrix obtained by the node is characterized by a feature vector; all connection relationships in the adjacency matrix are counted in the form of one-hot code;

[0058] S106: The obtained feature vector is put into a supervised neural network for training to obtain a final detection model;

[0059] S107: The netlist to be tested is subjected to S101-S105, and the feature vector obtained by S105 is put into the detection model generated by S106 for hardware Trojan detection, and the detection model outputs the hardware Trojan detection result of the entire netlist, if there is a suspected hardware Trojan node in the output result, it means that the circuit is not safe, and more detailed analysis needs to be performed on the suspected nodes.

[0060] In S101 of the present application: when modeling the netlist, the script is used to traverse the netlist, and the gates and wires in the netlist are recorded to obtain the preliminary graph structure, the gates are N in the above graph structure, and the wires are E in the graph structure, and the adjacency matrix is characterized by the collected information. The adjacency matrix established is a directed graph, which means that the gates have fan-in and fan-out relationships.

[0061] In S102 of the present application: the low-flip-probability connection relationship is summarized as Figure 3 and shown in Table 1, these features are summarized from the test set in TrustHub and related papers, and usually appear in the trigger circuit of the hardware Trojan, and most of them are edge nodes of the hardware Trojan, so the edge is identified with this structure, and the hardware Trojan and the normal circuit can be separated.

[0062] In S104 of the present application: unmatched nodes: such nodes are less suspected of being hardware trojan drive circuits, therefore the information of n levels around the node is aggregated in the form of aggregation in the graph neural network, that is, the nodes and connection information in the neighborhood of the node are obtained by forward and backward n-level breadth-first search, and the node information is added, a total of 2n+1 levels. The information is stored by an adjacency matrix.

[0063] Matched nodes: such nodes have considerable suspicion of being hardware trojan drive circuits, so a complete judgment needs to be made on the logic cone where the node is located. The generation of the logic cone is as follows:

[0064] 1) Search n levels from the target node to the fan-out direction to find the root node of the logic cone.

[0065] 2) Start from the root node of the logic cone and perform forward breadth-first search for 2n+1 levels to obtain a fixed-length logic cone.

[0066] 3) Finally, store the adjacency matrix of the logic cone.

[0067] In S104 of the present application: the sampling strategy for nodes is to sample and aggregate the information in the neighborhood around the node for embedding of the node. Since the matched nodes are likely to be in the edge area of the hardware trojan, the above sampling method will have two disadvantages: first, the result of forward sampling is the connection relationship of normal nodes, which will affect the training effect of the detection model; second, since it is in the edge of the hardware trojan trigger circuit, the result of backward sampling can only sample a small branch of the logic cone, which does not contribute much to the representation of the node as a hardware trojan. These two disadvantages will cause loss shock during model training, making it difficult to converge. Therefore, the present application uses a biased sampling method to completely represent the logic cone where the matched node is located. Since the logic cone can collect more information of the hardware trojan structure relative to the sampling method of backward breadth-first search, the connection relationship of the entire logic cone is used to judge whether the node is a hardware trojan.

[0068] In S105 of the present application: assuming that there are n types of gates in the netlist, then the one-hot code needs n 2 dimension. For example, suppose there are two types of gates, AND and OR gates, and there are connection relationships between AND-OR, OR-OR, AND-AND, and OR-AND, which are represented by one-hot codes [0, 1, 0, 0], [0, 0, 1, 0], [1, 0, 0, 0], and [0, 0, 0, 1]. Finally, these one-hot codes are added up to form the feature vector [1, 1, 1, 2] of the node.

[0069] In S106 of the present application: the training parameters are defined as follows: define TP as the number of correctly identified trojans, TN as the number of correctly identified normal nodes, FP as the number of incorrectly identified trojans, TN as the number of incorrectly identified normal nodes, TPR is defined as TP / (TP+TN), and TNR is defined as TN / (TN+FP). The main purpose of model parameter adjustment is to improve TPR while maintaining high TNR.

[0070] The hardware trojan detection method provided by the present application can also be implemented by other steps, Figure 1 The hardware trojan detection method provided by the present application is only one specific embodiment.

[0071] As shown in Figure 2 The hardware trojan detection system provided by the present application comprises:

[0072] A directed graph mapping module 1 is used to map the netlist embedded with trojans in the test set into a directed graph;

[0073] A connection structure induction module 2 is used to induce the low-flip-probability connection structure existing in the hardware trojan;

[0074] A structure matching module 3 is used to perform one-time structure matching on all nodes, and if a low-flip-rate structure exists in the front and rear connection relationship, the node is marked as a matched node, and if not, it is marked as an unmatched node.

[0075] A sampling strategy module 4 is used to perform different sampling strategies for different marked gates:

[0076] A formal statistics module 5 is used to represent the feature vectors of the adjacency matrix obtained by the nodes; all connection relationships in the adjacency matrix are statistically represented in the form of one-hot code;

[0077] A detection module acquisition module 6 is used to put the acquired feature vectors into a supervised neural network for training to obtain the final detection model;

[0078] A hardware trojan detection module 7 is used to perform hardware trojan detection, and the detection model outputs the hardware trojan detection result of the entire netlist. If the output result contains suspected hardware trojan nodes, it means that the circuit is not safe, and these suspected nodes need to be analyzed in more detail.

[0079] The technical solutions of the present application will be further described below with reference to the accompanying drawings.

[0080] Figure 2For the flow chart of the hardware Trojan detection method of the application, the application provides a gate-level hardware Trojan detection method based on machine learning, which first builds a detection model. The data set used in this embodiment is 7 small net tables of 200 gates RS232-T1000, RS232-T1100, RS232-T1200, RS232-T1300, RS232-T1400, RS232-T1500, RS232-T1600 and 5000 gate net tables S15850-T100, S35932-T100, S35932-T200, S35932-T300, S38417-T100, S38417-T200, S38417-T300, S38584-T100 and 20000 gate wb_conmax-T100. The first step is to use python language to analyze the text and model the graph structure of the net table, and the application uses the adjacency matrix to represent the graph. Then the low flip rate structure is induced to match the structure of all nodes in the net table, and the induced structure is shown in Table 1. Then the nodes are mixed sampled, if the node is not matched, the node is searched and a subgraph is established, and the sampling window used in the example is 5, that is, the breadth first search is 2 levels before and after; if the node is matched, the whole sampling of the logic cone where the node is located is needed. Finally, the connection structure in the feature subgraph is coded by one-hot code, and then accumulated to obtain a fixed length feature vector. Then the feature vector is put into the machine learning model for training, and the integrated learning method is used as the detection model in this embodiment. After continuously adjusting the parameters for model training, the model with the highest detection accuracy is selected for subsequent hardware Trojan detection. Finally, the net table to be tested is operated in the same way and put into the detection model to obtain the prediction result of the model.

[0081] Table 1 two-level connection relationship with low flip structure

[0082]

[0083] The training process of the detection model is step one-step six.

[0084] Step one, for the mapping of the directed graph of the net table, the gate type, gate name, port connection and wire in the net table are analyzed by using python language and regular table, and saved to the corresponding container. Then the interconnection information between the gates is obtained from the container and the corresponding adjacency matrix is constructed.

[0085] Step two, to summarize the low trigger probability connection structure in hardware Trojan, and used in structure matching in step three. The low trigger structure of hardware Trojan is summarized from the test set of TrustHub and related literature, as shown in Table 1. The traditional low trigger structure is AONN type, that is, the low trigger secondary structure composed of and gate, or gate, nand gate and nor gate, such as 1-8 in Table 1; and its analog such as multiplexer and register, XOR and XNOR gate are also applied in structure matching. With different library technology, more fan-in and more complex benchmark cells are integrated (such as low power design cells), and the gates with low trigger characteristics also need to be summarized into low trigger structure.

[0086] Step S3 is structure matching work, which is performed on all nodes in the netlist. In the embodiment of the present application, structure matching work is performed on two circuit subgraphs in Figure 4 . As shown in Figure 4 , the a node is summarized as a normal node because there is no low trigger structure in the backward connection relationship of the node; and the b node is summarized as a matching node because the connection relationship with the backward node is and gate-and gate.

[0087] Step four is hybrid sampling, and the sampling window in the embodiment of the present application is fixed at 5, including the node itself. As shown in Figure 4 , because a is an unmatched node, the sampling method is 2-level breadth-first algorithm forward and backward respectively, and the obtained subgraph is the neighborhood around the node; and because b is a matched node, the logic cone in which b is located needs to be obtained as much as possible, so the root node of the logic cone is found by 2-level depth-first search, and then 5-level forward breadth-first search is performed from the root node to sample the logic cone with b in the middle. Of course, the window length of the search can be changed, but the effect is better when the length is 5 or 7.

[0088] Step five is to represent the adjacency matrix obtained by the node with a feature vector. As shown in Figure 4 , assuming that there are 4 basic gate types in the embodiment of the present application, which are and, or, nand and nor, then the connection relationship represented by one-hot code has 16 kinds. The example one-hot code encoding position is as follows: and gate-and gate 1; and gate-or gate 2; and gate-nand gate 3; and gate-nor gate 4; or gate-and gate 5; or gate-or gate 6; or gate-nand gate 7; or gate-nor gate 8; nand gate-and gate 9; nand gate-or gate 10; nand gate-nand gate 11; nand gate-nor gate 12; nor gate-and gate 13; nor gate-or gate 14; nor gate-nand gate 15; nor gate-nor gate 1. For Figure ThreeA node is sampled, and because of its backward connection relationship, it does not belong to the low flip rate connection relationship in Table 1, so the two levels of breadth-first search are performed before and after it, and the sampled connection relationship is: 2 or gate-or gate (6), 1 NAND-or gate (10), 1 or gate-and gate (4), 1 and gate-or gate (2), 1 or gate-and NAND gate (7), 1 NAND gate to and gate (8), so the corresponding feature vector is [0, 1, 0, 1, 0, 2, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0]. For Figure Three B is sampled, and because the two backward connection relationships are and gate-and gate, they all belong to the low flip rate structure, so the logic cone sampling in the process needs to be performed, and the logic cone in which it is located is viewed, and the root node of the logic cone is the node where the fan-out direction two levels C of the sampling node B are located, and then the entire logic cone is restored by five levels of forward breadth-first search to obtain B. Figure 4 The sampled connection relationship is: 6 and gate-and gate (1), 4 or gate-and gate (5), 2 or gate-or gate (6), 1 NAND-or gate (10), 1 NAND-and gate (9), 3 and gate-or gate (2). Therefore, the corresponding feature vector is [6, 2, 0, 0, 4, 2, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0].

[0089] Step six, for detecting model training. The embodiment of the present application adopts a supervised integrated decision tree and an integrated random forest as the detection model, and these two models have the advantages of convenient calling and fast training speed, and at the same time, through testing, they also have a high accuracy rate in the task of hardware Trojan detection. The input is the feature vector described above, and the output is 1 or 0, which respectively indicates that the vector corresponds to a hardware Trojan or a normal node. After continuously adjusting the parameters for model training, the model with the highest detection accuracy is selected for subsequent hardware Trojan detection. The cross-validation method is used to divide multiple circuits used for training into a training set and a test set. The data of the training set is used to monitor the training of the model, and the data of the test set is used to evaluate the accuracy of the model. Finally, the model with the highest detection accuracy is used to detect the hardware Trojan of the netlist to be tested.

[0090] Step seven, for detecting the hardware Trojan of the netlist to be tested. The netlist to be tested needs to realize the representation of the feature vector, and finally the feature vectors of all nodes are put into the detection model for model prediction.

[0091] The integrated model used is realized by the sklearn library, and the number of integrated models used is 10. In the case of ensuring the accuracy of the model, the training speed of the model is very fast, and in the case of using gpu acceleration, all netlist cross-validation can be completed within 10 seconds. Figure 5The hardware Trojan detection precision achieved by the embodiments of the present application is more than 93% TPR and more than 95% TNR.

[0092] It should be noted that the embodiments of the present application can be realized by hardware, software or a combination of hardware and software. The hardware part can be realized by special logic; the software part can be stored in a memory and executed by a suitable instruction execution system, such as a microprocessor or a specially designed hardware. Those skilled in the art can understand that the above-mentioned devices and methods can be realized by computer executable instructions and / or included in processor control codes, for example, such codes are provided on a carrier medium, such as a magnetic disk, a CD or a DVD-ROM, a programmable memory, such as a read-only memory (firmware), or a data carrier, such as an optical or electronic signal carrier. The devices of the present application and their modules can be realized by hardware circuits, such as very large scale integrated circuits or gate arrays, semiconductors, such as logic chips, transistors, etc., or programmable hardware devices, such as field programmable gate arrays, programmable logic devices, etc., by software executed by various types of processors, or by a combination of the above-mentioned hardware circuits and software, such as firmware.

[0093] The above is only a specific embodiment of the present application, but the protection scope of the present application is not limited thereto, any modification, equivalent replacement and improvement within the technical range disclosed by the present application, within the spirit and principle of the present application, should be covered within the protection scope of the present application.

Claims

1. A hardware Trojan detection method, characterized in that, The hardware Trojan detection method performs detection model building; the low-flip-rate structure is matched with the interconnection structure of all gates in the to-be-tested netlist; all gates in the netlist are mixed sampled, if the gate does not belong to the low-flip-rate structure, the n-level circuit around the gate is searched and a subgraph is established, and if the gate belongs to the low-flip-rate structure, the logic cone where the gate is located is integrally sampled; all connection structures in the feature subgraph are coded by using a one-hot code, and then are accumulated to obtain a fixed-length feature vector; finally, all feature vectors are input to a machine learning classifier which has been trained to perform node classification, and a hardware Trojan node is detected; The hardware Trojan detection method comprises the following steps: In a first step, the netlist in which the Trojan is implanted in the test set is mapped into a directed graph, and the structure is G=(N, E), G is the adjacency matrix of the entire netlist, N is all gates in the netlist, and E is the connection relationship between the gates; In a second step, a low-flip-rate connection structure existing in the hardware Trojan is induced, and is used for structure matching in a third step; In the third step, structure matching is performed on all nodes, and when the low-flip-rate structure exists in the front and rear connection relationship, the node is marked as a matched node, and if not, the node is marked as an unmatched node; In a fourth step, different sampling strategies are adopted for different marked gates; In a fifth step, the adjacency matrix obtained by the node is represented by a feature vector; all connection relationships in the adjacency matrix are counted in the form of a one-hot code; In a sixth step, the obtained feature vector is put into a supervised neural network for training to obtain a final detection model; In a seventh step, the to-be-tested netlist is subjected to the first step to the fifth step, and the feature vector obtained in the fifth step is put into the detection model generated in the sixth step to perform hardware Trojan detection, and the detection model outputs the hardware Trojan detection result of the entire netlist; if the output result exists a suspected hardware Trojan node, it means that the circuit is not safe, and the suspected node needs to be analyzed in more detail; The fourth step is an unmatched node: the node is suspected to be a hardware Trojan driver circuit, and the neighborhood aggregation method in the graph neural network is adopted to aggregate the information of the n-level neighborhood of the node, the node and the connection information of the neighborhood of the node are obtained by performing forward and backward breadth-first search, and the information of the node itself is added, so that 2n+1 levels of information are stored in the adjacency matrix; The matched node: a complete judgment is performed on the logic cone; the generation of the logic cone is as follows: 1) The root node of the logic cone is found by searching n levels in the fan-out direction from the target node; 2) A fixed-length logic cone is obtained by performing forward breadth-first search for 2n+1 levels from the root node of the logic cone; 3) Finally, the adjacency matrix of the logic cone is stored; In the fourth step, the information of the neighborhood around the node is sampled and aggregated for node embedding; the matched node is completely characterized by using the biased sampling method, and the connection relationship of the entire logic cone is used to judge whether the node is a hardware Trojan. The fifth step netlist exists n types of gate, then the one-hot code needs n 2 When the netlist exists 2 types of gate, AND gate and OR gate, there are connection relationships of AND-OR, OR-OR, AND-AND, OR-AND, and the one-hot code of these connection relationships is represented as [0, 1, 0, 0], [0, 0, 1, 0], [1, 0, 0, 0], [0, 0, 0, 1], and finally the one-hot code is accumulated for the feature vector [1, 1, 1, 2] of the node. The training parameters of the sixth step are defined as follows: TP is the number of correctly identified trojans, TN is the number of correctly identified normal nodes, FP is the number of incorrectly identified trojans, TN is the number of incorrectly identified normal nodes, TPR is defined as TP / (TP+TN), and TNR is defined as TN / (TN+FP).

2. The hardware Trojan detection method of claim 1, wherein, The netlist is parsed using python language and the graph structure is modeled, and the graph is represented by an adjacency matrix; then the low-flip-rate structure is induced to match the structure of all nodes in the netlist.

3. The hardware Trojan detection method of claim 1, wherein, After obtaining the fixed-length feature vector by accumulation, the feature vector is put into the machine learning model for training, and a supervised neural network is used as the detection model for training. After continuously adjusting the parameters for model training, the model with the highest detection accuracy is selected for subsequent hardware Trojan detection. The same operation is performed on the test netlist and the detection model is obtained.

4. The hardware Trojan detection method of claim 1, wherein, When modeling the netlist in the first step, a script is used to traverse the netlist, record the gates and connections in the netlist, and obtain the initial graph structure. The gate is N in the graph structure, and the connection is E in the graph structure. The adjacency matrix is characterized by the collected information, and the adjacency matrix is a directed graph, which means that the gates have fan-in and fan-out relationships.

5. A computer device, comprising: The computer device includes a memory and a processor, and the memory stores a computer program, which is executed by the processor to perform the steps of the hardware Trojan detection method of any one of claims 1-4.

6. A hardware Trojan detection system for implementing the hardware Trojan detection method of any one of claims 1-4, characterized in that, The hardware Trojan detection system includes: A directed graph mapping module for mapping the netlist with embedded hardware Trojan in the test set to a directed graph; A connection structure induction module for inducing low-flip-probability connection structures existing in hardware Trojans; A structure matching module for performing a structure matching on all nodes. If a low-flip-rate structure exists in the front and rear connection relationship, the node is marked as a matched node. If not, it is marked as an unmatched node. A sampling strategy module for different sampling strategies for different marked gates: A formal statistical module for representing the adjacency matrix of the node as a feature vector. All connection relationships in the adjacency matrix are statistically represented in the form of one-hot code. A detection module acquisition module for placing the obtained feature vector into a supervised neural network for training to obtain a final detection model. A hardware Trojan detection module for detecting hardware Trojans. The detection model outputs the hardware Trojan detection result of the entire netlist. If the output result contains suspected hardware Trojan nodes, it means that the circuit is not safe and the suspected nodes need to be analyzed in more detail.

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