Non-volatile memory, memory system, and data erasing method of memory

Abstract

The present application provides a nonvolatile memory, a memory system, and a data erasing method of the memory, the method comprising: applying a first conduction voltage to a memory cell included in a first stack of a plurality of stacks to be erased; after applying the first conduction voltage, applying a source erasing voltage and a drain erasing voltage to a common source and a common drain, respectively; and applying a first voltage to a dummy memory cell included in a second stack of the plurality of stacks to be erased during a level ramp-up of the source erasing voltage and the drain erasing voltage to a peak level thereof.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology. Specifically, this application relates to a non-volatile memory, a memory system, and a method for erasing data from the memory. Background Technology

[0002] Recently, non-volatile memory with vertical storage cells has been widely used in electronic devices, which typically consist of multiple vertically stacked layers (also known as multiple decks). As the number of layers in non-volatile memory continues to increase, the problem of reduced channel current becomes particularly prominent. To solve this problem, electron-rich conductive plugs are usually placed between the multiple stacked layers.

[0003] It should be understood that the background section is intended to provide some useful background for understanding the technology; however, this content is not necessarily what was known or understood by a person skilled in the art prior to the filing date of this application. Summary of the Invention

[0004] One aspect of this application provides a data erasure method for a non-volatile memory, wherein the non-volatile memory includes: a plurality of memory blocks, each memory block including a plurality of stacks electrically connected to each other, each stack including a plurality of memory cells and at least one dummy memory cell adjacent to an end of the stack, at least one end of the stack having a plurality of drains, and at least one end of another stack having a common source, the method comprising: applying a first on-state voltage to memory cells included in a first stack of the plurality of stacks to be erased; after applying the first on-state voltage, applying a source erase voltage and a drain erase voltage to the common source and the drain, respectively; and during the period when the levels of the source erase voltage and the drain erase voltage rise to their peak levels, applying a first voltage to dummy memory cells included in a second stack of the plurality of stacks to be erased.

[0005] In one embodiment of this application, the applied first voltage is the induced voltage of the induced gate-induced drain leakage current.

[0006] In one embodiment of this application, the method further includes setting the memory cells included in the first stack to a floating state after the level of the first turn-on voltage rises to its peak level.

[0007] In one embodiment of this application, the method further includes: applying a first bias voltage to the memory cells included in the first stack after the level of the first turn-on voltage has climbed to its peak level.

[0008] In one embodiment of this application, the method further includes applying a ground voltage to the memory cells included in the second stack.

[0009] In one embodiment of this application, the second stack includes a top stack including a plurality of drain-select gates, and the method further includes: applying a second voltage less than the drain-erase voltage to at least one of the drain-select gates during the period when the levels of the source erase voltage and the drain erase voltage rise to their peak levels.

[0010] In one embodiment of this application, the first stack includes a top stack, the top stack including a drain-select gate, and the method further includes: applying a second on-state voltage to the drain-select gate while applying the first on-state voltage; and setting the drain-select gate to a floating state or applying a second bias voltage to the drain-select gate after the level of the second on-state voltage climbs to its peak level.

[0011] In one embodiment of this application, the first stack includes a bottom stack, the bottom stack including a source-select gate, and the method further includes: applying a third on-state voltage to the source-select gate while applying the first on-state voltage; and setting the source-select gate to a floating state or applying a third bias voltage to the source-select gate after the level of the third on-state voltage climbs to its peak level.

[0012] Another aspect of this application provides a data erasure method for a non-volatile memory, wherein the non-volatile memory includes: a plurality of memory blocks, each memory block including a plurality of stacks electrically connected to each other, each stack including a plurality of memory cells and at least one dummy memory cell adjacent to an end of the stack, one end of at least one stack including a plurality of drains, and one end of at least another stack including a common source, the method comprising: applying a first on voltage to memory cells included in a first stack of the plurality of stacks to be erased; applying a holding voltage to dummy memory cells included in a second stack of the plurality of stacks to be erased; after applying the first on voltage and the holding voltage, applying a source erase voltage and a drain erase voltage to the common source and the drain, respectively; and releasing the holding voltage of the dummy memory cell during the period when the levels of the source erase voltage and the drain erase voltage rise to their peak levels.

[0013] In one embodiment of this application, the method further includes setting the memory cells included in the first stack to a floating state after the level of the first turn-on voltage rises to its peak level.

[0014] In one embodiment of this application, the method further includes: applying a first bias voltage to the memory cells included in the first stack after the level of the first turn-on voltage has climbed to its peak level.

[0015] In one embodiment of this application, the method further includes applying a ground voltage to the memory cells included in the second stack.

[0016] In one embodiment of this application, the second stack includes a top stack including a plurality of drain-select gates, and the method further includes: applying a second voltage less than the drain-erase voltage to at least one of the drain-select gates during the period when the levels of the source erase voltage and the drain erase voltage rise to their peak levels.

[0017] In one embodiment of this application, the first stack includes a top stack, the top stack including a drain-select gate, and the method further includes: applying a second on-state voltage to the drain-select gate while applying the first on-state voltage; and setting the drain-select gate to a floating state or applying a second bias voltage to the drain-select gate after the level of the second on-state voltage climbs to its peak level.

[0018] In one embodiment of this application, the first stack includes a bottom stack, the bottom stack including a source-select gate, and the method further includes: applying a third on-state voltage to the source-select gate while applying the first on-state voltage; and after the level of the third on-state voltage rises to its peak level, setting the source-select gate to a floating state or applying a third bias voltage to the source-select gate.

[0019] Another aspect of this application provides a non-volatile memory, comprising: a memory block including a plurality of stacks electrically connected to each other, each stack including a plurality of memory cells and at least one dummy memory cell adjacent to an end of the stack, one end of at least one stack including a plurality of drains, and one end of at least another stack including a common source; a plurality of word lines, each word line coupled to a memory cell in the same row; a plurality of dummy word lines, each dummy word line coupled to a dummy memory cell in the same row; bit lines coupled to each drain; and peripheral circuitry coupled to the word lines, dummy word lines, bit lines, and common source, and configured to: apply a first on-state voltage to a memory cell included in a first stack of the plurality of stacks to be erased; after applying the first on-state voltage, apply a source erase voltage and a drain erase voltage to the common source and the drain, respectively; and apply a first voltage to a dummy memory cell included in a second stack of the plurality of stacks to be erased while the levels of the source erase voltage and the drain erase voltage rise to their peak levels.

[0020] In one embodiment of this application, the peripheral circuit is further configured to set the memory cells included in the first stack to a floating state after the level of the first turn-on voltage rises to its peak level.

[0021] In one embodiment of this application, the peripheral circuit is further configured to apply a first bias voltage to the memory cells included in the first stack after the level of the first turn-on voltage has climbed to its peak level.

[0022] One aspect of this application provides another non-volatile memory, comprising: a memory block including a plurality of stacks electrically connected to each other, each stack including a plurality of memory cells and at least one dummy memory cell adjacent to an end of the stack, one end of at least one stack including a plurality of drains, and one end of at least another stack including a common source; a plurality of word lines, each word line coupled to memory cells in the same row; a plurality of dummy word lines, each dummy word line coupled to a dummy memory cell in the same row; bit lines coupled to each drain; and peripheral circuitry connected to the word lines and dummy word lines. The dummy memory cells are coupled to bit lines and a common source and configured to: apply a first on-state voltage to memory cells included in a first stack of the plurality of stacks to be erased; apply a holding voltage to dummy memory cells included in a second stack of the plurality of stacks to be erased; after applying the first on-state voltage and the holding voltage, apply a source erase voltage and a drain erase voltage to the common source and the drain, respectively; and release the holding voltage of the dummy memory cells while the levels of the source erase voltage and the drain erase voltage rise to their peak levels.

[0023] In one embodiment of this application, the peripheral circuit is further configured to set the memory cells included in the first stack to a floating state after the level of the first turn-on voltage rises to its peak level.

[0024] In one embodiment of this application, the peripheral circuit is further configured to apply a first bias voltage to the memory cells included in the first stack after the level of the first turn-on voltage has climbed to its peak level.

[0025] Another aspect of this application provides a memory system comprising: a non-volatile memory as described in any of the preceding claims, configured to store data; and a memory controller coupled to the non-volatile memory and configured to control the non-volatile memory.

[0026] In one embodiment of this application, the memory system includes a solid-state drive or a memory card. Attached Figure Description

[0027] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. In the drawings,

[0028] Figure 1 This is a block diagram of an exemplary system including a memory according to some embodiments of this application;

[0029] Figure 2 This is a schematic diagram of an exemplary memory card having memory according to some embodiments of this application;

[0030] Figure 3 This is a schematic diagram of an exemplary solid-state drive (SSD) with memory according to some embodiments of this application;

[0031] Figure 4 This is a schematic diagram of a non-volatile memory including a storage array and peripheral circuitry according to some embodiments of this application;

[0032] Figure 5 This is a partial schematic diagram of a storage array included in a non-volatile memory according to some embodiments of this application;

[0033] Figure 6 A partial equivalent circuit diagram of a storage block included in a non-volatile memory according to some embodiments of this application;

[0034] Figure 7 This is a schematic flowchart of a data erasure method for non-volatile memory according to some embodiments of this application;

[0035] Figures 8-11The following is a voltage waveform timing diagram for a non-volatile memory according to some embodiments of this application;

[0036] Figure 12 This is a comparison diagram of the channel potential during the erase operation of a data erasure method for non-volatile memory according to some embodiments of this application. Detailed Implementation

[0037] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this application and are not intended to limit the scope of this application in any way. Throughout the specification, the same reference numerals refer to the same elements.

[0038] Note that references to "one embodiment," "exemplary," "implementation," "example implementation," "some implementations," etc., in the specification indicate that the described implementation may include a specific feature, structure, or characteristic, but each implementation may not necessarily include that specific feature, structure, or characteristic. Furthermore, these phrases do not necessarily refer to the same implementation. Additionally, when a specific feature, structure, or characteristic is described in connection with an implementation, whether explicitly stated or not, implementing that feature, structure, or characteristic in conjunction with other implementations will be within the knowledge of those skilled in the art.

[0039] Generally, terms can be understood at least partly from their use in context. For example, depending at least partly on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a" or "described" can also be understood to convey either a singular or a plural usage, depending at least partly on the context.

[0040] It is readily understood that the meanings of “above,” “on top,” and “above” in this application should be interpreted in the broadest possible sense, such that “above” means not only “directly on something” but also includes “on something” with an intermediate feature or layer therebetween, and that “on top” or “above” means not only “above” or “above” something but also includes “above” or “above” something without an intermediate feature or layer therebetween (i.e., directly on something).

[0041] As used herein, the term "layer" can be a region of a homogeneous or non-homogeneous continuous structure, the thickness of which is less than the thickness of the continuous structure. For example, a layer can be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes at the top and bottom surfaces of a continuous structure. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, and may include one or more layers therein, and / or may have one or more layers on, above, and / or below it. A layer can include multiple sublayers.

[0042] The accompanying drawings in this application are for illustrative purposes only and are not strictly to scale. For ease of explanation, the thickness, dimensions, and shapes of the parts have been slightly adjusted. For example, the terms “approximately,” “about,” and similar terms used herein are used as expressions of approximation rather than expressions of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by those skilled in the art.

[0043] It should also be understood that the terms "comprising," "including," "having," "containing," and / or "comprising" as used in this specification indicate the presence of the stated features, elements, and / or components, but do not exclude the presence or addition of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to indicate "one or more embodiments of this application."

[0044] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0045] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this application are not limited to the order in which they are described, but can be performed in any order or in parallel. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0046] Figure 1A block diagram of an exemplary system 400 including memory according to some embodiments of this application is shown. System 400 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 1 As shown, system 400 may include a host 408 and a memory system 402 having one or more memories 404 and a memory controller 406. The host 408 may be a processor of an electronic device, such as a central processing unit (CPU), or a system-on-a-chip (SoC), such as an application processor (AP). The host 408 may be configured to send or receive data stored in the memory 404.

[0047] According to some embodiments, memory controller 406 is coupled to memory 404 and host 408 and is configured to control memory 404, for example, to control peripheral circuitry 101 (described below) to perform data erasure, data write, or data read operations. Memory controller 406 can manage data stored in memory 404 and communicate with host 408. In some embodiments, memory controller 406 is designed to operate in low duty cycle environments, such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices such as personal computers, digital cameras, and mobile phones. In some embodiments, memory controller 406 is designed to operate in high duty cycle environments, such as SSDs or embedded multimedia cards (eMMCs) used for data storage in mobile devices (such as smartphones, tablets, laptops, etc.) and enterprise storage arrays. Memory controller 406 can be configured to control operations of memory 404, such as read, erase, and program operations. The memory controller 406 can also be configured to manage various functions related to data stored or to be stored in the memory 404, including bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 406 is also configured to process error correction codes (ECC) for data read from or written to the memory 404. The memory controller 406 may also perform any other suitable function, such as formatting the memory 404. The memory controller 406 can communicate with external devices (e.g., host 408) according to specific communication protocols. For example, the memory controller 406 can communicate with external devices via at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), High Speed ​​PCI (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Mini-Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, etc.

[0048] The memory controller 406 and one or more memories 404 can be integrated into various types of storage devices, for example, included in the same package, such as a Universal Flash Memory (UFS) package or an eMMC package. That is, the memory system 402 can be implemented as and packaged into different types of end electronic products. Figure 2In one example shown, the memory controller 406 and a single memory 404 can be integrated into the memory card 502. The memory card 502 can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a Memory Stick, a Multimedia Card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 502 may further include a connection between the memory card 502 and a host computer (e.g., Figure 1 The host (408) is electrically coupled to the memory card connector 504. In such a case... Figure 3 In another example shown, the memory controller 406 and multiple memories 404 can be integrated into the SSD 506. The SSD 506 may further include interfaces for connecting the SSD 506 to a host computer (e.g., Figure 1 The host 408 is electrically coupled to the SSD connector 508. In some embodiments, the storage capacity and / or operating speed of the SSD 506 is greater than the storage capacity and / or operating speed of the memory card 502.

[0049] Figure 4 A block diagram of a non-volatile memory 100 according to some embodiments of this application is shown. The non-volatile memory 100 can be used as... Figure 1 An example of the memory 404 shown, such as Figure 4 As shown, the non-volatile memory 100 includes a memory array 102 and peripheral circuitry 101 coupled together. In some embodiments, the memory array 102 and peripheral circuitry 101 may be arranged on the same chip. In other embodiments, the memory array 102 may be arranged on an array chip, and the peripheral circuitry 101 may be arranged on a different chip (e.g., implemented using complementary metal-oxide-semiconductor (CMOS) technology, and referred to as a CMOS chip). The array chip and the CMOS chip may be electrically coupled together via processes such as bonding. In some embodiments, the non-volatile memory 100 is an integrated circuit (IC) package that encapsulates one or more array chips and CMOS chips.

[0050] Optionally, the non-volatile memory 100 may be configured to store data in the memory array 102 and perform operations in response to received commands (CMDs). In some embodiments, the non-volatile memory 100 may receive write commands, read commands, erase commands, etc., and may perform operations accordingly.

[0051] In one implementation, the non-volatile memory 100 receives an erase command with an address, and then the non-volatile memory 100 resets one or more memory cells at that address to an unprogrammed state (or erased state), such as "1" for a NAND memory cell.

[0052] Typically, storage array 102 may include one or more storage planes 160, and each storage plane 160 may include multiple storage blocks (e.g., Figure 4 Blocks 1 through N are shown. Each storage block may also include multiple stacks that are stacked vertically (e.g., Figure 4 The diagram shows stacks 1 to M included in block-1. In some examples, concurrent operations may occur at different storage planes 160. In some implementations, each of stacks 1 to M is the smallest unit for performing an erase operation. It should be understood that... Figure 4 Blocks 2 to 3 shown may have multiple stacks similar to block 1, and this application does not limit this.

[0053] In some embodiments, the storage array 102 may be, for example, a flash memory array, and may be implemented using 3D NAND flash memory technology. In some embodiments, the peripheral circuitry 101 includes a row decoder 110, a page buffer circuitry 120, a data input / output (I / O) circuitry 130, a voltage generator 140, and a control circuitry 150 coupled together. The row decoder 110 may receive an address referred to as a row address (R-ADDR), generate word line (WL) signals and select line signals (such as drain select line (DSL) signals, source select line (SSL) signals, etc.) based on the row address, and provide the WL signals and select line signals to the storage array 102. Furthermore, during an erase operation, the row decoder 110 provided in this application may provide appropriate WL signals and select signals.

[0054] Page buffer circuitry 120 is coupled to the bit line (BL) of memory array 102 and is configured to buffer data during read and write operations. Data I / O circuitry 130 is coupled to page buffer circuitry 120 via data line DL. In one example (e.g., during a write operation), data I / O circuitry 130 is configured to receive data from external circuitry of non-volatile memory 100 and provide the received data to memory array 102 via page buffer circuitry 120.

[0055] Voltage generator 140 is configured to generate appropriate voltages for proper operation of non-volatile memory 100. In some embodiments of this application, voltage generator 140 may generate various erase voltages, source voltages, various on-state voltages, various bias voltages, etc., suitable for erase operations. For example, during an erase operation, a first on-state voltage is provided to row decoder 110 to drive word lines. In some examples, during an erase operation, voltage generator 140 may provide an erase voltage to page buffer circuitry 120 to drive bit lines (BLs). In some examples, the source voltage is provided as an array common source (ACS) voltage to the source terminals of memory cell array 102.

[0056] Control circuitry 150 is configured to receive commands (CMD) and addresses (ADDR), and based on these commands and addresses, to provide control signals to circuits such as row decoder 110, page buffer circuitry 120, data I / O circuitry 130, and voltage generator 140. For example, control circuitry 150 may generate row address R-ADDR and column address C-ADDR based on address ADDR, and provide row address R-ADDR to row decoder 110 and column address to data I / O circuitry 130. In another embodiment, control circuitry 150 may control voltage generator 140 to generate an appropriate voltage based on the received CMD. Control circuitry 150 may coordinate with other circuits to provide signals to memory array 102 at the appropriate time and with the appropriate voltage.

[0057] A portion of the control circuitry 150 can be configured to generate appropriate control signals to control other circuitry to provide appropriate signals to the memory array 102 for an erase operation using a stacked erase mechanism and a gate-induced drain leakage (GIDL) erase mechanism. Signals with appropriate timing and voltage for the memory array 102 can be used for data erase operations on non-volatile memory using the stacked erase mechanism and the GIDL erase mechanism.

[0058] like Figure 5 As shown, in some examples, multiple stacked bodies (e.g., Figure 4The stacks 1 to M included in block-1 shown may include three stacks, such as a top stack 452, a middle stack 454, and a bottom stack 450. Optionally, the bottom stack 450 may be located on the semiconductor layer 401. Exemplarily, each of the plurality of stacks (e.g., top stack 452, middle stack 454, and bottom stack 450) includes alternating gate conductive layers 415 and dielectric layers 417, which may be alternately stacked on the semiconductor layer 402. Optionally, the gate conductive layer 415 may include conductive materials such as tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. Optionally, the semiconductor layer 401 may include silicon (e.g., monocrystalline silicon, polycrystalline silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0059] Continue to refer to Figure 5 Block 1 may further include a NAND flash memory string 212, which includes a channel structure 412 extending vertically or substantially vertically through the gate conductive layer 415 and the dielectric layer 417. In some embodiments, the channel structure 412 includes a barrier layer 422, a memory layer 424, a tunneling layer 426, and a channel layer 420 disposed sequentially from the outside to the inside. Optionally, the channel layer 420 may include polysilicon. The tunneling layer 426 may include silicon oxide, silicon oxynitride, or any combination thereof. The memory layer 424 may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer 422 may include silicon oxide, silicon oxynitride, a high dielectric constant (high k) dielectric, or any combination thereof.

[0060] Continue to refer to Figure 5 In some examples where the storage capacity is increased by increasing the number of gate conductor layer 415 and dielectric layer 417, the problem of reduced current flowing through channel layer 420 due to the increased height becomes particularly prominent. This can typically be addressed by providing conductive plugs (e.g., conductive plugs 460 and 470) electrically connected to the channel layer (e.g., channel layer 420) between stack bodies (e.g., between top stack body 452 and middle stack body 454, and between middle stack body 454 and bottom stack body 450). Alternatively, conductive plugs 460 and 470 can be heavily N-type doped, allowing them to act as “electron banks” during erase operations, thereby increasing the current flowing through channel layer 420 and improving erase performance.

[0061] like Figure 6As shown, in some embodiments, the NAND memory string 212 also includes an electrode plug 416 located at its drain end, which may serve as part of the drain of the memory string 212-2.

[0062] Back Figure 5 In some examples, the semiconductor layer 401 can be heavily N-type doped to form an N-doped well region (NW), and the channel layer 420 can directly contact the NW, so the NW can serve as an ACS.

[0063] Optionally, during the erase operation, some gate conductive layers 415 located at the ends of the top stack 452 away from the semiconductor layer 401 can serve as drain select gates (DSGs), and the DSG 334 can be connected to the DSL 334 ( Figure 6 Coupled with the bottom stack 450, some gate conductor layers 415 located near the semiconductor layer 401 can serve as source select gates (SSGs), which can be coupled with SSL332 ( Figure 6 )coupling.

[0064] In some examples, some gate conductor layers 415 located between the DSG and SSG can serve as control gates 333. Figure 6 A memory cell (e.g.) is formed at the intersection of the control gate 333 and the channel structure 412. Figure 6 The storage cells 340-2, 340-3 and 340-1 shown can have their control gates brought out via their respective electrically connected WLs to perform operations such as reading and erasing on the storage cells.

[0065] Continue to refer to Figure 5 In some examples of multi-stack fabrication processes, due to the effects of deep-hole etching and / or multiple stack connection processes, some gate conductor layers at the junctions of adjacent stacks (e.g., adjacent top stack 452 and middle stack 454, adjacent middle stack 454 and bottom stack 450), such as gate conductor layer 415-1 connected to conductive plugs 460 and 470, are prone to varying degrees of process damage. This damage can affect the dummy memory cells (e.g., controlled by these damaged gate conductor layers 415-1). Figure 6 The operations performed by the dummy memory cell 343 shown may affect the reliability of the non-volatile memory 100. Alternatively, the dummy memory cell 343 controlled by the dummy gate layer 415-1 of the central stack 454 may be referred to as an inter-level dummy memory cell (IDP-DMY).

[0066] Refer again Figure 5In some examples, dummy gate layers 415-2 and 415-3 for process and electrical buffering may also be provided near the top and bottom ends of the respective stacks in the top stack 452 and bottom stack 450. Optionally, the dummy gate layers 415-2 near the top of the respective stacks in the top stack 452 and bottom stack 450 may be referred to as top dummy gate layers. In the top stack 452, these dummy gate layers 415-2 may, for example, be located between the drain select gate (DSG) and the control gate (333). Optionally, dummy memory cells 341 ( Figure 6 This can be called a top-level virtual memory unit (DMT).

[0067] In some examples, the dummy gate layer 415-3 near the bottom of the respective stack in the top stack 452 and the bottom stack 450 can be referred to as the bottom dummy gate layer, and the dummy memory cell 342 controlled by it ( Figure 6 This can be referred to as a bottom-level virtual memory unit (DMB).

[0068] like Figure 6 As shown, in some examples, NAND storage string 212 also includes multiple storage strings located in each stack, such as those located in the top stack 452. Figure 5 Storage string 212-2 in the middle stack 454 () Figure 5 ) stores string 212-3 and is located in the bottom stack 450 ( Figure 5 Storage string 212-1 in ). Optionally, conductive plug 460 can be used to electrically connect storage strings 212-2 and 212-3, and conductive plug 470 can be used to electrically connect storage strings 212-3 and 212-1.

[0069] Continue to refer to Figure 6 As described above, storage strings 212-2, 212-3 and 212-1 may each include a virtual storage unit 342, an interlayer virtual storage unit 343 and a virtual storage unit 341 that are electrically connected to conductive plugs 460 and 470, respectively.

[0070] Optionally, one end of the storage string 212-2 may include at least one drain select transistor 334-T, which may be controlled by a DSG. The drain terminal of the drain select transistor 334-T may be connected to a bit line 341, and a drain erase voltage may be applied via the bit line 341 during an erase operation.

[0071] Optionally, one end of the plurality of memory strings 212-1 may include at least one source select transistor 332-T, and the source terminals of the plurality of source select transistors 332-T may be connected to ACS 464.

[0072] In the non-volatile memory 100, the memory cells in each row of each stack (e.g., memory cells in the same row as memory cell 340) can be connected to the same WL 335, and multiple memory strings in each column (e.g., Figure 6 The storage strings 212-1, 212-2, and 212-3 shown can be connected to the same BL 341. Each WL can correspond to one page, and multiple pages form a storage block (e.g., Figure 4 (Blocks 1 to n are shown). Furthermore, in a non-volatile memory 100 having multiple stacks, each stack can be processed individually for efficient reading, writing, and erasing; for example, in a three-dimensional non-volatile memory, each stack can be erased independently of the other stacks. Additionally, read and write operations can be performed on memory pages comprising memory cells sharing the same WL.

[0073] It should be noted that the description of the non-volatile memory 100 including three stacks above is only an example. In other examples, the non-volatile memory 100 may include two or more stacks. The physical structure and circuit structure of these stacks may be similar to the example of three stacks above, and will not be described in detail here.

[0074] Although an exemplary structure of the non-volatile memory 100 has been described herein, it will be understood that one or more features may be omitted, substituted, or added from the structure of the non-volatile memory 100. Furthermore, the layers and materials described are merely illustrative.

[0075] Figure 7 A data erasure method 300 for the above-described non-volatile memory 100 according to some embodiments of this application is shown below, which will be described in conjunction with... Figures 5-12 Detailed instructions for erasing method 300. (Example) Figure 7 As shown, the erasure method 300 begins with operation S301, wherein a first on-state voltage may be applied to the memory cells included in the first stack of a plurality of stacks to be erased.

[0076] In some examples, among the multiple stacks to be erased, the stack currently to be erased may be referred to as the second stack, and the storage cells included in the second stack may be regarded as selected storage cells. During the erasure operation on the second stack, the erasure operation on the remaining stacks is not desired, and the remaining stacks may be referred to as the first stack, and the storage cells included in the first stack may be regarded as unselected storage cells. By erasing each stack in turn among the multiple stacks to be erased, a hierarchical erasure operation of the entire storage block (e.g., storage block-1) can be achieved.

[0077] Taking the erasure operation performed on the middle stack 454 as an example, such as Figure 8 As shown, at time t0, the first on-state voltage V can be applied to the unselected memory cells 340-2 and 340-1 of the top stack 452 and bottom stack 450 via WL addressing and the WL signal. _b V _b It can be greater than the threshold voltage V of unselected memory cell 340-2 and unselected memory cell 340-1. _th For example, the first turn-on voltage V _b For example, it can be 5V to 7V, the threshold voltage V for unselected memory cells 340-2 and 340-1. _th It can be 2V to 3V. Optionally, when a first turn-on voltage V is applied... _b Simultaneously, a second on-state voltage can be applied to the DSG included in the top stack 452, for example, to the DSL 334 coupled to the DSG. Figure 6 Apply a second turn-on voltage, the second turn-on voltage V _b The value can be greater than the threshold voltage of the drain-select transistor 334-T, and the value of the second conduction voltage is, for example, V. _b Optionally, when a first turn-on voltage V is applied... _b Simultaneously, a third on-state voltage can be applied to the SSG included in the bottom stack 450, for example, to the SSL 332 coupled to the SSG. Figure 6 Apply the third on-state voltage V _b Third conduction voltage V _b The value can be greater than the threshold voltage of the source selection transistor 332-T, and the value of the third conduction voltage is, for example, V. _b Each of the above-mentioned turn-on voltages can turn on the corresponding memory cell or selection transistor at time t1, thereby enabling the channels of unselected memory cell 340-2 and unselected memory cell 340-1 to be turned on, for example, causing the channels to be inverted (e.g., inverted to N-type channels).

[0078] like Figure 7 As shown, the erasure method 300 continues to operation S302, wherein, after applying the first turn-on voltage, a source erase voltage and a drain erase voltage may be applied to the common source and drain, respectively. Figure 8 As shown, in some examples, after channel inversion of unselected memory cells 340-2 and 340-1, for example at time t1, it can be achieved via ACS 464 ( Figure 6 ) and via BL 341 ( Figure 6 Apply source erase voltage V respectively _er1 and drain erase voltage V _er2 V _er1 and V _er2 The values ​​can be the same, for example, both being V. _erIn some examples, V _er For example, it can be 16V to 20V. The levels (e.g., positive potentials) of ACS 464 and BL341 can be conducted along the channel to the central stack 454.

[0079] Continue to refer to Figure 8 In some examples, at time t1, the aforementioned unselected memory cells 340-2, 340-1, DSG, and SSG can be set to a floating state. In V _er During the ramp-up to its peak voltage, the WL, DSL, and SSL of these unselected memory cells can couple out voltages higher than V. _er The voltage. Optionally, during the level conduction of ACS 464 and BL341, the levels on unselected memory cells 340-2, unselected memory cells 340-1, DSG, and SSG are always higher than the levels on ACS 464 and BL341, so that unselected memory cells 340-2 and unselected memory cells 340-1 on the top stack 452 and the bottom stack 450 will not be erased.

[0080] like Figure 9 As shown, in other examples, after the channels of unselected memory cells 340-2 and 340-1 are turned on, an additional first bias voltage may be applied to the unselected memory cells 340-2 and 340-1. The value of the first bias voltage may be, for example, V. _er Optionally, a second bias voltage can also be applied to the DSG via the DSL, the value of which may be, for example, V. _er Optionally, a third bias voltage can also be applied to the SSG via SSL, the value of which may be, for example, V. _er During the level conduction of ACS 464 and BL341, the levels on unselected memory cells 340-2, 340-1, DSG, and SSG are always higher than the levels on ACS 464 and BL341, so that unselected memory cells 340-2 and 340-1 on the top stack 452 and bottom stack 450 will not be erased.

[0081] like Figure 10 and Figure 11 As shown, in some examples, during the channel conduction of the levels of ACS 464 and BL 341, interlayer dummy memory cells 343 included in the middle stack 454 can be used. Figure 6 The corresponding WL _IDP Apply hold release voltage V _hold-releaseOptionally, during the conduction phase from the levels of ACS464 and BL341 to the conductive plugs 460 and 470, a holding voltage V can be applied to the interlayer dummy memory cell 343. _hold Maintain voltage V _hold For example, it can be 0V, so that the channel controlled by the dummy memory cell 343 is always at a low level before the levels of ACS 464 and BL 341 are conducted to conductive plugs 460 and 470.

[0082] Continue to refer to Figure 7 The erasure method 300 continues to operation S303, wherein a first voltage may be applied to the dummy memory cell included in the second stack of the plurality of stacks to be erased during the period when the levels of the source erasure voltage and the drain erasure voltage rise to their peak levels.

[0083] like Figure 8 and Figure 9 As shown, in some examples, the levels in ACS and BL can climb to their peak levels V. _er During this period, for example, when the level is conducted to the central stack 454, a first voltage for inducing GIDL can be applied to the dummy storage cell 343. The first voltage is, for example, an induced voltage V. _gidl Induced voltage V _gidl The value can be, for example, 10V-12V, to generate GIDL current through the memory strings 212-3 included in the central stack 454, thereby enabling GIDL erasure of the central stack 454.

[0084] like Figure 10 and Figure 11 As shown, in WL _IDP Apply holding voltage V _hold In some examples, the levels in ACS and BL can climb to their peak levels V. _er During this period, for example, at time t2 when the voltage level is conducted to conductive plugs 460 and 470, the holding voltage V applied by the dummy memory cell 343 is released. _hold This enables the generation of GILD current in storage string 212-3, achieving GILD erasure between stacks.

[0085] like Figure 10 and Figure 11 As shown, in some examples, the voltage level conducted via ACS to conductive plugs 460 and 470 via BL is, for example, 8V. As described above, the channel potential of the memory strings 212-3 included in the central stack 454 can be controlled to 0V when the holding voltage V applied by the dummy memory cell 343 is... _hold After release, as the levels of ACS and BL rise to their peak levels V _erDuring this period, if the peak level is, for example, 20V, the channel potential of the memory string 212-3 will rise to V. _hold-release V _hold-release For example, 12V. Therefore, V _hold-release Conductive plugs 460 and 470 and channel layer 420 can be heavily N-type doped. Figure 5 Electron-hole pairs are induced at the interface between the two layers, causing holes to travel along the channel layer 420 to each memory cell 340-3. Figure 6 The electrons move, while the electrons return to conductive plugs 460 and 470.

[0086] In some examples, WL _IDP The coupled voltage can rise to its peak level before the levels of ACS and BL.

[0087] Continue to refer to Figure 11 The levels of ACS and BL rise to their peak levels V. _er Subsequently, the channel potential of memory string 212-2 and memory string 212-2 included in the top stack 452 and bottom stack 450 is raised to V. _b +V _er The erase voltage V applied by ACS and BL _er A comparison chart of the channel potentials of memory strings 212-1 and 212-2 included in the top stack 452 and bottom stack 450, and the channel potential of memory string 212-3 included in the middle stack 454 over time can be referenced. Figure 12 .

[0088] In some examples of performing the above-described erasure operation, the selected memory cells 340-3 included in the central stack 454 may always remain grounded.

[0089] Some embodiments of this application apply a voltage smaller than the source erase voltage and the drain erase voltage V to the dummy storage cells 343 included in the central stack 454. _er V _hold-release Or the first voltage V _gidl On the one hand, it can realize a dual erasure mechanism of stack body erasure and GIDL erasure. On the other hand, it can avoid erasing the dummy memory 343 while erasing the selected memory cell 340-3 in the middle stack body 454, thereby improving the reliability of the non-volatile memory 100.

[0090] like Figure 9 As shown, the erasure operation can be completed at time t3. After time t3, it is applied to ACS, BL, and each WL, DSL, SSL, and WL. _IDPThe operating voltage can be returned to the corresponding reference voltage. In some examples, the state of each memory cell after erasure can also be verified after the erasure operation is completed. For example, it can be verified whether the threshold voltage of each memory cell after erasure reaches the target threshold voltage.

[0091] In some examples where the second stack includes the top stack 452, the levels of ACS and BL can climb to their peak levels V. _er During this period, for example, when the level is conducted to the top stack 452, a first voltage for inducing GIDL can be applied to the dummy storage cell 342 included in the top stack 452. The value of the first voltage can be, for example, 10V-12V, so as to generate GIDL current through the storage string 212-3 included in the top stack 452, thereby achieving GIDL erasure of the top stack 452.

[0092] Optionally, in some examples where the second stack includes the top stack 452, a second voltage for inducing GIDL may also be applied to the DSL 334 corresponding to the DSG when the level rise of ACS and BL is conducted to the top stack 452. This second voltage may work together with the first voltage applied to the dummy storage cell 342 to generate GIDL current.

[0093] In other examples where the second stack includes the top stack 452, a hold-release voltage V, operating similarly to that of the dummy storage cell 343, may be applied to the DSL334 corresponding to the DSG in the dummy storage cell 342 and the DSG when the level rise of ACS and BL is conducted to the top stack 452. _hold-release .

[0094] In some examples where the second stack includes a bottom stack 450, a similar erasure operation as described in the examples where the second stack includes a middle stack 454 or a top stack 452 can be used, which will not be elaborated upon in this application.

[0095] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of this application. It should be understood that the above are merely specific embodiments of this application and are not intended to limit this application. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A data erasing method of a nonvolatile memory, wherein, The non-volatile memory includes: a plurality of memory blocks, each memory block including a plurality of stacks electrically connected to each other, each stack including a plurality of memory cells and at least one dummy memory cell adjacent to an end of the stack, at least one end of the stack having a plurality of drains, and at least one end of another stack having a common source, characterized in that the method includes: A first on-state voltage is applied to the memory cells included in the first stack of the plurality of stacks to be erased; After applying the first turn-on voltage, a source erase voltage and a drain erase voltage are applied to the common source and the drain, respectively; and During the rise of the source erase voltage and the drain erase voltage to their peak levels, a first voltage is applied to the dummy memory cell included in the second stack of the plurality of stacks to be erased to induce gate-induced drain leakage current.

2. The method according to claim 1, further comprising: After the level of the first turn-on voltage rises to its peak level, the memory cells included in the first stack are set to a floating state.

3. The method according to claim 1, further comprising: After the level of the first turn-on voltage rises to its peak level, a first bias voltage is applied to the memory cells included in the first stack.

4. The method according to claim 1, further comprising: A ground voltage is applied to the storage cells included in the second stack.

5. The method of claim 1, wherein, The second stack includes a top stack, the top stack including a plurality of drain-select gates, and the method further includes: During the period when the source erase voltage and the drain erase voltage levels rise to their peak levels, a second voltage less than the drain erase voltage is applied to at least one of the drain select gates.

6. The method of claim 1, wherein, The first stack includes a top stack, the top stack including a drain-select gate, and the method further includes: While applying the first on-state voltage, a second on-state voltage is applied to the drain-select gate; and After the level of the second turn-on voltage rises to its peak level, the drain-select gate is set to a floating state or a second bias voltage is applied to the drain-select gate.

7. The method of claim 1, wherein, The first stack includes a bottom stack, the bottom stack including a source-select gate, and the method further includes: While applying the first on-state voltage, a third on-state voltage is applied to the source-select gate; and After the level of the third turn-on voltage rises to its peak level, the source select gate is set to a floating state or a third bias voltage is applied to the source select gate.

8. A data erasing method for a nonvolatile memory, wherein, The non-volatile memory comprises: a plurality of memory blocks, each memory block comprising a plurality of stacks electrically connected to each other, each stack comprising a plurality of memory cells and at least one dummy memory cell adjacent to an end of the stack, at least one end of at least one stack comprising a plurality of drains, and at least one end of another stack comprising a common source, characterized in that the method comprises: A first on-state voltage is applied to the memory cells included in the first stack of the plurality of stacks to be erased; A holding voltage is applied to the dummy memory cells included in the second stack of the plurality of stacks to be erased; After applying the first on-voltage and the holding voltage, a source erase voltage and a drain erase voltage are applied to the common source and the drain, respectively; and During the period when the source erase voltage and the drain erase voltage levels rise to their peak levels, the holding voltage of the dummy memory cell is released.

9. The method according to claim 8, further comprising: After the level of the first turn-on voltage rises to its peak level, the memory cells included in the first stack are set to a floating state.

10. The method of claim 8, further comprising: After the level of the first turn-on voltage rises to its peak level, a first bias voltage is applied to the memory cells included in the first stack.

11. The method of claim 8, further comprising: A ground voltage is applied to the storage cells included in the second stack.

12. The method of claim 8, wherein, The second stack includes a top stack, the top stack including a plurality of drain-select gates, and the method further includes: During the period when the source erase voltage and the drain erase voltage levels rise to their peak levels, a second voltage less than the drain erase voltage is applied to at least one of the drain select gates.

13. The method of claim 8, wherein, The first stack includes a top stack, the top stack including a drain-select gate, and the method further includes: While applying the first on-state voltage, a second on-state voltage is applied to the drain-select gate; and After the level of the second turn-on voltage rises to its peak level, the drain-select gate is set to a floating state or a second bias voltage is applied to the drain-select gate.

14. The method of claim 8, wherein, The first stack includes a bottom stack, the bottom stack including a source-select gate, and the method further includes: While applying the first on-state voltage, a third on-state voltage is applied to the source-select gate; and After the level of the third turn-on voltage rises to its peak level, the source select gate is either set to a floating state or a third bias voltage is applied to the source select gate.

15. A non-volatile memory, comprising: A memory block includes multiple stacks electrically connected to each other, each stack including multiple memory cells and at least one dummy memory cell adjacent to one end of the stack, at least one end of the stack including multiple drains, and at least one end of another stack including a common source. Multiple word lines, each word line coupled to a memory cell in the same row; Multiple dummy word lines, each dummy word line coupled to a dummy memory cell in the same row; Bit lines are coupled to each drain electrode; as well as The peripheral circuitry, coupled to the word lines, dummy word lines, bit lines, and common-source circuitry, is configured as follows: A first on-state voltage is applied to the memory cells included in the first stack of the plurality of stacks to be erased; After applying the first turn-on voltage, a source erase voltage and a drain erase voltage are applied to the common source and the drain, respectively. as well as During the rise of the source erase voltage and the drain erase voltage to their peak levels, a first voltage is applied to the dummy memory cell included in the second stack of the plurality of stacks to be erased to induce gate-induced drain leakage current.

16. The nonvolatile memory of claim 15, wherein, The peripheral circuit is also configured as follows: After the level of the first turn-on voltage rises to its peak level, the memory cells included in the first stack are set to a floating state.

17. The nonvolatile memory of claim 15, wherein, The peripheral circuit is also configured as follows: After the level of the first turn-on voltage rises to its peak level, a first bias voltage is applied to the memory cells included in the first stack.

18. A non-volatile memory, comprising: A memory block includes multiple stacks electrically connected to each other, each stack including multiple memory cells and at least one dummy memory cell adjacent to one end of the stack, at least one end of the stack including multiple drains, and at least one end of another stack including a common source. Multiple word lines, each word line coupled to a memory cell in the same row; Multiple dummy word lines, each dummy word line coupled to a dummy memory cell in the same row; Bit lines are coupled to each drain electrode; as well as The peripheral circuitry, coupled to the word lines, dummy word lines, bit lines, and common-source circuitry, is configured as follows: A first on-state voltage is applied to the memory cells included in the first stack of the plurality of stacks to be erased; A holding voltage is applied to the dummy memory cells included in the second stack of the plurality of stacks to be erased; After applying the first turn-on voltage and the holding voltage, a source erase voltage and a drain erase voltage are applied to the common source and the drain, respectively. as well as During the period when the source erase voltage and the drain erase voltage levels rise to their peak levels, the holding voltage of the dummy memory cell is released.

19. The nonvolatile memory of claim 18, wherein, The peripheral circuit is also configured as follows: After the level of the first turn-on voltage rises to its peak level, the memory cells included in the first stack are set to a floating state.

20. The nonvolatile memory of claim 18, wherein, The peripheral circuit is also configured as follows: After the level of the first turn-on voltage rises to its peak level, a first bias voltage is applied to the memory cells included in the first stack.

21. A memory system, comprising: The non-volatile memory as described in any one of claims 15-20 is configured to store data; as well as A memory controller is coupled to the non-volatile memory and configured to control the non-volatile memory.

22. The memory system of claim 21, comprising: Solid-state drive or memory card.

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