Method of forming a pattern

Abstract

The application relates to the field of semiconductor manufacturing, in particular to a pattern forming method, which comprises the following steps: sequentially forming a target layer, a transfer layer and a first guide pattern on a semiconductor substrate; using a directional self-assembly process to form a first etching pattern arranged in a horizontal direction or a vertical direction on the first guide pattern; taking the first etching pattern as a mask to etch the transfer layer to form a first transfer pattern; forming a second transfer pattern which is perpendicular to the first transfer pattern; and taking the first transfer pattern and the second transfer pattern as masks to etch the target layer to form a target pattern. The embodiment of the application combines DSA, PTD and NTD technologies and applies them to the image forming process, so that the formed image size is smaller, the process steps are reduced, and the process efficiency is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor manufacturing, and in particular to a method for forming a pattern. BACKGROUND

[0002] With the target pattern on the semiconductor memory becoming smaller and smaller, EUV lithography technology and spacer assisted pattern (SPACER ASSISTED PATTERNING) technology are increasingly applied to the field of semiconductor device manufacturing, but considering the equipment price and process immaturity of EUV lithography technology, spacer assisted self-aligned double pattern (SADP) and quadruple pattern technology (QUADRUPLE PATTERNING) are generally used. Specifically, the SADP process generally includes the steps of lithography-etch-spacer deposition-mandrel removal-etch (LITHO-ETCH-SPACER DEPO-MANDREL REMOVAL-ETCH), which can make smaller patterns on the wafer. With further reduction of pattern size, double pattern has been unable to meet the demand, and quadruple pattern technology (QUAD PATTERNING) has emerged, but its manufacturing process is more difficult. SUMMARY

[0003] The present application at least partially solves the above technical problems in the related art. To this end, the present application provides a method for forming a pattern to manufacture a smaller pattern.

[0004] To achieve the above-mentioned purpose, the first aspect of the present application provides a method for forming a pattern, comprising the following steps:

[0005] forming a target layer, a transfer layer and a first guide pattern on a semiconductor substrate in sequence;

[0006] forming a first etching pattern arranged in a horizontal direction or a vertical direction on the first guide pattern using a directed self-assembly process, and etching the transfer layer to form a first transfer pattern using the first etching pattern as a mask;

[0007] forming a second transfer pattern intersecting perpendicularly with the first transfer pattern;

[0008] etching the target layer to form a target pattern using the first transfer pattern and the second transfer pattern as a mask. BRIEF DESCRIPTION OF DRAWINGS

[0009] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0010] Figure 1 This diagram shows a structure after a first guiding pattern has been deposited on a target layer of a semiconductor substrate;

[0011] Figure 2 It shows in Figure 1 A schematic diagram of the structure after the deposition of a directional self-assembled material layer;

[0012] Figure 3 It shows in Figure 2 A schematic diagram of the structure after removing unwanted linear patterns;

[0013] Figure 4 It shows in Figure 3 A schematic diagram of the structure after a first transfer pattern and a second transfer pattern are formed;

[0014] Figure 5 It shows in Figure 4 Based on this, a structural schematic diagram is formed after the target pattern is created;

[0015] Figure 6 It shows in Figure 3 A schematic diagram of the structure after another type of first transfer pattern and second transfer pattern are formed;

[0016] Figure 7 It shows in Figure 6 Based on this, a structural schematic diagram is formed after the target pattern is created. Detailed Implementation

[0017] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0018] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0019] In the context of this disclosure, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0020] Embodiments of this application provide a method for forming a pattern, specifically including the following steps:

[0021] like Figure 1 As shown, a silicon nitride target layer and a silicon oxide transfer layer 10 are formed on a semiconductor substrate using the existing sidewall-assisted self-aligned double patterning (SADP) process. Then, a first guide pattern 11 is formed on the transfer layer 10 using positive tone development (PTD) technology. Specifically, the first guide pattern 11 is arranged along the horizontal direction. The first guide pattern 11 includes pinning stripes 110 and neutral stripes 111, which are spaced apart. The width of the pinning stripe 110 is 30 nm, and the width of the neutral stripe 111 is 90 nm.

[0022] like Figure 2 As shown, a directional self-assembly of block copolymer lithography (DSA) layer is formed on the first guiding pattern 11. After heating, the directional self-assembly of block copolymer lithography layer self-assembles to form a repeating block copolymer pattern 12. Specifically, the block copolymer pattern 12 includes a number of parallel linear patterns, each with a width of 30 nm.

[0023] like Figure 3 As shown, unwanted linear patterns are removed to form a first etched pattern 120 arranged in the horizontal direction. The retained linear patterns have gaps between them, wherein the width of the gap is 30 nm.

[0024] Next, using the first etched pattern 120 as a mask, the transfer layer 10 (IMAGING ETCH) is etched to form the first transfer pattern 13 arranged in a horizontal square, and the first etched pattern 120 and the first guide pattern 11 are removed.

[0025] Next, as Figure 4As shown, in the immersion lithography process (ArFIMM), negative tone development (NTD) is used to form a second transfer pattern 14 that is perpendicular to the first transfer pattern 13. The second transfer pattern 14 includes a rectangular pattern, wherein at least one rectangular pattern has a length of 30 nm and a width of 90 nm.

[0026] Next, as Figure 5 As shown, using the first transfer pattern 13 and the second transfer pattern 14 as masks, the silicon nitride target layer is selectively etched to form the target pattern 15. Finally, the photoresist and the first transfer pattern 13 and the second transfer pattern 14 are removed to obtain the desired result. Figure 5 The target pattern 15 is shown.

[0027] It is worth mentioning that the gap of the target pattern 15 is less than 40 nm, and preferably, the gap of the target pattern 15 is less than 30 nm.

[0028] It should be noted that the method for forming the second transfer pattern 14 is not limited to the steps described above, and may also include the following steps: forming the second guide pattern using positive development technology (PTD), and forming the second transfer pattern 14 using an orientation self-assembly process and a negative development technology. The second guide pattern and orientation assembly process in this step can refer to the aforementioned steps, such as... Figures 6-7 As shown, the target pattern 15 formed by this method may include several square type gaps, wherein the length and width of the square gaps are 30 nm.

[0029] Compared with the prior art, the embodiments of this application combine DSA, PTD and NTD technologies in the image formation process, resulting in smaller image size, fewer process steps and improved process efficiency.

[0030] The image generated in this embodiment can be applied to volatile memory devices such as DRAM devices and SRAM devices, or non-volatile memory devices such as Flash devices, PRAM devices, MRAM devices, and RRAM devices.

[0031] Furthermore, the aforementioned semiconductor device can be used in various electronic devices, specifically smartphones, computers, tablets, wearable smart devices, artificial intelligence devices, power banks, etc.

[0032] In the above description, the technical details of the patterning, etching, etc. of each layer are not described in detail. However, it should be understood by those skilled in the art that the layers, regions, etc. of the desired shape can be formed by various technical means. In addition, those skilled in the art can also design methods that are not exactly the same as the methods described above in order to form the same structure. In addition, although each embodiment is described separately above, this does not mean that the measures in each embodiment cannot be used advantageously in combination.

[0033] The embodiments of the present disclosure are described above. However, these embodiments are only for illustrative purposes, and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art can make various substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A method of forming a pattern, characterized by, The method comprises the following steps: forming a target layer, a transfer layer and a first guide pattern on a semiconductor substrate in sequence; forming a first etching pattern arranged in a horizontal direction or a vertical direction on the first guide pattern by using a directed self-assembly process, and etching the transfer layer to form a first transfer pattern by using the first etching pattern as a mask; forming a second transfer pattern intersecting the first transfer pattern perpendicularly; etching the target layer to form a target pattern by using the first transfer pattern and the second transfer pattern as masks.

2. The method of claim 1, wherein, The second transfer pattern is formed by using a negative development technique in a liquid immersion lithography process.

3. The method of claim 2, wherein, The second transfer pattern comprises a rectangular pattern.

4. The method of claim 1, wherein The step of forming the second transfer pattern comprises: forming a second guide pattern, and forming the second transfer pattern by using a directed self-assembly process and a negative development technique.

5. The method of claim 4, wherein, The second transfer pattern comprises a square pattern.

6. The method of claim 4, wherein, The directed self-assembly process comprises the following steps: forming a directed self-assembly material layer on the first guide pattern or the second guide pattern, and performing self-assembly on the directed self-assembly material layer to form a block copolymer pattern arranged in a repeating manner, and removing unnecessary parts.

7. The method of claim 6, wherein, The first guide pattern or the second guide pattern respectively comprises a plurality of pinning regions and neutral regions arranged at intervals, wherein the width of the neutral region is three times the width of the pinning region.

8. The method of claim 6, wherein, The block copolymer pattern comprises a plurality of linear patterns parallel to each other.

9. The method of claim 6, wherein, The target layer is made of silicon nitride, and the transfer layer is made of silicon oxide, and after the first transfer pattern is formed, the first etching pattern and the first guide pattern are removed.

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