Method for forming a semiconductor structure

Abstract

A method for forming a semiconductor structure includes: providing a substrate; forming a plurality of discretely arranged dummy gates on the substrate; forming a first dielectric layer on the substrate, the top of the first dielectric layer being lower than the top of the dummy gates; forming a second dielectric layer on the first dielectric layer, the top of the second dielectric layer being flush with the top of the dummy gates; removing the dummy gates to form an opening penetrating the first dielectric layer and the second dielectric layer; forming a high-k gate dielectric film on the top of the second dielectric layer, at the bottom and on the sidewalls of the opening; forming a metal layer in the opening, the top of the metal layer being flush with the top of the high-k gate dielectric film on the second dielectric layer; removing a part of the thickness of the metal layer to form a metal gate, and depositing a sacrificial dielectric layer; removing the sacrificial dielectric layer and the second dielectric layer, and the top of the metal gate being flush with the top of the first dielectric layer. The present invention helps to improve the controllability of the height of the metal gate.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular, to a method for forming a semiconductor structure. Background Art

[0002] The miniaturization of transistor size is the trend of semiconductor structure development. However, the continuous reduction of transistor size also brings a series of technical problems. For example, the gate dielectric layer is too thin, resulting in a high leakage current between the gate and the channel. The size reduction significantly increases the resistance of the polysilicon gate, etc.

[0003] Researchers have found that transistors formed by replacing silicon oxide or silicon oxynitride materials with a high-k gate dielectric layer and using a metal gate to replace the traditional polysilicon gate material, that is, high-k metal gate (HKMG, High K Metal Gate) transistors can effectively solve the above problems. On the one hand, the high-k gate dielectric layer can reduce the tunneling current between the gate and the channel. On the other hand, the resistivity of the metal gate is extremely small, which can effectively prevent the increase of the gate resistance.

[0004] However, the method for forming a semiconductor structure in the prior art still needs to be improved. Summary of the Invention

[0005] The problem solved by the present invention is to provide a method for forming a semiconductor structure, which helps to improve the controllability of the metal gate height.

[0006] To solve the above problems, the present invention provides a method for forming a semiconductor structure, including: providing a substrate; forming a plurality of discretely arranged dummy gates on the substrate; forming a first dielectric layer on the substrate, the top of the first dielectric layer being lower than the top of the dummy gates; forming a second dielectric layer on the first dielectric layer, the top of the second dielectric layer being flush with the top of the dummy gates; removing the dummy gates to form an opening penetrating the first dielectric layer and the second dielectric layer; forming a high-k gate dielectric film on the top of the second dielectric layer, the bottom and the sidewalls of the opening; forming a metal layer in the opening, the top of the metal layer being flush with the top of the high-k gate dielectric film on the second dielectric layer; removing a part of the thickness of the metal layer to form a metal gate, depositing a sacrificial dielectric layer; removing the sacrificial dielectric layer and the second dielectric layer, the top of the metal gate being flush with the top of the first dielectric layer.

[0007] Optionally, the process step of forming the metal layer includes: forming a metal film filling the opening on the high-k gate dielectric film, the top of the metal film being higher than the top of the high-k gate dielectric film on the second dielectric layer; using a first chemical mechanical polishing process to remove a part of the thickness of the metal film until the remaining top of the metal film is flush with the top of the high-k gate dielectric film on the second dielectric layer, and the remaining metal film forms the metal layer.

[0008] Optionally, the polishing liquid material for the first chemical mechanical polishing process includes alumina.

[0009] Optionally, during the process of forming the metal gate, it further includes: etching to remove the high-k gate dielectric film on the top of the second dielectric layer and on the sidewalls of the exposed openings, and the remaining high-k gate dielectric film forms the high-k gate dielectric layer.

[0010] Optionally, in the step of forming the sacrificial dielectric layer, the sacrificial dielectric layer covers the top of the second dielectric layer, the top of the high-k gate dielectric layer, and the top of the metal gate.

[0011] Optionally, a second chemical mechanical polishing process is used to remove the sacrificial dielectric layer and the second dielectric layer.

[0012] Optionally, the second chemical mechanical polishing process includes: performing a first polishing treatment on the sacrificial dielectric layer and the second dielectric layer until the sacrificial dielectric layer and the second dielectric layer are removed; performing a second polishing treatment on the top of the first dielectric layer and the top of the metal gate.

[0013] Optionally, the polishing liquid material for the first polishing treatment includes alumina; the polishing liquid material for the second polishing treatment includes silica.

[0014] Optionally, the material of the sacrificial dielectric layer is the same as that of the second dielectric layer.

[0015] Optionally, the material of the second dielectric layer is silicon nitride, silicon carbonitride, silicon carbon oxynitride, or silicon oxynitride, and the material of the sacrificial dielectric layer is silicon nitride, silicon carbonitride, silicon carbon oxynitride, or silicon oxynitride.

[0016] Optionally, the material of the first dielectric layer is silica.

[0017] Optionally, the step of forming the second dielectric layer includes: forming a second dielectric film on the top of the first dielectric layer, on the sidewalls and the top of the dummy gate, the top of the second dielectric film on the first dielectric layer is higher than the top of the dummy gate, or the top of the second dielectric film on the first dielectric layer is flush with the top of the dummy gate; forming a filling film covering the second dielectric film; using a third chemical mechanical polishing process to remove the filling film and the second dielectric film higher than the top of the dummy gate, and the remaining second dielectric film forms the second dielectric layer.

[0018] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0019] In the process of forming the metal layer, the high-k gate dielectric film on the second dielectric layer acts as a polishing stop layer, enabling the top of the formed metal layer to be flush with the top of the high-k gate dielectric film on the second dielectric layer. During the step of forming the metal layer, the high-k gate dielectric film on the second dielectric layer is retained. The high-k gate dielectric film can protect the top of the second dielectric layer, contributing to improving the height controllability of the formed metal layer. Subsequently, when forming the metal gate, it helps to better control the height of the metal gate. Moreover, after forming the metal layer, etching away a part of the thickness of the metal layer to form the metal gate helps to improve the flatness of the top of the metal gate. Description of the Drawings

[0020] Figures 1 to 7 is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure;

[0021] Figures 8 to 25 is a schematic structural diagram corresponding to each step in an embodiment of the method for forming a semiconductor structure according to the present invention. Detailed Description of the Invention

[0022] As can be seen from the background art, the performance of existing semiconductor structures still needs to be improved.

[0023] Now, an analysis is carried out in combination with a method for forming a semiconductor structure. The forming method includes: Refer to Figure 1 , providing a substrate 10; forming a plurality of discretely arranged dummy gates 20 on the substrate 10; forming spacers 24 on the sidewalls of the dummy gates 20; forming a first dielectric film (not shown in the figure) covering the tops of the spacers 24 and the dummy gates 20 on the substrate 10; back-etching the first dielectric film to form a first dielectric layer 31, the top of the first dielectric layer 31 being lower than the top of the dummy gates 20; forming a second dielectric layer 32 on the first dielectric layer 31, the top of the second dielectric layer 32 being flush with the top of the dummy gates 20; Refer to Figure 2 , removing the dummy gates 20 to form openings 25; Refer to Figure 3 , forming a high-k gate dielectric film 40 on the top of the second dielectric layer 32, the tops of the spacers 24, the bottom and sidewalls of the openings 25 (refer to Figure 2 ); forming a metal film 50 filling the openings 25 (refer to Figure 2 ) on the high-k gate dielectric film 40, the top of the metal film 50 being higher than the top of the high-k gate dielectric film 40 on the second dielectric layer 32; Refer to Figure 4 , using a chemical mechanical polishing process to remove the metal film 50 (refer to Figure 3 ) higher than the top of the second dielectric layer 32, and removing the high-k gate dielectric film 40 on the top of the second dielectric layer 32 (refer to Figure 3 ), leaving the metal film 50 (refer to Figure 3)Form the metal layer 51; refer to Figure 5 , remove the second dielectric layer 32, and remove the sidewall 24 that is higher than the top of the first dielectric layer 31, exposing a part of the sidewall of the high-k gate dielectric film 40; refer to Figure 6 , for the metal layer 51 (refer to Figure 5 ) and the high-k gate dielectric film 40 (refer to Figure 5 ), perform a planarization process until the metal layer 51 (refer to Figure 5 ) and the high-k gate dielectric film 40 (refer to Figure 5 ) that are higher than the top of the first dielectric layer 31 are removed, and the remaining metal layer 51 forms a metal gate 52, and the remaining high-k gate dielectric film 40 forms a high-k gate dielectric layer 41.

[0024] As Figure 4 shown, during the chemical mechanical polishing process, not only the metal film 50 (refer to Figure 3 ) that is higher than the top of the second dielectric layer 32 is polished and removed, but also the high-k gate dielectric film 40 (refer to Figure 3 ) on the top of the second dielectric layer 32 is polished and removed. After the high-k gate dielectric film 40 is polished and removed, the chemical mechanical polishing easily further polishes the top of the second dielectric layer 32 and synchronously polishes the metal film 50 (refer to Figure 2 ) in the opening 25 (refer to Figure 3 ), and it is not easy to control the height of the formed metal layer 51, resulting in the height of the metal layer 51 being lower than the preset value, and further causing the height of the subsequent formed metal gate 52 (refer to Figure 6 ) to be too low.

[0025] The above problems are more significant when the substrate 10 includes a short-channel region I and a long-channel region II. Figure 7 Corresponding to Figure 4 , Figure 7 shows a schematic structural diagram of the chemical mechanical polishing process steps when the substrate 10 includes a short-channel region I and a long-channel region II. Refer to Figure 7, the substrate 10 includes a short-channel region I and a long-channel region II. The short-channel region I and the long-channel region II together perform all the above steps before forming the metal gate 52. In the step of forming the first dielectric layer 31, since the adjacent dummy gate 20 pitch in the long-channel region II is greater than the adjacent dummy gate 20 pitch in the short-channel region I, and since the etch-back time is the same, in the long-channel region II and the short-channel region I, the volume of the first dielectric film removed by etch-back is the same, resulting in the thickness H2 of the first dielectric layer 31 formed in the long-channel region II being greater than the thickness H1 of the first dielectric layer 31 formed in the short-channel region I, and further causing the thickness H4 of the second dielectric layer 32 in the long-channel region II to be less than the thickness H3 of the second dielectric layer 32 in the short-channel region I. During the chemical mechanical polishing process, after polishing and removing the high-k gate dielectric film 40 (refer to Figure 3 ) on the top of the second dielectric layer 32 in the long-channel region II and the short-channel region I, the second dielectric layer 32 in the long-channel region II and the short-channel region I is further polished. During the polishing of the second dielectric layer 32 in the long-channel region II and the short-channel region I, since the thickness H4 of the second dielectric layer 32 in the long-channel region II is less than the thickness H3 of the second dielectric layer 32 in the short-channel region I, the polishing rate of the second dielectric layer 32 in the long-channel region II is faster. When the short-channel region I is still polishing the second dielectric layer 32, the second dielectric layer 32 in the long-channel region II has been completely polished and removed, and then the first dielectric layer 31 in the long-channel region II is polished. That is, when the short-channel region I is polished to the position shown by the dotted line L1, the long-channel region II has been polished to the position shown by the dash-dotted line L2. Once the long-channel region II is polished to the first dielectric layer 31, the polishing rate of the long-channel region II will further increase, resulting in the height of the metal layer 51 formed in the long-channel region II being too low. When forming the metal gate later, the risk of exposing the high-k gate dielectric layer at the bottom of the metal gate in the long-channel region II increases.

[0026] Furthermore, as shown in Figure 5 , first remove the second dielectric layer 32 (refer to Figure 4 ) and the sidewall 24 higher than the top of the first dielectric layer 31 to expose a part of the sidewall of the high-k gate dielectric film 40. Then, as shown in Figure 6 , by planarization, remove the metal layer 51 (refer to Figure 5 ) and the high-k gate dielectric film 40 (refer to Figure 5 ) higher than the top of the first dielectric layer 31. It is easy to form a concave surface on the top surface of the formed metal gate 52, resulting in poor formation quality of the metal gate 52 and affecting the subsequent electrical performance test of the semiconductor structure. In the case where the substrate 10 includes a short-channel region I and a long-channel region II, this problem is more serious for the long-channel region II.

[0027] The inventors have studied the above problems. Through creative labor, the inventors have noticed that in the process steps of forming the metal layer, retaining the high-k gate dielectric film on the second dielectric layer helps to better control the height of the metal gate. In addition, after forming the metal layer, etching away a part of the thickness of the metal layer to form the metal gate helps to improve the flatness of the top of the metal gate and improve the formation quality of the metal gate.

[0028] To make the above objects, features, and advantages of the present invention more obvious and understandable, the following specifically describes the embodiments of the present invention in detail with reference to the accompanying drawings.

[0029] Figures 8 to 25 It is a schematic structural diagram of the formation process of a semiconductor structure provided by an embodiment of the present invention.

[0030] Refer to Figure 8 , and a substrate 100 is provided.

[0031] In this embodiment, the substrate 100 is used to form fin field-effect transistors, and the substrate 100 includes a substrate 110 and discrete fin portions 120 located on the substrate 110.

[0032] The material of the substrate 110 is silicon, germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium. In this embodiment, the substrate 110 is a silicon substrate.

[0033] The material of the fin portion 120 is the same as that of the substrate 110. In this embodiment, the material of the fin portion 120 is silicon. In other embodiments, the material of the fin portion 120 may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium.

[0034] In this embodiment, the substrate 100 further includes an isolation layer 130 located on the substrate 110, and the isolation layer 130 covers the sidewalls of the fin portions 120.

[0035] The material of the isolation layer 130 is silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, the material of the isolation layer 130 is silicon oxynitride.

[0036] In one embodiment, the substrate 100 only includes a long-channel region; in another embodiment, the substrate 100 only includes a short-channel region; in still another embodiment, the substrate 100 includes a long-channel region and a short-channel region.

[0037] Refer to Figure 9 , and a plurality of discrete pseudo-gates 200 are formed on the substrate 100.

[0038] In this embodiment, a back-gate process is used to form the semiconductor structure, and the dummy gate 200 occupies a spatial position for the subsequent formation of a metal gate.

[0039] In this embodiment, the dummy gate 200 straddles the fin 120.

[0040] The dummy gate 200 is a single-layer structure or a stacked structure. In this embodiment, the dummy gate 200 is a stacked structure, and the dummy gate 200 includes a dummy oxide layer 210 and a dummy gate layer 220 located on the dummy oxide layer 210. The material of the dummy oxide layer 210 is silicon oxide or silicon oxynitride, and the material of the dummy gate layer 220 is polysilicon or amorphous carbon.

[0041] In other embodiments, the dummy gate 200 is a single-layer structure, and the dummy gate 200 only includes a dummy gate layer. The material of the dummy gate layer is polysilicon or amorphous carbon.

[0042] In this embodiment, in the step of forming the dummy gate 200, it further includes: forming a hard mask layer 230 on the top of the dummy gate 200.

[0043] The material of the hard mask layer 230 can be silicon nitride, silicon carbonitride, or silicon oxynitride. In this embodiment, the material of the hard mask layer 230 is silicon nitride.

[0044] In this embodiment, after forming the hard mask layer 230, it further includes: forming a spacer 240 on the sidewalls of the dummy gate 200 and the sidewalls of the hard mask layer 230.

[0045] In the subsequent process of removing the dummy gate 200, the spacer 240 can protect the sidewalls of the first dielectric layer and the second dielectric layer.

[0046] The spacer 240 can be a single-layer structure or a stacked structure. In this embodiment, the spacer 240 is a single-layer structure.

[0047] The material of the spacer 240 can be silicon nitride, silicon carbide, silicon carbonitride, silicon carbon oxynitride, silicon oxynitride, boron nitride, or boron carbonitride. In this embodiment, the material of the spacer 240 is silicon nitride.

[0048] Refer to Figures 10 to 12 , a first dielectric layer 310 is formed on the substrate 100, and the top of the first dielectric layer 310 is lower than the top of the dummy gate 200.

[0049] In this embodiment, the material of the first dielectric layer 310 is silicon oxide.

[0050] In this embodiment, the process steps of forming the first dielectric layer 310 include: refer to Figure 10 and Figure 11, a first dielectric film 301 is formed on the substrate 100, and the first dielectric film 301 covers the top of the hard mask layer 230 and the top of the sidewall 240; the first dielectric film 301 is planarized so that the top of the remaining first dielectric film 301 is flush with the top of the hard mask layer 230 and the top of the sidewall 240. Among them, as Figure 11 shown, the step of planarizing the first dielectric film 301 further includes grinding and removing a part of the thickness of the hard mask layer 230 and grinding the top of the sidewall 240; as Figure 12 shown, a part of the thickness of the first dielectric film 301 is etched away (refer to Figure 11 ), and the top of the remaining first dielectric film 301 is lower than the top of the dummy gate 200, forming the first dielectric layer 310, and the first dielectric layer 310 exposes a part of the sidewall of the sidewall 240.

[0051] In this embodiment, the first dielectric film 301 is formed by a fluid chemical vapor deposition process.

[0052] In this embodiment, during the process of etching away a part of the thickness of the first dielectric film 301, it further includes: etching away the hard mask layer 230 (refer to Figure 11 ), and etching away the sidewall 240 covering the sidewall of the hard mask layer 230.

[0053] Refer to Figures 13 to 17 , a second dielectric layer 320 is formed on the first dielectric layer 310, and the top of the second dielectric layer 320 is flush with the top of the dummy gate 200.

[0054] In this embodiment, the material of the second dielectric layer 320 is silicon nitride. In other embodiments, the material of the second dielectric layer 320 is silicon carbonitride, silicon carbon oxynitride or silicon oxynitride.

[0055] The forming step of the second dielectric layer 320 includes: as Figure 13 shown, a second dielectric film 302 is formed on the top of the first dielectric layer 310, the sidewall and the top of the dummy gate 200, and the top of the second dielectric film 302 on the first dielectric layer 310 is higher than the top of the dummy gate 200, or the top of the second dielectric film 302 on the first dielectric layer 310 is flush with the top of the dummy gate 200; as Figure 14 shown, a filling film 303 covering the second dielectric film 302 is formed; as Figures 15 to 17 shown, the filling film 303 and the second dielectric film 302 higher than the top of the dummy gate 200 are removed by a third chemical mechanical polishing process, and the remaining second dielectric film 302 forms the second dielectric layer 320.

[0056] In this embodiment, the second dielectric film 302 is formed by a deposition process.

[0057] In this embodiment, as Figure 13 shown, in the step of forming the second dielectric film 302, the top of the second dielectric film 302 on the sidewall of the sidewall 240, the top of the sidewall 240, and the top of the dummy gate 200 is higher than the top of the second dielectric film 302 on the first dielectric layer 310. The second dielectric film 302 on the sidewall of the sidewall 240, the top of the sidewall 240, and the top of the dummy gate 200 encloses a groove 304, and the second dielectric film 302 on the first dielectric layer 310 serves as the bottom of the groove 304.

[0058] In this embodiment, as Figure 14 shown, in the step of forming the filling film 303, the filling film 303 fills the groove 304 (refer to Figure 13 ), and the filling film 303 covers the top of the groove 304 (refer to Figure 13 ).

[0059] In this embodiment, the filling film 303 is formed by a deposition process.

[0060] The third chemical mechanical polishing process includes: as Figure 15 shown, planarizing the filling film 303 until the top of the groove 304 (refer to Figure 13 ) is exposed, that is, the top of the second dielectric film 302 on the sidewall of the sidewall 240, the top of the sidewall 240, and the top of the dummy gate 200 is exposed; as Figure 16 shown, using an etch-back process to remove a part of the thickness of the second dielectric film 302 and the filling film 303; as Figure 17 shown, using a planarization process to remove the remaining filling film 303 and remove the second dielectric film 302 higher than the top of the dummy gate 200 (refer to Figure 16 ), and the remaining second dielectric film 302 forms the second dielectric layer 320.

[0061] Refer to Figure 18 and Figure 19 , remove the dummy gate 200 (refer to Figure 17 ), and form an opening 250 penetrating through the first dielectric layer 310 and the second dielectric layer 320.

[0062] In this embodiment, the step of removing the dummy gate 200 includes: as Figure 18 shown, etching and removing the dummy gate layer 220 (refer to Figure 17 ); as Figure 19 shown, etching and removing the dummy oxide layer 210 (refer to Figure 18 ).

[0063] In this embodiment, in the step of removing the dummy gate 200, the sidewall 240 is retained, the opening 250 exposes the sidewall of the sidewall 240, and the sidewall 240 can protect the sidewalls of the first dielectric layer 310 and the second dielectric layer 320.

[0064] Reference Figure 20 and Figure 21 , a high-k gate dielectric film 400 is formed on the top of the second dielectric layer 320, at the bottom and on the sidewalls of the opening 250 (reference Figure 19 ); a metal layer 500 filling the opening 250 is formed, and the top of the metal layer 500 is flush with the top of the high-k gate dielectric film 400 on the second dielectric layer 320.

[0065] The material of the high-k gate dielectric film 400 is a high-k dielectric material (dielectric constant greater than 3.9). In this embodiment, the material of the high-k gate dielectric film 400 is HfO2; in other embodiments, the material of the high-k gate dielectric film 400 can also be HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or ZrO2.

[0066] In this embodiment, the forming process of the high-k gate dielectric film 400 is an atomic layer deposition process. The high-k gate dielectric film 400 formed by the atomic layer deposition process has a uniform thickness and good step coverage at the bottom corner of the opening 250.

[0067] The forming steps of the metal layer 500 include: as Figure 20 shown, a metal film 501 filling the opening 250 (reference Figure 19 ) is formed on the high-k gate dielectric film 400; as Figure 21 shown, a part of the thickness of the metal film 501 (reference Figure 20 ) is removed by a first chemical mechanical polishing process until the top of the remaining metal film 501 is flush with the top of the high-k gate dielectric film 400 on the second dielectric layer 320, and the remaining metal film 501 forms the metal layer 500.

[0068] The first chemical mechanical polishing process stops when grinding to the top of the high-k gate dielectric film 400 on the second dielectric layer 320. During the first chemical mechanical polishing process, the high-k gate dielectric film 400 on the second dielectric layer 320 acts as a polishing stop layer, which can protect the top of the second dielectric layer 320 and avoid the second dielectric layer 320 and the metal film 501 in the opening 250 (reference Figure 19 ) from being polished synchronously, thereby avoiding the first dielectric layer 310 and the opening 250 (reference Figure 19) The metal film 501 inside is also ground synchronously, which is conducive to controlling the height of the metal layer 500, helps to better control the height of the subsequent formed metal gate, and avoids affecting the subsequent electrical tests.

[0069] The material of the metal film 501 is Cu, W, Al or Ag. In this embodiment, the material of the metal film 501 is W.

[0070] In this embodiment, the abrasive material of the first chemical mechanical polishing process includes alumina. The process steps of the first chemical mechanical polishing process include: using a first polishing treatment to remove most of the metal film 501 above the top of the high-k gate dielectric film 400 on the second dielectric layer 320; using a second polishing treatment to remove the remaining metal film 501 on the top of the high-k gate dielectric film 400. The abrasive materials of the first polishing treatment and the second polishing treatment both include alumina.

[0071] In this embodiment, the selectivity of the abrasive of the second polishing treatment to the metal film 501 and the high-k gate dielectric film 400 is 53:1. Therefore, the second polishing treatment can well stay on the top of the high-k gate dielectric film 400 on the second dielectric layer 320, which is conducive to accurately controlling the top of the metal layer 500 to be flush with the top of the high-k gate dielectric film 400 on the second dielectric layer 320.

[0072] Refer to Figure 22 , etch away a part of the thickness of the metal layer 500 (refer to Figure 21 ), expose a part of the sidewall of the opening 250 (refer to Figure 19 ), and etch away the high-k gate dielectric film 400 (refer to Figure 19 ) on the top of the second dielectric layer 320 and the sidewall of the exposed opening 250 (refer to Figure 21 ). The remaining metal layer 500 forms a metal gate 510, and the remaining high-k gate dielectric film 400 forms a high-k gate dielectric layer 410.

[0073] The top of the metal gate 510 is flush with the top of the first dielectric layer 310, or the top of the metal gate 510 is lower than the top of the first dielectric layer 310. Subsequently, the second chemical mechanical polishing process is used to remove the second dielectric layer 320, which helps to ensure that the second dielectric layer 320 is removed cleanly and reduces the material residue of the second dielectric layer 320.

[0074] In this embodiment, the top of the metal gate 510 is flush with the top of the first dielectric layer 310.

[0075] Refer to Figure 23 , form a sacrificial dielectric layer 330 that fills the opening 250 exposed by the metal gate 510.

[0076] In this embodiment, the sacrificial dielectric layer 330 covers the top of the second dielectric layer 320, the top of the sidewall 240, the top of the high-k gate dielectric layer 410, and the top of the metal gate 510.

[0077] In this embodiment, the sacrificial dielectric layer 330 is formed by a deposition process.

[0078] The material of the sacrificial dielectric layer 330 is the same as that of the second dielectric layer 320. In this embodiment, the materials of both the sacrificial dielectric layer 330 and the second dielectric layer 320 are silicon nitride. In other embodiments, the material of the sacrificial dielectric layer 330 is silicon carbonitride, silicon carbon oxynitride, or silicon oxynitride.

[0079] Reference Figure 24 and Figure 25 , a second chemical mechanical polishing process is used to remove the sacrificial dielectric layer 330 and the second dielectric layer 320.

[0080] In this embodiment, before removing the sacrificial dielectric layer 330 and the second dielectric layer 320, a etching process is used to remove a part of the thickness of the metal layer 500 to form the metal gate 510, which helps to improve the flatness of the top of the metal gate 510, prevent the formation of a concave surface on the top of the metal gate 510, and helps to improve the formation quality of the metal gate 510.

[0081] In this embodiment, the second chemical mechanical polishing process includes: as Figure 24 shown, a first polishing treatment is performed on the sacrificial dielectric layer 330 (reference Figure 23 ) and the second dielectric layer 320 (reference Figure 23 ) until the sacrificial dielectric layer 330 and the second dielectric layer 320 are removed, and the first polishing treatment also removes the sidewall 240 that is higher than the top of the first dielectric layer 310; as Figure 25 shown, a second polishing treatment is performed on the top of the first dielectric layer 310 and the top of the metal gate 510, and the second polishing treatment also includes grinding the top of the sidewall 240 and the top of the high-k gate dielectric layer 410 to make the remaining top of the first dielectric layer 310, the top of the metal gate 510, the top of the sidewall 240, and the top of the high-k gate dielectric layer 410 flush.

[0082] The second polishing treatment can remove the remaining material of the second dielectric layer 320 on the top of the metal gate 510, further improve the surface flatness of the top of the metal gate 510, and ensure the consistent height of the metal gate 510.

[0083] In this embodiment, the abrasive material for the first polishing treatment includes alumina; the abrasive material for the second polishing treatment includes silica.

[0084] In this embodiment, the selectivity of the abrasive for the first polishing treatment with respect to the second dielectric layer 320 and the first dielectric layer 310 is 18:1. The selectivity of the abrasive for the first polishing treatment with respect to the second dielectric layer 320 and the metal gate 510 is also 18:1.

[0085] In this embodiment, the selectivity of the abrasive for the second polishing treatment with respect to the second dielectric layer 320 and the first dielectric layer 310 is 5:1. The selectivity of the abrasive for the second polishing treatment with respect to the second dielectric layer 320 and the metal gate 510 is 10:1.

[0086] The second dielectric layer 320 is completely removed by the first polishing treatment and the second polishing treatment, which can avoid the residue of the second dielectric layer 320 material on the top of the metal gate 510 and improve the formation quality of the metal gate 510.

[0087] It should be noted that since the second polishing treatment is performed simultaneously on the top of the first dielectric layer 310 and the top of the metal gate 510, and since the difference in the selectivity of the abrasive for the second polishing treatment with respect to the first dielectric layer 310 and the metal gate 510 is small and the polishing rates are both small, it is more difficult to form a concave surface on the top of the formed metal gate 510.

[0088] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be determined by the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, Including: Providing a substrate; Forming a plurality of discretely arranged dummy gates on the substrate; Forming a first dielectric layer on the substrate, the top of the first dielectric layer being lower than the top of the dummy gate; Forming a second dielectric layer on the first dielectric layer, the top of the second dielectric layer being flush with the top of the dummy gate; Removing the dummy gate to form a first opening penetrating through the first dielectric layer and the second dielectric layer; Forming a high-k gate dielectric film on the top of the second dielectric layer, the bottom and side walls of the first opening, and the high-k gate dielectric film forming a second opening in the first opening; Forming a metal layer in the second opening, the top of the metal layer being flush with the top of the high-k gate dielectric film on the second dielectric layer; Removing a part of the thickness of the metal layer to form a metal gate, depositing a sacrificial dielectric layer, and the sacrificial dielectric layer filling the exposed second opening of the metal gate; Removing the sacrificial dielectric layer and the second dielectric layer, and the top of the metal gate being flush with the top of the first dielectric layer.

2. The method for forming a semiconductor structure according to claim 1, wherein The process steps for forming the metal layer include: forming a metal film filling the second opening on the high-k gate dielectric film, the top of the metal film being higher than the top of the high-k gate dielectric film on the second dielectric layer; using a first chemical mechanical polishing process to remove a part of the thickness of the metal film until the remaining top of the metal film is flush with the top of the high-k gate dielectric film on the second dielectric layer, and the remaining metal film forms the metal layer.

3. The method for forming a semiconductor structure according to claim 2, wherein, The polishing liquid material of the first chemical mechanical polishing process includes alumina.

4. The method for forming a semiconductor structure according to claim 1, wherein During the process of forming the metal gate, it further includes: etching and removing the high-k gate dielectric film on the top of the second dielectric layer and the side walls of the exposed second opening, and the remaining high-k gate dielectric film forms a high-k gate dielectric layer, and the high-k gate dielectric layer is flush with the top of the first dielectric layer.

5. The method for forming a semiconductor structure according to claim 4, wherein, In the step of forming the sacrificial dielectric layer, the sacrificial dielectric layer covers the top of the second dielectric layer, the top of the high-k gate dielectric layer, and the top of the metal gate.

6. The method for forming a semiconductor structure according to claim 5, wherein, Using a second chemical mechanical polishing process to remove the sacrificial dielectric layer and the second dielectric layer.

7. The method for forming a semiconductor structure according to claim 6, wherein The second chemical mechanical polishing process includes: performing a first polishing process on the sacrificial dielectric layer and the second dielectric layer until the sacrificial dielectric layer and the second dielectric layer are removed; performing a second polishing process on the top of the first dielectric layer and the top of the metal gate.

8. The method for forming a semiconductor structure according to claim 7, wherein, The polishing liquid material of the first polishing process includes alumina; the polishing liquid material of the second polishing process includes silica.

9. The method for forming a semiconductor structure according to claim 6, wherein The material of the sacrificial dielectric layer is the same as the material of the second dielectric layer.

10. The method for forming a semiconductor structure according to claim 9, wherein, The material of the second dielectric layer is silicon nitride, silicon carbonitride, silicon carbon oxynitride, or silicon oxynitride, and the material of the sacrificial dielectric layer is silicon nitride, silicon carbonitride, silicon carbon oxynitride, or silicon oxynitride.

11. The method for forming a semiconductor structure according to claim 1, wherein, The material of the first dielectric layer is silica.

12. The method for forming a semiconductor structure according to claim 1, wherein The forming step of the second dielectric layer includes: forming a second dielectric film on the top of the first dielectric layer, on the sidewalls and at the top of the dummy gate, wherein the top of the second dielectric film on the first dielectric layer is higher than the top of the dummy gate, or the top of the second dielectric film on the first dielectric layer is flush with the top of the dummy gate; forming a filling film covering the second dielectric film; removing the filling film and the second dielectric film that are higher than the top of the dummy gate by using a third chemical mechanical polishing process, and the remaining second dielectric film forms the second dielectric layer.

Images