A method for realizing a high-power high-voltage transistor

Abstract

The present invention provides a method for implementing a high-power, high-voltage transistor, comprising: sequentially growing an n+ epitaxial layer and an n-epitaxial layer on an n-type silicon substrate; growing a gate oxide layer and depositing a polysilicon layer; forming a gate pattern and a p-channel region pattern, and forming the p-channel region by boron ion doping and boron diffusion; photolithographically defining the patterns of the transistor's n+ source and n+ drain regions, and forming the n+ source and n+ drain regions by phosphorus ion doping and diffusion; annealing the n+ source and n+ drain regions to oxidize the interface between the n+ source and n+ drain, the gate oxide layer, and the polysilicon layer in the transistor to an optimal thickness; depositing an interlayer oxide, photolithographically and etching to form ohmic contact windows with the gate, source, and drain, and depositing a metal layer to form the metallization interconnection of the transistor. This method eliminates etching of the gate oxide layer in the n+ source region, prevents undercutting of the gate oxide layer, and eliminates the possibility of gate oxide breakdown along the gate edge.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for realizing a high-power high-voltage transistor. Background Art

[0002] Currently, a known method for manufacturing a high-power, high-voltage double-diffused metal oxide semiconductor field-effect transistor (DMOSFET) includes: forming an epitaxial silicon structure with a protective oxide on the n-n+ surface, etching the protective oxide to form a gate oxide, depositing a polysilicon layer, forming a photolithographic pattern for the gate, etching the polysilicon layer, forming a p-channel region by boron ion doping and boron diffusion, forming an n+ source region by phosphorus ion implantation and diffusion, oxide etching, interlayer oxide deposition, forming contact regions with the gate and source, and then depositing a metallization layer;

[0003] However, this method has the following disadvantages: during etching of the gate oxide, undercutting of the oxide occurs under the polysilicon gate, and a gap is formed between the polysilicon gate and the n+ source in the gate edge region, which is subsequently filled with an interlayer oxide. Moreover, in terms of dielectric constant, the dielectric breakdown of the interlayer oxide is worse than that of the gate oxide, so the oxide breakdown between the gate and the n+ source will occur along the gate edge, ultimately reducing the breakdown voltage of the gate oxide and increasing the gate-source breakdown voltage;

[0004] Therefore, in order to overcome the existing problems, the present invention provides a method for realizing a high-power, high-voltage transistor. Through oxidation and other process steps, the junction area of ​​the transistor n+ source, n+ drain, gate oxide layer and polysilicon layer is oxidized to an optimal thickness, which can not only eliminate the etching of the gate oxide layer in the n+ source region, but also prevent the bottom of the gate oxide layer from being cut into. At the same time, the possibility of gate oxide breakdown along the gate edge is also eliminated. Summary of the Invention

[0005] The present invention provides a method for realizing a high-power high-voltage transistor, which is used to oxidize the junction area of ​​the transistor n+ source, n+ drain, gate oxide layer and polysilicon layer to an optimal thickness through process steps such as oxidation, thereby eliminating etching of the gate oxide layer in the n+ source region and preventing cutting into the bottom of the gate oxide layer. At the same time, the possibility of gate oxide breakdown along the gate edge is also eliminated.

[0006] A method for implementing a high-power high-voltage transistor, comprising:

[0007] Step 1: sequentially growing an n+ epitaxial layer and an n- epitaxial layer on an n-type silicon substrate, and growing a protective silicon oxide on the surface of the n- epitaxial layer;

[0008] Step 2: removing the protective silicon oxide, growing a gate oxide layer on the surface of the n-epitaxial layer, and depositing a polysilicon layer on the gate oxide layer;

[0009] Step 3: forming a gate pattern and a p-channel region pattern on the gate oxide layer and the polysilicon layer by photolithography and etching, then forming a p-channel region based on the p-channel region pattern by boron ion doping and boron diffusion, and growing protective silicon oxide in the p-channel region;

[0010] Step 4: Photolithographically defining the patterns of the n+ source region and the n+ drain region of the transistor on the protective oxide layer of the p-channel region, etching the protective oxide layer of the p-channel region, and forming the n+ source region and the n+ drain region by phosphorus ion doping and phosphorus diffusion;

[0011] Step 5: Before depositing the interlayer oxide, anneal the n+ source region and the n+ drain region to oxidize the interface between the n+ source and n+ drain, the gate oxide layer, and the polysilicon layer in the transistor to an optimal thickness;

[0012] Step 6: depositing an interlayer oxide, and forming ohmic contact windows with the gate, source and drain on the interlayer oxide by photolithography and etching, depositing a metal layer, and forming metal interconnection of the transistor on the metal layer by photolithography and etching.

[0013] Preferably, in a method for realizing a high-power high-voltage transistor, in step 5, the optimal thickness includes:

[0014] The optimal thickness is one to three times the thickness of the gate oxide layer.

[0015] Preferably, a method for implementing a high-power high-voltage transistor further includes:

[0016] The thickness of the oxide in the n+ source region and the gate oxide layer is 0.10 to 0.2 micrometers (μm), the resistivity of the polysilicon on the test component is 20 ohm.cm (Ohm.cm), and the gate-source breakdown voltage is 95-110V;

[0017] Wherein, the thickness of the n+ source oxide is greater than or equal to the thickness of the oxide in the gate oxide layer.

[0018] Preferably, a method for realizing a high-power high-voltage transistor, based on steps 1-6, constructing a device model, specifically comprises:

[0019] Determine the materials and device types required for the device model, and at the same time, determine the process flow of the device model;

[0020] The device model is constructed based on the materials, device types and process flow required for the device model.

[0021] Preferably, a method for realizing a high-power high-voltage transistor, after constructing the device model, further comprises:

[0022] Determine the target device designed and produced by the device model;

[0023] Performing parameter tests on the target device over a full power and frequency range, and determining aspects of the target device that require improvement based on the test results;

[0024] Determining a target structure for improving the target model based on the link that needs to be improved in the target device, and determining a process flow corresponding to the target structure;

[0025] The target model is improved based on the target structure for improving the target model and the process flow corresponding to the target structure.

[0026] Preferably, a method for realizing a high-power high-voltage transistor, after improving the target model, further comprises:

[0027] Testing and analyzing the improved target model, and determining the test results and analysis results;

[0028] The test results and the analysis results are fed back to the device model, and a database corresponding to the improved target model is constructed based on the feedback results.

[0029] Preferably, a method for implementing a high-power high-voltage transistor, based on feedback results, constructs a database corresponding to the improved target model, comprising:

[0030] Acquire feedback data corresponding to the feedback result, and at the same time, acquire model data corresponding to the improved target model;

[0031] Generate a database identifier based on the model data, determine a storage path of the database, and create a data receiving window based on the storage path and the database identifier;

[0032] The feedback data and the model data are received in the data receiving window to complete the construction of the database corresponding to the improved target model.

[0033] Preferably, in a method for realizing a high-power high-voltage transistor, in step 2, removing the protective silicon oxide comprises:

[0034] Obtaining a baseline thickness and a baseline area of ​​protective silicon oxide on the surface of the n-epitaxial layer, and simultaneously, evaluating a chemical dosage for removing the protective silicon oxide based on the baseline thickness and the baseline area of ​​the protective silicon oxide;

[0035] generating a first silicon oxide removal instruction according to a baseline thickness and a baseline area of ​​the protective silicon oxide and a chemical dosage for removing the protective silicon oxide;

[0036] Acquiring environmental parameter data of an environment in which the n-epitaxial layer is located, analyzing the environmental parameter data, and determining, based on the analysis results, whether the environment in which the n-epitaxial layer is located can effectively remove the protective silicon oxide;

[0037] When the environment of the n-epitaxial layer can effectively remove the protective silicon oxide, removing the protective silicon oxide on the surface of the n-epitaxial layer based on the first silicon oxide removal instruction;

[0038] When the environment of the n-epitaxial layer cannot effectively remove the protective silicon oxide, the environmental parameter data of the environment of the n-epitaxial layer is manually adjusted until the environment of the n-epitaxial layer can effectively remove the protective silicon oxide.

[0039] Preferably, a method for realizing a high-power high-voltage transistor, after removing the protective silicon oxide on the surface of the n-epitaxial layer, further comprises:

[0040] Acquiring a planar image on the surface of the n-epitaxial layer, and performing grayscale processing on the planar image to generate a grayscale planar image;

[0041] Extracting pixel points of the grayscale plane image and determining pixel features corresponding to the pixel points;

[0042] determining whether the protective silicon oxide on the surface of the n-epitaxial layer is completely removed according to the pixel feature corresponding to the pixel point;

[0043] When the protective silicon oxide on the surface of the n-epitaxial layer is completely removed, a gate oxide layer is grown on the surface of the n-epitaxial layer;

[0044] When the protective silicon oxide on the surface of the n-epitaxial layer is not completely removed, marking the protective silicon oxide based on the grayscale plane image and acquiring marking data;

[0045] Analyzing the marked data to determine the attachment area of ​​the protective silicon oxide on the n-epitaxial layer and the current concavity and convexity of the n-epitaxial layer;

[0046] Formulate a removal plan based on the attachment area of ​​the protective silicon oxide on the n-epitaxial layer and the current concavity and convexity of the n-epitaxial layer, and generate a second silicon oxide removal instruction according to the removal plan;

[0047] The protective silicon oxide on the surface of the n-epitaxial layer is removed again based on the second silicon oxide removal instruction.

[0048] Preferably, a method for realizing a high-power high-voltage transistor, in step 5, oxidizing the interface region between the n+ source and n+ drain, the gate oxide layer, and the polysilicon layer in the transistor to an optimal thickness, further comprises:

[0049] Connecting the gate oxide layer to a preset testing device, and at the same time, obtaining the breakdown voltage of the gate oxide layer and the n-epitaxial layer;

[0050] Adjusting a test voltage of the preset test device so that the test voltage is equal to the breakdown voltage;

[0051] Acquiring a charge of the preset test device, and calculating a current capacitance value of the gate oxide layer based on the charge of the preset test device and the test voltage;

[0052] Obtaining an effective capacitance area of ​​the gate oxide layer, and calculating and determining a current thickness value of the gate oxide layer based on a current capacitance value of the gate oxide layer and the effective capacitance area;

[0053] Determining, based on a current thickness value of the gate oxide layer, a target thickness value for oxidizing the interface region between the n+ source and n+ drain, the gate oxide layer, and the polysilicon layer in the transistor to an optimal thickness;

[0054] Determining monitoring instructions and control instructions for oxidizing the boundary region between the n+ source, the n+ drain, the gate oxide layer, and the polysilicon layer of the transistor according to the target thickness value;

[0055] Based on the monitoring instruction, the thickness of the oxidation of the n+ source, n+ drain, gate oxide layer and the boundary region of the polysilicon layer of the transistor is monitored, and the monitoring data is recorded according to a preset time period;

[0056] Setting a first monitoring threshold and a second monitoring threshold, wherein the first monitoring threshold is less than the second monitoring threshold, and the second monitoring threshold is equal to the target thickness value;

[0057] Reading the monitoring data in real time, and issuing a first alarm when the monitoring data is equal to the first monitoring threshold;

[0058] Simultaneously, an oxidation rate of an interface region between an n+ source and an n+ drain, a gate oxide layer, and a polysilicon layer in the transistor is oxidized based on the monitoring data;

[0059] estimating, based on the oxidation rate, a predicted time period when the monitoring data reaches the second monitoring threshold;

[0060] Initiating the control instruction based on the estimated time period, and timing according to the estimated time period based on the control instruction;

[0061] When the monitoring data is equal to the second monitoring threshold, a second alarm is issued, and based on the control instruction, the n+ source and n+ drain, the gate oxide layer and the junction area of ​​the polysilicon layer in the transistor are controlled to stop oxidation, so as to achieve the oxidation of the n+ source and n+ drain, the gate oxide layer and the junction area of ​​the polysilicon layer in the transistor to an optimal thickness.

[0062] Other features and advantages of the present invention will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present invention. The purposes and other advantages of the present invention can be realized and obtained by the structures particularly pointed out in the written description, claims, and drawings.

[0063] The technical solution of the present invention is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

[0065] Figure 1 This is a flow chart of a method for implementing a high-power high-voltage transistor in an embodiment of the present invention;

[0066] Figure 2 This is a structural diagram of step 1 in a method for implementing a high-power high-voltage transistor in an embodiment of the present invention;

[0067] Figure 3 This is a structural diagram of step 2 in a method for implementing a high-power high-voltage transistor in an embodiment of the present invention;

[0068] Figure 4 This is a structural diagram of step 3 in a method for implementing a high-power high-voltage transistor in an embodiment of the present invention;

[0069] Figure 5 This is a structural diagram of step 4 in a method for implementing a high-power high-voltage transistor in an embodiment of the present invention;

[0070] Figure 6 This is a structural diagram of step 5 in a method for implementing a high-power high-voltage transistor in an embodiment of the present invention;

[0071] Figure 7 A cross-sectional view of a transistor unit structure in a gate edge region after forming an oxidized region at the interface between the n+ source region and the gate in step 6 of a method for realizing a high-power high-voltage transistor in an embodiment of the present invention;

[0072] Figure 8 is a cross-sectional view of a high-voltage transistor unit structure in a gate edge region after forming a contact region according to a prototyping method in an embodiment of the present invention;

[0073] Figure 9 Graph showing the relationship between the gate-source breakdown voltage (Vgs) and the oxide thickness at the source and gate edge regions of a high-power device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0074] The preferred embodiments of the present invention are described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention.

[0075] Example 1:

[0076] This embodiment provides a method for implementing a high-power high-voltage transistor, such as Figure 1-7 As shown, including:

[0077] Step 1: sequentially growing an n+ epitaxial layer and an n- epitaxial layer on an n-type silicon substrate, and growing a protective silicon oxide on the surface of the n- epitaxial layer;

[0078] Step 2: removing the protective silicon oxide, growing a gate oxide layer on the surface of the n-epitaxial layer, and depositing a polysilicon layer on the gate oxide layer;

[0079] Step 3: forming a gate pattern and a p-channel region pattern on the gate oxide layer and the polysilicon layer by photolithography and etching, then forming a p-channel region based on the p-channel region pattern by boron ion doping and boron diffusion, and growing protective silicon oxide in the p-channel region;

[0080] Step 4: Photolithographically defining the patterns of the n+ source region and the n+ drain region of the transistor on the protective oxide layer of the p-channel region, etching the protective oxide layer of the p-channel region, and forming the n+ source region and the n+ drain region by phosphorus ion doping and phosphorus diffusion;

[0081] Step 5: Before depositing the interlayer oxide, anneal the n+ source region and the n+ drain region to oxidize the interface between the n+ source and n+ drain, the gate oxide layer, and the polysilicon layer in the transistor to an optimal thickness;

[0082] Step 6: depositing an interlayer oxide, and forming ohmic contact windows with the gate, source and drain on the interlayer oxide by photolithography and etching, depositing a metal layer, and forming metal interconnection of the transistor on the metal layer by photolithography and etching.

[0083] In this embodiment, a comparative analysis of the technical solution proposed in the present invention and the prototype shows that, before depositing the interlayer oxide, the n+ source and n+ drain regions are annealed until the oxide thickness at the junction is one to three times the gate oxide thickness. This eliminates gate oxide etching of the substrate in the source region and prevents undercutting of the gate oxide beneath the polysilicon gate. Increasing the oxide thickness increases the gate oxide thickness along the gate edge. Because the thermal oxide thickness along the gate edge is greater than or equal to the gate oxide thickness, the possibility of gate oxide breakdown along the gate edge is eliminated.

[0084] Among them, the selection of the oxide thickness range in the n+ source region and the n+ drain region depends on the following considerations: the lower limit of the oxide thickness is based on the fact that the thickness of the thermal oxide along the gate edge should not be less than the thickness of the gate oxide layer, and the thickness of the gate oxide layer determines its breakdown voltage, otherwise the oxide will break through the edge of the gate; the selection of the upper limit of the oxide thickness is based on the following fact: during the oxidation process of the source region, the crystallization of silicon will reduce its thickness, so the resistance of polysilicon increases, which will damage the dynamic characteristics of the transistor.

[0085] like Figure 7-8 As shown, through Figure 7 and Figure 8 The comparison clearly shows that the key point of the present invention is the optimization of the transistor unit structure in the gate edge area after the contact area is formed according to the prototype method, that is, the electric field distribution in the high-voltage area of ​​the high-power transistor is changed and optimized through process steps such as oxidation, thereby greatly improving the breakdown voltage of the transistor.

[0086] In this embodiment, the ohmic contact windows of the gate, source and drain are Figure 7 The ohmic contact region of the source, the ohmic contact region of the gate, and the ohmic contact region of the drain in the symmetrical structure.

[0087] In this embodiment, Figure 7 and Figure 8 Only the source region of the field effect transistor is shown, and the drain region also has a corresponding symmetrical structure.

[0088] The specific embodiments for the above steps 1-6 are as follows:

[0089] On silicon substrate <100> A protective oxide with a thickness of 0.1 μm is formed on the surface of the oriented n-n+ epitaxial structure. After removing the silicon surface oxide by chemical cleaning, a film with a thickness of 0.1 μm is grown in a dry oxygen and wet oxygen environment at a temperature of T = 1150 ° C. A gate layer is formed, a polysilicon layer with a thickness of 0.5 μm is deposited, and the polysilicon layer and the gate oxide layer are etched by photolithography and etching to form a gate pattern and a pattern of the p-channel region; based on the pattern of the p-channel region, boron ion doping and boron diffusion are performed by ion implantation to form a p-channel region, and the dose of the boron doping ion implantation is 3.75E13 / cm 2 The ion implantation energy was 60 KeV, boron diffusion was performed at 1150 ° C in nitrogen for 90 minutes, and 700 angstroms were grown at 900 ° C by wet oxygen and dry oxygen methods. The protective oxide layer is formed, and the source and drain regions of the transistor are patterned by photolithography on the protective oxide layer. The protective silicon oxide is etched and the ion implantation dose is 6.25E15 / cm 2 Phosphorus ion doping is performed under the process conditions of ion implantation energy of 100KeV, followed by annealing and oxidation before growing the interlayer oxide. The process conditions are annealing at 900℃ for 20 minutes in a nitrogen atmosphere and heat treatment in oxygen for 20 minutes to oxidize the interface between the transistor n+ source and drain and the gate oxide layer and the polysilicon layer to ~ Then, a layer of interlayer oxide with a thickness of 1.2μm is deposited by chemical vapor deposition (CVD). Ohmic contact windows with the gate, source and drain are formed by photolithography and etching; a metal layer is deposited; and metal interconnection of the transistor is formed by photolithography and ion etching.

[0090] In this embodiment, the oxide thickness in the source region and along the gate edge is 0.15 to 0.2 μm, the resistivity of the polysilicon on the test device is: Rs = 20 Ohm.cm, and the gate-source breakdown voltage is: Ugs = 95-110V.

[0091] In this embodiment, Figure 9 As shown, the relationship between the gate-source breakdown voltage (Vgs) of a high-power device and the oxide thickness of the source and gate edge regions is shown. Figure 8 It can be seen that compared with the prototype method, the method for manufacturing a high-power and high-voltage DMOS transistor proposed in the present invention can eliminate the breakdown of the oxide layer along the gate edge and significantly improve the gate-source breakdown voltage of the device.

[0092] The calculation formula that determines the relationship between the gate-source breakdown voltage (Vgs) of a high-power device and the oxide thickness at the source and gate edges is:

[0093] Vgs=1.174*d 0.5744 ; (1)

[0094] Where Vgs represents the gate-source breakdown voltage (Vgs), volts; d represents the oxide thickness at the gate edge region Angstrom;

[0095] The relationship between product yield and the oxide thickness at the source and gate edges is calculated using the following formula:

[0096] M=-2E -5 *d 2 +0.0851*d-10.816; (2)

[0097] Where M represents the product yield (percentage); d represents the oxide thickness at the gate edge. Angstrom.

[0098] Based on formula (2), it can be concluded that, compared with the prototype, the yield of the power transistor product manufactured by the present invention will be increased by nearly 100% when the oxide thickness of the source and gate edge regions is 1500 angstroms.

[0099] In this embodiment, after the p-channel region is formed by photolithography and etching in step 3, a protective oxide layer is grown in the p-channel region by wet oxygen and dry oxygen methods.

[0100] The beneficial effect of the above technical solution is that: through oxidation and other process steps, the boundary area between the transistor n+ source, n+ drain, gate oxide layer and polysilicon layer is oxidized to an optimal thickness, which can not only eliminate the etching of the gate oxide layer in the n+ source region, but also prevent the bottom of the gate oxide layer from being cut into. At the same time, it also eliminates the possibility of gate oxide breakdown along the gate edge.

[0101] Example 2:

[0102] Based on Example 1, this embodiment further provides a method for implementing a high-power high-voltage transistor, wherein the optimal thickness includes:

[0103] The optimal thickness, that is, the thickness of the oxide layer at the interface between the n+ source, n+ drain, gate oxide layer and polysilicon layer, is one to three times the thickness of the gate oxide layer.

[0104] The beneficial effect of the above technical solution is: by precisely controlling the annealing and oxidation of the source and drain regions until the oxide thickness is one to three times the gate oxide thickness, etching of the gate oxide of the substrate in the source region is eliminated and bottom cutting of the gate oxide below the polysilicon gate is prevented.

[0105] Example 3:

[0106] Based on Example 1, this embodiment provides a method for implementing a high-power high-voltage transistor, further comprising:

[0107] The thickness of the oxide in the n+ source region and the gate oxide layer is 0.15 to 0.2 μm, the resistivity of the polysilicon on the test component is 20 ohm.cm, and the gate-source breakdown voltage is 95-110 V;

[0108] The thickness of the oxide in the n+ source region is greater than or equal to the thickness of the oxide in the gate oxide layer.

[0109] The beneficial effect of the above technical solution is that, since the thickness of the thermal oxide along the gate edge is greater than or equal to the thickness of the gate oxide, the possibility of gate oxide breakdown along the gate edge is eliminated.

[0110] Example 4:

[0111] Based on Example 1, this embodiment provides a method for implementing a high-power high-voltage transistor. Based on steps 1-6, a device model is constructed, specifically including:

[0112] Determine the materials and device types required for the device model, and at the same time, determine the process flow of the device model;

[0113] The device model is constructed based on the materials, device types and process flow required for the device model.

[0114] In this embodiment, the materials and device types required for the device model are determined, and at the same time, the process flow of the device model is determined, for example: using silicon-based or compound semiconductor materials, such as silicon carbide (SiC), gallium nitride (GaN), gallium phosphide (GaP) or gallium arsenide (GaAs), diffused metal oxide semiconductor field effect (DMOS) devices or high electron mobility transistors (HEMT), etc.

[0115] In this embodiment, when constructing the device model, it is also necessary to construct the device model according to product requirements, such as device power, on-resistance, breakdown voltage, switching frequency, off-current, characteristic frequency, etc.

[0116] The beneficial effect of the above technical solution is that the method adopted by this invention can not only be used for silicon-based high-power and high-voltage DMOS transistors and related integrated circuits, but can also be extended to other types of semiconductor power devices and integrated circuits, such as compound semiconductor power devices and power integrated circuits.

[0117] Example 5:

[0118] Based on Example 4, this embodiment provides a method for implementing a high-power high-voltage transistor. After constructing the device model, the method further includes:

[0119] Determine the target device designed and produced by the device model;

[0120] Performing parameter tests on the target device over a full power and frequency range, and determining aspects of the target device that require improvement based on the test results;

[0121] Determining a target structure for improving the target model based on the link that needs to be improved in the target device, and determining a process flow corresponding to the target structure;

[0122] The target model is improved based on the target structure for improving the target model and the process flow corresponding to the target structure.

[0123] In this embodiment, a device designed and produced based on the device model is subjected to parameter testing in the full power and frequency range to determine aspects of the device that need improvement, such as the breakdown electric field distribution of low breakdown voltage, etc.

[0124] In this embodiment, the overall or local structure of the device (i.e., the target structure) and the corresponding process flow layer are improved according to the weak links of the device. For example, for low breakdown voltage, the method of the present invention can be used to change the field strength distribution of the breakdown voltage by changing the device structure, thereby achieving the effect of enhancing device performance.

[0125] The beneficial effect of the above technical solution is that the method changes the field intensity distribution of the breakdown voltage by changing the device structure, thereby achieving the effect of enhancing the device performance.

[0126] Example 6:

[0127] Based on Example 5, this embodiment provides a method for implementing a high-power high-voltage transistor, which, after improving the target model, further includes:

[0128] Testing and analyzing the improved target model, and determining the test results and analysis results;

[0129] The test results and the analysis results are fed back to the device model, and a database corresponding to the improved target model is constructed based on the feedback results.

[0130] The beneficial effect of the above technical solution is that by constructing a database corresponding to the improved target model, it is conducive to updating the data, thereby realizing the promotion of high-voltage transistors.

[0131] Example 7:

[0132] Based on Example 6, this embodiment provides a method for implementing a high-power high-voltage transistor, which constructs a database corresponding to the improved target model based on feedback results, including:

[0133] Acquire feedback data corresponding to the feedback result, and at the same time, acquire model data corresponding to the improved target model;

[0134] Generate a database identifier based on the model data, determine a storage path of the database, and create a data receiving window based on the storage path and the database identifier;

[0135] The feedback data and the model data are received in the data receiving window to complete the construction of the database corresponding to the improved target model.

[0136] In this embodiment, the database identifier may be used to indicate that only the database is created by the improved target model.

[0137] In this embodiment, the storage path may be the address where the database is stored.

[0138] In this embodiment, the data receiving window may be used to receive feedback data and model data.

[0139] The beneficial effects of the above technical solution are: by determining the model data, the database identifier of the database can be accurately determined, which is conducive to accurately constructing a database created only by the improved target model, and accurately receiving the model data and feedback data through the data receiving window, thereby accurately establishing the database.

[0140] Example 8:

[0141] Based on Example 1, this embodiment provides a method for realizing a high-power high-voltage transistor. In step 2, removing the protective silicon oxide includes:

[0142] Obtaining a baseline thickness and a baseline area of ​​protective silicon oxide on the surface of the n-epitaxial layer, and simultaneously, evaluating a chemical dosage for removing the protective silicon oxide based on the baseline thickness and the baseline area of ​​the protective silicon oxide;

[0143] generating a first silicon oxide removal instruction according to a baseline thickness and a baseline area of ​​the protective silicon oxide and a chemical dosage for removing the protective silicon oxide;

[0144] Acquiring environmental parameter data of an environment in which the n-epitaxial layer is located, analyzing the environmental parameter data, and determining, based on the analysis results, whether the environment in which the n-epitaxial layer is located can effectively remove the protective silicon oxide;

[0145] When the environment of the n-epitaxial layer can effectively remove the protective silicon oxide, removing the protective silicon oxide on the surface of the n-epitaxial layer based on the first silicon oxide removal instruction;

[0146] When the environment of the n-epitaxial layer cannot effectively remove the protective silicon oxide, the environmental parameter data of the environment of the n-epitaxial layer is manually adjusted until the environment of the n-epitaxial layer can effectively remove the protective silicon oxide.

[0147] In this embodiment, the reference thickness and the reference area refer to the theoretical thickness and the theoretical area of ​​the protective silicon oxide on the surface of the n-epitaxial layer.

[0148] In this embodiment, the first silicon oxide removal instruction may be to remove the generated silicon oxide for the first time.

[0149] In this embodiment, the environmental parameter data may be the temperature, humidity, etc. of the environment where the n-epitaxial layer is located.

[0150] The beneficial effects of the above technical solution are: by determining the baseline thickness and baseline area of ​​silicon oxide, the chemical dosage can be accurately determined. Secondly, based on the environmental parameter data of the environment where the n-epitaxial layer is located, whether the silicon oxide can be effectively removed is effectively evaluated, thereby achieving efficient removal of silicon oxide.

[0151] Example 9:

[0152] Based on Example 8, this embodiment provides a method for realizing a high-power high-voltage transistor, which, after removing the protective silicon oxide on the surface of the n-epitaxial layer, further includes:

[0153] Acquiring a planar image on the surface of the n-epitaxial layer, and performing grayscale processing on the planar image to generate a grayscale planar image;

[0154] Extracting pixel points of the grayscale plane image and determining pixel features corresponding to the pixel points;

[0155] determining whether the protective silicon oxide on the surface of the n-epitaxial layer is completely removed according to the pixel feature corresponding to the pixel point;

[0156] When the protective silicon oxide on the surface of the n-epitaxial layer is completely removed, a gate oxide layer is grown on the surface of the n-epitaxial layer;

[0157] When the protective silicon oxide on the surface of the n-epitaxial layer is not completely removed, marking the protective silicon oxide based on the grayscale plane image and acquiring marking data;

[0158] Analyzing the marked data to determine the attachment area of ​​the protective silicon oxide on the n-epitaxial layer and the current concavity and convexity of the n-epitaxial layer;

[0159] Formulate a removal plan based on the attachment area of ​​the protective silicon oxide on the n-epitaxial layer and the current concavity and convexity of the n-epitaxial layer, and generate a second silicon oxide removal instruction according to the removal plan;

[0160] The protective silicon oxide on the surface of the n-epitaxial layer is removed again based on the second silicon oxide removal instruction.

[0161] In this embodiment, the pixel feature may be the color of the pixel. For example, whether the silicon oxide is attached to the surface of the n-epitaxial layer may be determined based on whether the pixel is black or white.

[0162] In this embodiment, the marking data may be the number and position of the markings performed by the protective silicon oxide.

[0163] In this embodiment, the second silicon oxide removal instruction may be used to remove the remaining silicon oxide again when the first silicon oxide removal instruction fails to completely remove the silicon oxide.

[0164] In this embodiment, the step of obtaining the concavity and convexity of the n-epitaxial layer includes:

[0165] S101: Read the grayscale plane image and randomly select a point in the grayscale plane image as the target point ω t At the same time, based on the pixel features corresponding to the pixel points of the grayscale plane image, the target area where any protective silicon oxide is located on the grayscale plane image is determined, and the center point in the target area is determined as the reference point σ

[0166] S102: Select the target point ω based on the grayscale plane image t The adjacent pixel points ω t-1 、ω t+1 Draw a directed line segment ω t-1 ω t+1 ;

[0167] S103: Determine the judgment condition and judge the target point ω t Whether it is a convex point;

[0168]

[0169] Wherein, Δ represents the judgment condition; (m t , n t ) represents the target point ω t Coordinate point; (m t-1 , n t-1 )、(m t+1 , n t+1 ) represents the target point ω t The coordinates of the adjacent pixel points; (m σ , m σ ) represents the coordinate point of the reference point σ;

[0170] When Δ>0, the reference point σ and the target point ω are determined. t On the directed line segment ω t-1 ω t+1 On the same side, determine the target point ω t is a convex point;

[0171] When Δ≤0, the reference point σ and the target point ω are determined. t On the directed line segment ω t-1 ω t+1 On the opposite side of t Not a convex point;

[0172] S104: Repeat step S103 to determine all salient points in the grayscale plane image and mark the salient points;

[0173] S105: determining the total number of the convex points in the grayscale plane image, and calculating the concavo-convexity ratio of the n-epitaxial layer based on the total number of the convex points;

[0174]

[0175] Wherein, η represents the concavo-convex ratio of the n-epitaxial layer; R represents the total number of convex points in the grayscale plane image; G represents the total number of pixels in the grayscale plane image; M represents the total number of non-convex points in the grayscale plane image; ξ represents the error factor, and its value range is (0.703, 0.706);

[0176] In the above formula, The purpose is to obtain the average value so that the calculated concavity and convexity of the n-epitaxial layer is more accurate.

[0177] In the above step S104 , the number of cycles of repeating step S103 is 3*(n-2), and n represents the number of pixels in the plane image, and n>3.

[0178] The beneficial effect of the above technical solution is: by obtaining a planar image on the surface of the n-epitaxial layer, the removal status of the silicon oxide on the surface of the n-epitaxial layer can be accurately analyzed, and when it is not completely removed, a removal plan is formulated to effectively remove the silicon oxide on the surface of the n-epitaxial layer.

[0179] Example 10:

[0180] Based on Example 1, this embodiment provides a method for implementing a high-power high-voltage transistor. In step 5, the interface region between the n+ source and n+ drain, the gate oxide layer, and the polysilicon layer in the transistor is oxidized to an optimal thickness, and the method further includes:

[0181] Connecting the gate oxide layer to a preset testing device, and at the same time, obtaining the breakdown voltage of the gate oxide layer and the n-epitaxial layer;

[0182] Adjusting a test voltage of the preset test device so that the test voltage is equal to the breakdown voltage;

[0183] Acquiring a charge of the preset test device, and calculating a current capacitance value of the gate oxide layer based on the charge of the preset test device and the test voltage;

[0184] Obtaining an effective capacitance area of ​​the gate oxide layer, and calculating and determining a current thickness value of the gate oxide layer based on a current capacitance value of the gate oxide layer and the effective capacitance area;

[0185] Determining, based on a current thickness value of the gate oxide layer, a target thickness value for oxidizing the interface region between the n+ source and n+ drain, the gate oxide layer, and the polysilicon layer in the transistor to an optimal thickness;

[0186] Determining monitoring instructions and control instructions for oxidizing the boundary region between the n+ source, the n+ drain, the gate oxide layer, and the polysilicon layer of the transistor according to the target thickness value;

[0187] Based on the monitoring instruction, the thickness of the oxidation of the n+ source, n+ drain, gate oxide layer and the boundary region of the polysilicon layer of the transistor is monitored, and the monitoring data is recorded according to a preset time period;

[0188] Setting a first monitoring threshold and a second monitoring threshold, wherein the first monitoring threshold is less than the second monitoring threshold, and the second monitoring threshold is equal to the target thickness value;

[0189] Reading the monitoring data in real time, and issuing a first alarm when the monitoring data is equal to the first monitoring threshold;

[0190] Simultaneously, an oxidation rate of an interface region between an n+ source and an n+ drain, a gate oxide layer, and a polysilicon layer in the transistor is oxidized based on the monitoring data;

[0191] estimating, based on the oxidation rate, a predicted time period when the monitoring data reaches the second monitoring threshold;

[0192] Initiating the control instruction based on the estimated time period, and timing according to the estimated time period based on the control instruction;

[0193] When the monitoring data is equal to the second monitoring threshold, a second alarm is issued, and based on the control instruction, the n+ source and n+ drain, the gate oxide layer and the junction area of ​​the polysilicon layer in the transistor are controlled to stop oxidation, so as to achieve the oxidation of the n+ source and n+ drain, the gate oxide layer and the junction area of ​​the polysilicon layer in the transistor to an optimal thickness.

[0194] In this embodiment, the preset test device is set in advance and is used to test the breakdown voltage of the gate oxide layer and the n-epitaxial layer.

[0195] In this embodiment, the effective capacitance area may be an area in the gate oxide layer that can effectively store charges.

[0196] In this embodiment, the target thickness value may be a thickness value when the interface area is oxidized to a theoretical thickness, wherein the theoretical thickness value is obtained through multiple experimental trainings.

[0197] In this embodiment, the preset time period is set in advance and may be a time interval for monitoring the oxidation thickness of the boundary area.

[0198] In this embodiment, the first monitoring threshold may be the value at which the oxide thickness reaches the first alarm. By reaching the first monitoring threshold, the time to reach the second monitoring threshold (i.e., the target thickness value) can be well estimated, thereby starting the control instruction to time according to the estimated time period, thereby improving the accuracy of the control instruction and also improving the control of the optimal thickness of the interface area.

[0199] In this embodiment, the second monitoring threshold is the target thickness value.

[0200] In this embodiment, the estimated time period may be counted from the time point corresponding to the first monitoring threshold to the time point corresponding to the second monitoring threshold.

[0201] In this embodiment, the first alarm reminder may be an alarm operation performed simultaneously with light and vibration.

[0202] In this embodiment, the second alarm reminder can be an alarm operation performed simultaneously with light and sound.

[0203] The beneficial effect of the above technical solution is: by calculating and determining the current thickness value of the gate oxide layer, it is possible to determine the target thickness value for oxidizing the interface area of ​​the n+ source and n+ drain, the gate oxide layer, and the polysilicon layer in the transistor to the optimal thickness, and then by determining the first monitoring threshold and the second monitoring threshold, and monitoring according to the monitoring instructions, the target thickness value is accurately achieved through the control instructions, thereby improving the accuracy of monitoring, which is conducive to eliminating the etching of the gate oxide of the substrate in the source region and preventing the bottom of the gate oxide from being cut into below the polysilicon gate.

[0204] Obviously, those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if such changes and modifications fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. A method for realizing a high-power high-voltage transistor, characterized in that: include: Step 1: sequentially growing an n+ epitaxial layer and an n- epitaxial layer on an n-type silicon substrate, and growing a protective silicon oxide on the surface of the n- epitaxial layer; Step 2: removing the protective silicon oxide, growing a gate oxide layer on the surface of the n-epitaxial layer, and depositing a polysilicon layer on the gate oxide layer; Step 3: forming a gate pattern and a p-channel region pattern on the gate oxide layer and the polysilicon layer by photolithography and etching, then forming a p-channel region based on the p-channel region pattern by boron ion doping and boron diffusion, and growing protective silicon oxide in the p-channel region; Step 4: Photolithographically defining the patterns of the n+ source region and the n+ drain region of the transistor on the protective oxide layer of the p-channel region, etching the protective oxide layer of the p-channel region, and forming the n+ source region and the n+ drain region by phosphorus ion doping and phosphorus diffusion; Step 5: Before depositing the interlayer oxide, anneal the n+ source region and the n+ drain region to oxidize the interface between the n+ source and n+ drain, the gate oxide layer, and the polysilicon layer in the transistor to an optimal thickness; Step 6: depositing an interlayer oxide, and forming ohmic contact windows with the gate, source, and drain on the interlayer oxide by photolithography and etching, depositing a metal layer, and forming metal interconnects of the transistor on the metal layer by photolithography and etching; In step 2, removing the protective silicon oxide comprises: Obtaining a baseline thickness and a baseline area of ​​protective silicon oxide on the surface of the n-epitaxial layer, and simultaneously, evaluating a chemical dosage for removing the protective silicon oxide based on the baseline thickness and the baseline area of ​​the protective silicon oxide; generating a first silicon oxide removal instruction according to a baseline thickness and a baseline area of ​​the protective silicon oxide and a chemical dosage for removing the protective silicon oxide; Acquiring environmental parameter data of an environment in which the n-epitaxial layer is located, analyzing the environmental parameter data, and determining, based on the analysis results, whether the environment in which the n-epitaxial layer is located can effectively remove the protective silicon oxide; When the environment of the n-epitaxial layer can effectively remove the protective silicon oxide, removing the protective silicon oxide on the surface of the n-epitaxial layer based on the first silicon oxide removal instruction; When the environment in which the n-epitaxial layer is located cannot effectively remove the protective silicon oxide, manually adjusting the environmental parameter data of the environment in which the n-epitaxial layer is located until the environment in which the n-epitaxial layer is located can effectively remove the protective silicon oxide; After removing the protective silicon oxide on the surface of the n-epitaxial layer, the method further comprises: Acquiring a planar image on the surface of the n-epitaxial layer, and performing grayscale processing on the planar image to generate a grayscale planar image; Extracting pixel points of the grayscale plane image and determining pixel features corresponding to the pixel points; determining whether the protective silicon oxide on the surface of the n-epitaxial layer is completely removed according to the pixel feature corresponding to the pixel point; When the protective silicon oxide on the surface of the n-epitaxial layer is completely removed, a gate oxide layer is grown on the surface of the n-epitaxial layer; When the protective silicon oxide on the surface of the n-epitaxial layer is not completely removed, marking the protective silicon oxide based on the grayscale plane image and acquiring marking data; Analyzing the marked data to determine the attachment area of ​​the protective silicon oxide on the n-epitaxial layer and the current concavity and convexity of the n-epitaxial layer; Formulate a removal plan based on the attachment area of ​​the protective silicon oxide on the n-epitaxial layer and the current concavity and convexity of the n-epitaxial layer, and generate a second silicon oxide removal instruction according to the removal plan; removing the protective silicon oxide on the surface of the n-epitaxial layer again based on the second silicon oxide removal instruction; The step of obtaining the concavity and convexity of the n-epitaxial layer includes: S101: Read the grayscale plane image and randomly select a point in the grayscale plane image as a target point At the same time, based on the pixel features corresponding to the pixel points of the grayscale plane image, the target area where any protective silicon oxide is located on the grayscale plane image is determined, and the center point in the target area is determined as the reference point ; S102: Select the target point based on the grayscale plane image Neighboring pixels 、 Draw a directed line segment ; S103: Determine the judgment condition and judge the target point Whether it is a convex point; ； in, Indicates the judgment condition; Indicates the target point The coordinates of the points; 、 Indicates the target point The coordinates of the adjacent pixel points; Indicates the reference point The coordinates of the points; when , then determine the reference point and the target point On a directed line segment On the same side, determine the target point is a convex point; when , then determine the reference point and the target point On a directed line segment On the opposite side of Not a convex point; S104: Repeat step S103 to determine all salient points in the grayscale plane image and mark the salient points; S105: determining the total number of the convex points in the grayscale plane image, and calculating the concavo-convexity ratio of the n-epitaxial layer based on the total number of the convex points; ； in, represents the concavity and convexity of the n-epitaxial layer; represents the total number of the salient points in the grayscale plane image; Represents the total number of pixels of the grayscale plane image; represents the total number of non-convex points in the grayscale plane image; represents the error factor, and its value range is (0.703, 0.706); In step 5, the optimal thickness includes: The optimal thickness is one to three times the thickness of the gate oxide layer.

2. The method for realizing a high-power high-voltage transistor according to claim 1, wherein: Also includes: The thickness of the oxide in the n+ source region and the gate oxide layer is 0.15 to 0.2 μm, the resistivity of the polysilicon on the test device is 20 ohm.cm (Ohm.cm), and the gate-source breakdown voltage is 95-110V; The thickness of the oxide in the n+ source region is greater than or equal to the thickness of the oxide in the gate oxide layer.

3. The method for realizing a high-power high-voltage transistor according to claim 1, wherein: Based on steps 1-6, a device model is constructed, specifically including: Determine the materials and device types required for the device model, and at the same time, determine the process flow of the device model; The device model is constructed based on the materials, device types and process flow required for the device model.

4. The method for realizing a high-power high-voltage transistor according to claim 3, wherein: After constructing the device model, the following steps are also included: Determine the target device designed and produced by the device model; Performing parameter tests on the target device over a full power and frequency range, and determining aspects of the target device that require improvement based on the test results; Determining a target structure for improving the device model based on the link that needs to be improved in the target device, and determining a process flow corresponding to the target structure; The device model is improved based on a target structure for improving the device model and a process flow corresponding to the target structure.

5. The method for realizing a high-power high-voltage transistor according to claim 4, wherein: After improving the target structure, it also includes: Testing and analyzing the improved target structure, and determining the test results and analysis results; The test results and the analysis results are fed back to the device model, and a database corresponding to the improved target structure is constructed based on the feedback results.

6. The method for realizing a high-power high-voltage transistor according to claim 5, characterized in that: Building a database corresponding to the improved target structure based on the feedback results, including: Acquiring feedback data corresponding to the feedback result, and at the same time, acquiring model data corresponding to the improved target structure; Generate a database identifier based on the model data, determine a storage path of the database, and create a data receiving window based on the storage path and the database identifier; The feedback data and the model data are received in the data receiving window to complete the construction of a database corresponding to the improved target structure.

7. The method for realizing a high-power high-voltage transistor according to claim 1, wherein: In step 5, the n+ source and n+ drain, the gate oxide layer, and the interface region of the polysilicon layer in the transistor are oxidized to an optimal thickness, further comprising: Connecting the gate oxide layer to a preset testing device, and at the same time, obtaining the breakdown voltage of the gate oxide layer and the n-epitaxial layer; Adjusting a test voltage of the preset test device so that the test voltage is equal to the breakdown voltage; Acquiring a charge of the preset test device, and calculating a current capacitance value of the gate oxide layer based on the charge of the preset test device and the test voltage; Obtaining an effective capacitance area of ​​the gate oxide layer, and calculating and determining a current thickness value of the gate oxide layer based on a current capacitance value of the gate oxide layer and the effective capacitance area; Determining, based on a current thickness value of the gate oxide layer, a target thickness value for oxidizing the interface region between the n+ source and the n+ drain, the gate oxide layer, and the polysilicon layer in the transistor to an optimal thickness; Determining monitoring instructions and control instructions for oxidizing the boundary region between the n+ source, the n+ drain, the gate oxide layer, and the polysilicon layer of the transistor according to the target thickness value; Based on the monitoring instruction, the thickness of the oxidation of the n+ source, n+ drain, gate oxide layer and the boundary region of the polysilicon layer of the transistor is monitored, and the monitoring data is recorded according to a preset time period; Setting a first monitoring threshold and a second monitoring threshold, wherein the first monitoring threshold is less than the second monitoring threshold, and the second monitoring threshold is equal to the target thickness value; Reading the monitoring data in real time, and issuing a first alarm when the monitoring data is equal to the first monitoring threshold; Simultaneously, an oxidation rate of an interface region between an n+ source and an n+ drain, a gate oxide layer, and a polysilicon layer in the transistor is oxidized based on the monitoring data; estimating, based on the oxidation rate, a predicted time period when the monitoring data reaches the second monitoring threshold; Initiating the control instruction based on the estimated time period, and timing according to the estimated time period based on the control instruction; When the monitoring data is equal to the second monitoring threshold, a second alarm is issued, and based on the control instruction, the n+ source and n+ drain, the gate oxide layer and the junction area of ​​the polysilicon layer in the transistor are controlled to stop oxidation, so as to achieve the oxidation of the n+ source and n+ drain, the gate oxide layer and the junction area of ​​the polysilicon layer in the transistor to an optimal thickness.

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